DS90LT012AH High Temperature 3V LVDS Differential Line Receiver DS90LT012AH FEATURES DESCRIPTION

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DS90LT012AH www.ti.com

SNLS199A – SEPTEMBER 2005 – REVISED APRIL 2013

DS90LT012AH High Temperature 3V LVDS Differential Line Receiver

Check for Samples: DS90LT012AH

1

FEATURES

2

• -40 to +125°C Temperature Range Operation

• Compatible with ANSI TIA/EIA-644-A Standard

• >400 Mbps (200 MHz) Switching Rates

• 100 ps Differential Skew (Typical)

• 3.5 ns Maximum Propagation Delay

• Integrated Line Termination Resistor (100 Ω typical)

• Single 3.3V Power Supply Design (2.7V to 3.6V

Range)

• Power Down High Impedance on LVDS Inputs

• LVDS Inputs Accept LVDS/CML/LVPECL

Signals

• Pinout Simplifies PCB Layout

• Low Power Dissipation (10mW Typical@ 3.3V

Static)

• SOT-23 5-Lead Package

DESCRIPTION

The DS90LT012AH is a single CMOS differential line receiver designed for applications requiring ultra low power dissipation, low noise, and high data rates.

The devices are designed to support data rates in excess of 400 Mbps (200 MHz) utilizing Low Voltage

Differential Swing (LVDS) technology

The DS90LT012AH accepts low voltage (350 mV typical) differential input signals and translates them to 3V CMOS output levels. The DS90LT012AH includes an input line termination resistor for point-topoint applications.

The DS90LT012AH and companion LVDS line driver

DS90LV011AH provide a new alternative to high power PECL/ECL devices for high speed interface applications.

Connection Diagram

Figure 1. Top View

See Package Number DBV (R-PDSO-G5)

Functional Diagram

INPUTS

[IN+]

−

[IN

−

]

V

ID

≥ 0V

V

ID

≤ − 0.1V

Figure 2. DS90LT012AH

Truth Table

Full Fail-safe OPEN/SHORT or Terminated

OUTPUT

TTL OUT

H

L

H

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2005–2013, Texas Instruments Incorporated

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DS90LT012AH


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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings

(1)

Supply Voltage (V

DD

)

Input Voltage (IN+, IN − )

Output Voltage (TTL OUT)

Output Short Circuit Current

Maximum Package Power Dissipation @ +25°C

DBV Package

Derate DBV Package

Thermal resistance ( θ

JA

)

Storage Temperature Range

Lead Temperature Range Soldering

(4 sec.)

Maximum Junction Temperature

ESD Ratings

(2)

− 0.3V to +4V

− 0.3V to +3.9V

− 0.3V to (V

DD

+ 0.3V)

−

100mA

902mW

7.22 mW/°C above +25°C

138.5°C/W

−

65°C to +150°C

+260°C

+150°C

(1) “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be verified. They are not meant to imply that the devices should be operated at these limits.

Electrical Characteristics

specifies conditions of device operation.

(2) ESD Ratings:

DS90LT012AH:

(a) HBM (1.5 k Ω , 100 pF) ≥ 2kV

(b) EIAJ (0 Ω , 200 pF) ≥ 700V

(c) CDM ≥ 2000V

(d) IEC direct (330 Ω , 150 pF) ≥ 7kV

Recommended Operating Conditions

Supply Voltage (V

DD

)

Operating Free Air

Temperature (T

A

)

Min

+2.7

− 40

Typ

+3.3

25

Max

+3.6

+125

Units

V

°C

2

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Product Folder Links:

DS90LT012AH


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Electrical Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

(1) (2)

Symbol

V

TH

V

TL

V

CM

Parameter

Differential Input High Threshold

Differential Input Low Threshold

Common-Mode Voltage

Conditions

V

CM dependant on V

DD

(3)

Pin

IN+, IN −

I

IN

Δ I

IN

I

IND

Input Current (DS90LV012A)

Change in Magnitude of I

IN

Differential Input Current

V

DD

= 2.7V, V

ID

= 100mV

V

DD

= 3.0V to 3.6V, V

ID

= 100mV

T

A

= 125°C

V

IN

= +2.8V

V

DD

= 3.6V or 0V

V

IN

= 0V

V

IN

= +3.6V

V

DD

= 0V

V

IN

= +2.8V

V

DD

= 3.6V or 0V

V

IN

= 0V

V

IN

= +3.6V

V

DD

= 0V

V

IN+

= +0.4V, V

IN −

= +0V

V

IN+

= +2.4V, V

IN

−

= +2.0V

Min Typ

− 30

− 100 − 30

0.05

0.05

0.10

− 10

− 10

− 20

±1

±1

4

4

4

3 3.9

R

T

C

IN

V

OH

V

OL

I

OS

V

CL

I

DD

Integrated Termination Resistor

Input Capacitance

Output High Voltage

Output Low Voltage

Output Short Circuit Current

Input Clamp Voltage

No Load Supply Current

IN+ = IN

−

= GND

I

OH

= − 0.4 mA, V

ID

= +200 mV

I

OH

= − 0.4 mA, Inputs terminated

I

OH

= − 0.4 mA, Inputs shorted

I

OL

= 2 mA, V

ID

= − 200 mV

V

OUT

= 0V

(4)

I

CL

= − 18 mA

Inputs Open

TTL OUT

V

DD

100

3

3.1

2.4

2.4

2.4

3.1

3.1

−

15

0.3

−

50

− 1.5

− 0.7

5.4

Max

0

2.35

V

DD

- 0.3V

2.35

+10

+10

+20

4.4

0.5

−

100

9 mA

(1) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified (such as V

ID

).

(2) All typicals are given for: V

DD

(3) V

DD

= +3.3V and T

A

= +25°C.

is always higher than IN+ and IN

− voltage. IN+ and IN

− are allowed to have voltage range

−

0.05V to +2.35V when V

DD

|V

ID

| / 2 to V

DD

2.7V or when V

−

CM

0.3V when V

= |V

ID

DD

| / 2 to V

= 3.0V to 3.6V. V

ID

DD

−

0.3V when V

DD is not allowed to be greater than 100 mV when V

= 3.0V to 3.6V.

CM

= 2.7V and

= 0.05V to 2.35V when V

DD

=

(4) Output short circuit current (I

OS

) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification.

Ω pF

V

V

V

V mA

V mA

Units

mV mV

V

V

V

μ A

μ A

μ A

μ A

μ

A

μ A



DS90LT012AH


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DS90LT012AH


Switching Characteristics

Over Supply Voltage and Operating Temperature ranges, unless otherwise specified.

(1) (2)

Symbol

t

PHLD t

PLHD t

SKD1 t

SKD3 t

SKD4 t

TLH t

THL f

MAX

Parameter

Differential Propagation Delay High to Low

Differential Propagation Delay Low to High

Differential Pulse Skew |t

PHLD

− t

PLHD

|

Differential Part to Part Skew

(4)

(3)

Differential Part to Part Skew

(5)

Rise Time

Fall Time

Maximum Operating Frequency

(6)

Conditions

C

L

V

ID

= 15 pF

= 200 mV

(

Figure 3

and

Figure 4

)

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Min

1.0

1.0

0

0

0

200

0.3

0.4

350

175

250

Typ

1.8

1.7

100

Max Units

3.5

ns

3.5

400 ns ps

1.0

1.5

800

800 ns ns ps ps

MHz

(1) C

L

(2) Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z

O

(3) t includes probe and jig capacitance.

SKD1

= 50 Ω , t r and t f

(0% to 100%) ≤ 3 ns for IN±.

is the magnitude difference in differential propagation delay time between the positive-going-edge and the negative-going-edge of the same channel.

(4) t

SKD3

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices at the same V

DD and within 5°C of each other within the operating temperature range.

(5) t

SKD4

, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over the recommended operating temperature and voltage ranges, and across process distribution. t differential propagation delay.

SKD4 is defined as |Max − Min|

(6) f

MAX generator input conditions: t r

60%/40% duty cycle, V

OL

= t f

< 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35 peak to peak). Output criteria:

(max 0.4V), V

OH

(min 2.4V), load = 15 pF (stray plus probes). The parameter is specified by design. The limit is based on the statistical analysis of the device over the PVT range by the transition times (t

TLH and t

THL

).

4



DS90LT012AH


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DS90LT012AH


PARAMETER MEASUREMENT INFORMATION

Figure 3. Receiver Propagation Delay and Transition Time Test Circuit

Figure 4. Receiver Propagation Delay and Transition Time Waveforms

TYPICAL APPLICATIONS

Balanced System

Figure 5. Point-to-Point Application (DS90LT012AH)



DS90LT012AH


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DS90LT012AH


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APPLICATION INFORMATION

General application guidelines and hints for LVDS drivers and receivers may be found in the following application notes: LVDS Owner's Manual( SNLA187) , AN-808( SNLA028 ), AN-977( SNLA166 ), AN-971( SNLA165 ), AN-

916( SNLA219 ), AN-805( SNOA233 ), AN-903( SNLA034 ).

LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in

Figure 5 . This configuration provides a clean signaling environment for the fast edge rates of the

drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100 Ω . The internal termination resistor converts the driver output (current mode) into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account.

The DS90LT012AH differential line receiver is capable of detecting signals as low as 100 mV, over a ±1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V.

The driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be the result of a ground potential difference between the driver's ground reference and the receiver's ground reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V

(measured from each pin to ground). The device will operate for receiver input voltages up to V

DD

V

DD will turn on the ESD protection circuitry which will clamp the bus voltages.

, but exceeding

POWER DECOUPLING RECOMMENDATIONS

Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)

0.1

μ F and 0.001

μ F capacitors in parallel at the power supply pin with the smallest value capacitor closest to the device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple vias should be used to connect the decoupling capacitors to the power planes. A 10 μ F (35V) or greater solid tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply and ground.

PC BOARD CONSIDERATIONS

Use at least 4 PCB board layers (top to bottom): LVDS signals, ground, power, TTL signals.

Isolate TTL signals from LVDS signals, otherwise the TTL signals may couple onto the LVDS lines. It is best to put TTL and LVDS signals on different layers which are isolated by a power/ground plane(s).

Keep drivers and receivers as close to the (LVDS port side) connectors as possible.

DIFFERENTIAL TRACES

Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable) and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise induced on the differential lines is much more likely to appear as common-mode which is rejected by the receiver.

Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI will result! (Note that the velocity of propagation, v = c/E r where c (the speed of light) = 0.2997mm/ps or 0.0118

in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match differential impedance and provide isolation for the differential lines. Minimize the number of vias and other discontinuities on the line.

Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.

Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid discontinuities in differential impedance. Minor violations at connection points are allowable.

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DS90LT012AH

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TERMINATION

The DS90LT012AH integrates the terminating resistor for point-to-point applications. The resistor value will be between 90 Ω and 133 Ω .

THRESHOLD

The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maximum threshold of ±100mV for the LVDS receiver.

The DS90LV012A and DS90LT012A support an enhanced threshold region of − 100mV to 0V. This is useful for fail-safe biasing. The threshold region is shown in the Voltage Transfer Curve (VTC) in

Figure 6

. The typical

DS90LT012AH LVDS receiver switches at about − 30mV. Note that with V

ID

= 0V, the output will be in a HIGH state. With an external fail-safe bias of +25mV applied, the typical differential noise margin is now the difference from the switch point to the bias point. In the example below, this would be 55mV of Differential Noise Margin

(+25mV − ( − 30mV)). With the enhanced threshold region of − 100mV to 0V, this small external fail-safe biasing of

+25mV (with respect to 0V) gives a DNM of a comfortable 55mV. With the standard threshold region of ±100mV, the external fail-safe biasing would need to be +25mV with respect to +100mV or +125mV, giving a DNM of

155mV which is stronger fail-safe biasing than is necessary for the DS90LT012AH. If more DNM is required, then a stronger fail-safe bias point can be set by changing resistor values.

Figure 6. VTC of the DS90LT012AH LVDS Receiver

FAIL SAFE BIASING

External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5k Ω to 15k Ω range to minimize loading and waveform distortion to the driver. The commonmode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN-1194, “Failsafe Biasing of LVDS Interfaces”( SNLA051 ) for more information.

PROBING LVDS TRANSMISSION LINES

Always use high impedance (> 100k Ω ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz) scope. Improper probing will give deceiving results.

CABLES AND CONNECTORS, GENERAL COMMENTS

When choosing cable and connectors for LVDS it is important to remember:

Use controlled impedance media. The cables and connectors you use should have a matched differential impedance of about 100 Ω . They should not introduce major impedance discontinuities.

Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax) for noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by the receiver.

For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M

≤ d ≤ 10M, CAT 3

(category 3) twisted pair cable works well, is readily available and relatively inexpensive.



DS90LT012AH


7

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DS90LT012AH


Package Pin Number

SOT-23

4

3

5

1

2

Pin Name

IN −

IN+

TTL OUT

V

DD

GND

NC

Pin Descriptions

Inverting receiver input pin

Non-inverting receiver input pin

Receiver output pin

Power supply pin, +3.3V ± 0.3V

Ground pin

No connect

Description www.ti.com

8



DS90LT012AH


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REVISION HISTORY

Changes from Original (April 2013) to Revision A Page

• Changed layout of National Data Sheet to TI format ............................................................................................................

8



DS90LT012AH


9

PACKAGE OPTION ADDENDUM

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1-Nov-2015

PACKAGING INFORMATION

Orderable Device

DS90LT012AHMF

DS90LT012AHMF/NOPB

Status

(1)

NRND

ACTIVE

ACTIVE

Package Type Package

Drawing

SOT-23

SOT-23

DBV

DBV

Pins Package

5

5

Qty

Eco Plan

(2)

1000 TBD

1000 Green (RoHS

& no Sb/Br)

SOT-23 DBV 5 TBD

Lead/Ball Finish

(6)

Call TI

CU SN

MSL Peak Temp

(3)

Call TI

Level-1-260C-UNLIM

Op Temp (°C)

N05

N05

Device Marking

(4/5)

DS90LT012AHMFX/NOPB Call TI Call TI N05

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

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1-Nov-2015 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

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TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

2-Sep-2015

*All dimensions are nominal

Device

DS90LT012AHMF

DS90LT012AHMF/NOPB

Package

Type

Package

Drawing

SOT-23

SOT-23

DBV

DBV

Pins

5

5

SPQ

1000

1000

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

178.0

8.4

178.0

8.4

A0

(mm)

3.2

3.2

B0

(mm)

3.2

3.2

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

1.4

1.4

4.0

4.0

8.0

8.0

Q3

Q3

Pack Materials-Page 1

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PACKAGE MATERIALS INFORMATION

2-Sep-2015

*All dimensions are nominal

Device

DS90LT012AHMF

DS90LT012AHMF/NOPB

Package Type Package Drawing Pins

SOT-23

SOT-23

DBV

DBV

5

5

SPQ

1000

1000

Length (mm) Width (mm) Height (mm)

210.0

210.0

185.0

185.0

35.0

35.0

Pack Materials-Page 2

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DS90LT012AH High Temperature 3V LVDS Differential Line Receiver DS90LT012AH FEATURES DESCRIPTION

DS90LT012AH High Temperature 3V LVDS Differential Line Receiver

FEATURES

DESCRIPTION

Connection Diagram

Functional Diagram

Truth Table

Absolute Maximum Ratings

Recommended Operating Conditions

Electrical Characteristics

Switching Characteristics

PARAMETER MEASUREMENT INFORMATION

TYPICAL APPLICATIONS

APPLICATION INFORMATION

POWER DECOUPLING RECOMMENDATIONS

PC BOARD CONSIDERATIONS

DIFFERENTIAL TRACES

TERMINATION

THRESHOLD

FAIL SAFE BIASING

PROBING LVDS TRANSMISSION LINES

CABLES AND CONNECTORS, GENERAL COMMENTS

REVISION HISTORY

PACKAGING INFORMATION

TAPE AND REEL INFORMATION

Table of contents