DRV8860x 38-V 8-Channel Serial Interface Low-Side Driver 1 Features 3 Description

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1

DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

DRV8860x 38-V 8-Channel Serial Interface Low-Side Driver

1 Features

1

• 8-Channel Protected Low-side Driver

– Eight NMOS FETs with Overcurrent Protection

– Integrated Inductive Catch Diodes

– Serial Interface

– Open/Short Load Detection (DRV8860 only)

– Configurable 100% Output Timing

– Configurable PWM Duty Cycle

• Continuous Current Driving Capability

– 560 mA (Single Channel on) PW and PWP

– 200 mA (8 Channels on) PW

– 330 mA (8 Channels on) PWP

– Support Parallel Configuration

• 8 V to 38 V Supply Voltage Range

• Input Digital Noise Filter for Noise Immunity

• Internal Data Read Back Capability for Reliable

Control

• Protection and Diagnostic Features

– Overcurrent Protection (OCP)

– Open Load Detection (OL)

– Overtemperature Shutdown (OTS)

– Undervoltage Lockout (UVLO)

– Individual Channel Status Report

– Fault Condition Alarm

2 Applications

• Relays, Unipolar Stepper Motors

• Solenoids, Electromagnetic Drivers

• General Low-side Switch Applications

• LED driver with dimmer functionality (DRV8860A)

3 Description

The DRV8860 provides an 8-channel low side driver with overcurrent protection and open/shorted load detection. It has built-in diodes to clamp turn-off transients generated by inductive loads, and can be used to drive unipolar stepper motors, DC motors, relays, solenoids, or other loads.

The PWP package can supply up to 330 mA × 8 channel and The PW package can supply up to 200 mA × 8 channel continuous output current. A single channel can deliver up to 560 mA continuous output current.

A serial interface is provided to control the DRV8860 output drivers, configure internal setting register and read the fault status of each channel. DRV8860 devices can be daisy-chained together to use a single serial interface. Energizing-time and holding-PWM-

Duty cycles are configurable through serial interface as well. These functions allow for cooler running than always-on solutions.

Internal shutdown functions are provided for overcurrent protection, short-circuit protection, undervoltage lockout, and overtemperature.

DRV8860A does not include open load detection.

Fault information for each channel can be read out through serial interface and indicated by an external fault pin.

PART NUMBER

Device Information

(1)

PACKAGE BODY SIZE (NOM)

DRV8860

DRV8860A

TSSOP (16)

HTSSOP (16)

TSSOP (16)

5.00 mm × 6.40 mm

5.00 mm × 4.40 mm

5.00 mm × 6.40 mm

(1) For all available packages, see the orderable addendum at the end of the datasheet.

4 Simplified Schematic

8 to 38 V

ENABLE

LATCH

CLK

DIN

DOUT nFAULT

DRV8860

8 Channel Serial

Interface

Low-Side Driver

VM

600

500

400

300

200

100

0

0

N = 1

N = 2

N = 4

N = 8

N: Number of outputs active

12.5

25.0

37.5

50.0

Duty Cycle (%)

62.5

75.0

87.5

100.0

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015 www.ti.com

1 Features ..................................................................

1

2 Applications ...........................................................

1

3 Description .............................................................

1

4 Simplified Schematic.............................................

1

5 Revision History.....................................................

2

6 Pin Configuration and Functions .........................

4

7 Specifications.........................................................

5

7.1

Absolute Maximum Ratings ......................................

5

7.2

Handling Ratings ......................................................

5

7.3

Recommended Operating Conditions .......................

5

7.4

Thermal Information .................................................

5

7.5

Electrical Characteristics...........................................

6

7.6

Timing Requirements ................................................

6

7.7

Typical Characteristics ..............................................

8

8 Detailed Description ..............................................

8

8.1

Overview ...................................................................

8

8.2

Functional Block Diagram .........................................

9

8.3

Feature Description.................................................

10

Table of Contents

8.4

Device Functional Modes........................................

14

8.5

Programming...........................................................

16

8.6

Register Maps .........................................................

27

9 Application and Implementation ........................

28

9.1

Application Information............................................

28

9.2

Typical Application .................................................

28

10 Power Supply Recommendations .....................

30

10.1

Power Supply and Logic Sequencing ...................

30

11 Layout...................................................................

31

11.1

Layout Guidelines .................................................

31

11.2

Layout Example ....................................................

31

11.3

Thermal Consideration..........................................

32

12 Device and Documentation Support .................

33

12.1

Community Resources..........................................

33

12.2

Trademarks ...........................................................

33

12.3

Electrostatic Discharge Caution ............................

33

12.4

Glossary ................................................................

33

13 Mechanical, Packaging, and Orderable

Information ...........................................................

33

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (October 2015) to Revision E Page

• Added timing diagrams

Figure 1 , Figure 2

and

Table 2

,

Table 3

...........................................................................................

7

Changes from Revision C (October 2014) to Revision D Page

• Added I

(VM)

MAX = 4.5 V.........................................................................................................................................................

6

• Added I

OFF for DRV8860A .....................................................................................................................................................

6

• Changed t

OCP

From: MIN = 2.7 To: 2.0

μs .............................................................................................................................

6

• Updated Functional Block Diagram ........................................................................................................................................

9

Changes from Revision B (July 2014) to Revision C Page

• Added DRV8860A part to datasheet. ....................................................................................................................................

1

• Added caption to

Figure 9

...................................................................................................................................................

14

• Added caption to

Figure 10

.................................................................................................................................................

14

• Moved the Serial Control Interface information into the

Programming

section of the datasheet ........................................

16

• Moved the Register Maps information into the

Detailed Description

section of the datasheet ...........................................

27

• Changed

Figure 37

from a black background to a white background .................................................................................

29

• Added caption to

Figure 39

.................................................................................................................................................

31

• Changed title From: Thermal Information To:

Thermal Consideration

................................................................................

32

2 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: DRV8860 DRV8860A

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DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

Changes from Revision A (November 2013) to Revision B Page

• Added Feature: Serial Interface..............................................................................................................................................

1

• Changed the Features list for: Continuous Current Driving Capability...................................................................................

1

• Deleted Features: Programmable Current Profile ..................................................................................................................

1

• Updated the Application List ..................................................................................................................................................

1

• Changed Description sentence From: These functions allow for lower temperature operation rather than traditional always-on solutions. To: These functions allow for cooler running than traditional always-on solutions...............................

1

• Added the Handling Ratings table ..........................................................................................................................................

5

• Changed the MIN value for VM in the Recommended Operating Conditions table From: 8.2 V To: 8 V ..............................

5

• Added HTTSSOP (PWP) to the Thermal Information table ...................................................................................................

5

• Changed V

IL

From: MIN = - To: 0 V, TYP = 0.6 V To: - ........................................................................................................

6

• Changed V

IH

From: MIN = 2 V To: 1.5 V, MAX = - To: 5.3 V ...............................................................................................

6

• Changed V

HYS

From: MIN = - To: 100 mV, TYP = 0.45 V To: - ............................................................................................

6

• Added the Timing Requirements table ...................................................................................................................................

6

• Added the Overview section ..................................................................................................................................................

8

• Changed the description of the Recommended Output Current section..............................................................................

10

• Deleted the Example Output Configuration section. ............................................................................................................

12

• Changed the Serial Control Interface description text .........................................................................................................

16

Changes from Original (September 2013) to Revision A Page

• Added Features: Programmable Current Profile ....................................................................................................................

1

• Changed the MIN value for VM in the Recommended Operating Conditions table From: 8 V To: 8.2 V ..............................

5

• Added the Example Output Configuration section. ..............................................................................................................

12

Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: DRV8860 DRV8860A

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DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

6 Pin Configuration and Functions

PW (TSSOP) PACKAGE

(TOP VIEW)

VM

DIN

CLK

LATCH

GND

DOUT nFAULT

ENABLE

7

8

5

6

1

2

3

4

16

15

14

13

12

11

10

9

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8 www.ti.com

PWP (HTSSOP) PACKAGE

(TOP VIEW)

VM

DIN

CLK

LATCH

GND

DOUT nFAULT

ENABLE

7

8

5

6

1

2

3

4

16

15

14

13

12

11

10

9

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

Pin Functions

NAME PIN

I/O

(1)

DESCRIPTION

— Device ground

EXTERNAL COMPONENTS OR CONNECTIONS

GND

VM

ENABLE

LATCH

CLK

DIN

DOUT nFAULT

5

1

8

4

3

2

6

7

I

I

I

Output stage enable control input

I Serial latch signal

O

OD

Motor power supply

Serial clock input

Serial data input

Serial data output

Fault

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

OUT7

OUT8

16

15

14

13

12

11

10

9

O

O

O

O

O

O

O

O

Low-side output 1

Low-side output 2

Low-side output 3

Low-side output 4

Low-side output 5

Low-side output 6

Low-side output 7

Low-side output 8

(1) Directions: I = input, O = output, OD = open-drain output

All pins must be connected to ground

Connect to motor supply voltage. Bypass to GND with a 0.1

μF ceramic capacitor plus a 10 μF electrolytic capacitor.

Logic high to enable outputs, logic low to disable outputs. Internal logic and registers can be read and written to when ENABLE is logic low. Internal pulldown.

Refer to serial communication waveforms. Internal pulldown.

Rising edge clocks data into part for write operations. Falling edge clocks data out of part for read operations. Internal pulldown.

Serial data input from controller. Internal pulldown.

Serial data output to controller. Open-drain output with internal pullup.

Logic low when in fault condition. Open-drain output requires external pullup.

Faults: OCP, OTS, UVLO, OL (DRV8860 only)

NFET output driver. Connect external load between this pin and VM

NFET output driver. Connect external load between this pin and VM

NFET output driver. Connect external load between this pin and VM

NFET output driver. Connect external load between this pin and VM

NFET output driver. Connect external load between this pin and VM

NFET output driver. Connect external load between this pin and VM

NFET output driver. Connect external load between this pin and VM

NFET output driver. Connect external load between this pin and VM

COMPONENT

C

(VM1)

R

(nFAULT)

PIN 1

VM

V3P3

(1)

Table 1. External Components

PIN 2

GND nFAULT

RECOMMENDED

0.1 µF ceramic capacitor rated for VM

10 µF electrolytic capacitor rated for VM

> 4.7 k Ω

(1) V3P3 is not a pin on the DRV8860, but a V3P3 supply voltage pullup is required for open-drain output nFAULT.

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7 Specifications

DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1) (2) (3)

Power supply voltage range

Digital input pin current range

Digital output pin voltage range

Digital output pin current

Output voltage range

VM

ENABLE, LATCH, CLK, DIN

DOUT, nFAULT

DOUT, nFAULT

OUTx

Output current range OUTx

Operating virtual junction temperature range, T

J

MIN

–0.3

0

–0.5

–0.5

–0.3

MAX

40

20

7

7

40

Internally limited

–40 150

UNIT

V mA

V

V

V

A

°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(3) Power dissipation and thermal limits must be observed

7.2 Handling Ratings

T

V stg

(ESD)

Storage temperature range

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

(1)

Electrostatic discharge

Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins

(2)

MIN

–60

–2

–500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

MAX

150

2

500

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

VM

I

OUT

T

A

Motor power supply voltage range

Low-side driver current capability

Operating ambient temperature range

MIN

8

–40

UNIT

°C kV

V

NOM MAX UNIT

38 V

560 mA

85 °C

7.4 Thermal Information

(1) over operating free-air temperature range (unless otherwise noted)

Θ

JA

R

θJC(TOP)

R

θJB

Ψ

JT

Ψ

JB

R

θJC(BOTTOM)

THERMAL METRIC

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

TSSOP

PW (16 PINS)

103

37.9

48

3

47.4

N/A

HTSSOP

PWP (16 PINS)

40.9

28.5

23.2

0.9

23.0

3.0

UNIT

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953 .

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

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DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

7.5 Electrical Characteristics

T

A

= 25°C, over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS

POWER SUPPLIES

I

I

(VM)

V

(UVLO)

VM operating supply current

VM undervoltage lockout voltage

VM = 24 V

VM rising

LOGIC-LEVEL INPUTS (DIN, CLK, LATCH, ENABLE)

I

I

V

IL

V

IH

V

HYS

IL

IH

Input low voltage

Input high voltage

Input hysteresis

Input low current

Input high current

V

IN

= 0

V

IN

= 3.3 V

R

PD

Input pulldown resistance nFAULT, DOUT OUTPUTS (OPEN-DRAIN OUTPUTS)

V

OL

I

OH

R

PU

Output low voltage

Output high leakage current

Input pullup resistance

LOW-SIDE FET DRIVERS

I

O

= 5 mA

V

O

= 3.3 V, nFAULT

DOUT only (Pull up to internal 5.7 V)

R ds(on)

OFF

FET on resistance

Off-state leakage current

VM = 24 V, I

O

= 150 mA, T

J

= 25°C

VM = 24 V, I

O

= 150 mA, T

J

= 85°C

VM = 24 V, T

J

= 25°C, DRV8860

VM = 24 V, T

J

= 25°C, DRV8860A

HIGH-SIDE FREE-WHEELING DIODES

V

F

Diode forward voltage

PROTECTION CIRCUITS

VM = 2 4V, I

O

= 150 mA, T

J

= 25°C f

I

OCP

I

OL

Overcurrent protection trip level

Open load detect pull-down current

Each channel separately monitored

Per channel, DRV8860 only

V

OL

T

TSD

Open load detect threshold voltage

Thermal shutdown temperature

T

HYS

Thermal shutdown hysteresis

PWM CHOPPING FREQUENCY

Per channel, DRV8860 only

Die temperature

Die temperature

PWM

PWM chopping frequency

Duty cycle is > 25%

Duty cycle is 25%

Duty cycle is 12.5%

7.6 Timing Requirements

t

F t

OCP t

OL

Fall time

Overcurrent protection deglitch time

Open load detect deglitch time

I

O

= 150 mA, VM = 24 V, resistive load

VM = 24 V

Each channel separately monitored www.ti.com

MIN

0

1.5

100

–20

–1

TYP MAX UNIT

3 4.5

mA

8.2

V

100

0.7

5.3

20

100

V

V mV

µA

µA k Ω

0.5

1

V

µA k Ω

0

-0.5

1.4

1.5

1.8

30

Ω

0.5

µA

V

150

45

22

11

0.9

620

30

1.2

160

35

50

25

12.5

180 mA

µA

V

°C

°C

55

28 kHz

14

MIN

50

2.0

14

TYP

3.0

17

MAX UNIT

300 ns

3.85

µs

20 µs

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t

SU(LATCH)

LATCH t

CLK

CLK X t

CLKH t

CLKL

DIN X MSB t

SU(DIN) t

HD(DIN)

LSB

DOUT

8

9

6

7

NO.

1

2

3

4

5

Z MSB t

D(DOUT)

Figure 1. Serial Interface

REF DES t

CLK t

CLKH t

CLKL t

SU(DIN) t

H(DIN) t

SU(LATCH) t

H(LATCH) t

OFF(LATCH) t

D(DOUT) t f(LATCH) t r(LATCH)

Table 2. Serial Timing

CLK cycle time

DESCRIPTION

CLK high time

CLK low time

Setup time, DIN to CLK

Hold time, DIN to CLK

Setup time, LATCH to CLK

Hold time, LATCH to CLK

Inactive time between writes and read

Delay time, CLK to DOUT

1

1

2

MIN

5

2.5

2.5

1

1 t

H(LATCH)

LATCH

DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015 t

HD(LATCH)

TYP

LSB

MAX

1.5

X

X

Z

µs

µs

µs

µs

UNIT

µs

µs

µs

µs

µs

CLK

X

NO.

10

11

12

Part 1 Part 2 Part 3

Figure 2. Special Commands

REF DES t f(LATCH) t r(LATCH) t

H(LATCH)

Table 3. Special Commands

DESCRIPTION

LATCH fall to CLK rise

CLK fall to LATCH rise

LATCH high time

MIN

1

1

2

TYP

Part 4

MAX UNIT

µs

µs

µs

X

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DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

7.7 Typical Characteristics

1.90

1.85

1.80

1.75

1.70

1.65

1.60

1.55

1.50

0 10 20 30

VM Voltage (V)

40

Figure 3. Output ON Resistance

50

C004 www.ti.com

3.40

3.35

3.30

3.25

3.20

0 10 20 30

VM Voltage (V)

40

Figure 4. VM Operating Supply Current

50

C004

8 Detailed Description

8.1 Overview

The DRV8860 is an integrated 8-channel low side driver with overcurrent protection and open/short detection. It has built-in diodes to clamp turn-off transients generated by inductive loads, and can be used to drive unipolar stepper motors, DC motors, relays, solenoids, or other loads.

DRV8860 can supply up to 200 mA x 8 channel continuous output current. The current driving capability increases with lower PWM duty cycle. A single channel can deliver up to 560 mA continuous output current.

Refer to the current capability table for details.

A serial interface is provided to control the DRV8860 output drivers, configure internal register settings, and read the fault status of each channel. Multiple DRV8860 devices can be daisy-chained together to use a single serial interface. Energizing-time and holding-PWM-duty cycle are configurable through the serial interface as well.

These functions allow for cooler running than traditional always-on solutions.

Internal shutdown functions are provided for overcurrent protection, short-circuit protection, under voltage lockout and over temperature. DRV8860 can diagnosis an open load condition. DRV8860A does not include open load detection. Fault information for each channel can be read out through serial interface and is indicated by an external fault pin.

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8.2 Functional Block Diagram

10 µF

VM

0.1 µF

VM

ENABLE

LATCH

CLK

DIN

DOUT nFAULT

Power

Gate Drive

Logic LDO

Serial

Interface

Protection

Overcurrent

Undervoltage

Thermal

Open Load

Output

Core Logic

VM

Gate Drive,

OCP,

Open Load

Gate Drive,

OCP,

Open Load

VM

VM

Gate Drive,

OCP,

Open Load

VM

Gate Drive,

OCP,

Open Load

VM

Gate Drive,

OCP,

Open Load

VM

Gate Drive,

OCP,

Open Load

VM

Gate Drive,

OCP,

Open Load

VM

Gate Drive,

OCP,

Open Load

GND PPAD (PWP package only)

DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

OUT1

OUT1

OUT1

OUT1

OUT1

OUT1

OUT1

OUT1

VM

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DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

8.3 Feature Description

www.ti.com

8.3.1 Recommended Output Current

DRV8860 current capability will depend on several system application parameters such as system ambient temperature, maximum case temperature, and overall output duty cycle. The PWP package provides a better heatsinking capability through the PowerPAD™; and therefore, is cable of driving higher output current or operating at a slightly lower temperature than the device in PW package.

OUTPUT CURRENT RECOMMENDATION (PW PACKAGE) T

A

= 25°C

CONFIGURATION

1x output on (100% duty cycle)

OUTPUT CURRENT CAPACITY

566 mA

2x outputs on (100% duty cycle)

4x outputs on (100% duty cycle)

8x outputs on (100% duty cycle)

400 mA per output

283 mA per output

200 mA per output

600

N = 1

500

400

N = 2

300

200

N = 4

N = 8

100

N: Number of outputs active

0

0 12.5

25.0

37.5

50.0

62.5

75.0

87.5

100.0

Duty Cycle (%)

Figure 5. Output Current Capacity vs Duty Cycle for PW Package

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DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

Figure 6. Maximum Current Capacity vs Duty Cycle when Paralleling Outputs for DRV8860PW

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8.3.2 Daisy Chain Connection

Two or more DRV8860 devices may be connected together to use a single serial interface. The SDATOUT pin of the first device in the chain is connected to the SDATIN pin of the next device. The SCLK, LATCH, RESET, and nFAULT pins are connected together.

Timing diagrams are shown in

Figure 7

and

Figure 8

for the configuration of single devices, as well as two devices in daisy-chain connection.

8 ~38 V

GPIO

GPIO

GPIO

GPIO

LATCH

CLK

DIN

DOUT

OUT1

Host Processor DRV8860

GPIO nFAULT

OUT8

Figure 7. Single Device Connection

8 ~38 V

Host Processor

GPIO

GPIO

GPIO

GPIO

LATCH

CLK

DIN 1

DOUT 1

DRV8860

Device #1

OUT1

OUT8

LATCH

CLK

DIN 2

DOUT 2

DRV8860

Device #2

OUT1

OUT8

Figure 8. Daisy-Chain Connection

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DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

8.3.3 Protection Circuits

The DRV8860 is fully protected against undervoltage, overcurrent and overtemperature events.

8.3.3.1 Overcurrent Protection (OCP)

When output current exceeds OCP trigger level, corresponding channel will be automatically turned off. nFault pin will be set low and corresponding OCP flag in fault register will be set to 1.

Over current faults are automatically cleared whenever the corresponding output is turned off by setting the Data register bit to ‘0’. Alternatively, a Fault Reset special command will also clear this value. In either case, once all bits in the Fault register are clear, nFAULT is released.

8.3.3.2 Open Load Detection (OL) - DRV8860 only

When any output is in off status (the corresponding Data Register bit is set to ‘0’), a current sink pulls the node down with approximately 30 µA. If the voltage on the pin is sensed to be less than 1.2 V, then an open load condition is reported. nFAULT is driven low and the OL bit of the fault register (F8:F1) corresponding to the specific channel is set.

Open load faults are automatically cleared whenever the corresponding output is turned on by setting the Data register bit to ‘1’. Alternatively, a Fault Reset special command will also clear this value. In either case, once all bits in the Fault register are clear, nFAULT is released.

8.3.3.3 Thermal Shutdown (TSD)

If the die temperature exceeds safe limits, all outputs will be disabled, and the nFAULT pin will be driven low.

Once the die temperature has fallen to a safe level, operation will automatically resume. The nFAULT pin will be released after operation has resumed.

8.3.3.4 Undervoltage Lockout (UVLO)

If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the device will be disabled and internal logic will be reset. Operation will resume when VM rises above the UVLO threshold. nFAULT will not be asserted in this condition.

8.3.3.5 Digital Noise Filter

The DRV8860 features an internal noise filter on all digital inputs. In a noisy system, noise may disturb the serial daisy-chain interface. Without an input filter, this noise may result in an unexpected behavior or output state. The digital input filter is capable of removing unwanted noise frequencies while allowing fast communication over the serial interface.

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8.4 Device Functional Modes

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8.4.1 Internal Registers

The DRV8860 is controlled with a simple serial interface. There are three register banks that are used during operation: the Data register, the Control register, and the Fault register.

Register data movement flow and direction will be affected by special command.

Figure 9. Register Data Movement

In default condition, 8 Bit shift register data moves into output control register DATA-REG.

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Device Functional Modes (continued)

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Figure 10. 8 Bit Shift Register Data Movement

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8.5 Programming

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8.5.1 Serial Control Interface

DRV8860 is using a daisy chain serial interface. Data is latched into the register on the rising edge of the LATCH pin. Data is clocked in on the rising edge of CLK when writing, and data is clocked out on the falling edge of CLK when reading.

8.5.1.1 Data Writing Waveform

LATCH xxxx CLK xxxx xxxx

1 2 3 4 5 6 7 8 xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx xxxxx

A_D8 A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

Data Register Old Data Register Contents xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

Figure 11. Writing Data Register – Single Device

Data A

LATCH xxxx xx

CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 xx

DIN 1 A_D8 A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 B_D8 B_D7 B_D6 B_D5 B_D4 B_D3 B_D2 B_D1 xxxx xxx xxxx

DOUT 1 / DIN 2 A_D8 xxxxxxxxxxxx

A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 xxxx

Data Register 1 Old Data Register Contents ± Device #1 xxxxxxxxxxxxxxxxxxxxx

Data B

Data A Data Register 2 Old Data Register Contents ± Device #2 xxxxxxxxxxxxxxxxxxxxx

Figure 12. Writing Data Register – Daisy Chan xxxxxxxxxxxxxxxxxxxxx

Figure 13. Writing Data Register – Data Flow

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Programming (continued)

8.5.1.2 Fault Register Reading Waveform

LATCH

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CLK 1 xx

DOUT xxxx

Fault Register

F16

2

F15

3

F14

4

F13

5

F12

6

F11

7

F10

8

F9

9

F8

10

Fault Register Contents A

F7

11

F6

12

F5

13

F4

14

F3

15

F2

16

F1 xx

Figure 14. Reading Fault Register – Single Device

LATCH x CLK 1 2 3 4 5 6 7 8

DOUT 1 / DIN 2 F16 xxxx

DOUT 2 F16 xxxx

Fault Register #1

F15 F14

F15 F14

F13 F12

F13 F12

F11 F10

F11 F10

F9

F9

9 10

F8 F7

F8 F7

11

F6

F6

12

F5

F5

13 14

F4 F3

F4 F3

15

F2

F2

16 17 18 19 20 21 22

F1 xxxxxxxxx

F1 xxxxxxxxx

F16 F15 F14 F13 F12 F11

Control Register Contents A

Fault Register #2 Control Register Contents B

Figure 15. Reading Fault Register – Daisy Chain

Figure 16. Reading Fault Register – Data Flow

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Programming (continued)

8.5.1.3 Special Command

Besides output ON/OFF control and fault status reading back, DRV8860 has special functions to make system more robust or power efficient. These functions will need special command to initiate the device or configure the internal registers.

There are 5 Special Commands:

1. Write Control Register command

2. Read Control Register command

3. Read Data Register command

4. Fault Register Reset command

5. PWM Start command

Special wave form pattern on CLK and LATCH pin will issue the special command, as below

LATCH xxx

CLK xxx xxx xxx

1

Part 1

SPECIAL COMMAND

Write Control Register

Read Control Register

Read Data Register

Fault Register Reset

PWM Start

1 2 3 4 5 6 1 2 3 4 5 6

Part 2 Part 3

Figure 17. Special Command

Part 1

1

1

1

1

1

CLK CYCLES IN EACH PART

Part 2 Part 3

2

4

2

2

4

2

6

4

4

6

1 2 3

Part 4

Part 4

3

3

3

3

3

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8.5.1.3.1

Special command: Write Control Register

When Write-Control-Register command is issued, the following serial data will be latched into timing and duty control register.

LATCH

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SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

CLK x

1 1 2 1 2 1 2 3 1 2 3 4 5 6 7 8 xxxx

DIN x xxxx

A_C8 A_C7 A_C6 A_C5 A_C4 A_C3 A_C2 A_C1 xxxxxxxxx

Control Register xxxxxxxxxxxxxxxxxx

Figure 18. Writing Control Register – Single Device xxxx

Control A

LATCH xxx xx

CLK 1 1 2 1 2 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 xxx xx

DIN 1 A_C8 A_C7 A_C6 A_C5 A_C4 A_C3 A_C2 A_C1 B_C8 B_C7 B_C6 B_C5 B_C4 B_C3 B_C2 B_C1 xxxxxxxxx xxxx

DOUT 1 / DIN 2 A_C8 A_C7 A_C6 A_C5 A_C4 A_C3 A_C2 A_C1 xxxx xxxxxxxxxxxxxxxxxx

Control Register 1 Old Control Register Contents ± Device #1 Control B xxxxxxxxxxxxxxxxxxxxxxxxxxxx

Control Register 2 Old Control Register Contents ± Device #2 Control A xxxxxxxxxxxxxxxxxxxxxxxxxxxx

Figure 20. Writing Control Register – Data Flow

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8.5.1.3.2

Special command: Read Control Register

When Read-Control-Register command is issued, control register content will be copied to internal shift register and following CLK will shift this content out from DOUT pin. This provides a mechanism for system to verify the control register is correctly programmed.

LATCH

Figure 21. Read Control Register – Single Device

LATCH xx

CLK 1 1 2 3 4 1 2 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 xx

DOUT 1 / DIN 2 A_C8 A_C7 A_C6 A_C5 A_C4 A_C3 A_C2 A_C1 xxxxxxxxxx

DOUT 2 B_D8 xxxxxxxxxx

B_D7 B_D6 B_D5 B_D4 B_D3 B_D2 B_D1 xxxxxxxxxxxx

A_D8 A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 xxx

Control Register #1 Control Register Contents A

Control Register #2 Control Register Contents B

Figure 22. Read Control Register – Daisy Chain

Figure 23. Read Control Register – Data Flow

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8.5.1.3.3

Special command: Read Data Register

When Read-Data-Register command is issued, internal output data register content will be copied to internal shift register and following CLK will shift this content out from DOUT pin. This provides a mechanism for system to verify the output data is correctly programmed. It makes system more robust in noisy system.

LATCH

CLK 1 1 2 3 4 1 2 3 4 1 2 3 1 2 3 4 5 6 7 8 xx xxxx

DOUT A_D8 A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 xxxxx xxxxxxxxxxx

Data Register Data Register Contents A

Figure 24. Reading Data Register – Single Device

LATCH

CLK x

1 1 2 3 4 1 2 3 4 1 2 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DOUT 1 / DIN 2 x xxxxxxxxxx

A_D8 A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 xxxxxxxxxxxx

DOUT 2 xxxxxxxxxx

B_D8 B_D7 B_D6 B_D5 B_D4 B_D3 B_D2 B_D1 A_D8 A_D7 A_D6 A_D5 A_D4 A_D3 A_D2 A_D1 xxx

Data Register 1 Data Register Contents A

Data Register 2 Data Register Contents B

Figure 25. Reading Data Register – Daisy Chain

Figure 26. Reading Data Register – Data Flow

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8.5.1.3.4

Special command: Fault Register Reset

When Fault-Register-Reset command is issued, internal 16bit fault register will be cleared. System can use this method to clear out all fault condition in every chained device at once.

LATCH xxx

CLK xxx xxx

1

Fault Register

1 2 1 2 3 4

Fault Register Contents

1 2 3 xxxxxxxxxxx xxxxxxxxxxx xxxxxxxxxxx nFAULT Fault Condition

Figure 27. Fault Register Reset

No Fault Condition

8.5.1.3.5

Special command: PWM Start

When Fault-Register-Reset command is issued, output channel will ignore energizing time and directly enter into

PWM mode following the setting in control register.

LATCH xxx

1

OUTx

1 2 3 4 5 6 1 2 3 4 5 6 1 2 3

Max-On Time

Figure 28. PWM Start Command xxxxxxxxxxxxx xxxxxxxxxxxxx

PWM Chopping

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1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

C8

0

1

1 www.ti.com

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8.5.1.4 Output Energizing and PWM Control

The device output is defined by two stages: Energizing Phase and PWM Phase.

During the Energizing phase, the channel is turned on with 100% duty cycle for a duration set by Control register bits C4:C1.

In PWM chopping phase, with the PWM Duty Cycle defined by Control register bits C7:C5.

The behavior of each bit in the Control Register is described in

Table 4 .

X

X

X

X

0

X

X

X

X

X

1

1

1

1

0

0

0

X

X

X

X

X

C7

X

X

X

1

1

1

1

X

0

1

1

1

1

X

X

X

X

X

X

X

0

0

0

0

0

C4

X

0

0

X

X

X

X

0

X

X

X

X

X

1

1

0

0

0

1

1

X

X

X

X

X

C6

X

X

X

X

X

X

X

0

X

X

X

X

X

0

1

0

1

1

0

1

X

X

X

X

X

C5

X

X

X

0

0

1

1

X

1

0

0

1

1

X

X

X

X

X

X

X

1

1

0

0

1

C2

X

0

0

0

1

0

1

X

1

0

1

0

1

X

X

X

X

X

X

X

0

1

0

1

0

C1

X

0

1

Table 4. Control Register Settings

1

1

1

1

X

1

0

0

0

0

X

X

X

X

X

X

X

0

0

1

1

1

C3

X

0

0

50 ms

80 ms

110 ms

140 ms

170 ms

200 ms

230 ms

260 ms

300 ms

0%

Value

N/A

0 ms

3 ms

5 ms

10 ms

15 ms

20 ms

30 ms

DESCRIPTION

Outputs always in Energizing mode

No Energizing, starts in PWM chopping

Sets the Energizing Time (100% duty cycle) before

12.50% 12.5 kHz

25.00% 25 kHz

37.50%

50.00%

62.50% 50 kHz

75.00%

87.50% switching to PWM Phase

Output is off after Energizing Phase

Sets PWM chopping duty cycle. DC is the duty cycle that the low-side FET is on.

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There are five operation cases as described in

Figure 29

through

Figure 33 .

The output is turned on with 100% duty cycle.

OUTx Voltage (V)

VM www.ti.com

Time (ms)

OUTx Current (mA)

VM/R

L

Time (ms)

Max-On time

Figure 29. Case 1: Timer Enable Bit (C8) is 0 (Default Value)

The output is turned on in PWM chopping mode with duty cycle defined by Control register bits C7:C5.

OUTx Voltage (V)

VM

Time (ms)

OUTx Current (mA)

DC*VM/R

L

Time (ms)

PWM Chopping

Figure 30. Case 2: Timer Enable Bit (C8) is 1 and Energizing Timing Bits (C4:C1) are 0000

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The output is turned on in Energizing mode with 100% duty cycle for a duration set by Control register bits

C4:C1. After the timer expires, the output switches to PWM chopping mode with PWM Duty Cycle defined by

Control register bits C7:C5.

OUTx Voltage (V)

VM

Time (ms)

OUTx Current (mA)

VM/R

L

DC*VM/R

L

Time (ms)

Figure 31. Case 3: Timer Enable Bit (C8) is 1, Energizing Timing Bits (C4:C1) are NOT 0000, and PWM

Duty Bits (C7:C5) are NOT 000

The output is turned on in Energizing mode with 100% duty cycle for a duration set by Control register bits

C4:C1. After the timer expires, the output is turned off.

OUTx Voltage (V)

VM

Max-On time PWM Chopping

Time (ms)

OUTx Current (mA)

VM/R

L

Time (ms)

Max-On time

Figure 32. Case 4: Timer Enable Bit (C8) is 1, Energizing Timing Bits (C4:C1) are NOT 0000, and PWM

Duty Bits (C7:C5) are 00

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8.5.1.4.1

PWM Start Special Command Used

The output is turned on in Energizing mode with 100% duty cycle, and a timer is enabled with duration set by

Control register bits C4:C1. If the PWM Start special command is received before the timer expires, then the output switches to PWM chopping mode with PWM Duty Cycle defined by Control register bits C7:C5. If the timer expires and no PWM Start is received, then the device will stay in Energizing mode regardless of other PWM

Start commands.

OUTx Voltage (V)

VM

Time (ms)

OUTx Current (mA)

VM/R

L

DC*VM/R

L

Time (ms)

Max-On time

PWM Chopping

PWM Start

Figure 33. Case 5: Timer Enable Bit (C8) is 0, Energizing Timing Bits (C4:C1) are NOT 0000, and PWM

Duty Bits (C7:C5) are NOT 000

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8.6 Register Maps

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8.6.1 Data Register

The Data register is used to control the status of each of the eight outputs:

Figure 34. Data Register

D8

OUT8

R/W

D7

OUT7

R/W

D6

OUT6

R/W

D5

OUT5

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

D4

OUT4

R/W

D3

OUT3

R/W

D2

OUT2

R/W

D1

OUT1

R/W

When any bit is ‘1’, the corresponding output will be active. When any bit is ‘0’, the output will be inactive.

The data register is the default write location for the serial interface. In order to read back data from this register, the Data Register Readout special command is used.

8.6.2 Fault Register

The Fault register can be read to determine if any channel exist fault condition. OCP is an overcurrent fault and

OLD is an open load fault. OLD is not included on the DRV8860A

Figure 35. Fault Register

F16

OUT8 OCP

R/W

F8

OUT8 OL

R/W

F15

OUT7 OCP

R/W

F7

OUT7 OL

R/W

F14

OUT6 OCP

R/W

F6

OUT6 OL

R/W

F13

OUT5 OCP

R/W

F5

OUT5 OL

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

F12

OUT4 OCP

R/W

F4

OUT4 OL

R/W

F11

OUT3 OCP

R/W

F3

OUT3 OL

R/W

F10

OUT2 OCP

R/W

F2

OUT2 OL

R/W

F9

OUT1 OCP

R/W

F1

OUT1 OL

R/W

When any fault occurs, nFAULT pin will be driven low and corresponding Fault register bit will be set up as ‘1’.

OCP is a flag indicating overcurrent fault. ODP is a flag indicating open load fault.

Fault bits can be reset by two approaches:

1. Special command ‘FAULT RESET’ clear all fault bits.

2. Setting Data register to ON will clear corresponding OLD bits (DRV8860 only)

Setting Data register to OFF will clear corresponding OCP bits.

8.6.3 Control Register

The Control register is used to adjust the Energizing Time and PWM Duty Cycle of outputs:

Figure 36. Control Register

C8

Over All Enable

R/W

C7 C6

PWM Duty Cycle control

R/W

C5

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

C4 C3 C2

Energizing Time control

R/W

C1

Special command ‘WRITE CONTROL REGISTER’ is used to program control register.

Special command ‘READ CONTROL REGISTER’ is used to read back control register content.

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9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

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9.1 Application Information

The DRV8860 is an eight channel low side driver with protection features. The following design is a common application of the DRV8860.

9.2 Typical Application

VM DRV8860PWP

VM

VM OUT1

10uF

0.1uF

DIN OUT2

CLK OUT3

OUT4 LATCH

GND

V3P3

OUT5

OUT6

4.7k

Ÿ

DOUT nFAULT

ENABLE

OUT7

OUT8

9.2.1 Design Requirements

Parameter

Input voltage range

Current

Table 5. Design Parameters

Value

8 V – 38 V

330 mA per channel

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9.2.2 Detailed Design Procedure

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9.2.2.1 Drive Current

The current path is from VM, through the load, into the low-side sinking driver. Power dissipation I 2 R losses in one sink are calculated using

Equation 1

.

P

D

= I

2 x R

DS(on)

(1)

9.2.3 Application Curves

Figure 37. PWM Operation

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10 Power Supply Recommendations

The DRV8860 is designed to operate from an input voltage supply (VM) range between 8 and 38 V. A 0.1-µF ceramic capacitor rated for VM must be placed as close as possible to the VM pin. In addition to the local decoupling cap, additional bulk capacitance is required and must be sized accordingly to the application requirements.

Bulk capacitance sizing is an important factor in motor drive system design. It is dependent on a variety of factors including:

• Type of power supply

• Acceptable supply voltage ripple

• Parasitic inductance in the power supply wiring

• Type of load

• Load startup current

The inductance between the power supply and motor drive system will limit the rate current can change from the power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or dumps from the motor with a change in voltage. The user should size the bulk capacitance to meet acceptable voltage ripple levels.

The datasheet generally provides a recommended value but system level testing is required to determine the appropriate sized bulk capacitor.

Parasitic Wire

Inductance

Power Supply Motor Drive System

VM

+

±

+ Motor

Driver

GND

Local

Bulk Capacitor

IC Bypass

Capacitor

Figure 38. Example Setup of Motor Drive System with External Power Supply

10.1 Power Supply and Logic Sequencing

There is no specific sequence for powering-up the DRV8860. It is okay for digital input signals to be present before VM is applied. After VM is applied to the DRV8860, it begins operation based on the status of the control pins.

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11 Layout

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11.1 Layout Guidelines

• The VM pin should be bypassed to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.1μF rated for VM.

• This capacitor should be placed as close as possible to the VM pin on the device with a thick trace or ground plane connection to the device GND pin.

• The VM pin must be bypassed to ground using and appropriate bulk capacitor. This component must be located close to the DRV8860.

11.2 Layout Example

Where the pull-up voltage (V3P3) is an external supply in the range of the recommended operating conditions for the digital open-drain outputs.

10 µF

0.1 µF

V3P3

VM

DIN

CLK

LATCH

GND

DOUT nFAULT

ENABLE

OUT5

OUT6

OUT7

OUT8

OUT1

OUT2

OUT3

OUT4

Figure 39. DRV8860 Layout

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11.3 Thermal Consideration

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The DRV8860 device has thermal shutdown (TSD) as described in the

Thermal Shutdown (TSD)

section. If the die temperature exceeds approximately 150°C, the device is disabled until the temperature drops to a safe level.

Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient heatsinking, or too high of an ambient temperature.

11.3.1 Power Dissipation

Power dissipation in the DRV8860 device is dominated by the power dissipated in the output FET resistance,

R

DS(on)

. Use the following equation to calculate the estimated average power dissipation of each output when running a driving a load.

P

D

= R

DS(on) x I

O

2 where:

• P

D is the power dissipation of one channel

• R

DS(on) is the resistance of each FET

• I

O is the RMS output current being applied to each channel (2)

I

O is equal to the average current into the channel. Note that at startup, this current is much higher than normal running current; these peak currents and their duration must be also be considered.

The total device dissipation is the power dissipated in each channel added together.

The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and heatsinking.

NOTE

R

DS(on) increases with temperature, so as the device heats, the power dissipation increases. This fact must be taken into consideration when sizing the heatsink.

11.3.2 Heatsinking

The PowerPAD package uses an exposed pad to remove heat from the device. For proper operation, this pad must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this connection can be accomplished by adding a number of vias to connect the thermal pad to the ground plane.

On PCBs without internal planes, a copper area can be added on either side of the PCB to dissipate heat. If the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom layers.

For details about how to design the PCB, refer to the TI application report, PowerPAD™ Thermally Enhanced

Package ( SLMA002 ), and the TI application brief, PowerPAD Made Easy™ ( SLMA004 ), available at www.ti.com

.

In general, the more copper area that can be provided, the more power can be dissipated.

32 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: DRV8860 DRV8860A

www.ti.com

12 Device and Documentation Support

DRV8860, DRV8860A

SLRS065E – SEPTEMBER 2013 – REVISED NOVEMBER 2015

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use .

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.2 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2013–2015, Texas Instruments Incorporated

Product Folder Links: DRV8860 DRV8860A

Submit Documentation Feedback 33

PACKAGE OPTION ADDENDUM

www.ti.com

16-Nov-2015

PACKAGING INFORMATION

Orderable Device

DRV8860APW

DRV8860APWR

Status

(1)

ACTIVE

ACTIVE

Package Type Package

Drawing

TSSOP

TSSOP

PW

PW

Pins Package

16

16

Qty

Eco Plan

(2)

90 Green (RoHS

& no Sb/Br)

2000 Green (RoHS

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU

CU NIPDAU

MSL Peak Temp

(3)

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Op Temp (°C)

-40 to 85

-40 to 85

8860A

Device Marking

(4/5)

8860A

DRV8860PW

DRV8860PWPR

ACTIVE

ACTIVE

TSSOP

HTSSOP

PW

PWP

16

16

90 Green (RoHS

& no Sb/Br)

2000 Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAU

Level-1-260C-UNLIM

Level-3-260C-168 HR

-40 to 85

-40 to 85

8860

8860PWP

DRV8860PWR ACTIVE TSSOP PW 16 2000 Green (RoHS

& no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

CU NIPDAU Level-1-260C-UNLIM

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

-40 to 85 8860

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

16-Nov-2015

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

16-Nov-2015

*All dimensions are nominal

Device

DRV8860APWR

DRV8860PWPR

DRV8860PWR

Package

Type

Package

Drawing

TSSOP

TSSOP

PW

HTSSOP PWP

PW

Pins

16

16

16

SPQ

2000

2000

2000

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

12.4

330.0

330.0

12.4

12.4

A0

(mm)

6.9

6.9

6.9

B0

(mm)

5.6

5.6

5.6

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

1.6

1.6

1.6

8.0

12.0

8.0

12.0

8.0

12.0

Q1

Q1

Q1

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

16-Nov-2015

*All dimensions are nominal

Device

DRV8860APWR

DRV8860PWPR

DRV8860PWR

Package Type Package Drawing Pins

TSSOP

HTSSOP

TSSOP

PW

PWP

PW

16

16

16

SPQ

2000

2000

2000

Length (mm) Width (mm) Height (mm)

367.0

367.0

367.0

367.0

367.0

367.0

35.0

35.0

35.0

Pack Materials-Page 2

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