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FEATURES
•
Programmable Auto-RTS and Auto-CTS
•
In Auto-CTS Mode, CTS Controls the
Transmitter
•
In Auto-RTS Mode, RCV FIFO Contents, and
Threshold Control RTS
•
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment is on the Same Power Drop
•
Capable of Running With All Existing
TL16C450 Software
•
After Reset, All Registers Are Identical to the
TL16C450 Register Set
•
Up to 24-MHz Clock Rate for up to 1.5-Mbaud
Operation With V
CC
= 5 V
•
Up to 20-MHz Clock Rate for up to
1.25-Mbaud Operation With V
CC
= 3.3 V
•
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation With V
CC
= 2.5 V
•
Up to 10-MHz Clock Rate for up to 625-kbaud
Operation With V
CC
= 1.8 V
•
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and Serial
Data
•
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1 to
(2
16
- 1) and Generates an Internal 16 × Clock
•
Standard Asynchronous Communication Bits
(Start, Stop, and Parity) Added to or Deleted
From the Serial Data Stream
•
5-V, 3.3-V, 2.5-V, and 1.8 V Operation
•
Independent Receiver Clock Input
•
Transmit, Receive, Line Status, and Data Set
Interrupts Independently Controlled
•
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation and Detection
– 1-, 1 ½-, or 2-Stop Bit Generation
– Baud Generation (dc to 1 Mbit/s)
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
1.8-V to 5-V DUAL UART WITH 16-BYTE FIFOS
•
False-Start Bit Detection
•
Complete Status Reporting Capabilities
•
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
•
Line Break Generation and Detection
•
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, and Framing Error
Simulation
•
Fully Prioritized Interrupt System Controls
•
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
•
Available in 44-Pin PLCC (FN) or 32-Pin QFN
(RHB) Packages
•
Each UART's Internal Register Set May Be
Written Concurrently to Save Setup Time
•
Multi-Function Output (MF) Allows Users to
Select Among Several Functions, Saving
Package Pins
APPLICATIONS
•
Point-of-Sale Terminals
•
Gaming Terminals
•
Portable Applications
•
Router Control
•
Cellular Data
•
Factory Automation
DESCRIPTION
The TL16C2552 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two TL16C550D UARTs, each UART having its own register set and FIFOs. The two
UARTs share only the data bus interface and clock source, otherwise they operate independently.
Another name for the UART function is
Asynchronous Communications Element (ACE), and these terms will be used interchangeably. The bulk of this document describes the behavior of each
ACE, with the understanding that two such devices are incorporated into the TL16C2552.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2005–2006, Texas Instruments Incorporated
2
TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
Each ACE is a speed and voltage range upgrade of the TL16C550C, which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and to be transmitted characters. Each receiver and transmitter store up to 16 bytes in their respective
FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode, a selectable autoflow control feature can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow using handshakes between the RTS output and CTS input, thus eliminating overruns in the receive FIFO.
Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and stores the parallel data in its receive buffer or
FIFO, and each ACE performs parallel-to-serial conversions on data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The
CPU can read the status of either ACE at any time.
Each ACE includes complete modem control capability and a processor interrupt system that can be tailored to the application.
Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of from 1 to 65535, thus producing a 16× internal reference clock for the transmitter and receiver logic. Each ACE accommodates up to a
1.5-Mbaud serial data rate (24-MHz input clock). As a reference point, that speed would generate a
667-ns bit time and a 6.7-µs character time (for 8,N,1 serial data), with the internal clock running at 24
MHz.
Each ACE has a TXRDY and RXRDY output that can be used to interface to a DMA controller.
D5
D6
D7
A0
XTAL1
GND
XTAL2
A1
A2
CHSEL
INTB
7
10
11
12
8
9
13
14
15
16
17
D6
D7
A0
XTAL1
XTAL2
A1
A2
CHSEL
5
6
7
8
3
4
1
2
FN PACKAGE
(TOP VIEW)
6 5 4 3 2 1 44 43 42 41 40
TL16C2552FN
18 19 20 21 22 23 24 25 26 27 28
RHB PACKAGE
(TOP VIEW)
TL16C2552RHB www.ti.com
34
33
32
31
30
29
39
38
37
36
35
RXA
TXA
DTRA
RTSA
MFA
INTA
V
CC
TXRDYB
RIB
CDB
DSRB
20
19
18
17
24
23
22
21
RXA
TXA
RTSA
INTA
GND
NC
NC
CTSB
NC − No internal connection
NOTE: The 32-pin RHB package does not provide access to DSRA,
DSRB, RIA, RIB, CDA, CDB inputs and MFA, MFB, DTRA, DTRB,
TXRDYA, TXRDYB outputs.
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TL16C2552
TL16C2552 Block Diagram
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
A2 − A0
D7 − D0
CS
CHSEL
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
MFA
MFB
RESET
Data Bus
Interface
BAUD
Rate
Gen
BAUD
Rate
Gen
UART Channel A
16 Byte Tx FIFO
UART Regs
16 Byte Rx FIFO
UART Channel B
16 Byte Tx FIFO
UART Regs
16 Byte Rx FIFO
Tx
Rx
Tx
Rx
TXA
CTSA
DTRA
DSRA, RIA, CDA
RTSA
RXA
TXB
CTSB
DTRB
DSRB, RIB, CDB
RTSB
RXB
XTAL1
XTAL2
Crystal
OSC
Buffer
V
CC
GND
A.
MF output allows selection of OP, BAUDOUT, or RXRDY per channel.
NAME
A0
A1
A2
CDA, CDB
TERMINAL
FN NO.
RHB NO.
10
14
15
3
6
7
42, 30 –
CHSEL
CS
CTSA,
CTSB
16
18
40, 28
8
10
25, 17
DEVICE INFORMATION
TERMINAL FUNCTIONS
I/O DESCRIPTION
I
I
I
I
I
I
I Address 0 select bit. Internal registers address selection
Address 1 select bit. Internal registers address selection
Address 2 select bit. Internal registers address selection
Carrier detect (active low). These inputs are associated with individual UART channels A and
B. A low on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR).
Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0.
A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A.
CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate function register (AFR) can temporarily override CHSEL function, allowing the user to write to both channel register simultaneously with one write cycle when CS is low. It is especially useful during the initialization routine.
UART chip select (active low). This pin selects channel A or B in accordance with the state of the CHSEL pin. This allows data to be transferred between the user CPU and the 2552.
Clear to send (active low). These inputs are associated with individual UART channels A and
B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit data from the 2552. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation.
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4
TL16C2552
DSRA,
DSRB
DTRA,
DTRB
GND
IOR
IOW
NC
41, 29
37, 27
12, 22
INTA, INTB 34, 17
24
20
–
–
–
20
21, 9
14
11
18, 19
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SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
NAME
D0-D4
D5-D7
TERMINAL
FN NO.
RHB NO.
2 - 6 27 - 31
7 - 9 32, 1, 2
I/O DESCRIPTION
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring
I/O information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream.
I
Data set ready (active low). These inputs are associated with individual UART channels A and B. A logic low on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART. The state of these inputs is reflected in the modem status register (MSR).
O
Data terminal ready (active low). These outputs are associated with individual UART channels
A and B. A logic low on these pins indicates that theTLl16C2552 is powered on and ready.
These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR output to low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a reset.
O
I
I
Signal and power ground.
Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B.
INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in the interrupt enable register (IER). Interrupt conditions include: receiver errors, available receiver buffer data, available transmit buffer space or when a modem status flag is detected.
INTA-B are in the high-impedance state after reset.
Read input (active low strobe). A high to low transition on IOR will load the contents of an internal register defined by address bits A0-A2 onto the TL16C2552 data bus (D0-D7) for access by an external CPU.
Write input (active low strobe). A low to high transition on IOW will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits
A0-A2 and CSA and CSB
No internal connection
MFA, MFB
RESET
RIA, RIB
RTSA,
RTSB
RXA, RXB
TXA, TXB
TXRDYA,
TXRDYB
V
CC
35, 19
21
43, 31
36, 23
39, 25
38, 26
1, 32
33, 44
–
12
–
22, 13
24, 15
23, 16
–
26
O
I
I
I
O
I
O
O
Multi-function output. This output pin can function as the OP, BAUDOUT, or RXRDY pin. One of these output signal functions can be selected by the user programmable bits 1-2 of the alternate function register (AFR). These signal functions are described as follows:
1.
OP - When OP (active low) is selected, the MF pin is a logic 0 when MCR bit 3 is set to a logic 1 (see MCR bit 3). MCR bit 3 defaults to a logic 1 condition after a reset or power-up.
2.
BAUDOUT - When BAUDOUT function is selected, the 16× baud rate clock output is available at this pin.
3.
RXRDY - RXRDY (active low) is intended for monitoring DMA data transfers.
If it is not used, leave it unconnected.
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. See TL16C2552 external reset conditions for initialization details. RESET is an active-high input.
Ring indicator (active low). These inputs are associated with individual UART channels A and
B. A logic low on these pins indicates the modem has received a ringing signal from the telephone line. A low to high transition on these input pins generates a modem status interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR)
Request to send (active low). These outputs are associated with individual UART channels A and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send.
Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is available. After a reset, these pins are set to high. These pins only affects the transmit and receive operation when auto RTS function is enabled through the enhanced feature register
(EFR) bit 6, for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to the
2552. During the local loopback mode, these RX input pins are disabled and TX data is internally connected to the UART RX input internally.
Transmit data. These outputs are associated with individual serial transmit channel data from the 2552. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input.
Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level numbers of spaces available. They go high when the TX buffer is full.
Power supply inputs.
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NAME
XTAL1
XTAL2
TERMINAL
FN NO.
RHB NO.
11
13
4
5
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
I/O DESCRIPTION
I
O
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
). Alternatively, an external clock can be connected to XTAL1 to provide custom data rates.
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal oscillator output or buffered a clock output.
Detailed Description
Autoflow Control (see
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and ACE2 from a
TLC16C2552 with the autoflow control enabled. If not, overrun errors occur when the transmit data rate exceeds the receiver FIFO read latency.
ACE1 ACE2
Serial to
Parallel
RX TX
RCV
FIFO
Parallel to Serial
RTS CTS
XMT
FIFO
Flow
Control
Flow
Control
D7 −D0
D7 −D0
XMT
FIFO
Parallel to Serial
TX RX
Serial to
Parallel
RCV
FIFO
CTS RTS
Flow
Control
Flow
Control
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
Auto-RTS (See
Figure 2
and
Figure 3 )
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level of
1, 4, or 8 (see
Figure 3 ), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send an
additional byte after the trigger level is reached (assuming the sending ACE has another byte to send) because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see
), RTS is deasserted after the first data bit of the 16th character is present on the RX line. RTS is reasserted when the RCV FIFO has at least one available byte space.
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Auto-CTS (See
Figure 2
)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last stop bit that is currently being sent (see
). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and a receiver overrun error may result.
Enabling Autoflow Control and Auto-CTS
Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to a
1. Autoflow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem control register should be cleared (this assumes that a control signal is driving CTS).
Auto-CTS and Auto-RTS Functional Timing
SOUT
Start Bits 0 −7
Stop
Start Bits 0 −7
Stop
Start Bits 0 −7
Stop
CTS
Figure 2. CTS Functional Timing Waveforms
SIN
RTS
Start Byte N
Stop
Start Byte N+1
Stop
Start Byte
Stop
RD
(RD RBR)
1 2
N N+1
Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
SIN
RTS
RD
(RD RBR)
Byte 14 Byte 15
RTS Released After the
First Data Bit of Byte 16
Start Byte 16 Stop Start Byte 18 Stop
Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
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TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
Internal
Data Bus
8
S e c e l t
8
Receiver
FIFO
D(7 −0)
9−2
Data
Bus
Buffer
Receiver
Buffer
Register
Receiver
Shift
Register
XTAL1
XTAL2
11
13
Crystal
OSC
Buffer
Line
Control
Register
A0
10
A1
14
A2
15
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
CS
CHSEL
18
16
RESET
IOR
21
24
IOW
20
TXRDYA
1
MFA
35
TXRDYB
32
MFB
19
Line
Status
Register
Select and
Control
Logic
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Transmitter
FIFO
8
8
8
S e c e l t
34, 17
INTA, B
V
CC
GND
33, 44
12, 22
Power
Supply
Interrupt
Enable
Register
Interrupt
Identification
Register
8
8
Interrupt
Control
Logic
FIFO
Control
Register
A.
Pin numbers shown are for 44-pin PLCC FN package.
Figure 5. Functional Block Diagram
Receiver
Timing and
Control
Transmitter
Timing and
Control
8
Transmitter
Shift
Register
Modem
Control
Logic
39, 25
RXA, B
36, 23
RTSA, B
Autoflow
Control
(AFE)
38, 26
TXA, B
40, 28
37, 27
CTSA, B
DTRA, B
41, 29
DSRA, b
42, 30
43, 31
CDA,B
RIA, B
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SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
CC
(2)
Input voltage range at any input, V
I
Output voltage range, V
O
Operating free-air temperature, T
A
, TL16C2552
Operating free-air temperature, T
A
, TL16C2552I
Storage temperature range, T stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
UNIT
-0.5 V to 7 V
-0.5 V to 7 V
-0.5 V to 7 V
0°C to 70°C
-40°C to 85°C
-65°C to 150°C
260°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to V
SS
.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
1.8 V ±10%
V
CC
V
I
V
IH
V
IL
V
O
I
OH
I
OL
Supply voltage
Input voltage
High-level input voltage
Low-level input voltage
Output voltage
High-level output current (all outputs)
Low-level output current (all outputs)
Oscillator/clock speed
2.5 V ±10%
V
CC
V
I
V
IH
V
IL
V
O
I
OH
I
OL
Supply voltage
Input voltage
High-level input voltage
Low-level input voltage
Output voltage
High-level output current (all outputs)
Low-level output current (all outputs)
Oscillator/clock speed
3.3 V ±10%
V
CC
V
I
V
IH
V
IL
V
O
I
OH
I
OL
Supply voltage
Input voltage
High-level input voltage
Low-level input voltage
Output voltage
High-level output current (all outputs)
Low-level output current (all outputs)
Oscillator/clock speed
5 V ±10%
V
CC
V
I
Supply voltage
Input voltage
MIN
1.62
0
1.4
-0.3
0
MIN
2.25
0
1.8
-0.3
0
MIN
3
0
0.7V
CC
0
MIN
4.5
0
NOM
1.8
NOM
2.5
NOM
3.3
NOM
5
0.3V
CC
V
CC
1.8
3.2
20
MAX
5.5
V
CC
MAX
2.75
V
CC
2.75
0.6
V
CC
1
2
16
MAX
1.98
V
CC
1.98
0.4
V
CC
0.5
1
10
MAX
3.6
V
CC
UNIT
V
V
V
V
V mA mA
MHz
UNIT
V
V
UNIT
V
V
V
V
V mA mA
MHz
UNIT
V
V
V
V
V mA mA
MHz
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SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
RECOMMENDED OPERATING CONDITIONS (continued)
over operating free-air temperature range (unless otherwise noted)
5 V ±10%
V
IH
V
IL
V
O
I
OH
I
OL
High-level input voltage
Low-level input voltage
All except XTAL1, XTAL2
XTAL1, XTAL2
All except XTAL1, XTAL2
XTAL1, XTAL2
Output voltage
High-level output current (all outputs)
Low-level output current (all outputs)
Oscillator/clock speed
MIN
2
0.7V
CC
0
NOM MAX
0.8
0.3V
CC
V
CC
4
4
24
UNIT
V
V
V mA mA
MHz
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I
I
I
V
V
I
OH
OL
OZ
CC
1.8 V Nominal
PARAMETER
High-level output voltage
(2)
Low-level output voltage
Input current
(2)
High-impedance-state output current
Supply current
TEST CONDITIONS
I
OH
= -0.5 mA
I
OL
= 1 mA
V
CC
= 1.98 V, V floating
SS
= 0, V
I
= 0 to 1.98 V, All other terminals
V
CC
= 1.98 V, V
SS
= 0, V mode or chip deselected
I
= 0 to 1.98 V, Chip selected in write
V
CC
= 1.98 V, T
A
= 0°C, RXA, RXB, DSRA, DSRB, CDA, CDB,
CTSA, CTSB, RIA, and RIB at 1.4 V, All other inputs at 0.4 V,
XTAL1 at 10 MHz, No load on outputs
C i(CL
K)
C
O(C
LK)
C
I
C
O
Clock input impedance
Clock output impedance
Input impedance
Output impedance
V
T
CC
A
= 0, V
SS
= 0, f = 1 MHz,
= 25°C, All other terminals grounded
(1) All typical values are at V
CC
= 1.8 V and T
A
= 25°C.
(2) These parameters apply for all outputs except XTAL2.
MIN TYP
(1)
1.3
MAX UNIT
V
0.5
V
10 µA
15
20
6
10
±20 µA
1.5
mA
20 pF
30 pF
10 pF
20 pF
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V
OH
V
OL
I
I
I
OZ
I
CC
2.5 V Nominal
PARAMETER
High-level output voltage
(2)
Low-level output voltage
Input current
(2)
TEST CONDITIONS
I
OH
= -1 mA
I
OL
= 2 mA
V
CC
= 2.75 V, V floating
SS
= 0, V
I
= 0 to 2.75 V, All other terminals
High-impedance-state output V
CC current
= 2.75 V, V
SS
= 0, V
I
= 0 to 2.75 V, Chip selected in write mode or chip deselected
Supply current V
CC
= 2.75 V, T
A
= 0°C, RXA, RXB, DSRA, DSRB, CDA,
CDB, CTSA, CTSB, RIA, and RIB at 1.8 V, All other inputs at
0.6 V, XTAL1 at 16 MHz, No load on outputs
MIN TYP
(1)
1.8
MAX UNIT
V
0.5
10
V
µA
±20 µA
2.5
mA
(1) All typical values are at V
CC
= 2.5 V and T
A
= 25°C.
(2) These parameters apply for all outputs except XTAL2.
ADDED SPACE
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ELECTRICAL CHARACTERISTICS (continued)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
C i(CLK)
C
O(CLK)
C
I
C
O
2.5 V Nominal
PARAMETER
Clock input impedance
Clock output impedance
Input impedance
Output impedance
TEST CONDITIONS
V
CC
T
A
= 0, V
SS
= 0, f = 1 MHz,
= 25°C, All other terminals grounded
MIN TYP
(1)
15
20
6
10
MAX UNIT
20
30 pF pF
10
20 pF pF
ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I
I
I
V
V
I
OH
OL
OZ
CC
3.3 V Nominal
PARAMETER
High-level output voltage
(2)
Low-level output voltage
Input current
(2)
High-impedance-state output current
Supply current
TEST CONDITIONS
I
OH
= -1.8 mA
I
OL
= 3.2 mA
V
CC
= 3.6 V, V floating
SS
= 0, V
I
= 0 to 3.6 V, All other terminals
V
CC
= 3.6 V, V
SS
= 0, V
I
= 0 to 3.6 V, Chip selected in write mode or chip deselected
V
CC
= 3.6 V, T
A
= 0°C, RXA, RXB, DSRA, DSRB, CDA,
CDB, CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, XTAL1 at 20 MHz, No load on outputs
C i(CLK)
C
O(CLK)
C
I
C
O
Clock input impedance
Clock output impedance
Input impedance
Output impedance
V
T
CC
A
= 0, V
SS
= 0, f = 1 MHz,
= 25°C, All other terminals grounded
(1) All typical values are at V
CC
= 3.3 V and T
A
= 25°C.
(2) These parameters apply for all outputs except XTAL2.
MIN TYP
(1)
2.4
15
20
6
10
MAX UNIT
V
0.5
10
V
µA
±20
20
30
10
20
µA
4 mA pF pF pF pF
10
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ELECTRICAL CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
I
I
I
V
V
I
OH
OL
OZ
CC
5 V Nominal
PARAMETER
High-level output voltage
(2)
Low-level output voltage
Input current
(2)
High-impedance-state output current
Supply current
TEST CONDITIONS
I
OH
= -4 mA
I
OL
= 4 mA
V
CC
= 5.5 V, V
SS terminals floating
= 0, V
I
= 0 to 5.5 V, All other
V
CC
= 5.5 V, V
SS
= 0, V
I
= 0 to 5.5 V, Chip selected in write mode or chip deselected
V
CC
= 5.5 V, T
A
= 0°C, RXA, RXB, DSRA, DSRB,
CDA, CDB, CTSA, CTSB, RIA, and RIB at 2 V, All other inputs at 0.8 V, XTAL1 at 24 MHz, No load on outputs
C i(CLK)
C
O(CLK)
C
I
C
O
Clock input impedance
Clock output impedance
Input impedance
Output impedance
V
T
CC
A
= 0, V
SS
= 0, f = 1 MHz,
= 25°C, All other terminals grounded
(1) All typical values are at V
CC
= 5 V and T
A
= 25°C.
(2) These parameters apply for all outputs except XTAL2.
MIN TYP
(1)
4
15
20
6
10
MAX UNIT
V
0.4
10
V
µA
±20
7.5
mA
20
30
10
20
µA pF pF pF pF t h7 t d5 t d8 t d10 t d11 t d12 t d13 t w6 t w7 t
SU3 t h4 t h5 t w8 t w1 t w2 t cR t cW
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ALT.
SYMBOL
FIGURE
TEST
CONDITIONS
LIMITS
1.8 V 2.5 V 3.3 V
MIN MAX MIN MAX MIN MAX MIN
5 V
MAX
1 1 1 1 Pulse duration, RESET
Pulse duration, clock high
Pulse duration, clock low
Cycle time, read (t w7
+ t d8
+ t h7
)
Cycle time, write (t w6
+ t d5
+ t h4
)
Pulse duration, IOW or CS
Pulse duration, IOR or CS
Setup time, data valid before IOW
↑ or CS
↑
Hold time, address valid after IOW
↑ or CS
↑
Hold time, data valid after IOW
↑ or CS
↑
Hold time, data valid after IOR
↑ or CS
↑
Delay time, address valid before IOW
↓ or CS
↓
Delay time, address valid to IOR
↓ or CS
↓
Delay time, IOR
↓ or CS
↓ to data valid
Delay time, IOR
↑ or CS
↑ to floating data
Write cycle to write cycle delay
Read cycle to read cycle delay t
RESET t
XH t
XL
RC
WC t
RA t
AW t
AR t
RVD t
HZ t
IOW t
IOR t
DS t
WA t
DH
6
7
8
7
7
7
8
8
8
7
8
8
7
7
8
C
L
= 30 pF
C
L
= 30 pF
40
25
20
15
20
15
15
115
115
80
80
55
40
100
100
25
20
15
10
15
10
10
80
80
55
55
35
30
75
75
20
15
10
5
10
7
7
62
62
45
45
25
20
60
60
18
15
10
5
10
7
7
57
57
40
40
20
20
50
50
UNIT
µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
BAUD GENERATOR SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature, C
L
= 30 pF (for FN package only) t w3 t w4 t d1 t d2
PARAMETER
Pulse duration, BAUDOUT low
Pulse duration, BAUDOUT high
Delay time, XIN
↑ to BAUDOUT
↑
Delay time, XIN
↑↓ to BAUDOUT
↓
ALT.
SYMBOL
t
LW t
HW t
BLD t
BHD
FIGURE
6
6
6
6
TEST
CONDITIONS
CLK ÷ 2
CLK
÷
2
LIMITS
1.8 V 2.5 V 3.3 V 5 V
MIN MAX MIN MAX MIN MAX MIN MAX
80
80
50
50
42
42
35
35
55
55
40
40
30
30
25
25
UNIT
ns ns ns ns
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RECEIVER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(1) t d12 t d13 t d14 t d26
PARAMETER
Delay time, RCLK to sample
Delay time, stop to set INT or read RBR to LSI interrupt or stop to RXRDY
↓
Delay time, read RBR/LSR to reset INT
Delay time, RCV threshold byte to RTS
↑
ALT.
SYMBOL
t
SCD t
SINT t
RINT
FIGURE
9
8, 9, 10,
11, 12
8, 9, 10,
11, 12
19
TEST
CONDITIONS
C
L
= 30 pF
C
L
= 30 pF
20
1
LIMITS
1.8 V 2.5 V 3.3 V 5 V
MIN MAX MIN MAX MIN MAX MIN MAX
15
1
10
1 1
10
100 90 80 70 t d27 t d28 t d29
Delay time, read of last byte in receive FIFO to
RTS
↓
Delay time, first data bit of 16th character to RTS
↑
Delay time, RBRRD low to RTS
↓
19
20
20
C
L
= 30 pF
C
L
= 30 pF
C
L
= 30 pF
UNIT
ns
RCLK cycle ns
2 baudout cycles (2)
2 baudout cycles
2 baudout cycles
2 baudout cycles
(1) In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt identification register or line status register).
(2) A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.
TRANSMITTER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) t d15 t d16 t d17 t d18 t d19 t d20 t d21 t
SU4 t d25
PARAMETER
Delay time, initial write to transmit start
Delay time, start to INT
Delay time, IOW (WR THR) to reset INT
Delay time, initial write to INT (THRE (1) )
Delay time, read IOR
↑ to reset INT (THRE (1) )
Delay time, write to TXRDY inactive
Delay time, start to TXRDY active
Setup time, CTS
↑ before midpoint of stop bit
Delay time, CTS low to TX
↓
ALT. SYMBOL
t
IRS t
STI t
HR t
SI t
IR t
WXI t
SXA
FIGURE
14
14
14
14
14
15, 16
15, 16
18
18
TEST
CONDITIONS
C
L
= 30 pF
C
L
= 30 pF
C
L
= 30 pF
C
L
= 30 pF
C
L
= 30 pF
LIMITS
MIN
1.8 V 2.5 V 3.3 V 5 V
MAX MIN MAX MIN MAX MIN MAX
8 24 8 24 8 24 8
8
16
10
70
34
8
16
10
60
34
8
16
10
50
34
8
16
UNIT
24 baudout cycles
10 baudout cycles
50 ns
70
60
9
50
45
9
35
35
9
34 baudout cycles
35
35 ns ns
30
24
20
24
10
24
10
9 baudout cycles ns
24 baudout cycles
(1) THRE = Transmitter Holding Register Empty; IIR = Interrupt Identification Register.
MODEM CONTROL SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
t d22 t d23 t d24
Delay time, WR MCR to output
Delay time, modem interrupt to set INT
Delay time, RD MSR to reset INT
ALT.
SYMBOL
t
MDO t
SIM t
RIM
FIGURE
17
17
17
TEST
CONDITIONS
C
L
= 30 pF
C
L
= 30 pF
C
L
= 30 pF
2.5 V
LIMITS
1.8 V 3.3 V 5 V
MIN MAX MIN MAX MIN MAX MIN MAX
90
60
80
70
50
60
60
40
50
50
35
40
UNIT
ns ns ns
12
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0.5
0.4
0.3
0.2
0.1
V
T
CC
A
= 1.8 V
= 22
°
C
Supply Current vs
Frequency
0.0
0 1 2 3 4 5 6 7 f − Frequency − MHz
8 9 10
G001
Figure 6.
Supply Current vs
Frequency
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0
2.0
1.8
1.6
1.4
V
T
CC
A
= 3.3 V
= 22
°
C
2 4
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
6 8 10 12 14 f − Frequency − MHz
16 18 20
G003
Figure 8.
Typical Characteristics
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
Supply Current vs
Frequency
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0
V
T
CC
A
= 2.5 V
= 22
°
C
2 4 6 8 10 f − Frequency − MHz
12
Figure 7.
14
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
16
G002
Supply Current vs
Frequency
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
4.0
3.6
3.2
2.8
V
T
CC
A
= 5 V
= 22
°
C
4 8 12 16 f − Frequency − MHz
20
Figure 9.
Divisor = 1
Divisor = 2
Divisor = 3
Divisor = 10
Divisor = 255
24
G004
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TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
N
XTAL t w1 t w2 t d2 t d1
MFA,B
(1/1) t d1 t d2
MFA,B
(1/2) t w3 t w4
MFA,B
(1/3)
MFA,B
(1/N)
(N > 3)
2 XIN Cycles
(N −2) XIN Cycles
Figure 10. Input Clock and Baud Generator Timing Waveforms
(For FN Package Only) (When AFR2:1 = 01)
CHSEL,
A2 −A0 t d5
Valid Address t h4 t d5
Valid Address t w6 t w6
CS t d12 t w6 t w6
IOW
D7 −D0 www.ti.com
t h4 t su3 t h5
Valid Data
Figure 11. Write Cycle Timing Waveforms t su3
Valid Data t h5
14
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CHSEL,
A2 −A0
CS t d8
Valid Address t w7 t w7 t h7 t d13
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006 t d8
Valid Address t w7
TL16C2552 t h7 t w7
IOR
D7 −D0 t d10 t d10 t d11
Valid Data
Figure 12. Read Cycle Timing Waveforms
RCLK
(Internal)
Sample Clock
(Internal)
TL16C450 Mode:
RXA, RXB Start
Sample Clock
INT
(data ready)
8 CLKs
Data Bits 5− 8 Parity Stop t d12
50% t d13
50%
INT
(RCV error)
IOR
(read RBR)
Valid Data t d14
50%
50%
50%
Active t h11
IOR
(read LSR)
50%
Active t d14
Figure 13. Receiver Timing Waveforms
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RXA, RXB
Sample Clock
(Internal)
Trigger Level
INT
(FCR6, 7 = 0, 0)
INT
Line Status
Interrupt (LSI)
IOR
(RD LSR)
IOR
(RD RBR)
Data Bits 5 −8
Stop
50%
50% t d13
(see Note A) t d14
50% 50% t d14
Active
50%
50%
Active
Figure 14. Receive FIFO First Byte (Sets DR Bit) Waveforms
(FIFO at or above trigger level)
(FIFO below trigger level)
RXA, RXB
Sample Clock
(Internal)
Time-Out or
Trigger Level
Interrupt
Line Status
Interrupt (LSI)
Stop
50% t d13
(see Note A) t d13
50%
Top Byte of FIFO t d14
50% t d14
50%
50%
(FIFO at or above trigger level)
(FIFO below trigger level)
IOP
(RD LSR)
IOR
(RD RBR)
Active 50% 50% Active
Previous Byte
Read From FIFO
Figure 15. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
16
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TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
IOR
(RD RBR)
RXA, RXB
(first byte)
Stop
50% Active
See Note A
Sample Clock
(Internal) t d13
(see Note B)
RXRDYA, RXRDYB
50% t d14
50%
Figure 16. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
IOR
(RD RBR)
RXA, RXB
(first byte that reaches the trigger level)
Sample Clock
(Internal) t d13
(see Note B)
50%
Active
See Note A t d14
RXRDYA, RXRDYB
50% 50%
Figure 17. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
Start
50%
Data Bits Parity
Start
50%
TXA, TXB
INT
(THRE)
50% t d15
50% 50%
Stop t d16
50% 50% t d18 t d17 t d17
IOW
(WR THR)
50%
50%
50%
IOR t d19
50%
Figure 18. Transmitter Timing Waveforms
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IOW
(WR THR)
Byte 1
50%
TXA, TXB Data Parity
Stop
Start
50% t d20 t d21
TXRDYA, TXRDYB
50%
50%
Figure 19. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
IOW
(WR THR)
Byte 16
50%
TXA, TXB Data Parity
Stop
Start
50% t d20 t d21
TXRDYA, TXRDYB
50%
FIFO Full
50%
Figure 20. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
IOW
(WR MCR)
50% 50% t d22 t d22
RTSA, RTSB, DTRA,
DTRB, OPA, OPB
50% 50%
50%
CTSA, CTSB, DSRA,
DSRB, CDA, CDB
INT
(modem)
IOR
(RD MSR) t d23
50% t d24
50%
50%
50% t d23
RI
Figure 21. Modem Control Timing Waveforms
50%
18
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TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
CTSA, CTSB
TXA, TXB t su4
50% 50% t d25
50%
Midpoint of Stop Bit
Figure 22. CTS and TX Autoflow Control Timing (Start and Stop) Waveforms
Midpoint of Stop Bit
RXA, RXB
RTSA,
RTSB t d26
50% t d27
50%
IOR
RXA,
RXB
RTSA,
RTSB
50%
Figure 23. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms
15th Character
Midpoint of Data Bit 0
16th Character t d28
50% t d29
50%
IOR
50%
Figure 24. Auto-RTS Timing for RCV Threshold of 14 Waveforms
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TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
APPLICATION INFORMATION
C
P
U
B u s
D7 −D0
MEMR or I/OR
MEMW or I/OW
INTR
RESET
A0
A1
A2
A3
CS
D7 −D0
IOR
IOW
INTA, B
RESET
A0
A1
A2
TL16C2552
CHSEL
XTAL1
CS
TXA, B
RXA, B
RTSA, B
DTRA, B
DSRA, B
CDA, B
CTSA, B
RIA, B
XTAL2
(Optional)
EIA-232-D
Drivers and Receivers
3.072 MHz
33 pF
33 pF
Figure 25. Basic TL16C2552 Configuration www.ti.com
20
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A0 −A23
CPU
RSI/ABT
AD0 −AD15
PHI1 PHI2
PHI1 PHI2
TCU
TL16C2552
SLWS163A – SEPTEMBER 2005 – REVISED JUNE 2006
APPLICATION INFORMATION (continued)
Address
Decoder
TL16C2552
XTAL1
11
10, 14, 15
A0 −A2
XTAL2
13
(Optional)
Alternate
Crystal Control
16
18
CHSEL
CS
33 pF
33 pF
RSTO
RD
WR
Buffer
(Optional)
D0 −D7
DTRA, B
RTSA, B
37, 27
36, 23
21
RESET
2−9
D0 −D7
RIA, B
CDA, B
43, 31
42, 30
41, 29
DSRA, B
CTSA, B
40, 28
24
IOR
20
IOW
34, 17
INTA, B
TXA, B
38, 26
RXA, B
39, 25
2
3
8
6
5
20
1
7
1
EIA-232-D
Connector
GND
(V
SS
)
12, 22
V
CC
33, 44
A.
Pin numbers shown are for 44-pin PLCC FN package.
Figure 26. Typical TL16C2552 Connection
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PRINCIPLES OF OPERATION
Register Selection
DLAB
(1)
0
0
X
0
0
X
X
X
1
1
X
1
H
H
H
L
L
A2
L
L
L
L
L
H
L
A1
L
L
H
H
H
L
L
H
H
L
L
H
Table 1. Register Selection
L
H
L
L
H
A0
L
H
L
H
L
H
L
REGISTER
Receiver buffer (read), transmitter holding register (write)
Interrupt enable register
Interrupt identification register (read only)
FIFO control register (write)
Line control register
Modem control register
Line status register
Modem status register
Scratch register
Divisor latch (LSB)
Divisor latch (MSB)
Alternate function register (AFR)
(1) The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal is controlled by writing to this bit location (see
).
REGISTER/SIGNAL
Interrupt enable register
Interrupt identification register
FIFO control register
Line control register
Modem control register
Line status register
Modem status register
TX
INT
Interrupt condition (receiver error flag)
Interrupt condition (received data available)
Interrupt condition (transmitter holding register empty)
Interrupt condition (modem status changes)
OP
RTS
DTR
Scratch register
Divisor latch (LSB and MSB) registers
Receiver buffer register
Transmitter holding register
RCVR FIFO
XMIT FIFO
Alternate function register (AFR)
Table 2. ACE Reset Functions
RESET CONTROL
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset MCR3
Read LSR/MR
Read RBR/MR
Read IR/write THR/MR
RESET STATE
All bits cleared (0 - 3 forced and 4 - 7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits
4 - 5 are permanently cleared
All bits cleared
All bits cleared
All bits, except bit 3, cleared (6 - 7 permanent), MCR
3 set
Bits 5 and 6 are set; all other bits are cleared
Bits 0 - 3 are cleared; bits 4 - 7 are input signals
High
Output buffer enabled
Low
Low
Low
Read MSR/MR
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
MR/FCR1 - FCR0/DFCR0
MR/FCR2 - FCR0/DFCR0
Master reset
Low
Low
High
High
No effect
No effect
No effect
No effect
All bits cleared
All bits cleared
All bits cleared
22
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Accessible Registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are summarized in
Table 2 . These registers control ACE operations, receive data, and transmit data. Descriptions of
these registers follow
.
BIT
NO.
0
1
2
3
4
5
6
7
Table 3. Summary of Accessible Registers
0
Receiver Transmitte Interrupt
Buffer
Register r Holding
Register
Enable
Register
(Read
Only)
(Write
Only)
RBR
Data Bit
0 (1)
0
THR
Data Bit 0
1
IER
Enable
Received
Data
Available
Interrupt
(ERBI)
Data Bit 1 Data Bit 1
Data Bit 2 Data Bit 2
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Enable
Receiver
Line Status
Interrupt
(ELSI)
Data Bit 3
Data Bit 4
Data Bit 3
Data Bit 4
Enable
Modem
Status
Interrupt
(EDSSI)
0
Data Bit 5
Data Bit 6
Data Bit 7
Data Bit 5
Data Bit 6
Data Bit 7
0
0
0
2
Interrupt
Ident
.Register
(Read
Only)
IIR
0 if
Interrupt
Pending
0
0
FIFOs
Enabled
FIFOs
Enabled
(2)
(2)
2
FIFO
Control
Register
(Write
Only)
FCR
FIFO
Enable
Interrupt ID DMA Mode
Bit 3 (2) Select
REGISTER ADDRESS
DLAB = 0
3
Line
Control
Register
Interrupt ID Receiver
Bit 1 FIFO
Reset
LCR
Word
Length
Select Bit 0
(WLS0)
Word
Length
Select Bit 1
(WLS1)
Interrupt ID Transmitter Number of
Bit 2 FIFO Stop Bits
Reset (STB)
Parity
Enable
(PEN)
4
Modem
Control
Register
MCR
Data
Terminal
Ready
(DTR)
Request to
Send
(RTS)
OUT1
INT
Enable, OP
Control
5
Line
Status
Register
LSR
Data
Ready
(DR)
Overrun
6
Modem
Status
Register
MSR
Delta Clear to Send
(
∆
CTS)
Delta Data
Error (OE) Set Ready
Parity Error
(PE)
Framing
Error (FE)
(
∆
DSR)
Trailing
Edge Ring
Indicator
(TERI)
Delta Data
(
Carrier
Detect
∆
DCD)
Reserved Even Parity
Select
(EPS)
Loop
Reserved Stick Parity Autoflow Transmitter Data Set
Control
Enable
(AFE)
Holding
Register
(THRE)
Ready
(DSR)
Break
Control
0
Break
Interrupt
(BI)
Clear to
Send
(CTS)
Receiver
Trigger
(LSB)
Receiver
Trigger
(MSB)
Divisor
Latch
Access Bit
(DLAB)
0
Transmitter
Empty
(TEMT)
Error in
RCVR
FIFO (2)
Ring
Indicator
(RI)
Data
Carrier
Detect
(DCD)
7
Scratch
Register
SCR
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the TL16C450 mode.
0
Divisor
Latch
(LSB)
DLAB = 1
1
Divisor
Latch
(MSB)
2
Alternate
Function
Register
DLL
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
DLM
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
AFR
Concurrent
Write
BAUDOUT
Select
RXRDY
Select
0
0
0
0
0
FIFO Control Register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling.
•
Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits are written to or they are not programmed. Changing this bit clears the FIFOs.
•
Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not cleared. The 1 that is written to this bit position is self-clearing.
•
Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not cleared. The 1 that is written to this bit position is self-clearing.
•
Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
•
Bits 4 and 5: These two bits are reserved for future use.
•
Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see
).
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BIT 7
0
0
1
1
BIT 6
0
1
0
1
Table 4. Receiver FIFO Trigger Level
RECEIVER FIFO TRIGGER LEVEL (BYTES)
01
04
08
14
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FIFO Interrupt Mode Operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and like the interrupt, it is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06) has higher priority than the received data available (IIR = 04) interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.
It is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled:
1. FIFO time-out interrupt occurs if the following conditions exist: a.
At least one character is in the FIFO.
b.
The most recent serial character was received more than four continuous character times ago (if two stop bits are programmed, the second one is included in this time delay).
c.
The most recent microprocessor read of the FIFO has occurred more than four continuous character times before. This causes a maximum character received command to interrupt an issued delay of
160 ms at a 300-baud rate with a 12-bit character.
2. Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional to the baud rate).
3. When a time-out interrupt has occurred, it is cleared and the timer is cleared when the microprocessor reads one character from the receiver FIFO.
4. When a time-out interrupt has not occurred, the time-out timer is cleared after a new character is received or after the microprocessor reads the receiver FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as follows:
1. The transmitter holding register empty interrupt [IIR (3 -0) = 2] occurs when the transmit FIFO is empty. It is cleared [IIR (3 -0) = 1] when the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this interrupt) or the IIR is read.
2. The transmitter holding register empty interrupt is delayed one character time minus the last stop bit time when there have not been at least two bytes in the transmitter FIFO at the same time since the last time that the FIFO was empty. The first transmitter interrupt after changing FCR0 is immediate if it is enabled.
FIFO Polled Mode Operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts the ACE in the FIFO polled mode of operation. Because the receiver and transmitter are controlled separately, either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
•
LSR0 is set as long as one byte is in the receiver FIFO.
•
LSR1 - LSR 4 specify which error(s) have occurred. Character error status is handled the same way as when in the interrupt mode; the IIR is not affected since IER2 = 0.
•
LSR5 indicates when the THR is empty.
•
LSR6 indicates that both the THR and TSR are empty.
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•
LSR7 indicates whether any errors are in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver and transmitter FIFOs are still fully capable of holding characters.
Interrupt Enable Register (IER)
The IER enables each of the five types of interrupts (see Table 5) and enables INTRPT in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents of this register are summarized in
and are described in the following bullets.
•
Bit 0: When set, this bit enables the received data available interrupt.
•
Bit 1: When set, this bit enables the THRE interrupt.
•
Bit 2: When set, this bit enables the receiver line status interrupt.
•
Bit 3: When set, this bit enables the modem status interrupt.
•
Bits 4 through 7: These bits are not used (always cleared).
Interrupt Identification Register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with the most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
•
Priority 1 - Receiver line status (highest priority)
•
Priority 2 - Receiver data ready or receiver character time-out
•
Priority 3 - Transmitter holding register empty
•
Priority 4 - Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and encodes the type of interrupt in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in
and described in
Table 5 . Details on each bit is as follows:
•
Bit 0: This bit is used either in a hardwired prioritized or polled interrupt system. When bit 0 is cleared, an interrupt is pending. If bit 0 is set, no interrupt is pending.
•
Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in
.
•
Bit 3: This bit is always cleared in TL16C450 mode. In FIFO mode, bit 3 is set with bit 2 to indicate that a time-out interrupt is pending.
•
Bits 4 and 5: These two bits are not used (always cleared).
•
Bits 6 and 7: These bits are always cleared in TL16C450 mode. They are set when bit 0 of the FIFO control register is set.
Table 5. Interrupt Control Functions
PRIORITY
LEVEL
INTERRUPT TYPE INTERRUPT SOURCE INTERRUPT RESET
METHOD
INTERRUPT IDENTIFICATION
REGISTER
BIT 3 BIT 2 BIT 1 BIT 0
0
0
0
1
0
1
1
0
None
1
0
1
1
1
0
0
0
0
2
2
None
Receiver line status
None
Overrun error, parity error, framing error, or break interrupt
None
Read the line status register
Received data available Receiver data available in Read the receiver buffer the TL16C450 mode or register trigger level reached in the FIFO mode
Character time-out indication
No characters have been Read the receiver buffer removed from or input to register the receiver FIFO during the last four character times, and there is at least one character in it during this time
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INTERRUPT IDENTIFICATION
REGISTER
BIT 3 BIT 2 BIT 1 BIT 0
0 0 1 0
Table 5. Interrupt Control Functions (continued)
PRIORITY
LEVEL
INTERRUPT TYPE INTERRUPT SOURCE
3 Transmitter holding register empty
Transmitter holding register empty
0 0 0 0 4 Modem status Clear to send, data set ready, ring indicator, or data carrier detect
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INTERRUPT RESET
METHOD
Read the interrupt identification register (if source of interrupt) or writing into the transmitter holding register
Read the modem status register
Line Control Register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates the need for separate storage of the line characteristics in system memory. The contents of this register are summarized in
and described in the following bulleted list.
•
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in
Table 6. Serial Character Word Length
BIT 1
0
0
1
BIT 0
0
1
0
WORD LENGTH
5 bits
6 bits
7 bits
1 1 8 bits
•
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit
2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are shown in
.
Table 7. Number of Stop Bits Generated
BIT 2
0
1
1
Word Length Selected by Bits 1 and 2
Any word length
5 bits
6 bits
Number of Stop Bits Generated
1
1 ½
2
1 7 bits 2
1 8 bits 2
•
Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is cleared, no parity is generated or checked.
•
Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared, odd parity (an odd number of logic 1s) is selected.
•
Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit
5 is cleared, stick parity is disabled.
•
Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where TX is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no effect on the transmitter logic; it only effects TX.
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•
Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver buffer, the THR, or the IER.
Line Status Register (LSR)
NOTE:
The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register are summarized in
and described in the following bulleted list.
•
Bit 0: This bit is the data ready (DR) indicator for the receiver. DR is set whenever a complete incoming character has been received and transferred into the RBR or the FIFO. DR is cleared by reading all of the data in the RBR or the FIFO.
NOTE:
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
•
Bit 1: This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in the
RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO beyond the trigger level, an overrun error occurs only after the FIFO is full, and the next character has been completely received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The character in the shift register is overwritten, but it is not transferred to the FIFO.
•
Bit 2: This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the
FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the
FIFO.
•
Bit 3: This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character did not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the next start bit. The
ACE samples this start bit twice and then accepts the input data.
•
Bit 4: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after RX goes to the marking state for at least two RCLK samples and then receives the next valid start bit.
•
Bit 5: This bit is the THRE indicator. THRE is set when the THR is empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when THRE is set, an interrupt is generated. THRE is set when the contents of the THR are transferred to the TSR. THRE is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, THRE is set when the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO.
•
Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode, TEMT is set when the transmitter FIFO and shift register are both empty.
•
Bit 7: In the TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.
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Modem Control Register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is emulating a modem. The contents of this register are summarized in
and are described in the following bulleted list.
•
Bit 0: This bit (DTR) controls the DTR output.
•
Bit 1: This bit (RTS) controls the RTS output.
•
Bit 2: This bit (OUT1) is reserved for output and can also be used for loopback mode.
•
Bit 3: This bit (OUT2) controls the high-impedance state output buffer for the INT signal and the OP output.
When low, the INT signal is in a high-impedance state and OP is high. When high, the INT signal is enabled and OP is low. OP is presented on MF when AFR (2:1) = 00.
•
Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP is set, the following occurs:
– The transmitter TX is set high.
– The receiver RX is disconnected.
– The output of the TSR is looped back into the receiver shift register input.
– The four modem control inputs (CTS, DSR, CD, and RI) are disconnected.
– The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four modem control inputs.
– The four modem control outputs are forced to the inactive (high) levels.
•
Bit 5: This bit (AFE) is the autoflow control enable. When set, the autoflow control as described in the detailed description is enabled.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt's sources are now the lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in
MCR BIT 5 (AFE)
1
1
0
Table 8. ACE Flow Configuration
MCR BIT 1 (RTS)
1
0
X
ACE FLOW CONFIGURATION
Auto-RTS and auto-CTS enabled (autoflow control enabled)
Auto-CTS only enabled
Auto-RTS and auto-CTS disabled
Modem Status Register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change information; when a control input from the modem changes state, the appropriate bit is set. All four bits are cleared when the CPU reads the MSR. The contents of this register are summarized in
and are described in the following bulleted list.
•
Bit 0: This bit is the change in clear-to-send (
∆
CTS) indicator.
∆
CTS indicates that the CTS input has changed state since the last time it was read by the CPU. When
∆
CTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled (
∆
CTS is cleared), no interrupt is generated.
•
Bit 1: This bit is the change in data set ready (
∆
DSR) indicator.
∆
DSR indicates that the DSR input has changed state since the last time it was read by the CPU. When
∆
DSR is set and the modem status interrupt is enabled, a modem status interrupt is generated.
•
Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that the RI input to the chip has changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated.
•
Bit 3: This bit is the change in data carrier detect (
∆
DCD) indicator.
∆
DCD indicates that the DCD input to the chip has changed state since the last time it was read by the CPU. When
∆
DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated.
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•
Bit 4: This bit is the complement of the clear-to-send (CTS) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
•
Bit 5: This bit is the complement of the data set ready (DSR) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
•
Bit 6: This bit is the complement of the ring indicator (RI) input. When the ACE is in the diagnostic test mode
(LOOP [MCR4] = 1), this bit is equal to the MCR bit 2 (OUT1).
•
Bit 7: This bit is the complement of the data carrier detect (DCD) input. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).
DESIRED BAUD
RATE
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
Programmable Baud Generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16
MHz and divides it by a divisor in the range between 1 and (216 -1). The output frequency of the baud generator is sixteen times (16 y) the baud rate. The formula for the divisor is: divisor = XIN frequency input P (desired baud rate y 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
and
illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072
MHz respectively. For baud rates of 38.4 kbits/s and below, the error obtained is small. The accuracy of the selected baud rate is dependent on the selected crystal frequency (see
for examples of typical clock circuits).
Table 9. Baud Rates Using a 1.8432-MHz Crystal
DIVISOR USED TO GENERATE 16×
CLOCK
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND
ACTUAL
0.026
0.058
0.69
2.86
DESIRED BAUD
RATE
50
75
110
134.5
Table 10. Baud Rates Using a 3.072-MHz Crystal
DIVISOR USED TO GENERATE 16×
CLOCK
3840
2560
1745
1428
0.026
0.034
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DESIRED BAUD
RATE
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
Table 10. Baud Rates Using a 3.072-MHz Crystal (continued)
DIVISOR USED TO GENERATE 16×
CLOCK
1280
640
320
160
107
96
80
53
40
27
20
10
5
0.312
0.628
1.23
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External
Clock
Driver
XIN
V
CC
XIN
V
CC
C1
Crystal
R
P
Optional
Clock
Output
Optional
Driver
XOUT
Oscillator Clock to Baud Generator
Logic
RX2
XOUT
Oscillator Clock to Baud Generator
Logic
C2
Figure 27. Typical Clock Circuits
CRYSTAL
3.072 MHz
1.8432 MHz
16 MHz
Table 11. Typical Crystal Oscillator Network
R
P
1 M
Ω
1 M
Ω
1 M
Ω
RX2 (optional)
1.5 k
Ω
1.5 k
Ω
0 k
Ω
C1
10 - 30 pF
10 - 30 pF
33 pF
C2
40 - 60 pF
40 - 60 pF
33 pF
Receiver Buffer Register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is derived from the input clock divided by the programmed devisor. Receiver section control is a function of the ACE line control register.
The ACE RSR receives serial data from RX. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
Scratch Register
The scratch register is an 8-bit register that is intended for the programmer's use as a scratchpad in the sense that it temporarily holds the programmer's data without affecting any other ACE operation.
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Transmitter Holding Register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is derived from the input clock divided by the programmed devisor. Transmitter section control is a function of the ACE line control register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at TX. In the TL16C450 mode, if the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
Alternate Function Register (AFR) - Read/Write
This register is used to select specific modes of MF operation and to allow both UART register sets to be written concurrently.
AFR[0]: Concurrent Write Mode
When this bit is set, the CPU can write concurrently to the same register in both UARTs. This function is intended to reduce the dual UART initialization time. It can be used by the CPU when both channels are initialized to the same state. The external CPU can set or clear this bit by accessing either register set. When this bit is set, the channel select pin still selects the channel to be accessed during read operations. The user should ensure that LCR bit 7 of both channels are in the same state before executing a concurrent write to the registers at addresses 0, 1, or 2.
•
Logic 0 = No concurrent write (default)
•
Logic 1 = Register set A and B are written concurrently with a single external CPU I/O write operation.
AFR[2:1]: MF Output Select
These bits select a signal function for output on the MF A/B pins. These signal functions are described as: OP,
BAUDOUT, or RXRDY. Only one signal function can be selected at a time.
Bit 2
0
0
1
1
Bit 1
0
1
0
1
MF Function
MF Function
OP (default)
BAUDOUT
RXRDY
Reserved
AFR[7:3]: Reserved
All are initialized to logic 0.
Table 12. Typical Package Thermal Resistance Data
Package
32-Pin TQFP RHB
44-Pin PLCC FN
θ
JA
= xx
°
C/W
θ
JA
= 46.2
°
C/W
θ
JC
= xx
°
C/W
θ
JC
= 22
°
C/W
Package
32-Pin TQFP RHB
44-Pin PLCC FN
Table 13. Typical Package Weight
Weight in Grams
0.15
0.5
Submit Documentation Feedback
31
MECHANICAL DATA
MPLC004A – OCTOBER 1994
PLASTIC J-LEADED CHIP CARRIER FN (S-PQCC-J**)
20 PIN SHOWN
3
D
D1
1 19
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
0.020 (0,51) MIN
0.032 (0,81)
0.026 (0,66)
4 18
D2 / E2
E E1
D2 / E2
8 14
9 13
0.050 (1,27)
0.008 (0,20) NOM
0.021 (0,53)
0.013 (0,33)
0.007 (0,18)
M
NO. OF
PINS
**
52
68
84
20
28
44
D / E D1 / E1 D2 / E2
MIN MAX MIN MAX MIN MAX
0.385 (9,78)
0.485 (12,32)
0.395 (10,03)
0.495 (12,57)
0.350 (8,89)
0.450 (11,43)
0.356 (9,04)
0.456 (11,58)
0.685 (17,40)
0.785 (19,94)
0.695 (17,65)
0.795 (20,19)
0.650 (16,51)
0.750 (19,05)
0.656 (16,66)
0.756 (19,20)
0.985 (25,02)
1.185 (30,10)
0.995 (25,27)
1.195 (30,35)
0.950 (24,13)
1.150 (29,21)
0.958 (24,33)
1.158 (29,41)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.441 (11,20)
0.541 (13,74)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
0.469 (11,91)
0.569 (14,45)
4040005 / B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
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