THS3201

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THS3201 | Manualzz

Not Recommended for New Designs

D-8

DBV-5

DGN-8

DGK-8

THS3201 www.ti.com

.............................................................................................................................................................

SLOS416C – JUNE 2003 – REVISED JUNE 2009

1.8-GHz, LOW DISTORTION, CURRENT-FEEDBACK AMPLIFIER

1

FEATURES

23

Unity-Gain Bandwidth: 1.8 GHz

High Slew Rate: 6700 V/

µ

s (G = 2 V/V,

R

L

= 100 Ω, 10-V Step)

IMD

3

: –78 dBc at 20 MHz: (G = 10 V/V,

R

L

= 100 Ω, 2-V

PP

Envelope)

Noise Figure: 11 dB (G = 10 V/V, R

G

= 28 Ω,

R

F

= 255 Ω)

Input-Referred Noise (f >10 MHz)

– Voltage Noise: 1.65 nV/ √Hz

– Noninverting Current Noise: 13.4 pA/

√Hz

– Inverting Current Noise: 20 pA/ √Hz

Output Drive: 100 mA

Power-Supply Voltage Range: ±3.3 V to ±7.5 V

APPLICATIONS

Test and Measurement

ATE

High-Resolution, High-Sampling Rate ADC

Drivers

High-Resolution, High-Sampling Rate DAC

Output Buffers

DESCRIPTION

The THS3201 is a wideband, high-speed current-feedback amplifier, designed to operate over a wide supply range of ±3.3 V to ±7.5 V for today's high performance applications.

The wide supply range, combined with low distortion and high slew rate, makes the THS3201 ideally suited for arbitrary waveform driver applications. The distortion performance also enables driving high-resolution and high-sampling analog-to-digital converters (ADCs).

rate

Its high voltage operation capabilities make the

THS3201 especially suitable for many test, measurement, and ATE applications where lower voltage devices do not offer enough voltage swing capability. Output rise and fall times are nearly independent of step size (to first-order approximation), making the THS3201 ideal for buffering small to large step pulses with excellent linearity in high dynamic systems.

The THS3201 is offered in a 5-pin SOT-23, 8-pin

SOIC, and an 8-pin MSOP with PowerPAD™ packages.

Low-Noise, Low-Distortion, Wideband Application Circuit

+7.5 V

50

Source

50

V

I

49.9

+

THS3201

_

49.9

50

-7.5 V

768

768

NOTE

:

Power supply decoupling capacitors not shown

RELATED DEVICES AND DESCRIPTIONS

DEVICE DESCRIPTION

THS3202 ±7.5-V, 2-GHz Dual Low Distortion CFB Amplifier

THS3001 ±15-V, 420-MHz Low Distortion CFB Amplifier

THS3061 / 2 ±15-V, 300-MHz Low Distortion CFB Amplifier

THS3122 ±15-V, Dual CFB Amplifier With 350 mA Drive

OPA695 ±5-V, 1.7-GHz Low Distortion CFB Amplifier

8

NONINVERTING SMALL SIGNAL

FREQUENCY RESPONSE

7

6

5

R

F

= 768

4

3

2

1

0

100 k

Gain = 2.

R

L

= 100

,

V

O

= 0.2 V

PP

.

V

S

=

±

7.5 V

1 M 10 M 100 M

f - Frequency - Hz

1 G 10 G

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2003–2009, Texas Instruments Incorporated

Not Recommended for New Designs

THS3201

SLOS416C – JUNE 2003 – REVISED JUNE 2009 .............................................................................................................................................................

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range unless otherwise noted.

(1)

V

S

V

I

I

O

V

ID

T

J

T

J

T

A

T

STG

ESD ratings

Supply voltage

Input voltage

Output current

Differential input voltage

Continuous power dissipation

Maximum junction temperature

(2)

Maximum junction temperature, continuous operation, long term reliability

(3)

Operating free-air temperature range

Storage temperature range

HBM

CDM

MM

UNIT

16.5 V

±V

S

175 mA

±3 V

See

Dissipation Rating

Table

+150°C

+125°C

–40°C to +85°C

–65°C to +150°C

3000 V

1500 V

100 V

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(2) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.

(3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device.

PACKAGE

DBV (5)

D (8)

DGN (8)

(1)

DGK (8 pin)

PACKAGE DISSIPATION RATINGS

(1)

θ

JC

(°C/W)

55

38.3

4.7

54.2

θ

JA

(2)

(°C/W)

255.4

97.5

58.4

260

POWER RATING

(3)

(T

J

= +125°C)

T

A

≤ +25°C

391 mW

T

A

= +85°C

156 mW

1.02 W

1.71 W

410 mW

685 mW

385 mW 154 mW

(1) The THS3201 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heat sink and must be connected to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the

PowerPAD thermally enhanced package.

(2) This data was taken using the JEDEC standard High-K test PCB.

(3) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and long term reliability.

RECOMMENDED OPERATING CONDITIONS

T

A

Supply voltage

Operating free-air temperature range

Dual supply

Single supply

MIN

±3.3

6.6

–40

MAX

±7.5

15

+85

UNIT

V

°C

2

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Product Folder Link(s):

THS3201

Copyright © 2003–2009, Texas Instruments Incorporated

Not Recommended for New Designs

THS3201 www.ti.com

.............................................................................................................................................................

SLOS416C – JUNE 2003 – REVISED JUNE 2009

PART NUMBER

THS3201D

THS3201DR

THS3201DBVT

THS3201DBVR

THS3201DGN

THS3201DGNR

THS3201DGK

THS3201DGKR

PACKAGE/ORDERING INFORMATION

(1)

PACKAGE TYPE

SOIC-8

SOT-23

MSOP-8-PP

MSOP-8

PACKAGE MARKING

BEO

BEN

BGP

TRANSPORT MEDIA, QUANTITY

Rails, 75

Tape and Reel, 2500

Tape and Reel, 250

Tape and Reel, 3000

Rails, 80

Tape and Reel, 2500

Rails, 80

Tape and Reel, 2500

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com

.

PIN ASSIGNMENTS

DBV PACKAGE

SOT23-5

(TOP VIEW)

V

OUT

V

S

-

IN+

1

2

3

5

4

V

S+

IN

-

NC

V

IN

-

V

IN+

V

S

-

D, DGN, DGK PACKAGES

SOIC-8, MSOP-8

(TOP VIEW)

1

2

3

4

8

7

6

5

NC

V

S+

V

OUT

-

NC

NC = No internal connection.

See Note A.

A.

If a PowerPAD is used, it is electrically isolated from the active circuitry.

Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s):

THS3201

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3

Not Recommended for New Designs

THS3201

SLOS416C – JUNE 2003 – REVISED JUNE 2009 .............................................................................................................................................................

www.ti.com

ELECTRICAL CHARACTERISTICS: V

S

= ±7.5 V

At R

F

= 768 Ω, R

L

= 100 Ω, and G = +2, unless otherwise noted.

PARAMETER TEST CONDITIONS

TYP

+25°C +25°C

THS3201

OVER TEMPERATURE

0°C to –40°C to

+70°C +85°C

UNITS

MIN/

TYP/

MAX

AC PERFORMANCE

Small-signal bandwidth, –3 dB

(V

O

= 200 mV

PP

)

Bandwidth for 0.1 dB flatness

Large-signal bandwidth

Slew rate

Rise and fall time

Settling time to 0.1%

Settling time to 0.01%

Harmonic distortion

2 nd

-order harmonic

3 rd

-order harmonic

Third-order intermodulation distortion (IMD

3

)

G = +1, R

F

= 1.2 k Ω

G = +2, R

F

= 768 Ω

G = +5, R

F

= 619

G = +10, R

F

= 487 Ω

G = +2, V

O

= 200 mV pp

G = +2, V

O

= 2 V pp

G = +2, V

O

= 5-V step, Rise/Fall

G = +2, V

O

= 10-V step, Rise/Fall

G = +2, V

O

= 4-V step, Rise/Fall

G = –2, V

O

= 2-V step

1.8

850

565

520

380

880

5400/4000

9800/6700

0.7/0.9

20

60

–64

–73

–78

GHz

MHz

MHz

MHz

V/

µ s ns ns dBc dBc dBc

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Noise figure

Input voltage noise

Input current noise (noninverting)

Input current noise (inverting)

Differential gain

Differential phase

DC PERFORMANCE

Open-loop transimpedance gain

Input offset voltage

Average offset voltage drift

Input bias current (inverting)

Average bias current drift (–)

Input bias current (noninverting)

Average bias current drift (+)

G = +5, f = 10 MHz,

V

O

= 2 V pp

R

L

= 100 Ω

R

L

= 100 Ω

G = +10, f c

V

O(envelope)

= 20 MHz,

= 2 V pp

Δf = 1 MHz,

G = +10, f c

R

G

= 28

= 100 MHz, R

F

= 255 Ω, f > 10 MHz f > 10 MHz

G = +2, R

R

F

= 768

L

= 150 Ω,

NTSC

PAL

NTSC

PAL

V

O

= ±1 V, R

L

= 1 k Ω

V

CM

= 0 V

11

1.65

13.4

20

0.008%

0.004%

0.007°

0.011°

300

±0.7

±13

±14

200

±3

±60

±35

140

±3.8

±10

±80

±300

±45

±300

120

±4

±13

±85

±400

±50

±400 dB nV/ √Hz pA/ √Hz pA/ √Hz k Ω mV

µ

V/°C

µ

A nA/°C

µ

A nA/°C

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Min

Max

Typ

Max

Typ

Max

Typ

4

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Product Folder Link(s):

THS3201

Copyright © 2003–2009, Texas Instruments Incorporated

Not Recommended for New Designs

THS3201 www.ti.com

.............................................................................................................................................................

SLOS416C – JUNE 2003 – REVISED JUNE 2009

ELECTRICAL CHARACTERISTICS: V

S

= ±7.5 V (continued)

At R

F

= 768 Ω, R

L

= 100 Ω, and G = +2, unless otherwise noted.

PARAMETER TEST CONDITIONS

TYP

+25°C +25°C

THS3201

OVER TEMPERATURE

0°C to –40°C to

+70°C +85°C

UNITS

MIN/

TYP/

MAX

INPUT

Common-mode input range

Common-mode rejection ratio

Inverting input impedance, Z in

Input resistance

Input capacitance

OUTPUT

Voltage output swing

Current output, sourcing

Current output, sinking

Closed-loop output impedance

POWER SUPPLY

Minimum operating voltage

Maximum operating voltage

Maximum quiescent current

Power-supply rejection (+PSRR)

Power-supply rejection (–PSRR)

V

CM

= ±3.75 V

Open loop

Noninverting

Inverting

Noninverting

R

L

= 1 k Ω

R

L

= 100 Ω

R

L

= 20 Ω

G = +1, f = 1 MHz

Absolute minimum

Absolute maximum

V

S+

= 7 V to 8 V

V

S–

= –7 V to –8 V

±6

±5.8

115

100

0.01

±5.1

71

16

780

11

1

14

69

65

±5

60

±5.9

±5.7

105

85

±3.3

±8.25

18

63

58

±5

58

±5.8

±5.5

100

80

±3.3

±8.25

21

60

55

±5

58

±5.8

±5.5

100

80

±3.3

±8.25

21

60

55

V

V mA dB dB

V

V mA mA

Ω k Ω

Ω pF

V dB

Min

Max

Max

Min

Min

Min

Min

Min

Min

Typ

Min

Min

Typ

Typ

Typ

Typ

Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s):

THS3201

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5

Not Recommended for New Designs

THS3201

SLOS416C – JUNE 2003 – REVISED JUNE 2009 .............................................................................................................................................................

www.ti.com

ELECTRICAL CHARACTERISTICS: V

S

= ±5 V

At R

F

= 715 Ω, R

L

= 100 Ω, and G = +2, unless otherwise noted.

PARAMETER TEST CONDITIONS

TYP

+25°C +25°C

THS3201

OVER TEMPERATURE

0°C to –40°C to

+70°C +85°C

UNITS

MIN/

TYP/

MAX

AC PERFORMANCE

Small-signal bandwidth, –3dB

(V

O

= 200 mV

PP

)

Bandwidth for 0.1 dB flatness

Large-signal bandwidth

Slew rate

Rise and fall time

Settling time to 0.1%

Settling time to 0.01%

Harmonic distortion

2 nd

-order harmonic

3 rd

-order harmonic

Third-order intermodulation distortion (IMD

3

)

G = +1, R

F

= 1.2 k Ω

G = +2, R

F

= 715 Ω

G = +5, R

F

= 576

G = +10, R

F

= 464 Ω

G = +2, V

O

= 200 mV

PP

G = +2, V

O

= 2 V

PP

G = +2, V

O

= 5-V step, Rise/Fall

G = +2, V

O

= 4-V step, Rise/Fall

G = –2, V

O

= 2-V step

1.3

725

540

480

170

900

5200/4000

0.7/0.9

20

60

–69

–75

–81

GHz

MHz

MHz

MHz

V/

µ s ns ns ns dBc dBc dBc

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Noise figure

Input voltage noise

Input current noise (noninverting)

Input current noise (inverting)

Differential gain

Differential phase

DC PERFORMANCE

Open-loop transimpedance gain

Input offset voltage

Average offset voltage drift

Input bias current (inverting)

Average bias current drift (–)

Input bias current (noninverting)

Average bias current drift (+)

G = +5, f = 10 MHz,

V

O

= 2 V pp

R

L

= 100 Ω

R

L

= 100 Ω

G = +10, f c

V

O(envelope)

= 20 MHz,

= 2 V

PP

Δf = 1 MHz,

G = +10, f c

R

G

= 28

= 100 MHz, R

F

= 255 Ω, f > 10 MHz f > 10 MHz

G = +2, R

R

F

L

= 768 Ω

= 150 Ω,

NTSC

PAL

NTSC

PAL

V

O

= +1 V, R

L

= 1 k Ω

V

CM

= 0 V

11

1.65

13.4

20

0.006%

0.004%

0.03°

0.04°

300

±0.7

±13

±14

200

±3

±60

±35

140

±3.8

±10

±80

±300

±45

±300

120

±4

±13

±85

±400

±50

±400 dB nV/ √Hz pA/ √Hz pA/ √Hz k Ω mV

±V/°C

µ

A nA/°C

µ

A nA/°C

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Typ

Min

Max

Typ

Max

Typ

Max

Typ

6

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Product Folder Link(s):

THS3201

Copyright © 2003–2009, Texas Instruments Incorporated

Not Recommended for New Designs

THS3201 www.ti.com

.............................................................................................................................................................

SLOS416C – JUNE 2003 – REVISED JUNE 2009

ELECTRICAL CHARACTERISTICS: V

S

= ±5 V (continued)

At R

F

= 715 Ω, R

L

= 100 Ω, and G = +2, unless otherwise noted.

PARAMETER TEST CONDITIONS

TYP

+25°C +25°C

THS3201

OVER TEMPERATURE

0°C to –40°C to

+70°C +85°C

UNITS

MIN/

TYP/

MAX

INPUT

Common-mode input range

Common-mode rejection ratio

Inverting input impedance, Z

IN

Input resistance

Input capacitance

OUTPUT

Voltage output swing

Current output, sourcing

Current output, sinking

Closed-loop output impedance

POWER SUPPLY

Minimum operating voltage

Maximum operating voltage

Maximum quiescent current

Power-supply rejection (+PSRR)

Power-supply rejection (–PSRR)

V

CM

= ±2.5 V

Open loop

Noninverting

Inverting

Noninverting

R

L

= 1 k Ω

R

L

= 100 Ω

R

L

= 20 Ω

G = +1, f = 1 MHz

Absolute minimum

Absolute maximum

V

S+

= 4.5 V to 5.5 V

V

S–

= –4.5 V to –5.5 V

±3.65

±3.45

115

100

0.01

±2.6

71

17.5

780

11

1

14

69

65

±2.5

60

±3.5

±3.33

105

85

±3.3

±8.25

16.8

63

58

±2.5

58

±3.45

±3.25

100

80

±3.3

±8.25

19

60

55

±2.5

58

±3.4

±3.2

100

80

±3.3

±8.25

20

60

55

V mA mA

V

V mA dB dB k Ω

Ω pF

V dB

Min

Min

Min

Typ

Min

Max

Max

Min

Min

Min

Min

Typ

Typ

Typ

Typ

Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s):

THS3201

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THS3201

SLOS416C – JUNE 2003 – REVISED JUNE 2009 .............................................................................................................................................................

www.ti.com

TYPICAL CHARACTERISTICS

Table of Graphs (V

S

= ±7.5 V)

Noninverting small-signal frequency response

Inverting small-signal frequency response

Noninverting large-signal frequency response

Inverting large-signal frequency response

0.1 dB gain flatness frequency response

Capacitive load frequency response

Recommended switching resistance

2nd harmonic distortion

3rd harmonic distortion

2nd harmonic distortion, G = 2

3rd harmonic distortion, G = 2

2nd harmonic distortion, G = 5

3rd harmonic distortion, G = 5

2nd harmonic distortion, G = 10

3rd harmonic distortion, G = 10

Third-order intermodulation distortion (IMD

3

)

S-Parameter

Input voltage and current noise

Noise figure

Transimpedance

Input offset voltage

Input bias and offset current

Slew rate

Settling time

Quiescent current

Output voltage

Rejection ratio

Noninverting small-signal transient response

Inverting large-signal transient response

Overdrive recovery time

Differential gain

Differential phase

Closed-loop output impedance vs Capacitive Load vs Frequency vs Frequency vs Output voltage vs Output voltage vs Output voltage vs Output voltage vs Output voltage vs Output voltage vs Frequency vs Frequency vs Frequency vs Frequency vs Frequency vs Case Temperature vs Case Temperature vs Output voltage step vs Supply voltage vs Load resistance vs Frequency vs Number of loads vs Number of loads vs Frequency

26, 27

28

29

30

31

21

22

23

24

25

32

33

34

35

36

15

16

17

18, 19

20

10

11

12

13

14

FIGURE

1, 2

3

4

5

6

7

8

9

8

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Product Folder Link(s):

THS3201

Copyright © 2003–2009, Texas Instruments Incorporated

Not Recommended for New Designs

THS3201 www.ti.com

.............................................................................................................................................................

SLOS416C – JUNE 2003 – REVISED JUNE 2009

Table of Graphs (V

S

= ±5 V)

Noninverting small-signal frequency response

Inverting small-signal frequency response

0.1 dB gain flatness frequency response

2nd harmonic distortion

3rd harmonic distortion

2nd harmonic distortion, G = 2

3rd harmonic distortion, G = 2

2nd harmonic distortion, G = 5

3rd harmonic distortion, G = 5

2nd harmonic distortion, G = 10

3rd harmonic distortion, G = 10

Third-order intermodulation distortion (IMD

3

)

S-Parameter

Slew rate

Noninverting small-signal transient response

Inverting large-signal transient response

Overdrive recovery time vs Frequency vs Frequency vs Output voltage vs Output voltage vs Output voltage vs Output voltage vs Output voltage vs Output voltage vs Frequency vs Frequency vs Output voltage step

FIGURE

37

38

39

40

41

42

43

44

45

46

47

48

49, 50

51

52

53

54

Copyright © 2003–2009, Texas Instruments Incorporated

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THS3201

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THS3201

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www.ti.com

16

14

12

10

8

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

7

R

F

= 619

R

F

= 768

6

5

R

F

= 1 k

4

3

2

1

Gain = 2.

R

L

= 100

,

V

O

V

S

= 0.2 V

PP

=

±

7.5 V

.

0

100 k 1 M 10 M 100 M

f - Frequency - Hz

Figure 1.

1 G 10 G

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

G =-5, R

F

= 576

8

6

G = 2, R

F

= 715

4

2

R

L

= 100

,

V

O

V

S

= 2 V

PP

.

=

±

7.5 V

0

100 k 1 M 10 M

f - Frequency - Hz

100 M

Figure 4.

1 G

16

14

12

CAPACITIVE LOAD

FREQUENCY RESPONSE

R

(ISO)

= 30

, C

L

= 22 pF

R

(ISO)

= 20

,

C

L

= 50 pF

10

8

6

Gain = 5

R

F

R

V

L

S

= 619

= 100

=

±

7.5 V

4

2

0

R

(ISO)

= 15

,

C

L

= 100 pF

R

(ISO)

= 20

,

C

L

= 47 pF

-2

0 100 200 300

f - Frequency - MHz

400 500

Figure 7.

V

S

= ±7.5 V Graphs

NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

24

22

G = 10, R

F

= 487

20

18

16

G = 5, R

F

= 619

14

12

10

8

R

L

= 100

,

V

O

V

S

= 0.2 V

PP

=

±

7.5 V

.

G = 2, R

F

= 768

6

0

-2

4

2

G =1, R

-4

100 k 1 M

F

= 1.2 k

10 M 100 M 1 G 10 G

f - Frequency - Hz

Figure 2.

INVERTING LARGE-SIGNAL

FREQUENCY RESPONSE

16

14

12

G =-5, R

F

= 549

10

8

6

R

L

= 100

,

V

O

V

S

= 2 V

PP

=

±

7.5 V

.

4

2

0

-2

-4

100 k

G = -1, R

F

= 576

1 M 10 M

f - Frequency - Hz

100 M

Figure 5.

1 G

60

50

RECOMMENDED R

ISO vs

CAPACITIVE LOAD

Gain = 5,

R

F

R

L

= 619

= 100

,

V

S

=

±

7.5 V

40

30

20

10

0

10

_

+

R

ISO

C

L

C

L

- Capacitive Load - pF

Figure 8.

100

6.4

6.3

6.2

6.1

6

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

24

22

G = -10, R

F

= 499

20

18

16

14

12

G = -5, R

F

= 549

R

L

= 100

,

V

O

V

S

= 0.2 V

PP

=

±

7.5 V

.

10

8

6

4

G = -2, R

F

= 576

2

0

-2

G = -1, R

F

= 619

-4

100 k 1 M 10 M 100 M 1 G 10 G

f - Frequency - Hz

Figure 3.

0.1 dB GAIN FLATNESS

FREQUENCY RESPONSE

Gain = 2,

R

F

R

L

= 768

,

= 100

,

V

O

V

S

= 0.2 V

PP

=

±

7.5 V

,

5.9

5.8

5.7

5.6

100 k 1 M 10 M 100 M

f - Frequency - Hz

Figure 6.

1 G 10 G

-40

-50

-60

2nd HARMONIC DISTORTION vs

FREQUENCY

G = 10

R = 499

W

, R

G

= 54.9

W

G = 5

R = 619

W

,

R

G

= 154

W

-70

-80

-90

G = 2

R = 768

W

, R

G

= 768

W

Vs =

V out

±7.

5V

= 2V

PP

W

-100

1 10 f - Frequency - MHz

Figure 9.

100

10

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SLOS416C – JUNE 2003 – REVISED JUNE 2009

V

S

= ±7.5 V Graphs (continued)

-60

-70

-80

-90

-100

-110

0

3rd HARMONIC DISTORTION vs

FREQUENCY

-80

-85

-90

-95

-100

1

-60

-65

-70

-75

G = 2

R = 768

W

, R

G

= 768

W

Vs =

V out

±7.

5V

= 2V

PP

W

G = 5

R = 619

W

, R

G

= 154

W

G = 10

R = 499

W

, R

G

= 54.9

W

10 f - Frequency - MHz

Figure 10.

100

2nd HARMONIC DISTORTION

G = 5 vs

OUTPUT VOLTAGE

-30

-40

-50

Vs =

G = 5

±7.

5V

F

W

, R

G

= 154

W

32MHz

64MHz

16MHz

8MHz

4MHz

2MHz

1MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 13.

5 6

-60

-70

-80

-90

-100

-110

0

3rd ORDER HARMONIC DISTORTION

G = 10 vs

OUTPUT VOLTAGE

-30

-40

Vs = ±7.

G = 10

5V

F

W

, R

G

= 54.9

W

32MHz

-50

64MHz

16MHz

8MHz

4MHz 2MHz

1MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 16.

5 6

-30

-40

-50

-60

-70

-80

-90

-100

-110

0

2nd HARMONIC DISTORTION

G = 2 vs

OUTPUT VOLTAGE

Vs =

G = 2

±7.

5V

F

W

, R

G

= 768

W

64MHz

32MHz

16MHz

8MHz

4MHz

2MHz

1MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 11.

5 6

-60

-70

-80

-90

-100

-110

0

-30

-40

-50

3rd HARMONIC DISTORTION

G = 5 vs

OUTPUT VOLTAGE

Vs =

G = 5

±7.

5V

F

W

, R

G

= 154

W

32MHz

64MHz

16MHz

8MHz

4MHz

2MHz

1MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 14.

5 6

-40

3rd ORDER INTERMODULATION

DISTORTION vs

FREQUENCY

-50

Vs =

V out

±7.

5V

= 2V

PP

R = 100

W

G10

R = 499

W

, R

G

= 54.9

W

-60

-70

-80

-90

-100

10 20

G2

R = 768

W

, R

G

= 768

W

G5

R = 619

W

, R

G

= 154

W

80 90 100 30 40 50 60 70 f - Frequency - MHz

Figure 17.

-60

-70

-80

-90

-100

-110

0

-60

-70

-80

3rd HARMONIC DISTORTION

G = 2 vs

OUTPUT VOLTAGE

-30

-40

Vs =

G = 2

±7.

5V

F

W

, R

G

= 768

W

-50

64MHz

32MHz

-90

-100

-110

0

1MHz

16MHz

8MHz

4MHz

2MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 12.

5 6

2nd ORDER HARMONIC DISTORTION

G = 10 vs

OUTPUT VOLTAGE

-30

-40

Vs = ±7.

5V, G = 10

R = 499

W

, R

G

= 54.9

W

32MHz

64MHz

W

-50

16MHz 8MHz

4MHz

2MHz

1MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 15.

5 6

-20

0

V

S

=

±

7.5 V

Gain = +10

C = 0 pF

S-PARAMETER vs

FREQUENCY

S11

-40

S22

-60

-80

-100

1 M

S12

R

G

R

F

C

-

+

50

50

50

50

Source

10 M 100 M

f - Frequency - Hz

1 G 10 G

Figure 18.

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V

S

= ±7.5 V Graphs (continued)

-20

0

V

S

=

±

7.5 V

Gain = +10

C = 3.3 pF

S-PARAMETER vs

FREQUENCY

-40

S22

S12

-60

-80

-100

1 M

S11

R

G

R

F

C

-

+

50

50

50

50

Source

10 M 100 M

f - Frequency - Hz

1 G

Figure 19.

10 G

120

TRANSIMPEDANCE vs

FREQUENCY

V

S

=

±

5 and

±

7.5V

100

80

60

40

10

20

0

100 k

+

_

_

+

Gain W +

I

V

O

IB

1 M 10 M

f - Frequency - Hz

100 M

Figure 22.

1 G

SLEW RATE vs

OUTPUT VOLTAGE

10000

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

1

SR+

SR-

2 3 4 5 6 7 8

V out -

Output Voltage - Vstep

Figure 25.

9 10

1.5

1

0.5

50

45

40

35

30

25

20

15

10

100 k

3

2.5

2

1.5

1

INPUT VOLTAGE AND

CURRENT NOISE vs

FREQUENCY

V

S

T

A

=

±

7.5 V and

±

5 V

= 25

°

C

V n

V

S

=

±

7.5 V

Inverting

Noise Current

Noninverting

Current Noise

1 M 10 M

f - Frequency - Hz

100 M

Figure 20.

INPUT OFFSET VOLTAGE vs

CASE TEMPERATURE

V

S

=

±

5 V

0.5

0

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90

T

C

- Case Temperature -

°

C

Figure 23.

4

3.5

3

2.5

1.5

0.5

0

NOISE FIGURE vs

FREQUENCY

14

13

12

11

10

9

8

7

6

0

Gain = +10

R

G

R

F

V

S

= 28

= 255

=

±

7.5 V &

±

5 V

50 100 150 200 250 300 350 400

f - Frequency - MHz

Figure 21.

17

16

INPUT BIAS AND OFFSET CURRENT vs

CASE TEMPERATURE

7

V

S

=

±

7.5 V

6

15

I

IB

5

14

4

I

IB

+

13

3

12

I IB

11

I

OS

2

1

10

-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90

0

T

C

- Case Temperature -

°

C

Figure 24.

I OS

0

-0.5

-1

-1.5

0

SETTLING TIME

Rising Edge

Gain = -2

R

L

R

F

= 100

= 576

Ω f= 1 MHz

V

S

=

±

7.5 V

Falling Edge

2 4

t - Time - ns

6

Figure 26.

8 10

3

2.5

0

-0.5

-1

-1.5

-2

-2.5

-3

2

1.5

1

0.5

0

SETTLING TIME

Rising Edge

Gain = -2

R

R

L

= 100

F

= 576

Ω f= 1 MHz

V

S

=

±

7.5 V

Falling Edge

2.5

5

t - Time - ns

7.5

Figure 27.

10 12.5

12

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.............................................................................................................................................................

SLOS416C – JUNE 2003 – REVISED JUNE 2009

V

S

= ±7.5 V Graphs (continued)

QUIESCENT CURRENT vs

SUPPLY VOLTAGE

20

18

16

14

T

A

= 85

°

C

T

A

= 25

°

C

12

10

8

T

A

= -40

°

C

6

4

2

0

2 2.5

3 3.5

4 4.5

5 5.5

6 6.5

7 7.5

V

S

- Supply Voltage -

±

V

Figure 28.

0.3

NONINVERTING SMALL-SIGNAL

TRANSIENT RESPONSE

Output

0.2

0.1

0

-0.1

-0.2

-0.3

0.030

0.025

0.020

0.015

0.010

Input

Gain = 2

R

R

V

L

= 100

F =

715

S

=

±

7.5 V

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t - Time -

µ

s

Figure 31.

DIFFERENTIAL GAIN vs

NUMBER OF LOADS

Gain = 2

R

V

F

= 768

S

=

±

7.5 V

40 IRE - NTSC and Pal

Worst Case

±

100 IRE Ramp

PAL

NTSC

0.005

0

0 1 2 3 4 5 6

Number of Loads - 150

Figure 34.

7 8

4

3

2

6

5

1

0

-1

-2

-3

-4

-5

-6

OUTPUT VOLTAGE vs

LOAD RESISTANCE

-3

-4

-5

-6

-7

0

-1

-2

10

5

4

3

2

1

7

6

V

S

T

A

=

±

7.5 V

= -40 to 85

°

C

100

R

L

- Load Resistance -

Figure 29.

INVERTING LARGE-SIGNAL

TRANSIENT RESPONSE

1000

Gain = -5

R

R

V

L

= 100

F =

549

S

=

±

7.5 V

Input

Output

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t - Time -

µ

s

Figure 32.

DIFFERENTIAL PHASE vs

NUMBER OF LOADS

0.040

0.035

°

0.030

0.025

0.020

0.015

0.010

0.005

0

0

Gain = 2

R

F

V

S

= 768 k

=

±

7.5 V

40 IRE - NTSC and Pal

Worst Case

±

100 IRE Ramp

PAL

NTSC

1 2 3 4 5 6

Number of Loads - 150

Figure 35.

7 8

80

70

60

REJECTION RATIO vs

FREQUENCY

V

S

=

±

7.5 V

CMRR

50

40

30

20

10

0

100 k

PSRR+

1 M 10 M

f - Frequency - Hz

Figure 30.

100 M

0

-2

-4

-6

-8

-10

0

10

8

6

4

2

OVERDRIVE RECOVERY TIME

5

G = 2,

R

F

V

S

= 768

,

=

±

7.5 V

4

3

2

1

0.2

-3

-4

1

-5

0

-1

-2

0.4

0.6

t - Time -

µ

s

Figure 33.

0.8

CLOSED-LOOP OUTPUT IMPEDANCE vs

FREQUENCY

1000

100

10

Gain = 2

R

F

R

L

V

S

= 715

= 100

=

±

7.5 V

1

0.1

0.01

0.001

100 k 1 M 10 M

f - Frequency - Hz

Figure 36.

1 M 1 G

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NONINVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

24

22

20

G = 10, R

F

= 464

18

16

14

12

G = 5, R

F

= 576

10

R

L

= 100

,

V

O

V

S

= 0.2 V

=

±

5 V

PP

.

G = 2, R

F

= 715

8

6

4

2 G =1, R

F

= 1.2 k

0

-2

-4

100 k 1 M 10 M 100 M 1 G 10 G

f - Frequency - Hz

Figure 37.

2nd HARMONIC DISTORTION vs

FREQUENCY

-40

-50

-60

G = 10

R = 464

W

, R

G

= 51.1

W

G = 5

R = 576

W

,

R

G

= 143

W

-70

-80

-90

-100

1

V out

= 2V

PP

W

G = 2

R = 715

W

, R

G

= 715

W

10 100 f - Frequency - MHz

Figure 40.

3rd ORDER HARMONIC

DISTORTION, G = 2 vs

OUTPUT VOLTAGE

-30

-40

G = 2

F

W

, R

G

= 715

W

64MHz

-50

-60

-70

-80

-90

-100

-110

0

32MHz

1MHz

2MHz

4MHz

8MHz

16MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 43.

5 6

V

S

= ±5 V Graphs

INVERTING SMALL-SIGNAL

FREQUENCY RESPONSE

18

16

14

12

10

8

6

4

2

24

22

20

R

V

V

L

O

S

G = -10, R

G = -5, R

= 100

= 0.2 V

=

±

5 V

,

PP

.

G = -2, R

F

F

F

= 499

= 549

= 576

0

-2

-4

G =-1, R

100 k 1 M

F

= 576

10 M 100 M 1 G 10 G

f - Frequency - Hz

Figure 38.

3rd ORDER HARMONIC DISTORTION vs

FREQUENCY

-60

-65

G = 2

R = 715

W

, R

G

= 715

W

-70

-75

-80

V out

= 2V

PP

W

-85

-90

-95

-100

1

G = 5

R = 576

W

, R

G

= 143

W

G = 10

R = 464

W

, R

G

= 51.1

W

10 f - Frequency - MHz

100

Figure 41.

2nd ORDER HARMONIC

DISTORTION, G = 5 vs

OUTPUT VOLTAGE

-30

-40

G = 5

F

W

, R

G

= 143

W

-50

-60

-70

-80

32MHz

64MHz

1MHz

2MHz

-90

-100

16MHz

8MHz

4MHz

-110

0 1 2 3 4

V out

Output Voltage - V

PP

Figure 44.

5 6

6.4

6.3

6.2

0.1 dB GAIN FLATNESS

FREQUENCY RESPONSE

Gain = 2,

R

R

F

= 715

,

L

= 100

,

V

V

O

= 0.2 V

PP

,

S

=

±

5 V

6.1

6

5.9

5.8

5.7

5.6

100 k 1 M 10 M 100 M

f - Frequency - Hz

Figure 39.

1 G 10 G

-60

-70

-80

-90

-100

2nd ORDER HARMONIC DISTORTION

G = 2 vs

OUTPUT VOLTAGE

-30

-40

G = 2

RF = 715

W

, RG = 715

W

64MHz

-50

32MHz

16MHz

8MHz

4MHz

1MHz

2MHz

-110

0 6 1 2 3 4

V out

Output Voltage - V

PP

5

Figure 42.

-30

-40

-50

3rd ORDER HARMONIC

DISTORTION, G = 5 vs

OUTPUT VOLTAGE

64MHz

G = 5

F

W

, R

G

= 143

W

-60

-70

-80

-90

-100

-110

0

32MHz

1MHz

2MHz

4MHz

8MHz

16MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 45.

5 6

14

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.............................................................................................................................................................

SLOS416C – JUNE 2003 – REVISED JUNE 2009

V

S

= ±5 V Graphs (continued)

-60

-70

-80

-90

-100

-110

0

2nd ORDER HARMONIC

DISTORTION, G = 10 vs

OUTPUT VOLTAGE

-30

-40

R = 464

W

, R

G

= 51.1

W

32MHz

W

64MHz

-50

16MHz

8MHz

4MHz

1MHz

2MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 46.

5 6

-20

0

V

S

=

±

5 V

Gain = +10

C = 0 pF

S-PARAMETER vs

FREQUENCY

3rd ORDER HARMONIC

DISTORTION, G = 10 vs

OUTPUT VOLTAGE

-30

-40

-50

G = 10

F

W

, R

G

= 51.1

W

W

64MHz

-60

-70

32MHz

1MHz

-80

-90

-100

-110

0

2MHz

4MHz

8MHz

16MHz

1 2 3 4

V out

Output Voltage - V

PP

Figure 47.

5 6

-20

0

V

S

=

±

5 V

Gain = +10

C = 3.3 pF

S-PARAMETER vs

FREQUENCY

-65

-70

-75

-50

3rd ORDER INTERMODULATION

DISTORTION vs

FREQUENCY

-55

-60

V out

= 2V

PP

R = 100

W

G2

R = 715

W

, R

G

= 715

W

-80

-85

-90

-95

-100

10

G10

R = 464

W

,

R

G

= 51.1

W

G5

R = 576

W

,

R

G

= 143

W

80 90 100 20 30 40 50 60 70 f - Frequency - MHz

Figure 48.

SLEW RATE vs

OUTPUT VOLTAGE

6000

5000

SR+

4000

-40

S22

S12

-60

-80

-100

1 M

S11

R

G

R

F

C

-

+

50

50

50

50

Source

10 M 100 M

f - Frequency - Hz

1 G 10 G

Figure 49.

0.3

NONINVERTING SMALL-SIGNAL

TRANSIENT RESPONSE

Output

0.2

0.1

0

-0.1

-0.2

-0.3

Input

Gain = 2

R

V

L

S

= 100

R

F =

715

=

±

5 V

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t - Time -

µ

s

Figure 52.

3

2.5

2

1.5

1

0.5

-0.5

0

-1

-1.5

-2

-2.5

-3

-40

S22

S12

-60

-80

-100

1 M

S11

R

G

R

F

C

-

+

50

50

50

50

Source

10 M 100 M

f - Frequency - Hz

1 G 10 G

Figure 50.

INVERTING LARGE-SIGNAL

TRANSIENT RESPONSE

Gain = -5

R

V

L

S

= 100

R

F =

549

=

±

5 V

Input

Output

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

t - Time -

µ

s

Figure 53.

6

4

2

0

-2

-4

-6

0

3000

2000

1000

0

1

0.2

SR-

2 3 4

V out -

Output Voltage - Vstep

Figure 51.

OVERDRIVE RECOVERY TIME

3

G = 2,

R

F

= 715

,

V

S

=

±

5 V

2

1

0.4

0.6

t - Time -

µ

s

Figure 54.

0.8

-2

1

-3

0

-1

5

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APPLICATION INFORMATION

WIDEBAND, NONINVERTING OPERATION

The THS3201 is a unity-gain stable, 1.8-GHz current-feedback operational amplifier, designed to operate from a ±3.3-V to ±7.5-V power supply.

Figure 55

shows the THS3201 in a noninverting gain of 2-V/V configuration typically used to generate the performance curves.

Most of the curves were characterized using signal sources with 50-

Ω source impedance, and with measurement equipment presenting a 50-

Ω load impedance. The 49.9-Ω shunt resistor at the V

I terminal in

Figure 55

source impedance of the test generator.

matches the

7.5 V

+V

S

50

Source

V

I

49.9

768

+

100 pF

0.1

µ

F 6.8

µ

F

R

G

+

THS3201

_

R

F

768

49.9

50

100 pF

0.1

µ

F 6.8

µ

F

+

-7.5 V

-V

S

Figure 55. Wideband, Noninverting

Gain Configuration

Unlike voltage-feedback amplifiers, current-feedback amplifiers are highly dependent on the feedback resistor R

F for maximum performance and stability.

Table 1

shows the optimal gain setting resistors R

F and R

G at different gains to give maximum bandwidth with minimal peaking in the frequency response.

Higher bandwidths can be achieved, at the expense of added peaking in the frequency response, by using even lower values for R

F

. Conversely, increasing R decreases the bandwidth, but stability is improved.

F

Table 1. Recommended Resistor Values for

Optimum Frequency Response

Gain

(V/V)

1

2

5

10

–1

–2

–5

–10

THS3201 R

F for AC When R

LOAD

= 100 Ω

Supply Voltage

(V)

R

G

( Ω)

±7.5

±5

(

R

F

Ω)

1.2 k

1.2 k

±7.5

±5

±7.5

±5

±7.5

768

715

154.9

143

54.9

768

715

619

576

487

±5

±7.5

±5

±7.5 and ±5

±7.5 and ±5

±7.5 and ±5

51.1

619

576

287

110

49.9

464

619

576

576

549

499

WIDEBAND, INVERTING GAIN OPERATION

Figure 56

shows the THS3201 in a typical inverting gain configuration where the input and output impedances and signal gain from

Figure 55

are retained in an inverting circuit configuration.

7.5 V

+V

S

50

Source

V

I

R

G

287

R

M

60.4

+

THS3201

_

+

100 pF

0.1

µ

F 6.8

µ

F

49.9

50

R

F

576

100 pF

0.1

µ

F 6.8

µ

F

+

-7.5 V

-V

S

Figure 56. Wideband, Inverting Gain

Configuration

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SINGLE-SUPPLY OPERATION

The THS3201 has the capability to operate from a single supply voltage ranging from 6.6 V to 15 V.

When operating from a single power supply, care must be taken to ensure the input signal and amplifier are biased appropriately to allow for the maximum output voltage swing. The circuits shown in

Figure 57

demonstrate methods to configure an amplifier in a manner conducive for single-supply operation.

+V

S

50

Source

V

I

R

T

49.9

+

THS3201

_

49.9

50

+V

S

2

R

F

768

R

G

768

+V

S

2

R

F

V

S

576

50

Source

R

G

_

V

I

60.4

49.9

R

287

T

THS3201

+

50

+V

S

2

+V

S

2

Figure 57. DC-Coupled Single-Supply Operation

V

I

768

768

±

7.5 V

THS3201

-

+

±

7.5 V

75

ADC DRIVER APPLICATION

75

V

O(n)

The THS3201 can be used as a high-performance

ADC driver in applications like radio receiver IF stages, and test and measurement devices. All high-performance ADCs have differential inputs. The

THS3201 can be used in conjunction with a transformer as a drive amplifier in these applications.

Figure 59

and

Figure 60

show two different approaches.

In

Figure 59

, a transformer is used after the amplifier to convert the signal to differential. The advantage of this approach is fewer components are required.

R

OUT and R

T are required for impedance matching the transformer.

V

S+

75

75-

Transmission Line n Lines

75

75

Figure 58. Video Distribution Amplifier

Application

V

O(1)

0.1

µ

F

R

G

R

F

VIDEO HDTV DRIVERS

The exceptional bandwidth and slew rate of the

THS3201 matches the demands for professional video and HDTV. Most commercial HDTV standards requires a video passband of 30-MHz. To ensure high signal quality with minimal degradation of performance, a 0.1-dB gain flatness should be at least 7x the passband frequency to minimize group delay variations—requiring 210-MHz 0.1-dB frequency flatness from the amplifier. High slew rates ensure there is minimal distortion of the video signal.

Component video and RGB video signals require fast transition times and fast settling times to keep a high signal quality. The THS8135 , for example, is a

240-MSPS video digital-to-analog converter (DAC) and has a transition time approaching 4 ns. The

THS3201 is a perfect candidate for interfacing the output of such high-performance video components.

V

IN

THS3201

V

S-

R

OUT

1:n

24.9

R

T

47pF

24.9

47pF

ADC

CM

0.1

µ

F

0.1

µ

F

Figure 59. Differential ADC Driver Circuit 1

In

Figure 60 , a transformer is used before two

amplifiers to convert the signal to differential. The two amplifiers then amplify the differential signal. The advantage to this approach is each amplifier is required to drive half the voltage as before. R

T used to impedance match the transformer.

is

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V

IN

1:n

R

G

0.1

µ

F

R

G

R

T

V

S+

R

F

THS3201

THS3201

R

F

V

S-

24.9

47pF

24.9

47pF

ADC

CM

0.1

µ

F

Typically, a low value resistor in the range of 10

Ω to

100 Ω provides the required isolation. Together, the

R and C form a real pole in the s-plane located at the frequency: f

P

+

1

2 p RC

Placing this pole at about 10x the highest frequency of interest ensures it has no impact on the signal.

Since the resistor is typically a small value, it is very bad practice to place the pole at (or very near) frequencies of interest. At the pole frequency, the amplifiers sees a load with a magnitude of:

Ǹ

2 x R

If R is only 10 Ω, the amplifier is very heavily loaded above the pole frequency, and generates excessive distortion.

0.1

µ

F

Figure 60. Differential ADC Driver Circuit 2

It is almost universally recommended to use a resistor and capacitor between the op amp output and the ADC input as shown in both figures.

This resistor-capacitor (RC) combination has multiple functions:

The capacitor is a local charge reservoir for ADC

The resistor isolates the amplifier from the ADC

In conjunction, they form a low-pass noise filter

During the sampling phase, current is required to charge the ADC input sampling capacitors. By placing external capacitors directly at the input pins, most of the current is drawn from them. They are seen as a very low impedance source. They can be thought of as serving much the same purpose as a power-supply bypass capacitor to supply transient current, with the amplifier then providing the bulk charge.

Typically, a low-value capacitor in the range of 10 pF to 100 pF provides the required transient charge reservoir.

The capacitance and the switching action of the ADC is one of the worst loading scenarios that a high-speed amplifier encounters.

The resistor provides a simple means of isolating the associated phase shift from the feedback network and maintaining the phase margin of the amplifier.

DAC DRIVER APPLICATION

The THS3201 can be used as a high-performance

DAC output driver in applications like radio transmitter stages and arbitrary waveform generators.

All high-performance DACs have differential current outputs. Two THS3201s can be used as a differential drive amplifier in these applications, as shown in

Figure 61 .

R

PU on the DAC output is used to convert the output current to voltage. The 24.9Ω resistor and 47-pF capacitor between each DAC output and the op amp input is used to reduce the images generated at multiples of the sampling rate. The values shown form a pole at 136 MHz. R impedance of each amplifier.

OUT sets the output

V

S+

AV

DD

IOUT1

DAC

IOUT2

R

PU

R

PU

AV

DD

24.9

47pF

24.9

47pF

R

G

0.1

µ

F

R

G

THS3201

R

F

V

S-

R

F

THS3201

R

OUT

V

OUT1

R

OUT

V

OUT2

0.1

µ

F

Figure 61. Differential DAC Driver Circuit

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PRINTED CIRCUIT BOARD LAYOUT

TECHNIQUES FOR OPTIMAL

PERFORMANCE

Achieving optimum performance with high frequency amplifier-like devices in the THS3201 requires careful attention to board layout parasitic and external component types.

Recommendations that optimize performance include:

Minimize parasitic capacitance to any power or ground plane for the negative input and output pins by voiding the area directly below these pins and connecting traces and the feedback path.

Parasitic capacitance on the output and negative input pins can cause instability.

To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins and the feedback path. Otherwise, ground and power planes should be unbroken elsewhere on the board.

Minimize the distance (<0.25") from the power-supply pins to high frequency 0.1-

µ

F and

100 pF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors.

Larger (6.8

µ

F or more) tantalum decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the printed circuit board (PCB). The primary goal is to minimize the impedance seen in the differential-current return paths. For driving differential loads with the THS3201, adding a capacitor between the power-supply pins improves 2nd order harmonic distortion performance. This also minimizes the current loop formed by the differential drive.

Careful selection and placement of external components preserve the high-frequency performance of the THS3201. Resistors should be a very low reactance type.

Surface-mount resistors work best and allow a tighter overall layout. Again, keep their leads and PCB trace length as short as possible. Never use wirebound type resistors in a high frequency application.

Since the output pin and inverting input pins are the most sensitive to parasitic capacitance, always position the feedback and series output resistors, if any, as close as possible to the inverting input pins and output pins. Other network components, such as input termination resistors, should be placed close to the gain-setting resistors. Even with a low parasitic capacitance shunting the external resistors, excessively high resistor values can create significant time constants that can degrade performance. Good axial metal-film or surface-mount resistors have approximately

0.2 pF in shunt with the resistor. For resistor values >2.0 k

Ω this parasitic capacitance can add a pole and/or a zero that can affect circuit operation.

Keep resistor values as low as possible, consistent with load driving considerations.

Connections to other wideband devices on the board may be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load.

Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and determine if isolation resistors on the outputs are necessary. Low parasitic capacitive loads (< 4 pF) may not need an R

S since the THS3201 is nominally compensated to operate with a 2-pF parasitic load. Higher parasitic capacitive loads without an R

S are allowed as the signal gain increases (increasing the unloaded phase margin). If a long trace is required, and the

6-dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques).

A 50Ω environment is not necessary onboard, and in fact, a higher impedance environment improves distortion as shown in the distortion versus load plots. With a characteristic board trace impedance based on board material and trace dimensions, a matching series resistor into the trace from the output of the THS3201 is used as well as a terminating shunt resistor at the input of the destination device.

Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is un-acceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case. This does not preserve signal integrity as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some signal attenuation due to the voltage divider formed by the series output into the terminating impedance.

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Socketing a high-speed part like the THS3201 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response.

Best results are obtained by soldering the

THS3201 parts directly onto the board.

Pin 1

0.205

0.060

0.013

0.017

0.075

0.030

0.025

0.094

PowerPAD DESIGN CONSIDERATIONS

The THS3201 is available in a thermally-enhanced

PowerPAD family of packages. These packages are constructed using a downset leadframe upon which the die is mounted [see

Figure 62

(a) and

Figure 62

(b)]. This arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see

Figure 62 (c)]. Because

this thermal pad has direct thermal contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from the thermal pad.

The PowerPAD package allows for both assembly and thermal management in one manufacturing operation. During the surface-mount solder operation

(when the leads are being soldered), the thermal pad can also be soldered to a copper area underneath the package. Through the use of thermal paths within this copper area, heat can be conducted away from the package into either a ground plane or other heat dissipating device.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of surface-mount with the, heretofore, awkward mechanical methods of heatsinking.

DIE

Side View (a)

Thermal

Pad

DIE

End View (b)

Bottom View (c)

Figure 62. Views of Thermally-Enhanced Package

Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the recommended approach.

0.010

vias

0.035

0.040

Top View

Figure 63. DGN PowerPAD PCB Etch and

Via Pattern

PowerPAD PCB LAYOUT CONSIDERATIONS

1. Prepare the PCB with a top side etch pattern as shown in

Figure 63 . There should be etch for the

leads as well as etch for the thermal pad.

2. Place five holes in the area of the thermal pad.

These holes should be 10 mils in diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.

3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps dissipate the heat generated by the THS3201 IC. These additional vias may be larger than the 10-mil diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be soldered so that wicking is not a problem.

4. Connect all holes to the internal ground plane.

5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In this application, however, low thermal resistance is desired for the most efficient heat transfer.

Therefore, the holes under the THS3201

PowerPAD package should make their connection to the internal ground plane with a complete connection around the entire circumference of the plated-through hole.

6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This prevents solder from

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SLOS416C – JUNE 2003 – REVISED JUNE 2009 being pulled away from the thermal pad area during the reflow process.

7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.

8. With these preparatory steps in place, the IC is simply placed in position and run through the solder reflow operation as any standard surface-mount component. This results in a part that is properly installed.

POWER DISSIPATION AND THERMAL

CONSIDERATIONS

To maintain maximum output capabilities, the

THS3201 does not incorporate automatic thermal shutoff protection. The designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction temperature of +150°C is exceeded.

For best performance, design for a maximum junction temperature of +125°C.

Between +125°C and

+150°C, damage does not occur, but the performance of the amplifier begins to degrade.

The thermal characteristics of the device are dictated by the package and the PCB. Maximum power dissipation for a given package can be calculated using the following formula.

P

DMax

=

T

Max

T

-

A q

JA

Where:

P

DMax is the maximum power dissipation in the amplifier (W)

T

Max is the absolute maximum junction temperature (°C)

T

A is the ambient temperature (°C)

• θ

JA

• θ

JC

=

θ

JC

+

θ

CA is the thermal coefficient from the silicon junctions to the case (°C/W)

• θ

CA is the thermal coefficient from the case to the ambient air (°C/W)

For systems where heat dissipation is more critical, the THS3201 is offered in an 8-pin MSOP with

PowerPAD and also available in the SOIC-8

PowerPAD package, offering even better thermal performance.

The thermal coefficients for the

PowerPAD packages are substantially improved over the traditional SOIC. Maximum power dissipation levels are depicted in the graph for the available packages. The data for the PowerPAD packages assume a board layout that follows the PowerPAD layout guidelines referenced above and detailed in the PowerPAD application note number SLMA002 .

The following graph also illustrates the effect of not soldering the PowerPAD to a PCB. The thermal impedance increases substantially which may cause serious heat and performance issues. Be sure to always solder the PowerPAD to the PCB for optimum performance.

4.0

T

J

= 125

°

C

3.5

3.0

2.5

2.0

1.5

θ

JA

= 58.4

θ

°

C/W

JA

= 98

°

C/W

1.0

0.5

0.0

θ

JA

= 158

°

C/W

-40 -20 0 20 40 60

T

A

- Free-Air Temperature -

°

C

80 100

Results are With No Air Flow and PCB Size = 3”x3”

θ

θ

θ

JA

JA

JA

= 58.4

°

C/W for 8-Pin MSOP w/PowerPad (DGN)

= 98

°

C/W for 8-Pin SOIC High Test PCB (D)

= 158

°

C/W for 8-Pin MSOP w/PowerPad w/o Solder

Figure 64. Maximum Power Dissipation vs Ambient Temperature

When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to not only consider quiescent power dissipation, but also dynamic power dissipation. Often times, this is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS power dissipation can provide visibility into a possible problem.

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DESIGN TOOLS

PD

J9*

Evaluation Fixture, Spice Models, and

Applications Support

Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal an evaluation board has been developed for the THS3201 operational amplifier. The board is easy to use, allowing for straightforward evaluation of the device.

The evaluation board can be ordered through the Texas

Instruments web site at www.ti.com

, or through your local Texas Instruments sales representative. The schematic diagram, board layers, and bill of materials of the evaluation boards are provided below.

J1

Vin-

0

J2

Vin+

49.9

R3

768

R2

R4

R5

Vs+

768

2

7

_

8

3

+

U1

6

4 1

Vs -

J8*

PD Ref

R6

49.9

C7*

C8*

J4

R7

Vout

Not Populated

*Does Not Apply to the THS3201

J6

GND TP1

J7

VS-

FB1

C1

+

22

µ

F

C6

0.1

µ

F

VS-

C5

100 pF

VS+

C4

100 pF

FB2

J5

VS+

C3

0.1

µ

F

+

C2

22

µ

F

Figure 65. THS3201 EVM Circuit Configuration

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Figure 66. THS3201 EVM Board Layout

(Top Layer)

Figure 68. THS3201 EVM Board Layout

(Third Layer, Power)

Figure 67. THS3201 EVM Board Layout

(Second Layer, Ground)

Copyright © 2003–2009, Texas Instruments Incorporated

Figure 69. THS3201 EVM Board Layout

(Bottom Layer)

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12

13

14

15

16

17

18

19

20

6

7

9

10

11

3

4

1

2

ITEM DESCRIPTION

Bead, ferrite, 3 A, 80 Ω

Cap, 22

µ

F, tanatalum, 25 V, 10%

Cap, 100 pF, ceramic, 5%, 150 V

Cap, 0.1

µ

F, ceramic, X7R, 50 V

Open

Resistor, 49.9

Ω, 1/8 W, 1%

Resistor, 768 Ω, 1/8 W, 1%

Open

Resistor, 0 Ω, 1/4 W, 1%

Resistor, 49.9

Ω, 1/4 W, 1%

Test point, black

Open

Jack, Banana Receptance, 0.25” dia. hole

Connector, edge, SMA PCB jack

Standoff, 4-40 hex, 0.625” length

Screw, Phillips, 4-40, .250”

IC, THS3201

Board, printed circuit

Table 2. Bill of Materials

(1)

THS3201DGN EVM

SMD SIZE REF DES

1206

D

AQ12

0805

0805

0805

0805

1206

1206

1206

FB1, FB2

C1, C2

C4, C5

C3, C6

R7

R6

R3, R5

C7, C8

R2

R4

TP1

J8, J9

J5, J6, J7

J1, J2, J4

U1

PCB MANUFACTURER'S

QUANTITY PART NUMBER

2

2

(Steward) HI1206N800R-00

(AVX) TAJD226K025R

2

2

(AVX) AQ12EM101JAJME

(AVX) 08055C104KAT2A

1

1

2

2

1

(Phycomp) 9C08052A49R9FKHFT

(Phycomp) 9C08052A7680FKHFT

1

3

3

1

2

(KOA) RK73Z2BLTD

(Phycomp) 9C12063A49R9FKRFT

(Keystone) 5001

4

4

1

1

(HH Smith) 101

(Johnson) 142-0701-801

(Keystone) 1804

SHR-0440-016-SN

(TI) THS3201DGN

(TI) Edge # 6447972 Rev.A

(1) The components shown in the BOM were used in test by TI.

blank space

Computer simulation of circuit performance using

SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and R

F

-amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS3201 family of devices is available through the Texas Instruments web site ( www.ti.com

).

The Product Information Center (PIC) is available for design assistance and detailed product information.

These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself.

ADDITIONAL REFERENCE MATERIAL

PowerPAD Made Easy, application brief

( SLMA004 )

PowerPAD Thermally Enhanced Package, technical brief ( SLMA002 )

Voltage Feedback vs Current-Feedback Amplifiers

( SLVA051 )

Current-Feedback Analysis and Compensation

( SLOA021 )

Current-Feedback Amplifiers: Review, Stability, and Application ( SBOA081 )

Effect of Parasitic Capacitance in Op Amp Circuits

( SLOA013 )

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EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the input voltage and the output voltage ranges as specified in the table below.

Input Range, V

S

Input Range, V

I

Output Range, V

O

6.6 V (±3.3V) to 16.5V (±8.25V)

NOT TO EXCEED: Power-Supply Voltage Applied

NOT TO EXCEED: Power-Supply Voltage Applied

Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.

Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than +125°C. The EVM is designed to operate properly with certain components above +125°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright 2008, Texas Instruments Incorporated

Copyright © 2003–2009, Texas Instruments Incorporated

Product Folder Link(s):

THS3201

Submit Documentation Feedback

25

Not Recommended for New Designs

THS3201

SLOS416C – JUNE 2003 – REVISED JUNE 2009 .............................................................................................................................................................

www.ti.com

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (March 2008) to Revision C ..................................................................................................

Page

Changed 5-V Step to 10-V Step in second bullet of Features list ......................................................................................... 1

Deleted lead temperature row from Absolute Maximum Ratings table ................................................................................. 2

Changes from Revision A (January, 2004) to Revision B ..............................................................................................

Page

Updated document format ..................................................................................................................................................... 1

Updated Features, Applications, and Description sections

................................................................................................... 1

Updated Package/Ordering Information

................................................................................................................................ 3

Changed ±7.5-V slew rate typical values ............................................................................................................................... 4

Changed ±7.5-V rise and fall time typical values ................................................................................................................... 4

Changed ±7.5-V 2nd-order harmonic typical values .............................................................................................................. 4

Changed ±7.5-V 3rd-order harmonic typical values .............................................................................................................. 4

Deleted ±7.5-V 3rd-order intermodulation distortion specifications ....................................................................................... 4

Changed ±5-V slew rate typical values .................................................................................................................................. 6

Changed ±5-V rise and fall time typical values ...................................................................................................................... 6

Changed ±5-V 2nd-order harmonic typical values ................................................................................................................. 6

Changed ±5-V 3rd-order harmonic typical values ................................................................................................................. 6

Deleted ±5-V 3rd-order intermodulation distortion specifications .......................................................................................... 6

Added

Figure 9

through

Figure 17

; updated

Figure 25 ......................................................................................................... 8

Added

Figure 40

through

Figure 48 ; added

Figure 51 .......................................................................................................... 9

Deleted Power Supply section ............................................................................................................................................. 19

Updated first paragraph in Printed Circuit Board Layout section

......................................................................................... 19

26

Submit Documentation Feedback

Product Folder Link(s):

THS3201

Copyright © 2003–2009, Texas Instruments Incorporated

PACKAGE OPTION ADDENDUM

www.ti.com

17-Sep-2015

PACKAGING INFORMATION

Orderable Device

THS3201D

THS3201DBVR

THS3201DBVRG4

THS3201DBVT

THS3201DBVTG4

THS3201DG4

Status

(1)

NRND

NRND

NRND

NRND

NRND

NRND

Package Type Package

Drawing

SOIC

SOT-23

D

DBV

Pins Package

8

5

Qty

Eco Plan

(2)

75 Green (RoHS

& no Sb/Br)

3000 Green (RoHS

& no Sb/Br)

SOT-23 DBV 5

SOT-23

SOT-23

SOIC

DBV

DBV

D

5

5

8

3000 Green (RoHS

& no Sb/Br)

250 Green (RoHS

& no Sb/Br)

250

75

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

MSL Peak Temp

(3)

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Op Temp (°C)

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

THS3201DGK

THS3201DGKR

THS3201DGN

THS3201DGNG4

NRND

NRND

NRND

NRND

VSSOP

VSSOP

MSOP-

PowerPAD

MSOP-

PowerPAD

DGK

DGK

DGN

DGN

8

8

8

8

80 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

80 Green (RoHS

& no Sb/Br)

80 Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

0 to 70

0 to 70

-40 to 85

-40 to 85

THS3201DGNR

THS3201DGNRG4

NRND

NRND

MSOP-

PowerPAD

MSOP-

PowerPAD

SOIC

DGN

DGN

8

8

2500

2500

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAU

Level-1-260C-UNLIM

Level-1-260C-UNLIM

-40 to 85

-40 to 85

THS3201DR NRND D 8 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85

THS3201DRG4 NRND SOIC D 8 2500 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

-40 to 85

BEN

BEN

3201

3201

BGP

BGP

BEN

BEN

3201

Device Marking

(4/5)

BEO

BEO

BEO

BEO

3201

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

17-Sep-2015

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF THS3201 :

Enhanced Product: THS3201-EP

NOTE: Qualified Version Definitions:

Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

14-Mar-2016

*All dimensions are nominal

Device

THS3201DBVR

THS3201DBVT

THS3201DGKR

THS3201DGNR

THS3201DR

Package

Type

Package

Drawing

SOT-23 DBV

SOT-23 DBV

VSSOP DGK

MSOP-

Power

PAD

SOIC

DGN

D

Pins

5

5

8

8

8

SPQ

3000

250

2500

2500

2500

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

180.0

9.0

A0

(mm)

180.0

330.0

330.0

9.0

12.4

12.4

3.15

3.15

5.3

5.3

B0

(mm)

3.2

3.2

3.4

3.4

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

1.4

1.4

1.4

1.4

4.0

4.0

8.0

8.0

8.0

8.0

12.0

12.0

Q3

Q3

Q1

Q1

330.0

12.4

6.4

5.2

2.1

8.0

12.0

Q1

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

14-Mar-2016

*All dimensions are nominal

Device

THS3201DBVR

THS3201DBVT

THS3201DGKR

THS3201DGNR

THS3201DR

Package Type Package Drawing Pins

SOT-23

SOT-23

VSSOP

MSOP-PowerPAD

SOIC

DBV

DBV

DGK

DGN

D

8

8

5

5

8

SPQ

3000

250

2500

2500

2500

Length (mm) Width (mm) Height (mm)

182.0

182.0

358.0

358.0

367.0

182.0

182.0

335.0

335.0

367.0

20.0

20.0

35.0

35.0

38.0

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

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Consumer Electronics

Energy and Lighting

Industrial

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Space, Avionics and Defense

Video and Imaging www.ti-rfid.com

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Copyright © 2016, Texas Instruments Incorporated

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