MAX16997/MAX16998 High-Voltage Watchdog Timers with Adjustable Timeout Delay General Description

MAX16997/MAX16998 High-Voltage Watchdog Timers with Adjustable Timeout Delay General Description

19-4000; Rev 2; 8/09

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

General Description

The MAX16997/MAX16998 are microprocessor (µP) supervisory circuits for high-input-voltage and low-quiescent-current applications. These devices detect downstream circuit failures and provide switchover to redundant circuitry. See the Selector Guide for the different versions of this product family.

The MAX16997/MAX16998 family has four independent inputs for reset and watchdog functions. SWT and SRT inputs independently set the timeout periods of watchdog and reset timers through external capacitors.

RESETIN/EN monitor voltages at respective inputs. A resistive voltage-divider sets the reset threshold.

The MAX16998A/B/D generate two output signals,

RESET and ENABLE. RESET asserts whenever

RESETIN drops below its threshold voltage or when the watchdog timer detects a timing fault at WDI. Once asserted, and after all reset conditions are removed,

RESET remains low for the reset timeout period, t

RESET and then goes high. The MAX16997A generates one

, output signal (ENABLE) based on the voltage level at

EN and the signal at WDI.

The MAX16997A does not have a RESET output. The watchdog is disabled if the voltage at EN is below its threshold. The MAX16997A watchdog timer starts timing when the voltage at EN becomes higher than the preset threshold voltage level. Each time EN rises above the preset threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (t

WP

).

The MAX16997/MAX16998 are available in 8-pin leadfree µMAX

® packages and are fully specified over the

-40°C to +125°C automotive temperature range.

Automotive

Industrial

Applications

Features

o Wide 5V to 40V Input Voltage Range o 18µA Quiescent Current (Typical at +125°C) o Capacitor-Adjustable Timeout Period for

Watchdog and Reset

o Windowed Watchdog Timer Options

(MAX16998B/D)

o External Voltage Monitoring (RESETIN for the

MAX16998A/B/D and EN for the MAX16997A)

o Car Battery-Compatible EN Input o TTL- and CMOS-Compatible Open-Drain Outputs o 18V Maximum Open-Drain Reset Output Voltage o 28V Maximum Open-Drain Enable Output Voltage o Power-On/Power-Off Reset Functionality

(MAX16998A/B/D Only)

o AEC-Q100 Qualified o -40°C to +125°C Operating Temperature Range o Small (3mm x 3mm) µMAX Package o WDI Narrow Pulse Immunity

Ordering Information

PART

MAX16997AAUA+

MAX16997AAUA/V+

MAX16998AAUA+

MAX16998AAUA/V+

MAX16998BAUA+

MAX16998BAUA/V+

MAX16998DAUA+

MAX16998DAUA/V+

TEMP RANGE

-40°C to +125°C

-40°C to +125°C

-40°C to +125°C

-40°C to +125°C

-40°C to +125°C

-40°C to +125°C

-40°C to +125°C

-40°C to +125°C

PIN-PACKAGE

8 µMAX

8 µMAX

8 µMAX

8 µMAX

8 µMAX

8 µMAX

8 µMAX

8 µMAX

+Denotes a lead(Pb)-free/RoHS-compliant package.

/V Denotes Automotive qualified part.

Selector Guide

PART

WATCHDOG

WINDOW SIZE (%)

MAX16997A

MAX16998A

MAX16998B

MAX16998D

100

100

50

75

Pin Configurations appear at end of data sheet.

ENABLE

µMAX is a registered trademark of Maxim Integrated Products, Inc.

RESET

EN

RESETIN

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

ABSOLUTE MAXIMUM RATINGS

(All pins referenced to GND, unless otherwise noted.)

IN, ENABLE ............................................................-0.3V to +45V

WDI, RESET, EN .....................................................-0.3V to +20V

RESETIN .................................................................-0.3V to +20V

SRT, SWT................................................................-0.3V to +12V

Maximum Current (all pins).................................................30mA

Continuous Power Dissipation (T

A

= +70°C)

8-Pin µMAX (derate 4.8mW/°C above +70°C) ..........387.8mW

Junction-to-Case Thermal Resistance (

θ

JC

) (Note 1) ......42°C/W

Junction-to-Ambient Thermal Resistance (

θ

JA

) (Note 1).....206.3°C/W

Operating Temperature Range (T

A

) ..................-40°C to +125°C

Junction Temperature (T

J

) ...............................................+150°C

Storage Temperature Range .............................-65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to

www.maxim-ic.com/thermal-tutorial

.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

IN

= 14V, T

A

= T

J

= -40°C to +125°C, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

PARAMETER

Operating Voltage Range

Supply Current

SYMBOL CONDITIONS

V

IN

I

IN

T

A

= -40°C to +85°C

T

A

= -40°C to +125°C

I

RAMP_SWT

V

SWT

= 1.0V

I

RAMP_SRT

V

SRT

= 1.0V

MIN

5.0

450

410

TYP

18

18

500

500

SWT Ramp Current

SRT Ramp Current

SWT/SRT Ramp Threshold

Voltage

RESET TIMER

Power-On Reset Input Threshold

Voltage

RESETIN Input Leakage Current

V

RAMP

1.115

1.235

1.363

RESET Output Low Voltage

RESET Leakage Current

ENABLE Output Low Voltage

ENABLE Leakage Current

Minimum Reset Timeout Period

Reset Timeout Period

Maximum Reset Time Period

RESET to ENABLE Delay

RESETIN to RESET Delay

V

I

V

PON

LPON

OLRST

V

RESETIN

rising

V

RESETIN

falling

V

RESETIN

= 2V

RESET asserted, I

SINK

= 1mA

V

IN

= 1.1V, I

SINK

= 160µA, RESET asserted

RESET asserted, I

SINK

= 0.4mA

I

LKGR

V

OLEN

V

RESET

= 20V, RESET not asserted

ENABLE asserted, I

SINK

= 5mA

I

LKGE

V

ENABLE

= 14V, ENABLE not asserted t

RESETmin

C

SRT

= 390pF (Note 3) t

RESET

C

SRT

= 2000pF (Note 3) t

RESETmax

C

SRT

= 47nF t

REDL t

RRDL

RESETIN falling below V

PON

to RESET falling edge

1.135

1.255

1.383

1.115

1.235

1.363

0.1

0.9

0.4

0.4

0.1

0.4

0.1

1

5

116.09

1.5

1

MAX

40.0

30

60

550

600

UNITS

V

µA nA nA

V

V

µA

V

µA

V

µA ms ms ms

µs

µs

2 _______________________________________________________________________________________

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

ELECTRICAL CHARACTERISTICS (continued)

(V

IN

= 14V, T

A

= T

J

= -40°C to +125°C, unless otherwise noted. Typical values are at T

A

= +25°C.) (Note 2)

PARAMETER

WATCHDOG TIMER

SYMBOL CONDITIONS MIN TYP MAX UNITS

WDI Input Threshold

WDI Input Hysteresis

WDI Minimum Pulse Width

WDI Input Current

Minimum Watchdog Timeout

Watchdog Timeout Period

Maximum Watchdog Timeout

Watchdog Window

V

IH

V

IL

WDI

HYST t

WDImin

(Note 4)

I

WDI

WDI = 0 or 14V t

WPmin t

WP

C

SWT

= 680pF (Note 3)

C

SWT

= 1200pF (Note 3) t

WPmax

C

SWT

= 22nF

MAX16998B

D

WDI

MAX16998D

Start from WDI third wrong trigger

2.25

6.5

45

67.5

200

0.1

6.8

12

217.36

50

75

100

0.9

55

82.5

mV

µs

µA ms ms ms

%t

V

WP

WDI to ENABLE Output Delay

RESET Pullup Resistor Supply

Voltage

(Note 5) 2.25

2.5

18.00

µs

V

ENABLE Pullup Resistor Supply

Voltage

(Note 5) 2.25

2.5

28.00

V

Note 2: R

RESET and R

ENABLE are external pullup resistors for open-drain outputs. Connect R

RESET and R

ENABLE to a minimum 2.5V

voltage. Connect R

RESET to a maximum voltage of 18V and connect R

ENABLE to a maximum voltage of 28V.

Note 3: Calculated based on V

RAMP

= 1.235V and I

RAMP

= 500nA.

Note 4: WDI pulses narrower than 1µs will be ignored. WDI pulses wider than 6.5µs will be recognized.

Note 5: Not production tested, guaranteed by design.

(C

SWT

= C

SRT

= 1500pF, T

A

= +25°C, unless otherwise noted.)

10,000

RESET TIMEOUT PERIOD vs. C

SRT

I

RAMP

= 500nA

1000

10,000

WATCHDOG TIMEOUT PERIOD vs. C

SWT

I

RAMP

= 500nA

1000

100

10

1

0.1

0.1

1 10

C

SRT

(nF)

100 1000

100

10

1

0.1

Typical Operating Characteristics

1 10

C

SWT

(nF)

100 1000

SUPPLY CURRENT vs. SUPPLY VOLTAGE

22

20

18

16

26

24

14

12

10

0

RESET AND ENABLE NOT

ASSERTED

10 20 30

SUPPLY VOLTAGE (V)

40 50

_______________________________________________________________________________________ 3

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

Typical Operating Characteristics (continued)

(C

SWT

= C

SRT

= 1500pF, T

A

= +25°C, unless otherwise noted.)

SUPPLY CURRENT vs. TEMPERATURE

20.0

19.5

19.0

18.5

18.0

RESET AND ENABLE NOT

ASSERTED

17.5

17.0

16.5

16.0

15.5

15.0

-40 -25 -10 5 20 35 50 65 80

TEMPERATURE (

°C)

95 110 125

RESETIN TO RESET DELAY vs. TEMPERATURE

2.00

1.75

1.50

1.25

RESETIN FROM 2V TO 0V

100mV OVERDRIVE

1.00

0.75

50mV OVERDRIVE

0.50

0.25

0

-40 -25 -10 5 20 35 50 65

TEMPERATURE (

°C)

80 95 110 125

I

RAMP vs. TEMPERATURE

520

515

510

505

500

495

490

485

480

475

470

-40 -25 -10 5 20 35 50 65 80

TEMPERATURE (

°C)

95 110 125

RESETIN/EN THRESHOLD VOLTAGE vs. TEMPERATURE

1.35

1.33

1.30

1.28

1.25

RISING

1.23

1.20

1.18

1.15

FALLING

1.13

1.10

-40 -25 -10 5 20 35 50 65 80

TEMPERATURE (

°C)

95 110 125

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0

RESETIN/WATCHDOG PERIOD vs. SUPPLY VOLTAGE

8

7

6

5

4

3

2

1

0

4

WATCHDOG TIMEOUT

PERIOD (C

SWT

= 680pF)

RESET TIMEOUT

PERIOD (C

SRT

= 680pF)

8 12 16 20 24 28

SUPPLY VOLTAGE (V)

32 36 40

RESET OUTPUT VOLTAGE vs. SINK CURRENT

0.5

1.0

1.5

2.0

SINK CURRENT (mA)

2.5

3.0

4 _______________________________________________________________________________________

1.25

1.20

1.15

1.10

1.05

1.00

1.50

1.45

1.40

1.35

1.30

4

RESETIN/EN THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE

8

RISING

FALLING

12 16 20 24 28

SUPPLY VOLTAGE (V)

32 36 40

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0

RESETIN/WATCHDOG PERIOD vs. SUPPLY VOLTAGE

80

70

60

50

40

30

20

10

110

100

90

4

WATCHDOG TIMEOUT

PERIOD (C

SWT

= 10nF)

RESET TIMEOUT

PERIOD (C

SRT

= 10nF)

8 12 16 20 24 28

SUPPLY VOLTAGE (V)

32 36 40

ENABLE OUTPUT VOLTAGE vs. SINK CURRENT

5 10 15 20

SINK CURRENT (mA)

25 30

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

Pin Description

PIN

MAX16997A MAX16998A/B/D

1 1

2 —

3, 7 —

4

5

6

8

4

5

6

8

2

3

7

NAME FUNCTION

IN

EN

N.C.

SWT

GND

WDI

ENABLE

RESETIN

SRT

RESET

Power-Supply Input. Bypass IN to GND with a 0.1µF capacitor.

High-Impedance Input to the Enable Comparator. Depending on the voltage level at EN, the internal watchdog timer is turned on or off (see the EN Input section).

No Connection. Not internally connected.

Watchdog Timeout Adjustment Input. Connect a capacitor between SWT and GND to set the basic watchdog timeout period. Connect SWT to ground to disable the watchdog timer function. See the Selecting the Watchdog Timeout Capacitor section.

Ground

Watchdog Input.

MAX16997A/MAX16998A (Timeout Watchdog): Two consecutive WDI falling edges must occur at WDI within the watchdog timeout period or RESET asserts.

The watchdog timer clears when a falling edge occurs on WDI or whenever RESET is asserted. ENABLE asserts if three consecutive watchdog timeout periods have expired without a falling edge at WDI. WDI is a high-impedance input. Leaving

WDI unconnected will cause improper operation of the watchdog timer.

MAX16998B/D (Window Watchdog): WDI falling transitions within periods shorter than the closed window width or longer than the basic watchdog timeout period force RESET to assert low for the reset timeout period. The watchdog timer begins to count after RESET is deasserted. The watchdog timer clears when a WDI falling edge occurs or whenever RESET is asserted. ENABLE asserts if three consecutive watchdog timeout periods have expired without a falling edge at WDI. WDI is a high-impedance input. Leaving WDI unconnected will cause improper operation of the watchdog timer.

Open-Drain Enable Output. ENABLE asserts when three consecutive WDI faults occur. ENABLE remains low until three consecutive good WDI falling edges occur.

ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold.

These devices are guaranteed to be in correct ENABLE output logic state when

V

IN

remains greater than 1.1V.

Reset Input. High-impedance input to the reset comparator. When V

RESETIN

falls below 1.235V, RESET asserts. RESET remains asserted as long as V

RESETIN

is low and for the reset timeout period after RESETIN goes high. Connect V

RESETIN

to the center point of an external resistive divider to set the threshold for the externally monitored voltage. Connect RESETIN to a defined voltage logic-level.

Reset Timeout Adjustment Input. Connect a capacitor between SRT and GND to set the reset timeout period. See the Selecting the Reset Timeout Capacitor section.

Open-Drain Reset Output. RESET asserts whenever RESETIN drops below the selected reset threshold voltage (V

PON

). RESET remains low for the reset timeout period after all reset conditions are removed, and then goes high. RESET asserts for a period of t

RESET

whenever a WDI fault occurs. Connect RESET to a pullup resistor connected to a voltage higher than 2.5V (typ).

_______________________________________________________________________________________ 5

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

Functional Diagram

IN

MAX16997/MAX16998

PREG

RESET

V

BG

RESETIN (MAX16998)

EN (MAX16997)

WDI

I

RAMP

BUFFER

MAX16997A/

MAX16998A/B/D

LOGIC

ENABLE

V

BG

SRT

(MAX16998)

SWT

I

RAMP

V

BG

GND

6 _______________________________________________________________________________________

V

EN

V

PON

WDI

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

Timing Diagrams

V

HYST t

WP INITIAL t

WP t

WD t

WDI t

WP

1 t

WP

2 t

WP

3 t

WP t

WDI t

WDI t

WDI

1 2 3

ENABLE t

WP INITIAL

= WATCHDOG TIMEOUT PERIOD x 8 t

WP

= WATCHDOG TIMEOUT PERIOD t

WDI

= WDI TRIGGER PERIOD

3 CONSECUTIVE t

WP

WITHOUT TRIGGER ENABLE GOES LOW 3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH

Figure 1. MAX16997A Timing Diagram

V

RESETIN

V

PON

V

HYST

WDI t

RESET t

WP t

WDI t

WP t

WP t

WP t

WDI t

WDI t

WDI

1

2

3

1 2 3

RESET

ENABLE t

RESET

= RESET TIMEOUT PERIOD t

WP

= WATCHDOG TIMEOUT PERIOD t

WDI

= WDI TRIGGER PERIOD

3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW 3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH

Figure 2. MAX16998A Timing Diagram

_______________________________________________________________________________________ 7

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

Timing Diagrams (continued)

V

RESETIN

V

PON

WDI t

RESET t

WP t

OW

RESET

ENABLE

V

HYST t

WDI

PROPER WATCHDOG TRIGGER RESETS THE INTERNAL ENABLE COUNTER t

CW t

WP t

WP t

WP t

WDI t

WDI t

WDI

1 2 3

1 2 3 t

RESET

= RESET TIMEOUT PERIOD t

OW

= T OPEN WINDOW t

CW

= T CLOSED WINDOW t

WP

= t

CW

+ t

OW

t

WDI

= WDI TRIGGER PERIOD

3 CONSECUTIVE RESETS ENABLE GOES ACTIVE LOW 3 CONSECUTIVE WATCHDOG TRIGGER (WDI) ENABLE GOES ACTIVE HIGH

Figure 3. MAX16998B/D Timing Diagram

V

RESETIN

V

PON t

RESET

RESET

V

HYST t

RRDL t

RESET t

RESET

V

IN

= ENABLE

1.1V

WDI t

CW t

WP t

CW

≤ t

WDI

≤ t

WP t

WDI t

WDI t

WDI t

WDI t

WDI t

WDI

ENABLE DOES NOT GET ASSERTED IF THE VOLTAGE

AT RESETIN IS BELOW ITS THRESHOLD.

t

WP

THE WATCHDOG TIMER CLEARS

WHENEVER RESET IS ASSERTED.

t

WDI t

WDI t

CW

≤ t

WDI

≤ t

WP t = 0 t

OW

Figure 4. RESETIN, RESET, V

IN

, ENABLE, and WDI Voltage Monitoring

8 _______________________________________________________________________________________

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

Detailed Description

The MAX16997/MAX16998 are µP supervisory circuits for high-input-voltage and low-quiescent-current applications. These devices improve system reliability by monitoring the sub-system for software code execution errors. The MAX16997A/MAX16998A/B/D detect downstream circuit failures, and provide switchover to redundant circuitry. These devices provide complete adjustability for reset and watchdog functions.

The MAX16998A/B/D generate two output signals,

RESET and ENABLE, that depend on the voltage level at RESETIN and the signal at WDI. RESET asserts whenever RESETIN drops below the selected reset threshold voltage. RESET remains low for the reset timeout period after all reset conditions are deasserted, and then goes high. RESET also asserts for a period of t

RESET whenever a WDI fault occurs. The MAX16997A generates one output signal (ENABLE) based on the voltage level at EN and the signal at WDI.

The MAX16997A/MAX16998A provide watchdog timeout adjustability with an external capacitor. The

MAX16998A asserts RESET when two consecutive WDI falling edges do not occur within the watchdog timeout period. This device also asserts ENABLE if three consecutive watchdog timeout periods have elapsed without a falling edge at WDI. ENABLE remains low until three consecutive good WDI falling edges occur.

ENABLE does not assert if the voltage at RESETIN (EN) is below its threshold. For the MAX16997A, the watchdog timer starts timing if the voltage at EN is higher than a preset threshold level. Each time the voltage at

EN rises from below to above the preset threshold voltage, the initial watchdog timeout period is 8 times the normal watchdog timeout period (t

WP

). Other than described above, the MAX16997A behaves the same as the MAX16998A.

The MAX16998B/MAX16998D contain a window watchdog timer that looks for activity outside an expected window of operation. The window size is factory-set to

50% (MAX16998B) or 75% (MAX16998D) of the adjusted watchdog timeout period.

Reset Output (

RESET) (MAX16998A/B/D)

The reset output is typically connected to the reset input of the µC to start or restart it in a known state. The

MAX16998A/B/D provide an active-low open-drain reset logic to prevent code execution errors.

For the MAX16998A/B/D, RESET asserts whenever

RESETIN drops below the selected reset threshold voltage (V

PON

). RESET remains low for the reset timeout period after RESETIN exceeds the selected threshold voltage, and then goes high.

The MAX16998A asserts RESET for a period of t

RESET when two consecutive WDI falling edges do not occur within the adjusted watchdog timeout period. The

MAX16998B/D also assert RESET for a period of t

RESET when a WDI falling edge does not occur within the open window period.

Anytime reset asserts, the watchdog timer clears. At the end of the reset timeout period, RESET goes high, and the watchdog timer is restarted from zero (see the

Selecting the Watchdog Timeout Capacitor section).

Enable Output (

ENABLE)

If the µC fails to operate correctly (e.g., the software execution is stuck in a loop), WDI does not trigger any more and RESET pulls low, resetting the µC. If the µC does not work properly in the next loop either, the device asserts RESET again. After three watchdog timeout periods elapse with no falling edges at WDI,

ENABLE asserts and flags a backup circuit that can take over the operation.

ENABLE remains low until three consecutive WDI falling edges with periods shorter than the watchdog timeout occur. ENABLE does not assert if the voltage at

RESETIN (EN) is below its threshold. These devices are guaranteed to be in correct ENABLE output logic state when V

IN remains greater than 1.1V.

Power-On/Power-Off Sequence

Figure 5 shows the power-up and power-down sequence for RESET and ENABLE for the

MAX16998A/B/D.

On power-up, once V

IN reaches 1.1V, RESET goes logic-low. As RESETIN rises, RESET remains low. When

RESETIN rises above V

PON

, the reset timer starts and

RESET remains low. When the reset timeout period ends, RESET goes high.

On power-down, once RESETIN goes below V

PON

,

RESET goes low and remains low until V

IN drops below

1.1V. Figure 6 shows the detailed power-up sequence for the MAX16998A/B/D.

_______________________________________________________________________________________ 9

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

V

IN

V

IN

= 1.1V

V

RESETIN

V

PON t

RESET

RESET

V

HYST t

RESET t

RESET t

RESET

ENABLE

WDI t = 0 t

CW t

CW

≤ t

WDI

≤ t

WP t

WDI t

WDI t

WDI t

WDI t

WDI t

WDI t

WP t

WP t

WP t

WP

THE THREE CONSECUTIVE RESET COULD BE CAUSED BY THREE

TIMEOUTS AS SHOWN HERE OR BY THREE WDI FALLING EDGE

OUTSIDE THE OPEN WINDOW, OR A COMBINATION OF ANY RESET

CONDITIONS EXCEPT V

RESETIN

DROPS TOO LOW.

t

WDI t

WDI t

CW

≤ t

WDI

≤ t

WP t

OW

WDI RESET

WDT CLEARS AND

STARTS COUNTING

FROM O

Figure 5. Power-On Reset and Power-Down Reset for the MAX16998A/B/D

V

IN

= V

ENABLE

V

IN

= 1.1V

V

PON

V

HYST

V

RESETIN t

RESET

V

RESET

Figure 6. Detailed Power-Up Sequence for the MAX16998A/B/D

10 ______________________________________________________________________________________

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

RESETIN Input (MAX16998A/B/D)

The MAX16998A/B/D monitor the voltage at RESETIN using an adjustable reset threshold, set with an external resistive divider (see Figure 7). RESET asserts when

V

RESETIN is below 1.235V.

Use the following equations to calculate the externally monitored voltage (V

CC

).

V

TH

=

V

PON

R

1

R

2

+

1

R1

R2

V

CC

V

IN

MAX16998A/B/D

RESETIN where V

TH is the desired reset threshold voltage, and

V

PON

= 1.235V. To simplify the resistor selection, choose a value for R

2

(< than 1M

Ω) and calculate R

1

.

R

1

=

R

2

V

TH

V

PON

1

EN Input

The MAX16997A provides a high-impedance input (EN) to the enable comparator. Based on the voltage level at

EN, the watchdog timer is turned on or off. The watchdog timer starts timing if the voltage level at EN is higher than a preset threshold voltage (V

PON

). Each time the voltage at EN rises from below to above the preset threshold voltage, the initial watchdog timeout period is

8 times the normal watchdog timeout period (t

WP

).

period occur.

Watchdog Timer

MAX16997A

The watchdog circuit monitors the µC’s activity. For the

MAX16997A, the watchdog timer starts timing once the voltage at EN is higher than a preset threshold voltage.

ENABLE asserts if three consecutive watchdog timeout periods have elapsed without a falling edge at WDI.

ENABLE remains low until three consecutive WDI falling edges with periods shorter than the watchdog timeout

Each time the voltage at EN rises from below to above the preset threshold voltage, the first watchdog timeout period extends by a factor of 8 (8 x t

WP

). If a WDI falling edge occurs during that time, then the watchdog timeout period is immediately switched over to a single t

WP

.

If no watchdog falling edge occurs during this prolonged watchdog timeout period, ENABLE goes low at the end of this period and stays low. After this, the first falling edge at WDI switches the watchdog timeout period to a single t

WP

. See Figure 1. The MAX16997A watchdog timeout period (t

WP

) is adjustable by a single capacitor at SWT.

Figure 7. Setting RESETIN Voltage for the MAX16998A/B/D

MAX16998A

The MAX16998A asserts RESET when two consecutive

WDI falling edges do not occur within the adjusted watchdog timeout period (t

WP

). RESET remains asserted for the reset timeout period (t

RESET

) and then goes high. This device also asserts ENABLE if three consecutive watchdog timeout periods have elapsed without a falling edge at WDI. ENABLE remains low until three consecutive WDI falling edges with periods shorter than the watchdog timeout period occur (see Figure 2).

The internal watchdog timer is cleared by a RESET rising edge or by a falling edge at WDI. The watchdog timer remains cleared while RESET is asserted; as soon as RESET is released, the timer starts counting. WDI falling edges are ignored when RESET is low. If no WDI falling edge occurs within the watchdog timeout period,

RESET immediately goes low and stays low for the adjusted reset timeout period.

MAX16998B/D

The MAX16998B/D have a windowed watchdog timer.

The watchdog timeout period (t

WP

) is the sum of a closed window period (t

CW

) and an open window period

(t

OW

). If the µC issues a WDI falling edge within the open window period, RESET stays high. Once a WDI falling edge occurs within the closed window period, RESET immediately goes low and stays low for the adjusted reset timeout period (see Figure 3). If no WDI falling edge occurs within the watchdog timeout period, RESET immediately goes low and stays low for the adjusted reset timeout period. The open window size is factory-set to 50% of the watchdog timeout period for the

MAX16998B and 75% for the MAX16998D.

Figure 8 shows a WDI falling edge identified as a good or a bad WDI signal edge. In case 1, the WDI falling edge occurs within the closed window period and is considered a bad WDI falling edge (early fault); therefore, it asserts

RESET. Case 2 also shows another fault. In this case, no

______________________________________________________________________________________ 11

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

WDI falling edge occurs within the watchdog timeout period (t

WP

) and is considered a late fault that asserts

RESET. In case 3, the WDI falling edge occurs within the open window period and is considered a good WDI signal falling edge. In this case, RESET stays high. In case

4, the WDI falling edge occurs within the indeterminate region. In this case, the RESET state is indeterminate.

These devices assert ENABLE after three consecutive bad WDI falling edges. ENABLE returns high after three consecutive good WDI signal falling edges (see Figure 3).

Either a rising edge at RESET or a falling edge at WDI clears the internal watchdog timer. The watchdog timer remains cleared while RESET is asserted. The watchdog timer begins counting when RESET goes high.

WDI falling edges are ignored when RESET is low.

Applications Information

Selecting the Reset Timeout Capacitor

The reset timeout period is adjustable to accommodate a variety of µP applications. Adjust the reset timeout period

(t

RESET

) by connecting a capacitor (C

SRT

) between SRT and ground. See the Reset Timeout Period vs. C

SRT graph in the Typical Operating Characteristics. Calculate the reset timeout capacitance using the equation below:

C

SRT

= t

RESET

×

I

RAMP

V

RAMP where V

RAMP is in volts, t

RESET is in seconds, I

RAMP is in nA, and C

SRT is in nF.

RESET RISING EDGE t

WDImin

(50% or 75%) x t

WP t

WDImax

Leakage currents and stray capacitance (e.g., a scope probe, which induces both) at SRT may cause errors in the reset timeout period. If precise time control is required, use capacitors with low leakage current and high stability.

Selecting the Watchdog

Timeout Capacitor

The watchdog timeout period is adjustable to accommodate a variety of µP applications. With this feature, the watchdog timeout can be optimized for software execution. The programmer determines how often the watchdog timer should be serviced. Adjust the watchdog timeout period (t

WP

) by connecting a capacitor

(C

SWT

) between SWT and GND. For normal mode operation, calculate the watchdog timeout capacitance using the following equation:

C

SWT

= t

WP

×

4

I

RAMP

×

V

RAMP where V

RAMP is in volts, t

WP is in seconds, I

RAMP is in nA, and C

SWT is in nF. See the Watchdog Timeout Period vs.

C

SWT graph in the Typical Operating Characteristics.

For the MAX16998B/MAX16998D, the open window size is factory-set to 50% (MAX16998B) or 75% (MAX16998D) of the watchdog period. Leakage currents and stray capacitance (e.g., a scope probe, which induces both) at

SWT may cause errors in the watchdog timeout period. If precise time control is required, use capacitors with low leakage current and high stability. To disable the watchdog timer function, connect SWT to ground and connect

WDI to either the high- or low-logic state.

t

WP

CASE 1 (FAST FAULT)

CASE 2 (SLOW FAULT)

CASE 3 (GOOD WDI)

CASE 4 (INDETERMINATE)

CLOSED WINDOW INDETERMINATE OPEN WINDOW

Figure 8. The MAX16998B/D Window Watchdog Diagram

12 ______________________________________________________________________________________

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

Interfacing to Other Voltages for

Logic Compatibility

As shown in Figure 9, the open-drain RESET output can operate in the 2.5V to 18V range. This allows the device to interface a µP with other logic levels.

WDI Glitch Immunity

For additional glitch immunity, connect an RC lowpass filter as close as possible to WDI (see Figure 10).

For example, for glitches with duration of 1µs, a 12k

Ω resistor and a 47pF capacitor will provide immunity.

Layout Considerations

SRT and SWT are connected to internal precision current sources. When developing the layout for the application, minimize stray capacitance attached to SRT and SWT as well as leakage currents that can reach those nodes. SRT and SWT traces should be as short as possible. Route traces carrying high-speed digital signals and traces with large voltage potentials as far from SRT and SWT as possible. Leakage currents and stray capacitance (e.g., a scope probe, which induces both) at these pins may cause errors in the reset and/or watchdog timeout period. When evaluating these parts, use clean prototype boards to ensure accurate reset and watchdog timeout periods.

RESETIN is a high-impedance input and a high-impedance resistive divider (e.g., 100k

Ω to 1MΩ) sets the threshold level. Minimize coupling to transient signals by keeping the connections to this input short. Any DC leakage current at RESETIN (e.g., a scope probe) causes errors in the programmed reset threshold.

Typical Operating Circuits

RESET remains asserted as long as RESETIN is below the regulated voltage and for the reset timeout period after RESETIN goes high to assure that the monitored

LDO voltage is settled. Then, the µC starts operating and triggers WDI.

If the µC fails to operate correctly (e.g., the software execution is stuck in a loop), the WDI signal does not trigger the watchdog timer any more, and RESET is pulled low, resetting the µC. If the µC does not work properly in the next loop either, the device asserts

RESET again. After three watchdog timeout periods with no WDI falling edges, ENABLE asserts and flags backup or safety circuits that take over the operation.

5V TO 40V

IN

MAX16998A/B/D

RESET

N

GND

2.5V TO 18V

10k

V

CC

RESET

µP

GND

IN

MAX16998A/B/D

V

CC

GND

WDI

C

R

I/O

µP

GND

Figure 9. Interfacing to Other Voltage Levels Figure 10. Additional WDI Glitch Immunity Circuit

______________________________________________________________________________________ 13

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

V

BATT

IN

SRT

MAX16998A/B/D

ENABLE

V

CC

EN

BACKUP CIRCUITRY,

PERIPHERAL

5V

REGULATOR

R1

V

CC

RESET

R2

RESETIN

SWT WDI

RESET

µC

I/O

GND

GND

Figure 11. MAX16998A/B/D Switch Over to Backup Circuitry

V

BATT

IN

ENABLE

R1

V

CC

MAX16997A

R2

EN

SWT

WDI

GND

5V

REGULATOR

LDO

BACKUP

CIRCUITRY FLAGS

BACKUP CIRCUITRY,

PERIPHERAL

µC

I/O

GND

RESET

I/O

WATCHDOG 5V

SEPARATE

WATCHDOG

Figure 12. MAX16997A Application Diagram

14 ______________________________________________________________________________________

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

Pin Configurations

TOP VIEW

IN

EN

N.C.

SWT

1

2

3

4

+

MAX16997A

µMAX

8

7

6

5

ENABLE

N.C.

WDI

GND

IN

RESETIN

SRT

SWT

+

1

2

3

4

MAX16998A/B/D

8

7

6

5

ENABLE

RESET

WDI

GND

µMAX

PROCESS: BiCMOS

Chip Information Package Information

For the latest package outline information and land patterns, go to

www.maxim-ic.com/packages

.

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.

8 µMAX U8-1

21-0036

______________________________________________________________________________________ 15

High-Voltage Watchdog Timers with

Adjustable Timeout Delay

REVISION

NUMBER

0

1

2

REVISION

DATE

2/08

4/09

8/09

DESCRIPTION

Initial release

Added bullet to Features section, revised Electrical Characteristics table.

Added automotive qualified parts.

Revision History

PAGES

CHANGED

1, 2, 3

1

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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