LMH0394 3G HD/SD SDI Low Power Extended Reach Adaptive Cable... LMH0394 FEATURES DESCRIPTION

LMH0394 3G HD/SD SDI Low Power Extended Reach Adaptive Cable... LMH0394 FEATURES DESCRIPTION
LMH0394
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SNLS312L – AUGUST 2010 – REVISED APRIL 2013
LMH0394 3G HD/SD SDI Low Power Extended Reach Adaptive Cable Equalizer
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FEATURES
DESCRIPTION
•
The LMH0394 3 Gbps HD/SD SDI Low Power
Extended Reach Adaptive Cable Equalizer is
designed to equalize data transmitted over cable (or
any
media
with
similar
dispersive
loss
characteristics). The equalizer operates over a wide
range of data rates from 125 Mbps to 2.97 Gbps and
supports SMPTE 424M, SMPTE 292M, SMPTE
344M, SMPTE 259M, and DVB-ASI standards.
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
SMPTE 424M, SMPTE 292M, SMPTE 344M,
SMPTE 259M, and DVB-ASI Compliant
Equalized Cable Lengths (Belden 1694A):
200m at 2.97 Gbps, 220m at 1.485 Gbps, and
400m at 270 Mbps
Ultra Low Power Consumption: 115 mW
(Normal Operation)
Power Save Mode with Auto Sleep Control
(17 mW Typical Power Consumption in Power
Save Mode)
Designed for Crosstalk Immunity
Output De-Emphasis to Compensate for FR4
Board Trace Losses
Digital and Analog Programmable MUTEREF
Threshold
Optional SPI Register Access
Input Data Rates: 125 Mbps to 2.97 Gbps
Internally Terminated 100Ω LVDS Outputs with
Programmable Output Common Mode Voltage
and Swing
Programmable Launch Amplitude Optimization
Cable Length Indicator
Single 2.5V Supply Operation
16-pin WQFN Package
Industrial Temperature Range: −40°C to +85°C
Footprint Compatible with the LMH0384 and
also the LMH0344, LMH0044, and LMH0074 in
Pin Mode
The LMH0394 provides extended cable reach with
improved immunity to crosstalk and ultra low power
consumption. The equalizer includes active sensing
circuitry that ensures robust performance and
enhanced immunity to variations in the input signal
launch amplitude. The output driver offers
programmable de-emphasis for up to 40” of FR4
trace losses. The LMH0394 includes power
management to further reduce power consumption
when no input signal is present.
The LMH0394 supports two modes of operation. In
pin mode, the LMH0394 operates with control pins to
set its operating state, and is footprint compatible with
the LMH0384, LMH0344, and legacy SDI equalizers.
In SPI mode, an optional SPI serial interface can be
used to access and configure multiple LMH0394
devices in a daisy-chain configuration. This allows
programming the output common mode voltage and
swing, output de-emphasis level, input launch
amplitude, and power management settings, as well
as access to a cable length indicator and all pin mode
features.
APPLICATIONS
•
•
SMPTE 424M, SMPTE 292M, SMPTE 344M, and
SMPTE 259M Serial Digital Interfaces
Broadcast Video Routers, Switchers, and
Distribution Amplifiers
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2013, Texas Instruments Incorporated
LMH0394
SNLS312L – AUGUST 2010 – REVISED APRIL 2013
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Typical Application (Pin Mode)
Coaxial Cable
LMH0394 3G SDI
Adaptive Cable
Equalizer
LMH0341 3G SDI
Deserializer
1.0 PF
75:
SDO
SDI
SDI
5.6 nH
TXOUT
RXIN0
RXIN0
Reclocked
Loopthrough
TXOUT
SDO
1.0 PF
75:
RX[4:0]
CD
BYPASS
AUTO SLEEP
SPI_EN
RXCLK
MUTE
To FPGA
5-bit LVDS
+ clk
AEC-
AEC+
37.4:
MUTE
MUTEREF
MUTEREF
CD
BYPASS
AUTO SLEEP
1.0 PF
SDI
3
SPI_EN
4
MUTE
VCC
CD
13
LMH0394
(top view)
5
6
7
8
MUTEREF
2
14
BYPASS
SDI
15
AEC-
1
16
AEC+
VEE
VCC
Connection Diagram
12
AUTO SLEEP
11
SDO
10
SDO
9
VEE
DAP = VEE
Pin Mode (non-SPI) / SPI_EN = GND / LMH0344 Compatible
2
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SDI
3
SPI_EN
4
SCK
VCC
13
LMH0394
(top view)
5
6
7
8
MUTEREF
2
14
CD
SDI
15
AEC-
1
16
AEC+
VEE
MOSI
SNLS312L – AUGUST 2010 – REVISED APRIL 2013
VCC
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12
MISO
11
SDO
10
SDO
9
SS
DAP = VEE
The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative
power supply voltage.
SPI Mode / SPI_EN = VCC
16-Pin WQFN (See Package RUM0016A)
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PIN DESCRIPTIONS – Pin Mode (non-SPI) / SPI_EN = GND / LMH0344 Compatible
Pin
4
Name
I/O, Type
Description
1
VEE
Ground
Negative power supply (ground).
2
SDI
I, SDI
Serial data true input.
3
SDI
I, SDI
Serial data complement input.
4
SPI_EN
I, LVCMOS
SPI register access enable. This pin has an internal pulldown.
H = SPI register access mode.
L = Pin mode.
5
AEC+
I/O, Analog
AEC loop filter external capacitor (1µF) positive connection (capacitor is optional).
6
AEC-
I/O, Analog
AEC loop filter external capacitor (1µF) negative connection (capacitor is optional).
7
BYPASS
I, LVCMOS
Equalization bypass. This pin has an internal pulldown.
H = Equalization is bypassed (no equalization occurs).
L = Normal operation.
8
MUTEREF
I, Analog
Mute reference input. Sets the threshold for CD and (with CD tied to MUTE) determines the
maximum cable to be equalized before muting. MUTEREF may be either unconnected or
connected to ground for normal CD operation.
9
VEE
I, LVCMOS
Connect this pin to ground or drive it logic low.
10
SDO
O, LVDS
Serial data complement output.
11
SDO
O, LVDS
Serial data true output.
12
AUTO SLEEP
I, LVCMOS
Auto Sleep. AUTO SLEEP has precedence over MUTE and BYPASS. This pin has an
internal pullup.
H = Device will power down when no input is detected.
L = Normal operation (device will not enter auto power down).
13
VCC
Power
Positive power supply (+2.5V).
14
MUTE
I, LVCMOS
Output mute. CD may be tied to this pin to inhibit the output when no input signal is present.
MUTE has precedence over BYPASS. This pin has an internal pulldown.
H = Outputs forced to a muted state.
L = Outputs enabled.
15
CD
O, LVCMOS
Carrier detect.
H = No input signal detected.
L = Input signal detected.
16
VCC
Power
Positive power supply (+2.5V).
DAP
VEE
Ground
Connect exposed DAP to negative power supply (ground).
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PIN DESCRIPTIONS – SPI Mode / SPI_EN = VCC
Pin
Name
I/O, Type
Description
1
VEE
Ground
Negative power supply (ground).
2
SDI
I, SDI
Serial data true input.
3
SDI
I, SDI
Serial data complement input.
4
SPI_EN
I, LVCMOS
SPI register access enable. This pin has an internal pulldown.
H = SPI register access mode.
L = Pin mode.
5
AEC+
I/O, Analog
AEC loop filter external capacitor (1µF) positive connection (capacitor is optional).
6
AEC-
I/O, Analog
AEC loop filter external capacitor (1µF) negative connection (capacitor is optional).
7
CD
O, LVCMOS
Carrier detect.
H = No input signal detected.
L = Input signal detected.
8
MUTEREF
I, Analog
Mute reference input. Sets the threshold for CD and (with CD tied to MUTE) determines the
maximum cable to be equalized before muting. MUTEREF may be either unconnected or
connected to ground for normal CD operation.
9
SS (SPI)
I, LVCMOS
SPI slave select. This pin has an internal pullup.
10
SDO
O, LVDS
Serial data complement output.
11
SDO
O, LVDS
Serial data true output.
12
MISO (SPI)
O, LVCMOS
SPI Master Input / Slave Output. LMH0394 control data transmit.
13
VCC
Power
Positive power supply (+2.5V).
14
SCK (SPI)
I, LVCMOS
SPI serial clock input.
15
MOSI (SPI)
I, LVCMOS
SPI Master Output / Slave Input. LMH0394 control data receive. This pin has an internal
pulldown.
16
VCC
Power
Positive power supply (+2.5V).
DAP
VEE
Ground
Connect exposed DAP to negative power supply (ground).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1)
Supply Voltage
3.1V
−0.3V to VCC+0.3V
Input Voltage (all inputs)
−65°C to +150°C
Storage Temperature Range
Junction Temperature
Package Thermal Resistance
+125°C
θJA 16-pin WQFN
+40°C/W
θJC 16-pin WQFN
+6°C/W
ESD Rating (HBM)
≥±6 kV
ESD Rating (MM)
≥±300V
≥±2 kV
ESD Rating (CDM)
(1)
Absolute Maximum Ratings are those parameter values beyond which the life and operation of the device cannot be ensured. The
stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values.
The table of Electrical Characteristics specifies acceptable device operating conditions.
Recommended Operating Conditions
Supply Voltage (VCC – VEE)
2.5V ±5%
Input Coupling Capacitance
1.0 µF
−40°C to +85°C
Operating Free Air Temperature (TA)
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DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2).
Symbol Parameter
VIH
Input Voltage High Level
VIL
Input Voltage Low Level
VSDI
Input Voltage Swing
VCMIN
Input Common Mode Voltage
VSSP-P
Differential Output Voltage, P-P
VOD
Differential Output Voltage
ΔVOD
Change in Magnitude of VOD for
Complimentary Output States
VOS
Offset Voltage
ΔVOS
Change in Magnitude of VOS for
Complimentary Output States
IOS
Output Short Circuit Current
Conditions
Reference
Logic Inputs
0m cable length (3)
SDI, SDI
Min
Max
Units
1.7
VCC
V
VEE
0.7
V
880
mVP−P
720
100Ω load, default register
settings, Figure 1 (4)
SDO, SDO
700
900
mVP-P
250
350
450
mV
50
mV
1.35
V
50
mV
30
mA
1.1
MUTEREF
VOH
Output Voltage High Level
IOH = -2 mA
VOL
Output Voltage Low Level
IOL = +2 mA
ICC
Supply Current
Normal operation (5)
Power save mode
6
CD, MISO
V
500
MUTEREF Range
(2)
(3)
(4)
(5)
800
1.65
MUTEREF DC Voltage (floating)
(1)
Typ
1.2
1.3
V
0.8
V
2.0
V
0.2
V
45
65
mA
7
10
mA
Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated
referenced to VEE = 0 Volts.
Typical values are stated for VCC = +2.5V and TA = +25°C.
The LMH0394 can be optimized for different launch amplitudes via the SPI.
The differential output voltage and offset voltage are adjustable via the SPI.
Typical ICC is measured with a 2.97 Gbps input signal.
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AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1).
Symbol
Parameter
BRMIN
Minimum Input Data Rate
BRMAX
Maximum Input Data Rate
Conditions
Reference
Min
SDI, SDI
Typ
125
Units
Mbps
2970
Mbps
Jitter for Various Cable Lengths 2.97 Gbps, Belden 1694A,
0-100 meters (2)
0.2
UI
2.97 Gbps, Belden 1694A,
100-140 meters (2)
0.3
UI
2.97 Gbps, Belden 1694A,
140-180 meters (2)
0.5
UI
2.97 Gbps, Belden 1694A,
180-200 meters
0.55
1.485 Gbps, Belden 1694A,
0-200 meters (2)
0.3
270 Mbps, Belden 1694A,
0-400 meters (2)
Output Rise Time, Fall Time
20% – 80%, 100Ω load,
Figure 1 (3)
UI
0.2
1.485 Gbps, Belden 1694A,
200-220 meters
tr, tf
Max
SDO, SDO
UI
0.3
UI
90
130
ps
ps
Mismatch in Rise/Fall Time
(3)
2
15
tOS
Output Overshoot
(3)
1
5
RLIN
Input Return Loss
5 MHz - 1.5 GHz (4)
SDI, SDI
1.5 GHz - 3.0 GHz (4)
UI
%
15
dB
10
dB
RIN
Input Resistance
single-ended
1.5
kΩ
CIN
Input Capacitance
single-ended
0.7
pF
(1)
(2)
(3)
(4)
Typical values are stated for VCC = +2.5V and TA = +25°C.
Based on design and characterization data over the full range of recommended operating conditions of the device. Jitter is measured in
accordance with SMPTE RP 184, SMPTE RP 192, and the applicable serial data transmission standard: SMPTE 424M, SMPTE 292M,
or SMPTE 259M.
Specification is ensured by characterization.
Input return loss is dependent on board design. The LMH0394 exceeds this specification on the SD394 evaluation board with a return
loss network consisting of a 5.6 nH inductor in parallel with a 75Ω series resistor on the input.
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SPI Interface AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1).
Symbol
Parameter
Conditions
Reference
Min
Typ
Max
Units
Recommended Input Timing Requirements
fSCK
SCK Frequency
tPH
SCK Pulse Width High
SCK
tPL
SCK Pulse Width Low
tSU
MOSI Setup Time
tH
MOSI Hold Time
tSSSU
SS Setup Time
tSSH
SS Hold Time
tSSOF
SS Off Time
20
Figure 2, Figure 3
MHz
40
% SCK
period
40
% SCK
period
Figure 2, Figure 3
MOSI
4
ns
4
ns
Figure 2, Figure 3
SS
14
ns
4
ns
1
SCK
period
Switching Characteristics
tODZ
MISO Driven-to-TRI-STATE
Time
tOZD
tOD
(1)
Figure 3
MISO
20
ns
MISO TRI-STATE-to-Driven
Time
10
ns
MISO Output Delay Time
15
ns
Typical values are stated for VCC = +2.5V and TA = +25°C.
Timing Diagrams
VODVOS
VOD+
80%
80%
+ VOD
VSSP-P
0V differential
20%
- VOD
20%
VSSP-P = (VOD+) – (VOD-)
tr
tf
Figure 1. LVDS Output Voltage, Offset, and Timing Parameters
SS
(host)
tSSSU
tPH
tPL
tSSH
SCK
(host)
tH
tSU
MOSI
(host)
0
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
tOZD
MISO
(device)
tSSOF
Hi-Z
D4
D3
D2
D1
D0
tODZ
'21¶7 &$5(
Hi-Z
Figure 2. SPI Write
8
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SS
(host)
tSSSU
tSSH tSSOF
tSSH tSSOF tSSSU
tPL
tPH
SCK
(host)
tH
tSU
MOSI
(host)
³8x1´
1 A6 A5 A4 A3 A2 A1 A0
³16x1´
tOZD
tOZD
tODZ
MISO Hi-Z
(device)
Hi-Z
'21¶7 &$5(
tOD
tODZ
1 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 1
Hi-Z
Figure 3. SPI Read
Block Diagram (Pin Mode)
BYPASS
Output
Driver
SDI
DC
Restoration/
Level Control
Equalizer
Filter
SDI
SDO
SDO
De-Emphasis
Control
CD
Energy
Detect
Carrier
Detect
Energy
Detect
6
MUTEREF
MUTEREF
MUTE
SPI Control
SPI_EN
Automatic
Equalization
Control
AEC+
AEC-
AUTO SLEEP
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DEVICE OPERATION
BLOCK DESCRIPTION
The Equalizer Filter block is a multi-stage adaptive filter. If Bypass is high, the equalizer filter is disabled.
The DC Restoration / Level Control block receives the differential signals from the equalizer filter block. This
block incorporates a self-biasing DC restoration circuit to fully DC restore the signals. If Bypass is high, this
function is disabled.
The signals before and after the DC Restoration / Level Control block are used to generate the Automatic
Equalization Control (AEC) signal. This control signal sets the gain and bandwidth of the equalizer filter.
The Carrier Detect block generates the carrier detect signal based on the SDI input and an adjustment from the
Mute Reference block.
The SPI Control block uses the MOSI, MISO, SCK, and SS signals in SPI mode to control the SPI registers.
SPI_EN selects between SPI mode and pin mode. In pin mode, SPI_EN is driven logic low.
The Output Driver produces SDO and SDO.
MUTE REFERENCE (MUTEREF)
The mute reference sets the threshold for CD and (with CD tied to MUTE) determines the amount of cable to
equalize before automatically muting the outputs. This is set by applying a voltage inversely proportional to the
length of cable to equalize. The applied voltage must be greater than the MUTEREF floating voltage (typically
1.3V) in order to change the CD threshold. As the applied MUTEREF voltage is increased, the amount of cable
that can be equalized before carrier detect is de-asserted and the outputs are muted is decreased. MUTEREF
may be left unconnected or connected to ground for normal CD operation. Optionally, the LMH0394 allows the
mute reference to be set digitally via SPI register 03h.
Figure 4 shows the minimum MUTEREF input voltage required to force carrier detect to inactive vs. Belden 1694A
cable length. The results shown are valid for Belden 1694A cable lengths of 0-200m at 2.97 Gbps, 0-220m at
1.485 Gbps, and 0-400m at 270 Mbps.
2.2
MUTEREF(V)
2.0
1.8
1.6
1.4
1.2
0 50 100 150 200 250 300 350 400
BELDEN 1694A CABLE LENGTH (m)
Figure 4. MUTEREF vs. Belden 1694A Cable Length
CARRIER DETECT (CD) AND MUTE
Carrier detect CD indicates if a valid signal is present at the LMH0394 input. This signal is logical OR operation
of the internal energy detector and MUTEREF setting (if used). The internal energy detector detects energy across
different data rates. If MUTEREF is used, the carrier detect threshold will be altered accordingly. CD provides a
high voltage when no signal is present at the LMH0394 input. CD is low when a valid input signal is detected.
MUTE can be used to manually mute or enable SDO and SDO. Applying a high input to MUTE will mute the
LMH0394 outputs by forcing the output to a logic 1. Applying a low input will force the outputs to be active.
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In pin mode, CD and MUTE may be tied together to automatically mute the output when no input signal is
present.
AUTO SLEEP
The auto sleep mode allows the LMH0394 to power down when no input signal is detected. If the AUTO SLEEP
pin is set high, the LMH0394 goes into a deep power save mode when no signal is detected. The device powers
on again once an input signal is detected. The auto sleep functionality can be turned off by setting AUTO SLEEP
low or tying this pin to ground. An additional auto sleep setting available in SPI mode can be used to force the
equalizer to power down regardless of whether there is an input signal or not. Auto sleep has precedence over
mute and bypass modes.
In auto sleep mode, the time to power down the equalizer when the input signal is removed is less than 200 µs
and should not have any impact on the system timing requirements. The device will wake up automatically once
an input signal is detected, and the delay between signal detection and full functionality of the equalizer is
negligible (about 5 ms). The overall system will be limited only by the settling time constant of the equalizer
adaptation loop.
INPUT INTERFACING
The LMH0394 accepts either differential or single-ended input. The input must be AC coupled. The Typical
Application (Pin Mode) diagram on the front page shows the typical configuration for a single-ended input. The
unused input must be properly terminated as shown.
The LMH0394 can be optimized for different launch amplitudes via the SPI (see LAUNCH AMPLITUDE
OPTIMIZATION in the SPI Register Access section).
The LMH0394 correctly handles equalizer pathological signals for standard definition and high definition serial
digital video, as described in SMPTE RP 178 and RP 198, respectively.
OUTPUT INTERFACING
SDO and SDO together are internally terminated 100Ω LVDS outputs. These outputs can be DC coupled to most
common differential receivers.
The default output common mode voltage (VOS) is 1.2V. The output common mode voltage may be adjusted via
the SPI in 200 mV increments, from 0.8V to 1.2V (see OUTPUT DRIVER ADJUSTMENTS AND DE-EMPHASIS
SETTING in the SPI Register Access section). When the output common mode is supply referenced, the
common mode voltage is about 1.35V (for 700 mVP-P differential swing). This adjustable output common mode
voltage offers flexibility for interfacing to many types of receivers.
The default differential output swing (VSSP-P) is 700 mVP-P. The differential output swing may be adjusted via the
SPI. Valid options are 400, 600, 700, or 800 mVP-P (see OUTPUT DRIVER ADJUSTMENTS AND DEEMPHASIS SETTING in the SPI Register Access section).
The LMH0394 output should be DC coupled to the input of the receiving device where possible. 100Ω differential
transmission lines should be used to connect between the LMH0394 outputs and the input of the receiving
device.
The LMH0394 output should not be DC coupled to CML inputs. If there are strong pullup resistors (i.e. 50Ω) at
the receiving device, AC coupling should be used. The value of these AC-coupling capacitors should be large
enough (typically 4.7 µF) to accommodate for the SD pathological video pattern.
Figure 5 shows an example of a DC-coupled interface between the LMH0394 and LMH0346 SDI reclocker. The
differential transmission line should be terminated with a 100Ω resistor at the receiving device as shown. The
resistor should be placed as close as possible to the LMH0346 input. If desired, this network may be terminated
with two 50Ω resistors and a center-tap capacitor to ground in place of the single 100Ω resistor.
Figure 6 shows an example of a DC-coupled interface between the LMH0394 and LMH0356 SDI reclocker. The
LMH0356 inputs have internal 50Ω terminations (100Ω differential) to terminate the transmission line, so no
additional components are required.
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The LMH0394 output driver is equipped with programmable output de-emphasis to minimize inter-symbol
interference caused by the loss dispersion from driving signals across PCB traces (see OUTPUT DRIVER
ADJUSTMENTS AND DE-EMPHASIS SETTING in the SPI Register Access section). De-emphasis works with
all combinations of output common mode voltage and output voltage swing settings to support DC coupling to the
receiving device.
Coaxial Cable
1.0 PF
75:
SDI
LMH0394
1.0 PF
5.6 nH
SDI
SDO
SDI
100: Differential T-Line
LMH0346
3G/HD/SD
SDI Reclocker
100:
SDI
SDO
75:
37.4:
Figure 5. DC Output Interface to LMH0346 Reclocker
Coaxial Cable
75:
1.0 PF
SDI
1.0 PF
5.6 nH
SDO
LMH0394
SDI
SDI0
LMH0356
3G/HD/SD
SDI Reclocker
100: Differential T-Line
SDO
SDI0
75:
37.4:
Figure 6. DC Output Interface to LMH0356 Reclocker
12
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SPI REGISTER ACCESS
Setting SPI_EN high enables the optional SPI register access mode. In SPI mode, the LMH0394 provides
register access to all of its features along with a cable length indicator, programmable output de-emphasis,
programmable output common mode voltage and swing, digital MUTEREF, and launch amplitude optimization.
There are eight supported 8-bit registers in the device (see Table 1). The LMH0394 supports SPI daisy-chaining
among an unlimited number of LMH0394 devices. With SPI_EN set low, the device operates in pin mode and is
footprint compatible with the LMH0384, LMH0344, LMH0044, and LMH0074.
SPI Transaction Overview
Each SPI transaction to a single device is 16-bits long. The transaction is initiated by driving SS low, and
completed by returning SS high. The 16-bit MOSI payload consists of the read/write command (“1” for reads and
“0” for writes), the seven address bits of the device register (MSB first), and the eight data bits (MSB first). The
LMH0394 MOSI input data is latched on the rising edge of SCK, and the MISO output data is sourced on the
falling edge of SCK.
In order to facilitate daisy-chaining, the prior SPI command, address, and data are shifted out on the MISO
output as the current command, address, and data are shifted in on the MOSI input. For SPI writes, the MISO
output is typically ignored as “Don't Care” data. For SPI reads, the MISO output provides the requested read data
(after 16 periods of SCK). The MISO output is active when SS low, and tri-stated when SS is high.
SPI Write
The SPI write is shown in Figure 2. The SPI write is 16 bits long. The 16-bit MOSI payload consists of a “0” (write
command), seven address bits, and eight data bits. The SS signal is driven low, and the 16 bits are sent to the
LMH0394's MOSI input. After the SPI write, SS must return high. The prior SPI command, address, and data
shifted out on the MISO output during the SPI write is shown as “Don't Care” on the MISO output in Figure 2.
SPI Read
The SPI read is shown in Figure 3. The SPI read is 32 bits long, consisting of a 16-bit read transaction followed
by a 16-bit dummy read transaction to shift out the read data on the MISO output. The first 16-bit MOSI payload
consists of a “1” (read command), seven address bits, and eight “1”s which are ignored. The second 16-bit MOSI
payload consists of 16 “1”s which are ignored but necessary in order to shift out the requested read data on the
MISO output. The SS signal is driven low, and the first 16 bits are sent to the LMH0394's MOSI input. The prior
SPI command, address, and data are shifted out on the MISO output during the first 16-bit transaction, and are
typically ignored (this is shown as “Don't Care” on the MISO output in Figure 3. SS must return high and then is
driven low again before the second 16 bits (all “1”s) are sent to the LMH0394's MOSI input. Once again, the prior
SPI command, address, and data are shifted out on the MISO output, but this data now includes the requested
read data. The read data is available on the MISO output during the second 8 bits of the 16-bit dummy read
transaction, as shown by D7-D0 in Figure 3.
SPI Daisy-Chain Operation
The LMH0394 SPI controller supports daisy-chaining the serial data between an unlimited number of LMH0394
devices. Each LMH0394 device is directly connected to the SCK and SS pins on the host. However, only the first
LMH0394 device in the chain is connected to the host’s MOSI pin, and only the last device in the chain is
connected to the host’s MISO pin. The MISO pin of each intermediate LMH0394 device in the chain is connected
to the MOSI pin of the next LMH0394 device, creating a serial shift register.
This daisy-chain architecture is shown in Figure 7.
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MISO
Device 2
Device 3
Device N
LMH0394
LMH0394
LMH0394
LMH0394
MISO
MOSI
MISO
SS
MOSI
SCK
SS
MISO
SS
MOSI
SCK
MISO
SCK
MOSI
SS
MOSI
Device 1
SCK
Host
SCK
SS
Figure 7. SPI Daisy Chain System Architecture
In a daisy-chain configuration of N LMH0394 devices, the host conceptually sees a shift register of length 16xN.
Therefore the length of SPI transactions (as previously described) is 16xN bits, and SS must be asserted for
16xN clock cycles for each SPI transaction.
SPI Daisy-Chain Write
Figure 8 shows the SPI daisy-chain write for a daisy-chain of N devices. The SS signal is driven low and SCK is
toggled for 16xN clocks. The 16xN bit MOSI payload (sent to Device 1 in the daisy-chain) consists of the 16-bit
SPI write data for Device N (the last device in the chain), followed by the write data for Device N-1, Device N-2,
etc., ending with the write data for Device 1 (the first device in the chain). The 16-bit SPI write data for each
device consists of a “0” (write command), seven address bits, and eight data bits. After the SPI daisy-chain write,
SS must return high and then the write occurs for all devices in the daisy-chain.
SPI Write Data
0 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SS
(host)
SCK
(host)
16xN clocks
MOSI (host)
MOSI Device 1
Device N
Write Data
Device N-1
Write Data
Device N-2
Write Data
Device N-3
Write Data
Device 1
Write Data
MISO Device 1
MOSI Device 2
'21¶7 &$5(
Device N
Write Data
Device N-1
Write Data
Device N-2
Write Data
Device 2
Write Data
MISO Device N-1
MOSI Device N
'21¶7 &$5(
'21¶7 &$5(
'21¶7 &$5(
'21¶7 &$5(
Device N
Write Data
Figure 8. SPI Daisy-Chain Write
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SPI Daisy-Chain Read
Figure 9 shows the SPI daisy-chain read for a daisy-chain of N devices. The SPI daisy-chain read is 32xN bits
long, consisting of 16xN bits for the read transaction followed by 16xN bits for the dummy read transaction (all
“1”s) to shift out the read data on the MISO output. The SS signal is driven low and SCK is toggled for 16xN
clocks. The first 16xN bit MOSI payload (sent to Device 1 in the daisy-chain) consists of the 16-bit SPI read data
for Device N (the last device in the chain), followed by the read data for Device N-1, Device N-2, etc., ending with
the read data for Device 1 (the first device in the chain). The 16-bit SPI read data for each device consists of a
“1” (read command), seven address bits, and eight “1”s (which are ignored). After the first 16xN bit transaction,
SS must return high (to latch the data) and then is driven low again before the second 16xN bit transaction of all
“1”s is sent to the MOSI input. The requested read data is shifted out on MISO starting with the data for Device N
and ending with the data for Device 1. After this transaction, SS must return high.
SPI Read Data
³8x1´
1 A6 A5 A4 A3 A2 A1 A0
SS
(host)
SCK
(host)
MOSI
(host)
MISO
(host)
16xN clocks
Device N
Read Data
Device N-1
Read Data
'21¶7 &$5(
16xN clocks
Device 1
Read Data
³16x1´
³16x1´
³16x1´
Device N
Read Data
Device N-1
Read Data
Device 1
Read Data
SPI Read Data
1 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Figure 9. SPI Daisy-Chain Read
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SPI Daisy-Chain Read and Write Example
The following example further clarifies LMH0394 SPI daisy-chain operation. Assume a daisy-chain of three
LMH0394 devices (Device 1, Device 2, and Device 3), with Device 1 as the first device in the chain and Device 3
as the last device in the chain, as shown by the first three devices in Figure 7. Since there are three devices in
the daisy-chain, each SPI transaction is 48-bits long.
This example shows an SPI operation combining SPI reads and writes in order to accomplish the following three
tasks:
1. Write 0x22 to register 0x01 of Device 1 in order to set the output swing to 400 mVP-P.
2. Read the contents of register 0x00 of Device 2.
3. Write 0x10 to register 0x00 of Device 3 in order to force the sleep mode.
Figure 10 shows the two 48-bit SPI transactions required to complete these tasks (the bits are shifted in left to
right).
48-bit SPI Transaction #1
(Device 3)
R/W Addr
48-bit SPI Transaction #2
(Device 2)
(Device 1)
(Device 3)
Data R/W Addr
Data R/W Addr
Data
R/W Addr
(Device 2)
(Device 1)
Data R/W Addr
Data R/W Addr
Data
MOSI
(host)
0
0x01
0x22
1
0x00
0xFF
0
0x00
0x10
1
0x7F
0xFF
1
0x7F
0xFF
1
0x7F
0xFF
MISO
(host)
X
XX
XX
X
XX
XX
X
XX
XX
0
0x01
0x22
1
0x00
0x88
0
0x00
0x10
Figure 10. SPI Daisy-Chain Read and Write Example
The following occurs at the end of the first transaction:
1. Write 0x22 to register 0x01 of Device 1.
2. Latch the data from register 0x00 of Device 2.
3. Write 0x10 to register 0x00 of Device 3.
In the second transaction, three dummy reads (each consisting of 16 “1”s) are shifted in, and the read data from
Device 2 (with value 0x88) appears on MISO in the 25th through 32nd clock cycles.
SPI Daisy-Chain Length Detection
A useful operation for the host may be to detect the length of the daisy-chain. This is a simple matter of shifting
in a series of dummy reads with a known data value (such as 0x5A). For an SPI daisy-chain of N LMH0394
devices, the known data value will appear on the host's MISO pin after N+1 writes. Assuming a daisy-chain of
three LMH0394 devices, the result of this operation is shown in Figure 11.
R/W Addr
MOSI
(host)
1
MISO
(host)
X
Data R/W Addr
Data R/W Addr
Data R/W Addr
Data
0x7F
0x5A
1
0x7F
0x5A
1
0x7F
0x5A
1
0x7F
0x5A
XX
XX
X
XX
XX
X
XX
XX
1
0x7F
0x5A
Figure 11. SPI Daisy-Chain Length Detection
OUTPUT DRIVER ADJUSTMENTS AND DE-EMPHASIS SETTING
The output driver swing (amplitude), offset voltage (common mode voltage), and de-emphasis level are
adjustable via SPI register 01h.
The output swing is adjustable via bits [7:6] of SPI register 01h. The default value for these register bits is “10”
for a peak to peak differential output voltage of 700 mVP-P. The output swing can be set for 400 mVP-P,
600 mVP‑P, 700 mVP-P, or 800 mVP-P.
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The offset voltage is adjustable via bits [5:4] of SPI register 01h. The default value for these register bits is “10”
for an output offset of 1.2V. The output common mode voltage may be adjusted in 200 mV increments, from 0.8V
to 1.2V. It can be set to “11” for the maximum offset voltage. At this maximum offset voltage setting, the outputs
are referenced to the positive supply and the offset voltage is around 1.35V.
The output de-emphasis is turned on or off by bit 3 of SPI register 01h, and the de-emphasis level is set by bits
[2:1] of SPI register 01h. The output de-emphasis level may be set for 0 dB (for driving up to 10” FR4), 3 dB (for
driving 10-20” FR4), 5 dB (for driving 20-30” FR4), or 7 dB (for driving 30-40” FR4).
LAUNCH AMPLITUDE OPTIMIZATION
The LMH0394 can compensate for attenuation of the input signal prior to the equalizer. This compensation is
useful for applications with a passive splitter at the equalizer input or a non-ideal input termination network, and
is controlled by SPI register 02h.
Bit 7 of SPI register 02h is used for the launch amplitude setting. At the default setting of “0”, the LMH0394
operates normally and expects a launch amplitude of 800 mVP-P. Bit 7 may be set to “1” to optimize the LMH0394
for input signals with 6 dB of attenuation (400 mVP-P).
CABLE LENGTH INDICATOR (CLI)
The cable length indicator (CLI) provides an indication of the length of the cable attached to input. CLI is
accessible via bits [7:0] of SPI register 06h. The 8-bit setting ranges in decimal value from 0 to 247 (“00000000”
to “11110111” binary), corresponding to 0 to 400m of Belden 1694A cable. For 3G and HD input, CLI is 1.25m
per step. For SD input, CLI is 1.25m per step, less 20m, from 0 to 191 decimal, and 3.5m per step from 192 to
247 decimal.
To calculate the Belden 1694A cable length (in meters) from the CLI decimal value for 3G or HD input:
(1)
To calculate the Belden 1694A cable length (in meters) from the CLI decimal value for SD input:
(2)
Figure 12 shows typical CLI values vs. Belden 1694A cable length. CLI is valid for Belden 1694A cable lengths of
0-200m at 2.97 Gbps, 0-220m at 1.485 Gbps, and 0-400m at 270 Mbps. Note: Given the continuous adaptive
nature of the equalizer, this setting changes by some steps constantly.
250
225
CLI (decimal value)
200
175
150
SD
125
100
75
50
3G/HD
25
0
0 50 100 150 200 250 300 350 400
BELDEN 1694A CABLE LENGTH (m)
Figure 12. CLI vs. Belden 1694A Cable Length
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APPLICATION INFORMATION
APPLICATION CIRCUIT (SPI MODE)
Figure 13 shows the application circuit for the LMH0394 in SPI mode. (Note: The application circuit shows an
external capacitor connected between the AEC+ and AEC- pins as commonly configured in legacy equalizers.
This capacitor is optional and not necessary for the LMH0394; the AEC+ and AEC- pins may be left unconnected
with no change in performance.)
(SPI) MISO
(SPI) SCK
(SPI) MOSI
VCC
VCC
0.1 PF
VCC
75:
13
VCC
14
SCK
15
SDO
SPI_EN
5
37.4:
4
SDI
MUTEREF
1.0 PF
LMH0394
SS
12
11
10
Differential
Output
9
DAP
8
5.6 nH
SDO
CD
3
SDI
7
2
AEC-
1.0 PF
MISO
6
75:
VEE
AEC+
1
Coaxial Cable
MOSI
VCC
16
0.1 PF
1.0 PF
CD
MUTEREF
(SPI) SS
Figure 13. Application Circuit (SPI Mode)
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INTERFACING TO 3.3V SPI
The LMH0394 may be controlled via optional SPI register access. The LMH0394 SPI pins support 2.5V
LVCMOS logic levels and are compliant with JEDEC JESD8-5 (see DC Electrical Characteristics). Care must be
taken when interfacing the SPI pins to other voltage levels.
The 2.5V LMH0394 SPI pins may be interfaced to a 3.3V compliant SPI host by using a voltage divider or level
translator. One implementation is a simple resistive voltage divider as shown in Figure 14.
MOSI
3.16 k:
MISO
3.3V
SCK
Compliant
SPI Host
3.16 k:
9.76 k:
SS
LMH0394
9.76 k:
3.16 k:
9.76 k:
Figure 14. 3.3V SPI Interfacing
CROSSTALK IMMUNITY
Single-ended SDI signals are susceptible to crosstalk and good design practices should be employed to
minimize its effects. Most crosstalk originates through capacitive coupling from adjacent signals routed closely
together via traces and connectors. To reduce capacitive coupling, SDI signals should be appropriately spaced
apart or insulated from one another. This can be accomplished by physically isolating signal traces in the layout
and by providing additional ground pins between signal traces in connectors as necessary. These techniques
help to reduce crosstalk but do not eliminate it.
The LMH0394 was designed specifically with crosstalk in mind and incorporates advanced circuit design
techniques that help to isolate and minimize the effects of cross-coupling in high-density system designs. Lab
evaluations and customer testimonials have shown other adaptive cable equalizers are much more susceptible to
crosstalk, resulting in significant cable reach degradation. The LMH0394’s enhanced design results in minimal
degradation in cable reach in the presence of crosstalk and overall superior immunity against cross-coupling
from neighboring channels.
PCB LAYOUT RECOMMENDATIONS
For information on layout and soldering of the WQFN package, pease refer to the following application note: AN1187 Leadless Leadframe Package (LLP) application report (literature number SNOA401).
The SMPTE 424M, 292M, and 259M standards have stringent requirements for the input return loss of receivers,
which essentially specify how closely the input must resemble a 75Ω network. Any non-idealities in the network
between the BNC and the equalizer will degrade the input return loss. Care must be taken to minimize
impedance discontinuities between the BNC and the equalizer to ensure that the characteristic impedance of this
trace is 75Ω. Please consider the following PCB recommendations:
• Use surface mount components, and use the smallest components available. In addition, use the smallest
size component pads.
• Select trace widths that minimize the impedance mismatch between the BNC and the equalizer.
• Select a board stack up that supports both 75Ω single-ended traces and 100Ω loosely-coupled differential
traces.
• Place return loss components closest to the equalizer input pins.
• Maintain symmetry on the complimentary signals.
• Route 100Ω traces uniformly (keep trace widths and trace spacing uniform along the trace).
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Avoid sharp bends in the signal path; use 45° or radial bends.
Place bypass capacitors close to each power pin, and use the shortest path to connect equalizer power and
ground pins to the respective power or ground planes.
Remove ground plane under input/output components to minimize parasitic capacitance.
SPI Registers
Table 1. SPI Registers
Address
R/W
Name
00h
R/W
General Control
Bits
Default
Description
Carrier Detect
6
Mute
0
Mute has precedence over
Bypass.
0: Normal operation.
1: Outputs muted.
5
Bypass
0
0: Normal operation.
1: Equalizer bypassed.
Sleep Mode
01
Sleep mode control. Sleep has
precedence over Mute and
Bypass.
00: Disable sleep mode (force
equalizer to stay enabled).
01: Sleep mode active when no
input signal detected.
10: Force equalizer into sleep
mode (powered down)
regardless of whether there is
an input signal or not.
11: Reserved.
2
Reserved
0
Reserved as 0. Always write 0
to this bit.
1
Master Reset
0
Reset registers and state
machine. (This bit is selfclearing.)
0: Normal operation.
1: Reset registers and state
machine.
0
Acquisition Reset
0
Reset state machine. (This bit is
self-clearing.)
0: Normal operation.
1: Reset state machine.
4:3
20
Field
7
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Read only.
0: No carrier detected.
1: Carrier detected.
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Table 1. SPI Registers (continued)
Address
R/W
Name
Bits
Field
01h
R/W
Output Driver
7:6
Output Swing
10
Output driver swing (VSSP-P).
00: VSSP-P = 400 mVP-P.
01: VSSP-P = 600 mVP-P.
10: VSSP-P = 700 mVP-P.
11: VSSP-P = 800 mVP-P.
5:4
Offset Voltage
10
Output driver offset voltage
(common mode voltage).
00: VOS = 0.8V.
01: VOS = 1.0V.
10: VOS = 1.2V.
11: VOS referenced to positive
supply.
3
De-Emphasis
0
Output driver de-emphasis
control.
0: De-emphasis disabled.
1: De-emphasis enabled.
De-Emphasis Amplitude
Level
01
Output driver de-emphasis
level.
00: 0 dB (no de-emphasis).
01: 3 dB de-emphasis.
10: 5 dB de-emphasis.
11: 7 dB de-emphasis.
0
Reserved
0
Reserved (read only).
7
Launch Amplitude Control
0
Launch amplitude optimization
setting.
0: Normal optimization with no
external attenuation (800 mVP-P
launch amplitude).
1: Optimized for 6 dB external
attenuation (400 mVP-P launch
amplitude).
2:1
02h
03h
R/W
R/W
Launch Amplitude
Control
MUTEREF
05h
R
R
Device ID
Rate Indicator
Description
6:0
Reserved
1101000
Reserved as 1101000. Always
write 1101000 to these bits.
7:6
Reserved
00
Reserved as 00. Always write
00 to these bits.
MUTEREF Mode
0
0: Use MUTEREF pin.
1: Use digital MUTEREF.
5
04h
Default
4:0
Digital MUTEREF Setting
7:6
Reserved
00
Reserved.
5:4
EQ ID
01
00:
01:
10:
11:
3:0
Die Revision
7:6
Reserved
5
4:0
11111
0011
00
Rate Indicator
Reserved
Digital MUTEREF (10m per
step).
00000: Mute when cable (EQ
boost) ≥ 10m.
......
01111: Mute when cable (EQ
boost) ≥ 160m.
......
11111: Never mute.
LMH0384 device.
LMH0394 device.
LMH0395 device.
Reserved.
Die revision.
Reserved.
0: SD.
1: 3G/HD.
11000
Reserved.
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Table 1. SPI Registers (continued)
22
Address
R/W
Name
Bits
Field
06h
R
Cable Length Indicator
7:0
Cable Length Indicator
Cable Length Indicator (CLI),
with 10% accuracy.
00000000: Short cable.
......
11110111: Maximum cable.
11111000: Reserved.
......
11111111: Reserved.
07h
R
Launch Amplitude
Indication
7:2
Launch Amplitude
Indication
Indication of launch amplitude:
1% or 0.08 dB per step with 5%
accuracy.
000000: Nominal -32%.
......
011111: Nominal -1%.
100000: Nominal.
100001: Nominal +1%.
......
111111: Nominal +31%.
1:0
Reserved
Reserved.
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Default
Description
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REVISION HISTORY
Changes from Revision K (April 2013) to Revision L
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 22
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PACKAGE OPTION ADDENDUM
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15-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMH0394SQ/NOPB
ACTIVE
WQFN
RUM
16
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L0394
LMH0394SQE/NOPB
ACTIVE
WQFN
RUM
16
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L0394
LMH0394SQX/NOPB
ACTIVE
WQFN
RUM
16
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
L0394
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMH0394SQ/NOPB
WQFN
RUM
16
LMH0394SQE/NOPB
WQFN
RUM
LMH0394SQX/NOPB
WQFN
RUM
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
16
250
178.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
16
4500
330.0
12.4
4.3
4.3
1.3
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH0394SQ/NOPB
WQFN
RUM
16
1000
213.0
191.0
55.0
LMH0394SQE/NOPB
WQFN
RUM
16
250
213.0
191.0
55.0
LMH0394SQX/NOPB
WQFN
RUM
16
4500
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
RUM0016A
SQB16A (Rev A)
www.ti.com
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