LPC5410x

LPC5410x
LPC5410x
32-bit ARM Cortex-M4F/M0+ MCU; 104 KB SRAM; 512 KB
flash, 3 x I2C, 2 x SPI, 4 x USART, 32-bit counter/ timers,
SCTimer/PWM, ADC
Rev. 1.0 — 5 November 2014
Product data sheet
1. General description
The LPC5410x are ARM Cortex-M4F based microcontrollers for embedded applications.
These devices include an optional ARM Cortex-M0+ coprocessor, 104 KB of on-chip
SRAM, 512 KB on-chip flash, five general-purpose timers, one State-Configurable Timer
with PWM capabilities (SCTimer/PWM), one RTC/alarm timer, one 24-bit Multi-Rate Timer
(MRT), a Windowed Watchdog Timer (WolyWDT), four USARTs, two SPIs, three
Fast-mode plus I2C-bus interfaces with high-speed slave mode, and one 12-bit 4.8
Msamples/sec ADC.
The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power
consumption, enhanced debug features, and a high level of support block integration. The
ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with
separate local instruction and data buses as well as a third bus for peripherals, and
includes an internal prefetch unit that supports speculative branching. The ARM
Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. The
Cortex-M4F is the Cortex-M4 with the inclusion of the 32-bit Floating Point Unit.
The ARM Cortex-M0+ coprocessor is an energy-efficient and easy-to-use 32-bit core
which is code- and tool-compatible with the Cortex-M4F core. The Cortex-M0+
coprocessor offers up to 100 MHz performance with a simple instruction set and reduced
code size.
2. Features and benefits
 Dual processor cores: ARM Cortex-M4 and ARM Cortex-M0+. The M0+ core runs at
the same frequency as the M4 core. Both cores operate up to a maximum frequency of
100 MHz.
 ARM Cortex-M4F core (version r0p1):
 ARM Cortex-M4 processor, running at a frequency of up to 100 MHz.
 Floating Point Unit (FPU) and Memory Protection Unit (MPU).
 ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC).
 Non-maskable Interrupt (NMI) input with a selection of sources.
 Serial Wire Debug with eight breakpoints and four watch points.
Includes Serial Wire Output for enhanced debug capabilities.
 System tick timer.
 ARM Cortex-M0+ core (version r0p1):
 ARM Cortex-M0+ processor, running at a frequency of up to 100 MHz.
 ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller





LPC5410x
Product data sheet
 Non-maskable Interrupt (NMI) input with a selection of sources.
 Serial Wire Debug with four breakpoints and two watch points.
 System tick timer.
On-chip memory:
 Up to 512 KB on-chip flash program memory with flash accelerator and 256 byte
page erase and write.
 104 KB SRAM for code and data use.
ROM API support:
 Flash In-Application Programming (IAP) and In-System Programming (ISP).
 Power control API.
Serial interfaces:
 Four USART interfaces with synchronous mode and 32 kHz mode for wake-up
from Deep-sleep and Power-down modes. The USARTs include a FIFO buffer and
share a fractional baud-rate generator.
 Two SPI interfaces, each with four slave selects and flexible data configuration.
The SPIs include a FIFO buffer. The slave function is able to wake up the device
from Deep-sleep and Power-down modes.
 Three I2C-bus interfaces supporting fast mode and Fast-mode Plus with data rates
of up to 1Mbit/s and with multiple address recognition and monitor mode. Each
I2C-bus interface also supports High Speed Mode (3.4 Mbit/s) as a slave. The slave
function is able to wake up the device from Deep-sleep and Power-down modes.
Digital peripherals:
 DMA controller with 22 channels and 20 programmable triggers, able to access all
memories and DMA-capable peripherals.
 Up to 50 General-Purpose Input/Output (GPIO) pins. Most GPIOs have
configurable pull-up/pull-down resistors, programmable open-drain mode, and
input/output inverter.
 GPIO registers are located on the AHB for fast access. The DMA supports GPIO
ports.
 Up to eight GPIOs can be selected as pin interrupts (PINT), triggered by rising,
falling or both input edges.
 Two GPIO grouped interrupts (GINT) enable an interrupt based on a logical
(AND/OR) combination of input states.
 CRC engine.
Timers:
 Five 32-bit general purpose timers/counters, with up to 4 capture inputs and 4
compare outputs, PWM mode, and external count input. Specific timer events can
be selected to generate DMA requests.
 One State Configurable Timer/PWM (SCT) with 6 input and 8 output functions
(including capture and match). Inputs and outputs can be routed to/from external
pins and internally to/from selected peripherals. Internally, the SCT supports 13
captures/matches, 13 events and 13 states.
 32-bit Real-time clock (RTC) with 1 s resolution running in the always-on power
domain. A timer in the RTC can be used for wake-up from all low power modes
including Deep power-down, with 1 ms resolution. The RTC is clocked by the 32
kHz oscillator.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller


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






LPC5410x
Product data sheet
 Multiple-channel multi-rate 24-bit timer (MRT) for repetitive interrupt generation at
up to four programmable, fixed rates.
 Windowed Watchdog Timer (WWDT).
 Ultra-low power Micro-tick Timer, running from the Watchdog oscillator, that can be
used to wake up the device from low power modes.
 Repetitive Interrupt Timer (RIT) for debug time-stamping and general-purpose use.
Analog peripheral: 12-bit, 12-channel, Analog-to-Digital Converter (ADC) supporting
4.8 Msamples/s. The ADC supports two independent conversion sequences.
Clock generation:
 12 MHz internal RC oscillator.
 External clock input for clock frequencies of up to 24 MHz.
 Internal low-power, watchdog oscillator with a nominal frequency of 500 kHz
(WDOSC).
 32 kHz low-power RTC oscillator.
 System PLL allows CPU operation up to the maximum CPU rate. May be run from
the internal RC oscillator, the external clock input CLKIN, or the RTC oscillator.
 Clock output function for monitoring internal clocks.
 Frequency measurement unit for measuring the frequency of any on-chip or
off-chip clock signal.
Power-saving modes and wake-up:
 Integrated PMU (Power Management Unit) to minimize power consumption.
 Reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.
 Wake-up from Deep-sleep and Power-down modes via activity on the USART, SPI,
and I2C peripherals.
 Wake-up from Sleep, Deep-sleep, Power-down, and Deep power-down modes
using the RTC alarm.
 The Micro-tick Timer can wake-up the device from the Deep power-down mode by
using the watchdog oscillator when no other on-chip resources are running.
Single power supply 1.62 V to 3.6 V.
Power-On Reset (POR).
Brown-Out Detect (BOD) with separate thresholds for interrupt and forced reset.
JTAG boundary scan supported.
Unique device serial number for identification.
Operating temperature range 40 °C to 105 °C.
Available in a 3.288 x 3.288 mm WLCSP49 package and LQFP64 package.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
3. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
LPC54102J512UK49
WLCSP49
wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x
0.54 mm
-
LPC54102J256UK49
WLCSP49
wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x
0.54 mm
-
LPC54101J512UK49
WLCSP49
wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x
0.54 mm
-
LPC54101J256UK49
WLCSP49
wafer level chip-size package; 49 (7 x 7) bumps; 3.288 x 3.288 x
0.54 mm
-
LPC54102J512BD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10  10  1.4 SOT314-2
mm
LPC54102J256BD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10  10  1.4 SOT314-2
mm
LPC54101J512BD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10  10  1.4 SOT314-2
mm
LPC54101J256BD64
LQFP64
plastic low profile quad flat package; 64 leads; body 10  10  1.4 SOT314-2
mm
3.1 Ordering options
Table 2.
Type number
Flash/KB
Total
Core M4
SRAM/KB w/ FPU
Core M0+ GPIO
LPC54102J512UK49
512
104
1
1
39
LPC54102J256UK49
256
104
1
1
39
LPC54101J512UK49
512
104
1
0
39
LPC54101J256UK49
256
104
1
0
39
LPC54102J512BD64
512
104
1
1
50
LPC54102J256BD64
256
104
1
1
50
LPC54101J512BD64
512
104
1
0
50
LPC54101J256BD64
256
104
1
0
50
[1]
LPC5410x
Product data sheet
Ordering options
All of the parts include five general-purpose timers, one State-Configurable Timer with PWM capabilities
(SCTimer/PWM), one RTC/alarm timer, one 24-bit Multi-Rate Timer (MRT), a Windowed Watchdog Timer
(WWDT), four USARTs, two SPIs, three Fast-mode plus I2C-bus interfaces with high-speed slave mode,
and one 12-bit 4.8 Msamples/sec ADC.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
4. Marking
Terminal 1
index area
n
1
Terminal 1 index area
aaa-011231
Fig 1.
LQFP64 package marking
aaa-015675
Fig 2.
WLCSP49 package marking
The LPC5410x LQFP64 package has the following top-side marking:
•
•
•
•
First line: LPC5410xJ512
Second line: BD64
Third line: xxxxxxxxxxxx
Fourth line: xxxyywwx[R]x
– yyww: Date code with yy = year and ww = week.
– R = Chip revision.
The LPC5410x WLCSP49 package has the following top-side marking:
•
•
•
•
First line: LPC5410x
Second line: J512UK49
Third line: xxxxxxxx
Fourth line: xxxyyww
– yyww: Date code with yy = year and ww = week.
• Fifth line: xxxxx
• Sixth line: NXP x[R]x
– R = Chip revision.
LPC5410x
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
5. Block diagram
Serial Wire
Debug
JTAG boundary
scan
CLKIN
Debug Interface
Power-on Reset
Brownout Detect
FPU
MPU
ARM
Cortex M0+
DMA
controller
System PLL
clock generation,
power control,
and other
system functions
CLKOUT
System
D-code
I-code
ARM
Cortex M4
Internal RC osc.
RESET
Flash
acclerator
Flash
512 kB
SRAM0
64 kB
SRAM1
32 kB
SC Timer
Multilayer
AHB Matrix
SRAM2
8 kB
Mailbox
Boot and driver
ROM 64 kB
CRC
engine
DMA
registers
GPIO
VFIFO
registers
ADC
12 ch, 12-bit
Sync APB
bridge
APB slave group 0
Sync APB
bridge
Multi-rate Timer
Frequency Measurement Unit
APB slave group 1
3x 32-bit timers (T2, T3, T4)
USART 0, 1, 2, and 3
GPIO global interrupts 0 and 1
I2C0, 1, 2
I/O configuration
SPI0, 1
System control
2x 32-bit timers (T0, T1)
Flash registers
Fractional Rate Generator
PMU registers
Windowed Watchdog
Watchdog oscillator
MicroTick Timer
RTC Alarm
Real Time Clock
RTC Power Domain
divider
32 kHz
oscillator
aaa-015626
Gray-shaded peripheral blocks provide dedicated request lines or triggers for DMA transfers.
Fig 3.
LPC5410x Block diagram
LPC5410x
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
6. Pinning information
6.1 Pinning
G
F
E
D
C
B
A
1
2
3
4
ball A1 (pin #1)
index area
Fig 4.
LPC5410x
Product data sheet
5
6
7
aaa-015470
WLCSP49 Pin configuration
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
7 of 60
LPC5410x
NXP Semiconductors
33 RTCXIN
34 VDDREG
35 RTCXOUT
36 PIO0_2
37 PIO0_3
38 PIO0_4
39 PIO0_5
40 PIO0_6
41 PIO0_7
42 PIO1_11
43 PIO0_8
44 PIO0_9
45 PIO0_10
46 PIO0_11
47 PIO0_12
48 PIO0_13
32-bit ARM Cortex-M4F/M0+ microcontroller
PIO0_14 49
32 PIO0_1
PIO0_15 50
31 PIO0_0
PIO1_12 51
30 PIO1_10
SWCLK/ PIO0_16 52
29 PIO1_9
SWDIO/ PIO0_17 53
28 PIO1_8
PIO1_13 54
27 PIO1_7
VSS 55
26 PIO1_6
VDD 56
25 VSS
LPC5410x
PIO1_2 16
PIO1_1 15
PIO1_0 14
PIO0_31 13
PIO0_30 12
17 PIO1_3
PIO0_29 11
18 PIO1_4
RESET 64
PIO1_17 10
PIO0_22 63
VSS 9
19 PIO1_5
VDD 8
20 VSSA
PIO1_15 62
PIO1_16 7
PIO0_21 61
PIO0_28 6
21 VREFN
PIO0_27 5
22 VREFP
PIO0_20 60
PIO0_26 4
PIO0_19 59
PIO0_25 3
23 VDDA
PIO0_24 2
24 VDD
PIO0_18 58
PIO0_23 1
PIO1_14 57
aaa-013021
Fig 5.
LPC5410x
Product data sheet
LQFP64 Pin configuration
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
6.2 Pin description
On the LPC5410x, digital pins are grouped into two ports. Each digital pin may support up
to four different digital functions and one analog function, including General Purpose I/O
(GPIO).
PIO0_0
PIO0_1
PIO0_2
PIO0_3
PIO0_4
PIO0_5
B6
-
-
C7
C6
LPC5410x
Product data sheet
32
36
37
38
39
[2]
[2]
[2]
[2]
[2]
[2]
Z
Z
Z
Z
Z
Z
Type
31
Description
[1]
A6
Reset state
LQFP64
Symbol
Pin description
WLCSP49
Table 3.
I/O
PIO0_0 — General-purpose digital input/output pin.
I
U0_RXD — Receiver input for USART0.
I/O
SPI0_SSEL0 — Slave Select 0 for SPI0.
I
CT32B0_CAP0 — 32-bit timer0 capture input 0.
I
R — Reserved.
O
SCT0_OUT3 — SCT0 output 3. PWM output 3.
I/O
PIO0_1 — General-purpose digital input/output pin.
O
U0_TXD — Transmitter output for USART0.
I/O
SPI0_SSEL1 — Slave Select 1 for SPI0.
I
CT32B0_CAP1 — 32-bit timer0 capture input 1.
I
R — Reserved.
O
SCT0_OUT1 — SCT0 output 1. PWM output 1.
I/O
PIO0_2 — General-purpose digital input/output pin.
I
U0_CTS — Clear To Send input for USART0.
I
R — Reserved.
I
CT32B2_CAP1 — 32-bit timer2 capture input 1.
I
R — Reserved.
I/O
PIO0_3 — General-purpose digital input/output pin.
O
U0_RTS — Request To Send output for USART0.
I
R — Reserved.
O
CT32B1_MAT3 — 32-bit timer1 match output 3.
I
R — Reserved.
I/O
PIO0_4 — General-purpose digital input/output pin.
I/O
U0_SCLK — USART0 clock in synchronous USART mode.
I/O
SPI0_SSEL2 — Slave Select 2 for SPI0.
I
CT32B0_CAP2 — 32-bit timer0 capture input 2.
I
R — Reserved.
I/O
PIO0_5 — General-purpose digital input/output pin.
I
U1_RXD — Receiver input for USART1.
O
SCT0_OUT6 — SCT0 output 6. PWM output 6.
O
CT32B0_MAT0 — 32-bit timer0 match output 0.
I
R — Reserved.
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Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
PIO0_6
PIO0_7
PIO0_8
PIO0_9
PIO0_10
PIO0_11
PIO0_12
D6
D5
E7
E6
E5
F7
LPC5410x
Product data sheet
41
43
44
45
46
47
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Z
Z
Z
Z
Z
Z
Z
Type
40
Description
[1]
D7
Reset state
LQFP64
Symbol
Pin description …continued
WLCSP49
Table 3.
I/O
PIO0_6 — General-purpose digital input/output pin.
O
U1_TXD — Transmitter output for USART1.
I
R — Reserved.
O
CT32B0_MAT1 — 32-bit timer0 match output 1.
I
R — Reserved.
I/O
PIO0_7 — General-purpose digital input/output pin.
I/O
U1_SCLK — USART1 clock in synchronous USART mode.
O
SCT0_OUT0 — SCT0 output 0. PWM output 0.
O
CT32B0_MAT2 — 32-bit timer0 match output 2.
I
R — Reserved.
I
CT32B0_CAP2 — 32-bit timer0 capture input 2.
I/O
PIO0_8 — General-purpose digital input/output pin.
I
U2_RXD — Receiver input for USART2.
O
SCT0_OUT1 — SCT0 output 1. PWM output 1.
O
CT32B0_MAT3 — 32-bit timer0 match output 3.
I
R — Reserved.
I/O
PIO0_9 — General-purpose digital input/output pin.
O
U2_TXD — Transmitter output for USART2.
O
SCT0_OUT2 — SCT0 output 2. PWM output 2.
I
CT32B3_CAP0 — 32-bit timer3 capture input 0.
I
R — Reserved.
I/O
SPI0_SSEL0 — Slave Select 0 for SPI0.
I/O
PIO0_10 — General-purpose digital input/output pin.
I/O
U2_SCLK — USART2 clock in synchronous USART mode.
O
SCT0_OUT3 — SCT0 output 3. PWM output 3.
O
CT32B3_MAT0 — 32-bit timer3 match output 0.
I
R — Reserved.
I/O
PIO0_11 — General-purpose digital input/output pin.
I/O
SPI0_SCK — Serial clock for SPI0.
I
U1_RXD — Receiver input for USART1.
O
CT32B2_MAT1 — 32-bit timer2 match output 1.
I
R — Reserved.
I/O
PIO0_12 — General-purpose digital input/output pin.
I/O
SPI0_MOSI — Master Out Slave in for SPI0.
O
U1_TXD — Transmitter output for USART1.
O
CT32B2_MAT3 — 32-bit timer2 match output 3.
I
R — Reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
PIO0_13
PIO0_14/
TCK
PIO0_15
F6
49
[2]
[2]
Z
Z
Type
48
Description
[1]
G7
Reset state
LQFP64
Symbol
Pin description …continued
WLCSP49
Table 3.
I/O
PIO0_13 — General-purpose digital input/output pin.
I/O
SPI0_MISO — Master In Slave Out for SPI0.
O
SCT0_OUT4 — SCT0 output 4. PWM output 4.
O
CT32B2_MAT0 — 32-bit timer2 match output 0.
I
R — Reserved.
I/O
PIO0_14 — General-purpose digital input/output pin.
In boundary scan mode: TCK (Test Clock).
G6
50
[2]
Z
I/O
SPI0_SSEL0 — Slave Select 0 for SPI0.
O
SCT0_OUT5 — SCT0 output 5. PWM output 5.
O
CT32B2_MAT1 — 32-bit timer2 match output 1.
I
R — Reserved.
I/O
PIO0_15 — General-purpose digital input/output pin.
In boundary scan mode: TDO (Test Data Out).
SWCLK/
PIO0_16
SWDIO/
PIO0_17
PIO0_18/
TRST
F5
G5
G4
LPC5410x
Product data sheet
52
53
58
[2]
[2]
[2]
Z
Z
Z
I/O
SPI0_SSEL1 — Slave Select 1 for SPI0.
I/O
SWO — Serial wire trace output.
O
CT32B2_MAT2 — 32-bit timer2 match output 2.
I
R — Reserved.
I/O
PIO0_16 — General-purpose digital input/output pin. After booting, this pin is
connected to the SWCLK.
I/O
SPI0_SSEL2 — Slave Select 2 for SPI0.
I
U1_CTS — Clear To Send input for USART1.
O
CT32B3_MAT1 — 32-bit timer3 match output 1.
I
R — Reserved.
I/O
SWCLK — Serial Wire Clock. JTAG Test Clock. This is the default function after
booting.
I/O
PIO0_17 — General-purpose digital input/output pin. After booting, this pin is
connected to SWDIO.
I/O
SPI0_SSEL3 — Slave Select 3 for SPI0.
O
U1_RTS — Request To Send output for USART1.
O
CT32B3_MAT2 — 32-bit timer3 match output 2.
I
R — Reserved.
I/O
SWDIO — Serial Wire Debug I/O. This is the default function after booting.
I/O
PIO0_18 — General-purpose digital input/output pin. In boundary scan mode:
TRST (Test Reset).
O
U3_TXD — Transmitter output for USART3.
O
SCT0_OUT0 — SCT0 output 0. PWM output 0.
O
CT32B0_MAT0 — 32-bit timer0 match output 0.
I
R — Reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
PIO0_19/
TDI
PIO0_20
PIO0_21
PIO0_22
PIO0_23
PIO0_24
PIO0_25
F3
E3
G2
F2
F1
E2
LPC5410x
Product data sheet
60
61
63
1
2
3
[2]
[2]
[2]
[2]
[3]
[3]
[3]
Z
Z
Z
Z
Z
Z
Z
Type
59
Description
[1]
G3
Reset state
LQFP64
Symbol
Pin description …continued
WLCSP49
Table 3.
I/O
PIO0_19 — General-purpose digital input/output pin. In boundary scan mode:
TDI (Test Data In).
I/O
U3_SCLK — USART3 clock in synchronous USART mode.
O
SCT0_OUT1 — SCT0 output 1. PWM output 1.
O
CT32B0_MAT1 — 32-bit timer0 match output 1.
I
R — Reserved.
I/O
PIO0_20 — General-purpose digital input/output pin. In boundary scan mode:
TMS (Test Mode Select).
I
U3_RXD — Receiver input for USART3.
I/O
U0_SCLK — USART0 clock in synchronous USART mode.
I
CT32B3_CAP0 — 32-bit timer3 capture input 0.
I
R — Reserved.
I/O
PIO0_21 — General-purpose digital input/output pin.
O
CLKOUT — Clockout pin.
O
U0_TXD — Transmitter output for USART0.
O
CT32B3_MAT0 — 32-bit timer3 match output 0.
I
R — Reserved.
I/O
PIO0_22 — General-purpose digital input/output pin.
I
CLKIN — Clock input.
I
U0_RXD — Receiver input for USART0.
O
CT32B3_MAT3 — 32-bit timer3 match output 3.
I
R — Reserved.
I/O
PIO0_23 — General-purpose digital input/output pin.
I/O
I2C0_SCL — I2C0 clock input/output.
I
R — Reserved.
I
CT32B0_CAP0 — 32-bit timer0 capture input 0.
I
R — Reserved.
I/O
PIO0_24 — General-purpose digital input/output pin.
I/O
I2C0_SDA — I2C0 data input/output.
I
R — Reserved.
I
CT32B0_CAP1 — 32-bit timer0 capture input 1.
I
R — Reserved.
O
CT32B0_MAT0 — 32-bit timer0 match output 0.
I/O
PIO0_25 — General-purpose digital input/output pin.
I/O
I2C1_SCL — I2C1 clock input/output.
I
U1_CTS — Clear To Send input for USART1.
I
CT32B0_CAP2 — 32-bit timer0 capture input 2.
I
R — Reserved.
I
CT32B1_CAP1 — 32-bit timer1 capture input 1.
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
PIO0_26
PIO0_27
PIO0_28
PIO0_29/
ADC0_0
PIO0_30/
ADC0_1
PIO0_31/
ADC0_2
D2
D1
D3
C1
C2
LPC5410x
Product data sheet
5
6
11
12
13
[3]
[3]
[3]
[4]
[4]
[4]
Z
Z
Z
Z
Z
Z
Type
4
Description
[1]
E1
Reset state
LQFP64
Symbol
Pin description …continued
WLCSP49
Table 3.
I/O
PIO0_26 — General-purpose digital input/output pin.
I/O
I2C1_SDA — I2C1 data input/output.
I
R — Reserved.
I
CT32B0_CAP3 — 32-bit timer0 capture input 3.
I
R — Reserved.
I/O
PIO0_27 — General-purpose digital input/output pin.
I/O
I2C2_SCL — I2C2 clock input/output.
I
R — Reserved.
I
CT32B2_CAP0 — 32-bit timer2 capture input 0.
I
R — Reserved.
I/O
PIO0_28 — General-purpose digital input/output pin.
I/O
I2C2_SDA — I2C2 data input/output.
I
R — Reserved.
O
CT32B2_MAT0 — 32-bit timer2 match output 0.
I
R — Reserved.
I/O;
AI
PIO0_29/ADC0_0 — General-purpose digital input/output pin (default). ADC
input channel 0 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
-
R — Reserved.
O
SCT0_OUT2 — SCT0 output 2.
O
CT32B0_MAT3 — 32-bit timer0 match output 3.
I
R — Reserved.
I
CT32B0_CAP1 — 32-bit timer0 capture input 1.
O
CT32B0_MAT1 — 32-bit timer0 match output 1.
I/O;
AI
PIO0_30/ADC0_1 — General-purpose digital input/output pin (default). ADC
input channel 1 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
-
R — Reserved.
O
SCT0_OUT3 — SCT0 output 3.
O
CT32B0_MAT2 — 32-bit timer0 match output 2.
I
R — Reserved.
I
CT32B0_CAP2 — 32-bit timer0 capture input 2.
I/O;
AI
PIO0_31/ADC0_2 — General-purpose digital input/output pin (default). ADC
input channel 2 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
ISP entry pin. A LOW level on this pin during reset starts the ISP command
handler.
-
R — Reserved.
I
U2_CTS — Clear To Send input for USART2.
I
CT32B2_CAP2 — 32-bit timer2 capture input 2.
I
R — Reserved.
I
CT32B0_CAP3 — 32-bit timer0 capture input 3.
O
CT32B0_MAT3 — 32-bit timer0 match output 3.
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Rev. 1.0 — 5 November 2014
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LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
PIO1_0/
ADC0_3
PIO1_1/
ADC0_4
PIO1_2/
ADC0_5
PIO1_3/
ADC0_6
PIO1_4/
ADC0_7
B1
A1
B2
A2
LPC5410x
Product data sheet
15
16
17
18
[4]
[4]
[4]
[4]
[4]
Z
Z
Z
Z
Z
Type
14
Description
[1]
C3
Reset state
LQFP64
Symbol
Pin description …continued
WLCSP49
Table 3.
I/O;
AI
PIO1_0/ADC0_3 — General-purpose digital input/output pin (default). ADC
input channel 3 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
-
R — Reserved.
O
U2_RTS — Request To Send output for USART2.
O
CT32B3_MAT1 — 32-bit timer3 match output 1.
I
R — Reserved.
I
CT32B0_CAP0 — 32-bit timer0 capture input 0.
I/O;
AI
PIO1_1/ADC0_4 — General-purpose digital input/output pin (default). ADC
input channel 4 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
-
R — Reserved.
I/O
SWO — Serial wire trace output.
O
SCT0_OUT4 — SCT0 output 4.
I/O;
AI
PIO1_2/ADC0_5 — General-purpose digital input/output pin (default). ADC
input channel 5 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
-
R — Reserved.
I/O
SPI1_SSEL3 — Slave Select 3 for SPI1.
O
SCT0_OUT5 — SCT0 output 5.
I/O;
AI
PIO1_3/ADC0_6 — General-purpose digital input/output pin (default). ADC
input channel 6 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
-
R — Reserved.
I/O
SPI1_SSEL2 — Slave Select 2 for SPI1.
O
SCT0_OUT6 — SCT0 output 6.
I
R — Reserved.
I/O
SPI0_SCK — Serial clock for SPI0.
I
CT32B0_CAP1 — 32-bit timer0 capture input 1.
I/O;
AI
PIO1_4/ADC0_7 — General-purpose digital input/output pin (default). ADC
input channel 7 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
-
R — Reserved.
I/O
SPI1_SSEL1 — Slave Select 1 for SPI1.
O
SCT0_OUT7 — SCT0 output 7.
I
R — Reserved.
I/O
SPI0_MISO — Master In Slave Out for SPI0.
O
CT32B0_MAT1 — 32-bit timer0 match output 1.
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Rev. 1.0 — 5 November 2014
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LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
PIO1_5/
ADC0_8
PIO1_6/
ADC0_9
PIO1_7/
ADC0_10
PIO1_8/
ADC0_11
PIO1_9
A5
B5
C5
-
LPC5410x
Product data sheet
26
27
28
29
[4]
[4]
[4]
[4]
[2]
Z
Z
Z
Z
Z
Type
19
Description
[1]
B3
Reset state
LQFP64
Symbol
Pin description …continued
WLCSP49
Table 3.
I/O;
AI
PIO1_5/ADC0_8 — General-purpose digital input/output pin (default). ADC
input channel 8 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
-
R — Reserved.
I/O
SPI1_SSEL0 — Slave Select 0 for SPI1.
I
CT32B1_CAP0 — 32-bit timer1 capture input 0.
I
R — Reserved.
O
CT32B1_MAT3 — 32-bit timer1 match output 3.
I
R — Reserved.
I/O;
AI
PIO1_6/ADC0_9 — General-purpose digital input/output pin (default). ADC
input channel 9 if the DIGIMODE bit is set to 0 in the IOCON register for this pin.
-
R — Reserved.
I/O
SPI1_SCK — Serial clock for SPI1.
I
CT32B1_CAP2 — 32-bit timer1 capture input 2.
-
R — Reserved.
O
CT32B1_MAT2 — 32-bit timer1 match output 2.
I
R — Reserved.
I/O;
AI
PIO1_7/ADC0_10 — General-purpose digital input/output pin (default). ADC
input channel 10 if the DIGIMODE bit is set to 0 in the IOCON register for this
pin.
-
R — Reserved.
I/O
SPI1_MOSI — Master Out Slave in for SPI1.
O
CT32B1_MAT2 — 32-bit timer1 match output 2.
-
R — Reserved.
I
CT32B1_CAP2 — 32-bit timer1 capture input 2.
I
R — Reserved.
I/O;
AI
PIO1_8/ADC0_11 — General-purpose digital input/output pin (default). ADC
input channel 11 if the DIGIMODE bit is set to 0 in the IOCON register for this
pin.
-
R — Reserved.
I/O
SPI1_MISO — Master In Slave Out for SPI1.
O
CT32B1_MAT3 — 32-bit timer1 match output 3.
I
R — Reserved.
I
CT32B1_CAP3 — 32-bit timer1 capture input 3.
I
R — Reserved.
I/O
PIO1_9 — General-purpose digital input/output pin.
I
R — Reserved.
I/O
SPI0_MOSI — Master Out Slave In for SPI0.
I
CT32B0_CAP2 — 32-bit timer0 capture input 2.
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LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
PIO1_10
PIO1_11
PIO1_12
PIO1_13
PIO1_14
PIO1_15
PIO1_16
PIO1_17
-
-
-
-
-
-
-
42
51
54
57
62
7
[2]
[2]
[2]
[2]
[2]
[2]
[2]
Z
Z
Z
Z
Z
Z
Z
Type
30
Description
[1]
-
Reset state
LQFP64
Symbol
Pin description …continued
WLCSP49
Table 3.
I/O
PIO1_10 — General-purpose digital input/output pin.
I
R — Reserved.
O
U1_TXD — Transmitter output for USART1.
O
SCT0_OUT4 — SCT0 output 4.
I/O
PIO1_11 — General-purpose digital input/output pin.
I
R — Reserved.
O
U1_RTS — Request To Send output for USART1.
I
CT32B1_CAP0 — 32-bit timer1 capture input 0.
I/O
PIO1_12 — General-purpose digital input/output pin.
I
R — Reserved.
I
U3_RXD — Receiver input for USART3.
O
CT32B1_MAT0 — 32-bit timer1 match output 0.
I/O
SPI1_SCK — Serial clock for SPI1.
I/O
PIO1_13 — General-purpose digital input/output pin.
I
R — Reserved.
O
U3_TXD — Transmitter output for USART3.
O
CT32B1_MAT1 — 32-bit timer1 match output 1.
I/O
SPI1_MOSI — Master Out Slave In for SPI1.
I/O
PIO1_14 — General-purpose digital input/output pin.
I
R — Reserved.
I
U2_RXD — Receiver input for USART2.
O
SCT0_OUT7 — SCT0 output 7.
I/O
SPI1_MISO — Master In Slave Out for SPI1.
I/O
PIO1_15 — General-purpose digital input/output pin.
I
R — Reserved.
O
SCT0_OUT5 — SCT0 output 5.
I
CT32B1_CAP3 — 32-bit timer1 capture input 3.
I/O
SPI1_SSEL0 — Slave Select 0 for SPI1.
I/O
PIO1_16 — General-purpose digital input/output pin.
I
R — Reserved.
O
CT32B0_MAT0 — 32-bit timer0 match output 0.
I
CT32B0_CAP0 — 32-bit timer0 capture input 0.
I/O
SPI1_SSEL1 — Slave Select 1 for SPI1.
10
[2]
Z
I/O
PIO1_17 — General-purpose digital input/output pin.
[5]
I; IA
I
External reset input: A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at
address 0. Wakes up the part from Deep power-down mode. Pull-up enabled.
RESET
G1
64
RTCXIN
A7
33
RTC oscillator input.
RTCXOUT B7
35
RTC oscillator output.
LPC5410x
Product data sheet
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LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
Table 3.
B4
22
-
VREFN
-
21
-
VDDA
A4
23
-
VDD
C4;
F4
8,
24,
56,
34
-
-
Single digital 1.62 V to 3.6 V power supply.
VSS
D4;
E4
9,
25,
55
-
-
Ground.
VSSA
A3
20
Type
Reset state
VREFP
[1]
LQFP64
Description
WLCSP49
Symbol
Pin description …continued
ADC positive reference voltage.
-
ADC negative reference voltage.
Analog supply voltage 1.62 V to 3.6 V.
Analog ground.
[1]
Z = high-impedance; pull-up/pull-down disabled (inputs can float); I = input, O = output, IA = inactive; PD = pull-down enabled, PU =
pull-up enabled (weak pull-up resistor pulls up pin to VDD); Reset state reflects the pin state at reset without boot code operation.
[2]
5 V tolerant pad with 15 ns programmable glitch filter (5 V tolerant if VDD present; if VDD not present, do not exceed 3.6 V); provides
digital I/O functions with TTL levels and hysteresis; normal drive strength (see Figure 11).
[3]
Specialized I2C pads.
[4]
Digital I/O pad with analog functionality.
[5]
Reset pad.
LPC5410x
Product data sheet
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Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
7. Functional description
7.1 Architectural overview
The ARM Cortex-M4F includes three AHB-Lite buses: the system bus, the I-code bus,
and the D-code bus. The I-code and D-code core buses allow for concurrent code and
data accesses from different slave ports.
The LPC5410x uses a multi-layer AHB matrix to connect the ARM Cortex-M4 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals that are on different slave ports of the matrix to be accessed
simultaneously by different bus masters.
7.2 ARM Cortex-M4F processor
The ARM Cortex-M4F is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M4F offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware multiply and
divide, interruptable/continuable multiple load and store instructions, automatic state save
and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
7.3 ARM Cortex-M4 integrated Floating Point Unit (FPU)
The FPU fully supports single-precision add, subtract, multiply, divide, multiply and
accumulate, and square root operations. It also provides conversions between fixed-point
and floating-point data formats, and floating-point constant instructions.
The FPU provides floating-point computation functionality that is compliant with the
ANSI/IEEE Std 754-2008, IEEE Standard for Binary Floating-Point Arithmetic, referred to
as the IEEE 754 standard.
7.4 ARM Cortex-M0+ co-processor
The ARM Cortex-M0+ co-processor offers high performance and very low power
consumption. This processor uses a 2-stage pipeline von Neumann architecture and a
small but powerful instruction set providing high-end processing hardware. The processor
includes a single-cycle multiplier, an NVIC with 32 interrupts and a separate system tick
timer.
7.5 Memory Protection Unit (MPU)
The Cortex-M4F includes a Memory Protection Unit (MPU) which can be used to improve
the reliability of an embedded system by protecting critical data within the user
application.
The MPU allows separating processing tasks by disallowing access to each other's data,
disabling access to memory regions, allowing memory regions to be defined as read-only
and detecting unexpected memory accesses that could potentially break the system.
LPC5410x
Product data sheet
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LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
The MPU separates the memory into distinct regions and implements protection by
preventing disallowed accesses. The MPU supports up to eight regions each of which can
be divided into eight subregions. Accesses to memory locations that are not defined in the
MPU regions, or not permitted by the region setting, will cause the Memory Management
Fault exception to take place.
7.6 Nested Vectored Interrupt Controller (NVIC) for Cortex-M4F
The NVIC is an integral part of the Cortex-M4F. The tight coupling to the CPU allows for
low interrupt latency and efficient processing of late arriving interrupts.
7.6.1 Features
•
•
•
•
•
Controls system exceptions and peripheral interrupts.
Eight programmable interrupt priority levels, with hardware priority level masking.
Relocatable vector table.
Non-Maskable Interrupt (NMI).
Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags.
7.7 Nested Vectored Interrupt Controller (NVIC) for Cortex-M0+
The NVIC is an integral part of the Cortex-M0+. The tight coupling to the CPU allows for
low interrupt latency and efficient processing of late arriving interrupts.
7.7.1 Features
•
•
•
•
•
Controls system exceptions and peripheral interrupts.
Four programmable interrupt priority levels, with hardware priority level masking.
Relocatable vector table.
Non-Maskable Interrupt (NMI).
Software interrupt generation.
7.7.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but may have several
interrupt flags.
7.8 System Tick timer (SysTick)
The ARM Cortex-M4F includes a system tick timer (SysTick) that is intended to generate
a dedicated SYSTICK exception. The clock source for the SysTick can be the IRC or the
Cortex-M4F core clock.
7.9 On-chip static RAM
The LPC5410x support 104 KB SRAM with separate bus master access for higher
throughput and individual power control for low-power operation.
LPC5410x
Product data sheet
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LPC5410x
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32-bit ARM Cortex-M4F/M0+ microcontroller
7.10 On-chip flash
The LPC5410x supports 512 KB of on-chip flash memory.
7.11 On-chip ROM
The 64 kB on-chip ROM contains the boot loader and the following Application
Programming Interfaces (API):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming.
• Power control API for configuring power consumption and PLL settings.
LPC5410x
Product data sheet
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LPC5410x
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32-bit ARM Cortex-M4F/M0+ microcontroller
7.12 Memory mapping
The LPC5410x incorporates several distinct memory regions. The APB peripheral area is
512 kB in size and is divided to allow for up to 32 peripherals.Each peripheral is allocated
16 kB of space simplifying the address decoding. The registers incorporated into the CPU,
such as NVIC, SysTick, and sleep mode control, are located on the private peripheral bus.
Figure 6 shows the overall map of the entire address space from the user program
viewpoint following reset.
APB1 peripherals
Memory space
4 GB
(reserved)
private peripheral bus
(reserved)
APB peripheral group 1
APB peripheral group 0
Peripheral FIFOs (VFIFO)
ADC0
(reserved)
Mailbox
(reserved)
SCT0
reserved
CRC Engine
(reserved)
DMA registers
14
Timer 1
13
Timer 0
0xE000 0000
12
(reserved)
0x4400 0000
11
(reserved)
10
SPI 1
0x4200 0000
9
SPI 0
0x4010 0000
8
(reserved)
7
I 2C 2
6
I2C 1
5
I2C 0
4
USART 3
0x1C03 8000
3
USART 2
0x1C03 4000
2
USART 1
0x1C03 0000
1
USART 0
0x1C02 C000
0
ASYNCHSYSCON
0x1C01 C000
APB0 peripherals
0x4008 0000
0x1C03 C000
0x1C01 8000
31-30
(reserved)
0x1C01 4000
29
MRT
0x1C01 0000
28
RIT
27 -21
(reserved)
20
Input Mux
19 :16
(reserved)
15
RTC
0x1C00 8000
0x1C00 4000
GPIO
0x1C00 0000
reserved
0x0340 2000
SRAM2 (8 kB)
0x0340 0000
(reserved)
Boot and Driver ROM
(reserved)
0x0301 0000
0x400B 4000
0x400B 0000
0x400A C000
0x400A 8000
0x400A 4000
0x400A 0000
0x4009 C000
0x4009 8000
0x4009 4000
0x4009 0000
0x4008 C000
0x4008 8000
0x4007 4000
0x4007 0000
0x4005 4000
0x4005 0000
0x4004 0000
Watchdog Timer
13:12
(reserved)
11
ADVSYSCON
0x0300 0000
9
Flash controller
0x0201 8000
8
MicroTick Timer
SRAM0 (up to 64 kB)
0x0200 0000
0x0008 0000
512 kB flash memory
0x0000 0000
active interrupt vectors
IOCON
6
PINT
5
GINT 1
4
GINT 0
3
Timer 4
2
Timer 3
1
Timer 2
0
Syscon
0x0000 00C0
0x0000 0000
0x4008 0000
0x4007 FFFF
14
7
0x4008 4000
0x4007 8000
reserved
0x0201 0000
Fig 6.
0x400B 8000
10
SRAM1 (up to 32 kB)
reserved
0x400F FFFF
0x400B C000
0xFFFF FFFF
0x4000 0000
(reserved)
(reserved)
0xE010 0000
APB peripheral
bit-band addressing
(reserved)
31-15
0x4003 C000
0x4003 8000
0x4002 C000
0x4002 8000
0x4002 4000
0x4002 0000
0x4001 C000
0x4001 8000
0x4001 4000
0x4001 0000
0x4000 C000
0x4000 8000
0x4000 4000
0x4000 0000
aaa-015472
LPC5410x Memory mapping
LPC5410x
Product data sheet
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LPC5410x
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32-bit ARM Cortex-M4F/M0+ microcontroller
7.13 General Purpose I/O (GPIO)
The LPC5410x provides two GPIO ports with a total of 50 GPIO pins.
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The current level
of a port pin can be read back no matter what peripheral is selected for that pin.
See Table 3 for the default state on reset.
7.13.1 Features
• Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
be achieved.
– Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
• Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
• Direction control of individual bits.
• All I/O default to inputs after reset.
• All GPIO pins can be selected to create an edge- or level-sensitive GPIO interrupt
request.
• One GPIO group interrupt can be triggered by a combination of any pin or pins.
7.14 AHB peripherals
7.14.1 DMA controller
The DMA controller allows peripheral-to memory, memory-to-peripheral, and
memory-to-memory transactions. Each DMA stream provides unidirectional DMA
transfers for a single source and destination.
7.14.1.1
Features
• One channel per on-chip peripheral direction: typically one for input and one for output
for most peripherals.
•
•
•
•
•
•
•
LPC5410x
Product data sheet
DMA operations can optionally be triggered by on- or off-chip events.
Priority is user selectable for each channel.
Continuous priority arbitration.
Address cache.
Efficient use of data bus.
Supports single transfers up to 1,024 words.
Address increment options allow packing and/or unpacking data.
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7.15 Digital serial peripherals
7.15.1 USART
7.15.1.1
Features
• Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in
synchronous mode for USART functions.
• 7, 8, or 9 data bits and 1 or 2 stop bits.
• Synchronous mode with master or slave operation. Includes data phase selection and
continuous clock option.
•
•
•
•
•
•
•
Multiprocessor/multidrop (9-bit) mode with software address compare.
•
•
•
•
•
•
Received data and status can optionally be read from a single register
RS-485 transceiver output enable.
Autobaud mode for automatic baud rate detection
Parity generation and checking: odd, even, or none.
Software selectable oversampling from 5 to 16 clocks in asynchronous mode.
One transmit and one receive data buffer.
RTS/CTS for hardware signaling for automatic flow control. Software flow control can
be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an
RTS output.
Break generation and detection.
Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.
Built-in Baud Rate Generator with auto-baud function.
A fractional rate divider is shared among all USARTs.
Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in
receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS
detect, and receiver sample noise detected.
• Loopback mode for testing of data and flow control.
• In synchronous slave mode, wakes up the part from deep-sleep and power-down
modes.
• Special operating mode allows operation at up to 9600 baud using the 32 kHz RTC
oscillator as the UART clock. This mode can be used while the device is in
Deep-sleep or Power-down mode and can wake-up the device when a character is
received.
• USART transmit and receive functions work with the system DMA controller.
7.15.2 SPI serial I/O controller
7.15.2.1
Features
• Data frames of 1 to 16 bits supported directly. Larger frames supported by software or
DMA set-up.
• Master and slave operation.
• Data can be transmitted to a slave without the need to read incoming data. This can
be useful while setting up an SPI memory.
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• Control information can optionally be written along with data. This allows very
versatile operation, including “any length” frames.
• Four Slave Select input/outputs with selectable polarity and flexible usage.
• Activity on the SPI in slave mode allows wake-up from Deep-sleep and Power-down
modes on any enabled interrupt.
7.16 I2C-bus interface
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be
controlled by more than one bus master connected to it.
7.16.1 Features
• All I2Cs support standard, fast mode, and Fast-mode Plus with data rates of up to
1 Mbit/s.
•
•
•
•
•
All I2Cs support high-speed slave mode with data rates of up to 3.4 Mbit/s.
Independent Master, Slave, and Monitor functions.
Supports both Multi-master and Multi-master with Slave functions.
Multiple I2C slave addresses supported in hardware.
One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C-bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.
• Activity on the I2C in slave mode allows wake-up from Deep-sleep and Power-down
modes on any enabled interrupt.
7.17 Counter/timers
7.17.1 General-purpose 32-bit timers/external event counter
The LPC5410x includes five general-purpose 32-bit timer/counters.
The timer/counter is designed to count cycles of the system derived clock or an
externally-supplied clock. It can optionally generate interrupts, generate timed DMA
requests, or perform other actions at specified timer values, based on four match
registers. Each timer/counter also includes two capture inputs to trap the timer value when
an input signal transitions, optionally generating an interrupt.
7.17.1.1
Features
• A 32-bit timer/counter with a programmable 32-bit prescaler.
• Counter or timer operation.
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• Up to three 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also generate an
interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to two external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• Up to two match registers can be used to generate timed DMA requests.
• The timer and prescaler may be configured to be cleared on a designated capture
event. This feature permits easy pulse width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
• PWM mode using up to two match channels for PWM output.
7.17.2 State Configurable Timer/PWM (SCTimer/PWM) subsystem
The SCTimer/PWM (SCT0) allows a wide variety of timing, counting, output modulation,
and input capture operations. The inputs and outputs of the SCTimer/PWM are shared
with the capture and match inputs/outputs of the 32-bit general-purpose counter/timers.
The SCTimer/PWM can be configured as two 16-bit counters or a unified 32-bit counter. In
the two-counter case, in addition to the counter value the following operational elements
are independent for each half:
• State variable
• Limit, halt, stop, and start conditions
• Values of Match/Capture registers, plus reload or capture control values
In the two-counter case, the following operational elements are global to the SCT, but the
last three can use match conditions from either counter:
•
•
•
•
•
7.17.2.1
Clock selection
Inputs
Events
Outputs
Interrupts
Features
• Two 16-bit counters or one 32-bit counter.
• Counter(s) clocked by bus clock or selected input.
• Up counter(s) or up-down counter(s).
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• State variable allows sequencing across multiple counter cycles.
• Event combines input or output condition and/or counter match in a specified state.
• Events control outputs, interrupts, and the SCT states.
– Match register 0 can be used as an automatic limit.
– In bi-directional mode, events can be enabled based on the count direction.
– Match events can be held until another qualifying event occurs.
• Selected event(s) can limit, halt, start, or stop a counter.
• Supports:
– 6 inputs
– up to 8 outputs
– 13 match/capture registers
– 13 events
– 13 states
• PWM capabilities including dead time and emergency abort functions
7.17.3 Windowed WatchDog Timer (WWDT)
The purpose of the watchdog is to reset the controller if software fails to periodically
service it within a programmable time window.
7.17.3.1
Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time prior to
watchdog time-out.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
•
•
•
•
Incorrect feed sequence causes reset or interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in
multiples of Tcy(WDCLK)  4.
• The Watchdog Clock (WDCLK) uses the WDOSC as the clock source.
7.17.4 RTC timer
The RTC timer is a 32-bit timer which counts down from a preset value to zero. At zero,
the preset value is reloaded and the counter continues. The RTC timer uses the 32 kHz
clock input to create a 1 Hz or 1 kHz clock.
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7.17.5 Multi-Rate Timer (MRT)
The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with four channels. Each
channel can be programmed with an independent time interval, and each channel
operates independently from the other channels.
7.17.5.1
Features
• 24-bit interrupt timer.
• Four channels independently counting down from individually set values.
• Repeat and one-shot interrupt modes.
7.18 12-bit Analog-to-Digital Converter (ADC)
The ADC supports a resolution of 12-bit and fast conversion rates of up to 4.8
Msamples/s. Sequences of analog-to-digital conversions can be triggered by multiple
sources. Possible trigger sources are the SCT, external pins, and the ARM TXEV
interrupt.
The ADC supports a variable clocking scheme with clocking synchronous to the system
clock or independent, asynchronous clocking for high-speed conversions
The ADC includes a hardware threshold compare function with zero-crossing detection.
The threshold crossing interrupt is connected internally to the SCT inputs for tight timing
control between the ADC and the SCT.
7.19 Features
•
•
•
•
•
12-bit successive approximation analog to digital converter.
Input multiplexing among up to 12 pins.
Two configurable conversion sequences with independent triggers.
Optional automatic high/low threshold comparison and “zero crossing” detection.
Measurement range VREFN to VREFP (typically 3 V; not to exceed VDDA voltage
level).
• 12-bit conversion rate of 4.8 MHz. Options for reduced resolution at higher conversion
rates.
• Burst conversion mode for single or multiple inputs.
• Synchronous or asynchronous operation. Asynchronous operation maximizes
flexibility in choosing the ADC clock frequency, Synchronous mode minimizes trigger
latency and can eliminate uncertainty and jitter in response to a trigger
7.20 System control
7.20.1 Clock sources
The LPC5410x supports one external and two internal clock sources:
• The Internal RC (IRC).
• Watchdog oscillator (WDOSC).
• External clock source from the digital I/O pin CLKIN.
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7.20.1.1
Internal RC oscillator (IRC)
The IRC can be used as the clock that drives the system PLL and subsequently the CPU.
The nominal IRC frequency is 12 MHz.
Upon power-up or any chip reset, the LPC5410x uses the IRC as the clock source.
Software may later switch to one of the other available clock sources.
7.20.1.2
Watchdog oscillator (WDOSC)
The watchdog oscillator is a low-power internal oscillator. The WDOSC can be used to
provide a clock to the WWDT and to the entire chip. The nominal output frequency is
500 kHz.
7.20.1.3
Clock input
An external square-wave clock source can be supplied on the digital I/O pin CLKIN.
7.20.2 System PLL
The system PLL accepts an input clock frequency in the range of 32 kHz to 12 MHz. The
input frequency is multiplied up to a high frequency with a Current Controlled Oscillator
(CCO).
The PLL can be enabled or disabled by software.
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7.20.3 Clock Generation
irc_clk
00
CLKIN
wdt_clk
01
sysclk
10
Main clocks elect A
MAINCLKSELA[1:0]
irc_clk
CLKIN
wdt_clk
32k_clk
00
00
01
10
11
01 main clock
PLL0
(Main PLL)
10
32k_clk
System PLL
settings
PLLc lock select
SYSPLLCLKSEL [1:0 ]
CPU Clock
Divider
pll_clk
to CPU, AHB
bus, Sync
APB, etc.
System clockd ivider
SYSAHBCLKDIV[7:0]
11
main clock
Main clock selectB
MAINCLKSELB[1:0]
CLKIN
pll_clk
irc_clk
wdt_clk
00
01
10
11
00
Async APB
Divide r
to async
APBb ridge
Async APB clock divider
ASYNCAPBCLKDIV[7:0]
APB clocks electB
ASYNCAPBCLKSELB[1:0]
01
APB clocks electA
ASYNCAPBCLKSELA[1:0]
main clock
00
pll_clk
irc_clk
ADC Clock
Divider
01
10
ADCc lock divider
ADCCLKDIV[7:0]
ADCc locks elect
ADCCLKSEL[1:0]
main clock
CLKIN
wdt_clk
irc_os c
00
CLKOUTDIV[7:0]
01
00
10
32k_osc
11
CLKOUT
Divider
CLKOUT
11
CLKOUT selectA
CLKOUTSELA[1:0]
Fig 7.
to ADC
CLKOUT selectB
CLKOUTSELB[1:0]
aaa-015553
LPC5410x clock generation
7.20.4 Power control
The LPC5410x supports four reduced power modes: Sleep, Deep-sleep, Power-down,
and Deep power-down modes.
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7.20.4.1
Sleep mode
When Sleep mode is entered, the clock to the core is stopped along with any unused
peripherals. Waking up from the Sleep mode does not need any special sequence other
than re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt
occurs. Peripheral functions continue operation during Sleep mode and may generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, memory systems and related controllers, internal
buses, and unused peripherals.
7.20.4.2
Deep-sleep mode
In Deep-sleep mode, all peripheral clocks and all clock sources are off with the option of
keeping the IRC, the 32 kHz clock, and the WDOSC running. In addition, all analog blocks
are shut down and the flash is put in stand-by mode. In Deep-sleep mode, the application
can keep some of the internal clocks and the BOD circuit running for self-timed wake-up
and BOD protection.
The LPC5410x can wake up from Deep-sleep mode via a reset, digital pins selected as
inputs to the pin interrupt block, RTC alarm, Micro-tick, a watchdog timer interrupt, or an
interrupt from the USART (in 32 kHz mode or synchronous slave mode), the SPI, or any of
the I2C peripherals. For wake-up from Deep-sleep mode, the SPI and I2C peripherals
must be configured in slave mode.
Any interrupt used for waking up from Deep-sleep mode must be enabled in one of the
SYSCON wake-up enable registers and the NVIC.
In Deep-sleep mode, the state of the LPC5410x is retained. Deep-sleep mode allows for
very low quiescent power and fast wake-up options.
7.20.4.3
Power-down mode
In Power-down mode, all peripheral clocks and all clock sources are off with the option of
keeping the 32 kHz clock, and the WDOSC running. In addition, all analog blocks and the
flash are shut down. In Power-down mode, the application can keep the BOD circuit
running for BOD protection.
The LPC5410x can wake up from Power-down mode via a reset, digital pins selected as
inputs to the pin interrupt block, RTC alarm, Micro-tick, a watchdog timer interrupt, or an
interrupt from the USART (in 32 kHz mode or synchronous slave mode), the SPI, or any of
the I2C peripherals.
In power-down mode, the state of the LPC5410x is retained. Power-down mode reduces
power consumption compared to Deep-sleep mode at the expense of longer wake-up
times.
7.20.4.4
Deep power-down mode
In Deep power-down mode, power is shut off to the entire chip except for the RTC power
domain, the RESET pin, and the Micro-tick timer if enabled. The LPC5410x can wake up
from Deep power-down mode via the RESET pin, the RTC alarm, or, without an external
signal, by using the time-out of the Micro-tick timer.
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7.20.5 Brownout detection
The LPC5410x includes a monitor for the voltage level on the VDD pin. If this voltage falls
below a fixed level, the BOD sets a flag that can be polled or cause an interrupt. In
addition, a separate threshold level can be selected to cause chip reset.
7.20.6 Safety
The LPC5410x includes a Windowed WatchDog Timer (WWDT), which can be enabled by
software after reset. Once enabled, the WWDT remains locked and cannot be modified in
any way until a reset occurs.
7.21 Code security (Code Read Protection - CRP)
This feature of the LPC5410x allows user to enable different levels of security in the
system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD)
and In-System Programming (ISP) can be restricted. When needed, CRP is invoked by
programming a specific pattern into a dedicated flash location. IAP commands are not
affected by the CRP.
In addition, ISP entry can be invoked by pulling a pin on the LPC5410x LOW on reset.
This pin is called the ISP entry pin.
There are three levels of Code Read Protection:
1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot
be erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. CRP3 fully disables any access to the chip via SWD and ISP. It is up to the user’s
application to provide (if needed) flash update mechanism using IAP calls or a call to
reinvoke ISP command to enable a flash update via USART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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7.22 Emulation and debugging
Debug and trace functions are integrated into the ARM Cortex-M4F and ARM
Cortex-M0+. Serial wire debug and trace functions are supported. The ARM Cortex-M4F
is configured to support up to eight breakpoints and four watch points. The ARM
Cortex-M0+ is configured to support up to four breakpoints and two watch points. In
addition, a boundary scan mode is provided.
The ARM SYSREQ reset is supported and causes the processor to reset the peripherals,
execute the boot code, restart from address 0x0000 0000, and break at the user entry
point.
The SWD pins are multiplexed with other digital I/O pins. On reset, the pins assume the
SWD functions by default.
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8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).[1]
Symbol
Parameter
Conditions
VDD
supply voltage (core and on pin VDD
external rail)
VDDA
analog supply voltage
on pin VDDA
Vref
reference voltage
on pin VREFP
input voltage
VI
[2]
Max
Unit
0.5
+4.6
V
0.5
+4.6
V
0.5
+4.6
V
[6][7]
0.5
5.0
V
[5]
0.5
+5.0
V
[8][9]
0.5
VDD
V
-
only valid when the VDD > 1.8 V;
Min
5 V tolerant I/O pins
VI
input voltage
on I2C open-drain pins
VIA
analog input voltage
on digital pins configured for an
analog function
IDD
supply current
per supply pin
[3]
-
100
mA
per ground pin
[3]
-
100
mA
-
100
mA
[2]
0.5
+4.6
V
[10]
65
+150
C
-
+150
C
ISS
ground current
Ilatch
I/O latch-up current
(0.5VDD) < VI < (1.5VDD);
Tj < 125 C
Vi(rtcx)
32 kHz oscillator input
voltage
Tstg
storage temperature
Tj(max)
maximum junction
temperature
[1]
The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless
otherwise noted.
c) The limiting values are stress ratings only and operating the part at these values is not recommended and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 11.
[2]
Maximum/minimum voltage above the maximum operating voltage (see Table 11) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3]
The peak current is limited to 25 times the corresponding maximum current.
[4]
Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
[5]
VDD present or not present. Compliant with the I2C-bus standard. 5.5 V can be applied to this pin when VDD is powered down.
[6]
Applies to all 5 V tolerant I/O pins except true open-drain pins.
[7]
Including the voltage on outputs in 3-state mode.
[8]
An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated
exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the
ADC inputs for a long time affects the reliability of the device and reduces its lifetime.
[9]
It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin.
[10] Dependent on package type.
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9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following
equation:
T j = T amb +  P D  R th  j – a  
(1)
• Tamb = ambient temperature (C),
• Rth(j-a) = the package junction-to-ambient thermal resistance (C/W)
• PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of
the I/O pins is often small and many times can be negligible. However it can be significant
in some applications.
Table 5.
Thermal resistance
Symbol Parameter
Conditions
Max/Min
Unit
JEDEC (4.5 in  4 in); still air
LQFP64 Package
Rth(j-a)
Rth(j-c)
thermal resistance from
junction to ambient
58  15 %
C/W
Single-layer (4.5 in  3 in); still air 81  15 %
C/W
18  15 %
C/W
41  15 %
C/W
thermal resistance from
junction to case
WLCSP49 Package
LPC5410x
Product data sheet
Rth(j-a)
thermal resistance from
junction to ambient
Rth(j-c)
thermal resistance from
junction to case
JEDEC (4.5 in  4 in); still air
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10. Static characteristics
10.1 General operating conditions
Table 6.
General operating conditions
Tamb = 40 C to +105 C, unless otherwise specified.
Symbol
Parameter
Conditions
fclk
clock frequency
internal CPU/system clock
VDD
supply voltage (core
and external rail)
VDDA
analog supply voltage
Min
Typ[1]
Max
-
-
100
MHz
1.62
3.3
3.6
V
1.62
3.3
3.6
V
0.5
-
+3.6
V
0.5
-
+3.6
V
Unit
RTC oscillator pins
Vi(rtcx)
32 kHz oscillator input
voltage
on pin RTCXIN
Vo(rtcx)
32 kHz oscillator output on pin RTCXOUT
voltage
[1]
Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages.
[2]
Excluding bonding pad capacitance. Based on simulation, not tested in production.
10.2 CoreMark score
Table 7.
CoreMark score
Tamb = 25C, VDD = 3.3V
Parameter
Conditions
Typ
Unit
(Iterations/s) /
MHz
ARM Cortex-M4F in active mode; ARM Cortex-M0+ in sleep mode
CoreMark score
CoreMark score
CoreMark code executed from
SRAM;
CCLK = 12 MHz
[1][3][4]
2.5
CCLK = 84 MHz
[2][3][4]
2.6
(Iterations/s) /
MHz
CCLK = 96 MHz
[2][3][4]
2.6
(Iterations/s) /
MHz
CCLK = 12 MHz
[1][3][4]
2.5
CCLK = 84 MHz
[2][3][4]
2.2
(Iterations/s) /
MHz
CCLK = 96 MHz
[2][3][4]
2.2
(Iterations/s) /
MHz
CoreMark code executed from
flash;
[1]
Clock source 12 MHz IRC. PLL disabled.
[2]
Clock source 12 MHz IRC. PLL enabled.
[3]
Characterized through bench measurements using typical samples.
[4]
Compiler settings: Keil µVision v.5.1.0, optimization level 3, optimized for time on.
LPC5410x
Product data sheet
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(Iterations/s) /
MHz
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32-bit ARM Cortex-M4F/M0+ microcontroller
10.3 Power consumption
Power measurements in Active, Sleep, Deep-sleep, and Power-down modes were
performed under the following conditions:
•
•
•
•
Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
Configure GPIO pins as outputs using the GPIO DIR register.
Write 1 to the GPIO CLR register to drive the outputs LOW.
All peripherals disabled.
Table 8.
Static characteristics: Power consumption in active and sleep modes
Tamb = 40 C to +105 C, unless otherwise specified.1.62 V <= VDD <= 3.6 V.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
ARM Cortex-M0+ in active mode; ARM Cortex-M4F in sleep mode
IDD
IDD
IDD
supply current
supply current
supply current
LPC5410x
Product data sheet
CoreMark code executed from
SRAM;
CCLK = 12 MHz
[2][4]
-
1.4
-
mA
CCLK = 84 MHz
[3][4]
-
4.6
-
mA
CCLK = 96 MHz
[3][4]
-
5.2
-
mA
CCLK = 12 MHz
[2][4]
-
1.6
-
mA
CCLK = 84 MHz
[3][4]
-
5.4
-
mA
CCLK = 96 MHz
[3][4]
-
6.0
-
mA
CCLK = 12 MHz
[2][4][5]
-
1.5
-
mA
CCLK = 84 MHz
[3][4][5]
-
6.2
-
mA
CCLK = 96 MHz
[3][4][5]
-
7.2
-
mA
CoreMark code executed from
flash;
Calculating Fibonacci numbers
executed from flash;
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32-bit ARM Cortex-M4F/M0+ microcontroller
Table 8.
Static characteristics: Power consumption in active and sleep modes
Tamb = 40 C to +105 C, unless otherwise specified.1.62 V <= VDD <= 3.6 V.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
ARM Cortex-M4F in active mode; ARM Cortex-M0+ in sleep mode
supply current
IDD
supply current
IDD
supply current
IDD
supply current
IDD
CoreMark code executed from
SRAM;
CCLK = 12 MHz
[2][4][6]
-
1.5
-
mA
CCLK = 84 MHz
[3][4][6]
-
7.9
-
mA
CCLK = 96 MHz
[3][4][6]
-
9.2
-
mA
CCLK = 12 MHz
[2][4][5]
-
1.7
-
mA
CCLK = 84 MHz
[3][4][5]
-
8.0
-
mA
CCLK = 96 MHz
[3][4][5]
-
9.4
-
mA
CCLK = 12 MHz
[2][4][6]
-
2.1
-
mA
CCLK = 84 MHz
[3][4][6]
-
9.0
-
mA
CCLK = 96 MHz
[3][4][6]
-
10.4
-
mA
CCLK = 12 MHz
[2][4][5]
-
1.7
-
mA
CCLK = 84 MHz
[3][4][5]
-
8.0
-
mA
CCLK = 96 MHz
[3][4][5]
-
9.4
-
mA
Calculating Fibonacci numbers
executed from SRAM;
CoreMark code executed from
flash;
Calculating Fibonacci numbers
executed from flash;
[1]
Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), 3.3V.
[2]
Clock source 12 MHz IRC. PLL disabled.
[3]
Clock source 12 MHz IRC. PLL enabled.
[4]
Characterized through bench measurements using typical samples.
[5]
Compiler settings: Keil µVision v.5.10, optimization level 0, optimized for time off.
[6]
Compiler settings: Keil µVision v.5.12, optimization level 0, optimized for time off.
LPC5410x
Product data sheet
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32-bit ARM Cortex-M4F/M0+ microcontroller
Table 9.
Static characteristics: Power consumption in deep-sleep, power-down, and deep power-down modes
Tamb = 40 C to +105 C, unless otherwise specified.VDD = 3.3 V.
Symbol
Parameter
supply current
IDD
Min
Typ[1]
Max
Unit
deep-sleep mode; all SRAM
on
[2]
-
317
-
A
power-down mode;
[2]
-
3.5
-
A
SRAM0 (64 KB) powered
-
5
-
A
SRAM0 (64 KB), SRAM1
(32 KB) powered
-
6
-
A
SRAM0 (64 KB), SRAM1
(32 KB), SRAM2 (8 KB)
powered
-
6.2
-
A
-
135
-
nA
-
280
-
nA
Conditions
first 8 KB in SRAM0
powered
deep power-down mode;
[2]
RTC oscillator input
grounded (RTC oscillator
disabled)
RTC oscillator running with
external crystal
[1]
Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), nominal supply voltages.
[2]
Characterized through bench measurements using typical samples.
Table 10. Static characteristics: Power consumption in deep-sleep, power-down, and deep power-down modes
Tamb = 40 C to +105 C, unless otherwise specified.VDD = 1.62 V.
Symbol
Parameter
supply current
IDD
Min
Typ[1]
Max
Unit
deep-sleep mode; all SRAM
on
[2]
-
238
-
A
power-down mode;
[2]
-
3
-
A
SRAM0 (64 KB) powered
-
4
-
A
SRAM0 (64 KB), SRAM1
(32 KB) powered
-
5
-
A
SRAM0 (64 KB), SRAM1
(32 KB), SRAM2 (8 KB)
powered
-
5.3
-
A
-
84
-
nA
-
114
-
nA
Conditions
first 8 KB in SRAM0
powered
deep power-down mode;
[2]
RTC oscillator input
grounded (RTC oscillator
disabled)
RTC oscillator running with
external crystal
[1]
Typical ratings are not guaranteed. Typical values listed are at room temperature (25 C), nominal supply voltages.
[2]
Characterized through bench measurements using typical samples.
LPC5410x
Product data sheet
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32-bit ARM Cortex-M4F/M0+ microcontroller
10.4 Pin characteristics
Table 11. Static characteristics: pin characteristics
Tamb = 25C, 1.62 V <= VDD <= 3.6 V unless otherwise specified.
Symbol Parameter
Conditions
Min
Typ[1]
Max
Unit
RESET pin
VIH
HIGH-level input
voltage
0.8  (VDD)
-
5.0
V
VIL
LOW-level input voltage
0.5
-
0.3  (VDD)
V
Vhys
hysteresis voltage
0.05  (VDD)
-
-
V
Standard I/O pins
Input characteristics
IIL
LOW-level input current VI = 0 V; on-chip pull-up resistor
disabled
-
-
10[2]
nA
IIH
HIGH-level input
current
VI = VDD; on-chip pull-down resistor
disabled
-
-
10[2]
nA
VI
input voltage
pin configured to provide a digital
function;
VDD  1.8 V
0
-
5.0
V
VDD = 0 V
0
-
3.6
V
1.5
-
5.0
V
[5]
VIH
HIGH-level input
voltage
2.0
-
5.0
V
VIL
LOW-level input voltage 1.62 V <= VDD < 2.7 V
0.5
-
+0.4
V
2.7 V <= VDD <= 3.6 V
0.5
-
+0.8
V
0.1  VDD
-
-
V
0
-
VDD
V
-
-
10[2]
nA
-
-
V
Vhys
1.62 V <= VDD < 2.7 V
2.7 V <= VDD <= 3.6 V
hysteresis voltage
Output characteristics
VO
output voltage
IOZ
OFF-state output
current
VOH
HIGH-level output
voltage
VOL
IOH
IOL
IOHS
LOW-level output
voltage
HIGH-level output
current
LOW-level output
current
output active
VO = 0 V; VO = VDD; on-chip
pull-up/pull-down resistors disabled
IOH = 4 mA; 1.62 V <= VDD < 2.7 V
VDD  0.4
IOH = 6 mA; 2.7 V <= VDD <= 3.6 V
VDD  0.4
IOL = 4 mA; 1.62 V <= VDD < 2.7 V
-
-
0.4
V
IOL = 6 mA; 2.7 V <= VDD <= 3.6 V
-
-
0.4
V
VOH = VDD  0.4 V; 1.62
V <= VDD < 2.7 V
4
-
-
mA
VOH = VDD  0.4 V; 2.7
V <= VDD <= 3.6 V
6
-
-
mA
VOL = 0.4 V; 1.62 V <= VDD < 2.7 V
4
-
-
mA
VOL = 0.4 V; 2.7 V <= VDD <= 3.6 V
6
-
-
mA
-
-
87
mA
-
-
35
mA
-
-
77
mA
-
-
30
mA
HIGH-level short-circuit drive HIGH; connected to ground;
output current
2.7 V <= VDD <= 3.6 V
[6]
1.62 V <= VDD <= 1.98 V
IOLS
LOW-level short-circuit
output current
drive LOW; connected to VDD;
[6]
2.7 V <= VDD <= 3.6 V
1.62 V <= VDD <= 1.98 V
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LPC5410x
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32-bit ARM Cortex-M4F/M0+ microcontroller
Table 11. Static characteristics: pin characteristics …continued
Tamb = 25C, 1.62 V <= VDD <= 3.6 V unless otherwise specified.
Symbol Parameter
Open-drain
I2C
Conditions
Min
Typ[1]
Max
Unit
pins
VIH
HIGH-level input
voltage
0.7  VDD
-
-
V
VIL
LOW-level input voltage
0
-
0.3  VDD
V
Vhys
hysteresis voltage
0.1  VDD
-
-
V
-
4.5
-
A
[7]
ILI
input leakage current
VI = VDD
VI = 5 V
-
-
10
A
IOL
LOW-level output
VOL = 0.4 V; pin configured for
standard mode or fast mode
4.0
-
-
mA
VOL = 0.4 V; pin configured for
Fast-mode Plus
20.0
-
-
mA
current
Pin capacitance
Cio
input/output
capacitance
I2C-bus pins
[8]
-
-
6.0
pF
pins with digital functions only
[8]
-
-
2.0
pF
[1]
Typical ratings are not guaranteed.
[2]
Based on characterization. Not tested in production.
[3]
Not characterized on samples or in production.
[4]
Characterized on the bench for typical samples.
[5]
With respect to ground.
[6]
Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[7]
To VSS.
[8]
Excluding bonding capacitance. Simulated values.
VDD
IOL
Ipd
pin PIO0_n
+
A
IOH
Ipu
pin PIO0_n
-
+
A
aaa-010819
Fig 8.
LPC5410x
Product data sheet
Pin input/output current measurement
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32-bit ARM Cortex-M4F/M0+ microcontroller
11. Dynamic characteristics
11.1 Flash memory
Table 12. Flash characteristics
Tamb = 40 C to +105 C, unless otherwise specified. VDD = 1.62 V to 3.6 V for read operations;
VDD = 2.7V to 3.6V for erase/program operations.
Symbol
Parameter
Conditions
Nendu
endurance
sector erase/program
tret
retention time
ter
erase time
tprog
programming
time
Min
Typ
Max
Unit
10000
-
-
cycles
page erase/program; page
in large sector
1000
-
-
cycles
page erase/program; page
in small sector
10000
-
-
cycles
powered
10
-
-
years
unpowered
10
-
-
years
page, sector, or multiple
consecutive sectors
-
100
-
ms
-
1
-
ms
[1]
[2]
[1]
Number of erase/program cycles.
[2]
Programming times are given for writing 512 bytes from RAM to the flash. Data must be written to the flash
in blocks of 512 bytes. Tamb = 25 C.
11.2 I/O pins
Table 13. Dynamic characteristic: I/O pins[1]
Tamb = 40 C to +85 C; 1.62 V  VDD(IO)  3.6 V
Symbol Parameter Conditions
Min
Typ
Max
Unit
1.0
-
2.5
ns
1.6
-
3.8
ns
2.7 V <= VDD <= 3.6 V
0.9
-
2.5
ns
1.62 V <= VDD <= 1.98 V
1.7
-
4.1
ns
1.9
-
4.3
ns
2.9
-
7.8
ns
1.9
-
4.0
ns
Standard I/O pins - normal drive strength
tr
rise time
pin configured as output; SLEW = 1 (fast
mode);
[2][3]
2.7 V <= VDD <= 3.6 V
1.62 V <= VDD <= 1.98 V
tf
tr
fall time
rise time
pin configured as output; SLEW = 1 (fast
mode);
pin configured as output; SLEW = 0
(standard mode);
[2][3]
[2][3]
2.7 V <= VDD <= 3.6 V
1.62 V <= VDD <= 1.98 V
tf
fall time
pin configured as output; SLEW = 0
(standard mode);
[2][3]
2.7 V <= VDD <= 3.6 V
1.62 V <= VDD <= 1.98 V
LPC5410x
Product data sheet
tr
rise time
pin configured as input
[4]
tf
fall time
pin configured as input
[4]
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
2.7
-
6.7
ns
0.3
-
1.3
ns
0.2
-
1.2
ns
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32-bit ARM Cortex-M4F/M0+ microcontroller
[1]
Simulated data.
[2]
Simulated using 10 cm of 50 Ω PCB trace with 5 pF receiver input. Rise and fall times measured between
80 % and 20 % of the full output signal level.
[3]
The slew rate is configured in the IOCON block the SLEW bit. See the LPC54xxx user manual.
[4]
CL = 20 pF. Rise and fall times measured between 90 % and 10 % of the full input signal level.
11.3 Wake-up process
Table 14. Dynamic characteristic: Typical wake-up times from low power modes
VDD = 3.3 V;Tamb = 25 C; using IRC as the system clock.
Symbol Parameter
twake
wake-up
time
Conditions
[2][3]
from Sleep mode
Min
Typ[1]
Max Unit
-
1.6
-
s
-
18
-
s
-
s
70
-
s
18
-
s
200
-
s
[2]
from Deep-sleep mode with full
SRAM retention:
to code executing in flash
[2]
to code executing in SRAM
[2]
from Power-down mode
to code executing in flash
[2]
to code executing in SRAM
from deep power-down,mode;
RTC disabled; using RESET pin.
[4]
-
[1]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[2]
The wake-up time measured is the time between when a GPIO input pin is triggered to wake the device up
from the low power modes and from when a GPIO output pin is set in the interrupt service routine (ISR)
wake-up handler.
[3]
IRC enabled, all peripherals off.
[4]
RTC disabled. Wake-up from deep power-down causes the part to go through entire reset
process. The wake-up time measured is the time between when the RESET pin is triggered to wake the
device up and when a GPIO output pin is set in the reset handler.
11.4 IRC
Table 15. Dynamic characteristic: IRC oscillator
Tamb = 25 C; 1.62 V  VDD  3.6 V.[1]
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fosc(RC)
internal RC oscillator
frequency
-
11.88
12
12.12
MHz
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
11.5 RTC oscillator
See Section 13.3 for connecting the RTC oscillator to an external clock source.
Table 16. Dynamic characteristic: RTC oscillator
1.62  VDD  3.6[1]
LPC5410x
Product data sheet
Symbol
Parameter
Conditions
Min
Typ[2]
Max
Unit
fi
input frequency
-
-
32.768
-
kHz
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32-bit ARM Cortex-M4F/M0+ microcontroller
[1]
Parameters are valid over operating temperature range unless otherwise specified.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
11.6 Watchdog oscillator
Table 17.
Dynamic characteristics: Watchdog oscillator
Symbol
Parameter
fosc(int)
internal oscillator
frequency
Dclkout
clkout duty cycle
Conditions
[2]
JPP-CC
peak-peak period
jitter
[3][4]
tstart
start-up time
[4]
Min
Typ[1] Max Unit
-
500
-
kHz
48
-
52
%
-
1
20
ns
-
4
-
μs
[1]
Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2]
The typical frequency spread over processing and temperature (Tamb = 40 C to +105 C) is 40 %.
[3]
Actual jitter dependent on amplitude and spectrum of substrate noise.
[4]
Guaranteed by design. Not tested in production samples.
11.7 I2C-bus
Table 18. Dynamic characteristic: I2C-bus pins[1]
Tamb = 40 C to +105 C; 1.62 V  VDD  3.6 V.[2]
Symbol
Parameter
Conditions
fSCL
SCL clock frequency
Standard-mode
Fast-mode
Fast-mode Plus
0
fall time
tf
[4][5][6][7]
Min
Max
Unit
0
100
kHz
0
400
kHz
1
MHz
300
ns
of both SDA and SCL signals Standard-mode
tLOW
tHIGH
tHD;DAT
tSU;DAT
LOW period of the SCL clock
HIGH period of the SCL clock
data hold time
data set-up time
[3][4][8]
[9][10]
Fast-mode
20 + 0.1  Cb
300
ns
Fast-mode Plus
-
120
ns
Standard-mode
4.7
-
s
Fast-mode
1.3
-
s
Fast-mode Plus
0.5
-
s
Standard-mode
4.0
-
s
Fast-mode
0.6
-
s
Fast-mode Plus
0.26
-
s
Standard-mode
0
-
s
Fast-mode
0
-
s
Fast-mode Plus
0
-
s
Standard-mode
250
-
ns
Fast-mode
100
-
ns
Fast-mode Plus
50
-
ns
[1]
Guaranteed by design. Not tested in production.
[2]
Parameters are valid over operating temperature range unless otherwise specified. See the I2C-bus specification UM10204 for details.
[3]
tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
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[4]
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
[5]
Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall times are allowed.
[6]
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at
250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines
without exceeding the maximum specified tf.
[7]
In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[8]
The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[9]
tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the
LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
tf
SDA
tSU;DAT
70 %
30 %
70 %
30 %
tHD;DAT
tf
70 %
30 %
SCL
tVD;DAT
tHIGH
70 %
30 %
70 %
30 %
70 %
30 %
tLOW
S
Fig 9.
1 / fSCL
002aaf425
I2C-bus pins clock timing
LPC5410x
Product data sheet
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32-bit ARM Cortex-M4F/M0+ microcontroller
12. Analog characteristics
12.1 12-bit ADC characteristics
Table 19. 12-bit ADC static characteristics
Tamb = 25 C; VDD = 3.3 V; VREFP = VDDA; VSSA = 0; VREFN = VSSA. ADC calibrated at T = 25C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VDDA
V
72
MHz
4.8
Msamples/s
[2]
VIA
analog input
voltage
fclk(ADC)
ADC clock
frequency
fs
sampling
frequency
ED
differential
linearity error
EL(adj)
integral
non-linearity
EO
offset error
Verr(FS)
LPC5410x
Product data sheet
0
calibration enabled
full-scale error
voltage
-
-
-
[1][3]
-
 0.8
LSB
[1][4]
-
 1.4
LSB
[1][5]
-
 1.3
LSB
[1][6]
-
 0.06
%
[1]
Based on characterization; not tested in production.
[2]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply
voltages.
[3]
The differential linearity error (ED) is the difference between the actual step width and the ideal step width.
See Figure 10.
[4]
The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and
the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 10.
[5]
The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the
straight line which fits the ideal curve. See Figure 10.
[6]
The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual
transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See
Figure 10.
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32-bit ARM Cortex-M4F/M0+ microcontroller
offset
error
EO
gain
error
EG
4095
4094
4093
4092
4091
4090
(2)
7
code
out
(1)
6
5
(5)
4
(4)
3
(3)
2
1 LSB
(ideal)
1
0
1
2
3
4
5
6
7
4090
4091
4092
4093
4094
4095
4096
VIA (LSBideal)
offset error
EO
1 LSB =
VREFP - VSS
4096
002aaf436
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 10. 12-bit ADC characteristics
LPC5410x
Product data sheet
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32-bit ARM Cortex-M4F/M0+ microcontroller
Table 20. ADC sampling times[1]
-40 °C <= Tamb <= 85 °C; 1.62 V <= VDDA <= 3.6 V; 1.62 V <= VDD <= 3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
20
-
-
ns
0.05 kΩ <= Zo < 0.1 kΩ
23
-
-
ns
0.1 kΩ <= Zo < 0.2 kΩ
26
-
-
ns
ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 12 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
0.2 kΩ <= Zo < 0.5 kΩ
31
-
-
ns
0.5 kΩ <= Zo < 1 kΩ
47
-
-
ns
1 kΩ <= Zo < 5 kΩ
75
-
-
ns
ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 10 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
15
-
-
ns
0.05 kΩ <= Zo < 0.1 kΩ
18
-
-
ns
0.1 kΩ <= Zo < 0.2 kΩ
20
-
-
ns
0.2 kΩ <= Zo < 0.5 kΩ
24
-
-
ns
0.5 kΩ <= Zo < 1 kΩ
38
-
-
ns
1 kΩ <= Zo < 5 kΩ
62
-
-
ns
-
-
ns
ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 8 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
12
0.05 kΩ <= Zo < 0.1 kΩ
13
-
-
ns
0.1 kΩ <= Zo < 0.2 kΩ
15
-
-
ns
0.2 kΩ <= Zo < 0.5 kΩ
19
-
-
ns
0.5 kΩ <= Zo < 1 kΩ
30
-
-
ns
1 kΩ <= Zo < 5 kΩ
48
-
-
ns
9
-
-
ns
0.05 kΩ <= Zo < 0.1 kΩ
10
-
-
ns
ADC inputs ADC_5 to ADC_0 (fast channels); ADC resolution = 6 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
0.1 kΩ <= Zo < 0.2 kΩ
11
-
-
ns
0.2 kΩ <= Zo < 0.5 kΩ
13
-
-
ns
0.5 kΩ <= Zo < 1 kΩ
22
-
-
ns
1 kΩ <= Zo < 5 kΩ
36
-
-
ns
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 12 bit
ts
LPC5410x
Product data sheet
sampling time
Zo < 0.05 kΩ
[3]
43
-
-
ns
0.05 kΩ <= Zo < 0.1 kΩ
46
-
-
ns
0.1 kΩ <= Zo < 0.2 kΩ
50
-
-
ns
0.2 kΩ <= Zo < 0.5 kΩ
56
-
-
ns
0.5 kΩ <= Zo < 1 kΩ
74
-
-
ns
1 kΩ <= Zo < 5 kΩ
105
-
-
ns
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Table 20. ADC sampling times[1] …continued
-40 °C <= Tamb <= 85 °C; 1.62 V <= VDDA <= 3.6 V; 1.62 V <= VDD <= 3.6 V
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
-
ns
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 10 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
35
-
0.05 kΩ <= Zo < 0.1 k
38
-
-
ns
0.1 kΩ <= Zo < 0.2 k
40
-
-
ns
0.2 kΩ <= Zo < 0.5 k
46
-
-
ns
0.5 kΩ <= Zo < 1 k
61
-
-
ns
1 kΩ <= Zo < 5 k
86
-
-
ns
27
-
-
ns
0.05 kΩ <= Zo < 0.1 k
29
-
-
ns
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 8 bit
ts
sampling time
Zo < 0.05 kΩ
[3]
0.1 kΩ <= Zo < 0.2 k
32
-
-
ns
0.2 kΩ <= Zo < 0.5 k
36
-
-
ns
0.5 kΩ <= Zo < 1 k
48
-
-
ns
1 kΩ <= Zo < 5 k
69
-
-
ns
20
-
-
ns
0.05 kΩ <= Zo < 0.1 k
22
-
-
ns
0.1 kΩ <= Zo < 0.2 k
23
-
-
ns
ADC inputs ADC_11 to ADC_6 (slow channels); ADC resolution = 6 bit
ts
LPC5410x
Product data sheet
sampling time
Zo < 0.05 kΩ
[3]
0.2 kΩ <= Zo < 0.5 k
26
-
-
ns
0.5 kΩ <= Zo < 1 k
36
-
-
ns
1 kΩ <= Zo < 5 k
51
-
-
ns
[1]
Characterized through simulation. Not tested in production.
[2]
The ADC default sampling time is 2.5 ADC clock cycles. To match a given analog source output
impedance, the sampling time can be extended by adding up to seven ADC clock cycles for a maximum
sampling time of 9.5 ADC clock cycles. See the TSAMP bits in the ADC CTRL register.
[3]
Zo = analog source output impedance.
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32-bit ARM Cortex-M4F/M0+ microcontroller
13. Application information
13.1 Standard I/O pin configuration
Figure 11 shows the possible pin modes for standard I/O pins:
•
•
•
•
•
Digital output driver: enabled/disabled.
Digital input: Pull-up enabled/disabled.
Digital input: Pull-down enabled/disabled.
Digital input: Repeater mode enabled/disabled.
Z mode; High impedance (no cross-bar currents for floating inputs).
The default configuration for standard I/O pins is Z mode. The weak MOS devices provide
a drive capability equivalent to pull-up and pull-down resistors.
VDDIO
ESD
enable output driver
data output from core
PIN
slew rate bit SLEW
input buffer enable bit EZI
data input to core
GLITCH
FILTER
filter select bit ZIF
pull-up enable bit EPUN
ESD
pull-down enable bit EPD
analog I/O
VSSIO
aaa-015595
The glitch filter rejects pulses of typical 12 ns width.
Fig 11. Standard I/O and RESET pin configuration
13.2 I/O power consumption
I/O pins are contributing to the overall dynamic and static power consumption of the part.
If pins are configured as digital inputs, a static current can flow depending on the voltage
level at the pin and the setting of the internal pull-up and pull-down resistors. This current
can be calculated using the parameters Rpu and Rpd given in Table 11 for a given input
voltage VI. For pins set to output, the current drive strength is given by parameters IOH and
IOL in Table 11, but for calculating the total static current, you also need to consider any
external loads connected to the pin.
LPC5410x
Product data sheet
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32-bit ARM Cortex-M4F/M0+ microcontroller
I/O pins also contribute to the dynamic power consumption when the pins are switching
because the VDD supply provides the current to charge and discharge all internal and
external capacitive loads connected to the pin in addition to powering the I/O circuitry.
The contribution from the I/O switching current Isw can be calculated as follows for any
given switching frequency fsw if the external capacitive load (Cext) is known (see Table 11
for the internal I/O capacitance):
Isw = VDD x fsw x (Cio + Cext)
13.3 RTC oscillator
In the RTC oscillator circuit, only the crystal (XTAL) and the capacitances CRTCX1 and
CRTCX2 need to be connected externally. Typical capacitance values for CRTCX1 and
CRTCX2 are CRTCX1/2 = 20 (typical)  4 pF.
An external clock can be connected to RTCX1 if RTCX2 is left open. The recommended
amplitude of the clock signal is Vi(RMS) = 100 mV to 200 mV with a coupling capacitance of
5 pF to 10 pF.
LPC5410x
RTCX1
RTCX2
XTAL
CRTCX2
CRTCX1
aaa-015554
Fig 12. RTC 32 kHz oscillator circuit
LPC5410x
Product data sheet
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32-bit ARM Cortex-M4F/M0+ microcontroller
14. Package outline
WLCSP49: wafer level chip-scale package; 49 bumps; 3.29 x 3.29 x 0.54 mm (backside coating included)
B
D
LPC5410
A
ball A1
index area
A2
A
E
A1
detail X
e1
C
Øv
Øw
b
e
G
C A B
C
y
e
F
E
e2
D
C
B
A
1
ball A1
index area
2
3
4
5
6
7
X
0
3 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
A
A1
A2
b
D
E
e
max 0.58 0.23 0.37 0.29 3.318 3.318
nom 0.54 0.20 0.34 0.26 3.288 3.288 0.4
min 0.50 0.17 0.31 0.23 3.258 3.258
e1
e2
2.4
2.4
v
w
y
0.05 0.015 0.03
Note
Backside coating 40 µm
Outline
version
wlcsp49_lpc5410_po
References
IEC
LPC5410
JEDEC
JEITA
European
projection
Issue date
13-09-16
14-11-03
---
Fig 13. WLCSP49 Package outline
LPC5410x
Product data sheet
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LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
E HE
A
A2
(A 3)
A1
wM
θ
bp
pin 1 index
64
Lp
L
17
detail X
16
1
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
v
w
y
1
0.75
0.45
0.2
0.12
0.1
Z D (1) Z E (1)
1.45
1.05
1.45
1.05
θ
7o
o
0
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT314-2
136E10
MS-026
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
00-01-19
03-02-25
Fig 14. LQFP64 Package outline
LPC5410x
Product data sheet
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32-bit ARM Cortex-M4F/M0+ microcontroller
15. Soldering
Footprint information for reflow soldering of WLCSP49 package
LPC5410_NSMD
Hx
P
P
Hy
see detail X
recommend stencil thickness: 0.1 mm
solder land (SL)
solder paste deposit (SP)
solder land plus solder paste
solder resist opening (SR)
SL
occupied area
SP
SR
Dimensions in mm
detail X
P
SL
SP
SR
Hx
Hy
0.4
0.24
0.27
0.31
3.5
3.5
Issue date
14-04-08
14-11-05
wlcsp49_lpc5410_fr
Fig 15. WLCSP49 Soldering footprint
LPC5410x
Product data sheet
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LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
Footprint information for reflow soldering of LQFP64 package
SOT314-2
Hx
Gx
P2
Hy
(0.125)
P1
Gy
By
Ay
C
D2 (8×)
D1
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
0.500
P2
Ax
Ay
Bx
By
0.560 13.300 13.300 10.300 10.300
C
D1
D2
1.500
0.280
0.400
Gx
Gy
Hx
Hy
10.500 10.500 13.550 13.550
sot314-2_fr
Fig 16. LQFP64 Soldering footprint
LPC5410x
Product data sheet
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32-bit ARM Cortex-M4F/M0+ microcontroller
16. Abbreviations
Table 21.
LPC5410x
Product data sheet
Abbreviations
Acronym
Description
AHB
Advanced High-performance Bus
APB
Advanced Peripheral Bus
API
Application Programming Interface
DMA
Direct Memory Access
GPIO
General Purpose Input/Output
IRC
Internal RC
LSB
Least Significant Bit
MCU
MicroController Unit
PLL
Phase-Locked Loop
SPI
Serial Peripheral Interface
TCP/IP
Transmission Control Protocol/Internet Protocol
TTL
Transistor-Transistor Logic
USART
Universal Asynchronous Receiver/Transmitter
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17. Revision history
Table 22.
Revision history
Document ID
Release date Data sheet status
Change notice Supersedes
LPC5410x v1.0
20141105
-
LPC5410x
Product data sheet
Product data sheet
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-
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18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
LPC5410x
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
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© NXP Semiconductors N.V. 2014. All rights reserved.
57 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
LPC5410x
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
58 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
20. Contents
1
2
3
3.1
4
5
6
6.1
6.2
7
7.1
7.2
7.3
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 4
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 7
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional description . . . . . . . . . . . . . . . . . . 18
Architectural overview . . . . . . . . . . . . . . . . . . 18
ARM Cortex-M4F processor . . . . . . . . . . . . . . 18
ARM Cortex-M4 integrated Floating Point Unit
(FPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.4
ARM Cortex-M0+ co-processor . . . . . . . . . . . 18
7.5
Memory Protection Unit (MPU). . . . . . . . . . . . 18
7.6
Nested Vectored Interrupt Controller (NVIC)
for Cortex-M4F . . . . . . . . . . . . . . . . . . . . . . . . 19
7.6.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.6.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19
7.7
Nested Vectored Interrupt Controller (NVIC)
for Cortex-M0+ . . . . . . . . . . . . . . . . . . . . . . . . 19
7.7.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.7.2
Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 19
7.8
System Tick timer (SysTick) . . . . . . . . . . . . . . 19
7.9
On-chip static RAM. . . . . . . . . . . . . . . . . . . . . 19
7.10
On-chip flash . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.11
On-chip ROM . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.12
Memory mapping . . . . . . . . . . . . . . . . . . . . . . 21
7.13
General Purpose I/O (GPIO) . . . . . . . . . . . . . 22
7.13.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.14
AHB peripherals . . . . . . . . . . . . . . . . . . . . . . . 22
7.14.1
DMA controller . . . . . . . . . . . . . . . . . . . . . . . . 22
7.14.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.15
Digital serial peripherals . . . . . . . . . . . . . . . . . 23
7.15.1
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.15.2
SPI serial I/O controller. . . . . . . . . . . . . . . . . . 23
7.15.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.16
I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 24
7.16.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.17
Counter/timers . . . . . . . . . . . . . . . . . . . . . . . . 24
7.17.1
General-purpose 32-bit timers/external event
counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.17.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.17.2
State Configurable Timer/PWM (SCTimer/PWM)
subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.17.2.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17.3
Windowed WatchDog Timer (WWDT) . . . . . .
7.17.3.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17.4
RTC timer. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.17.5
Multi-Rate Timer (MRT) . . . . . . . . . . . . . . . . .
7.17.5.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.18
12-bit Analog-to-Digital Converter (ADC). . . .
7.19
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.20
System control . . . . . . . . . . . . . . . . . . . . . . . .
7.20.1
Clock sources . . . . . . . . . . . . . . . . . . . . . . . .
7.20.1.1 Internal RC oscillator (IRC) . . . . . . . . . . . . . .
7.20.1.2 Watchdog oscillator (WDOSC). . . . . . . . . . . .
7.20.1.3 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.20.2
System PLL . . . . . . . . . . . . . . . . . . . . . . . . . .
7.20.3
Clock Generation . . . . . . . . . . . . . . . . . . . . .
7.20.4
Power control . . . . . . . . . . . . . . . . . . . . . . . . .
7.20.4.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . .
7.20.4.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . .
7.20.4.3 Power-down mode . . . . . . . . . . . . . . . . . . . . .
7.20.4.4 Deep power-down mode . . . . . . . . . . . . . . . .
7.20.5
Brownout detection . . . . . . . . . . . . . . . . . . . .
7.20.6
Safety. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.21
Code security (Code Read Protection - CRP)
7.22
Emulation and debugging . . . . . . . . . . . . . . .
8
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
9
Thermal characteristics . . . . . . . . . . . . . . . . .
10
Static characteristics . . . . . . . . . . . . . . . . . . .
10.1
General operating conditions . . . . . . . . . . . . .
10.2
CoreMark score . . . . . . . . . . . . . . . . . . . . . . .
10.3
Power consumption . . . . . . . . . . . . . . . . . . . .
10.4
Pin characteristics . . . . . . . . . . . . . . . . . . . . .
11
Dynamic characteristics. . . . . . . . . . . . . . . . .
11.1
Flash memory . . . . . . . . . . . . . . . . . . . . . . . .
11.2
I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3
Wake-up process . . . . . . . . . . . . . . . . . . . . . .
11.4
IRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.5
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . .
11.6
Watchdog oscillator . . . . . . . . . . . . . . . . . . . .
11.7
I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
Analog characteristics . . . . . . . . . . . . . . . . . .
12.1
12-bit ADC characteristics . . . . . . . . . . . . . . .
13
Application information . . . . . . . . . . . . . . . . .
13.1
Standard I/O pin configuration . . . . . . . . . . . .
13.2
I/O power consumption . . . . . . . . . . . . . . . . .
13.3
RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . .
14
Package outline. . . . . . . . . . . . . . . . . . . . . . . .
25
26
26
26
27
27
27
27
27
27
28
28
28
28
29
29
30
30
30
30
31
31
31
32
33
34
35
35
35
36
39
41
41
41
42
42
42
43
43
45
45
49
49
49
50
51
continued >>
LPC5410x
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.0 — 5 November 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
59 of 60
LPC5410x
NXP Semiconductors
32-bit ARM Cortex-M4F/M0+ microcontroller
15
16
17
18
18.1
18.2
18.3
18.4
19
20
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
55
56
57
57
57
57
58
58
59
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 5 November 2014
Document identifier: LPC5410x
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