7A SIMPLE SWITCHER Power Module with 2.95V-17V Input and Current Sharing LMZ31707
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SLVSBV7A – JUNE 2013 – REVISED AUGUST 2013
7A SIMPLE SWITCHER
®
Power Module with 2.95V-17V Input and Current Sharing in QFN Package
Check for Samples: LMZ31707
1
FEATURES
23
• Complete Integrated Power Solution Allows
Small Footprint, Low-Profile Design
• 10mm x 10mm x 4.3mm Package
– Pin Compatible with LMZ31710 & LMZ31704
• Efficiencies Up To 95%
• Eco-mode™ / Light Load Efficiency (LLE)
• Wide-Output Voltage Adjust
0.6 V to 5.5 V, with 1% Reference Accuracy
• Supports Parallel Operation for Higher Current
• Optional Split Power Rail Allows
Input Voltage Down to 2.95 V
• Adjustable Switching Frequency
(200 kHz to 1.2 MHz)
• Synchronizes to an External Clock
• Provides 180° out-of-phase Clock Signal
• Adjustable Slow-Start
• Output Voltage Sequencing / Tracking
• Power Good Output
• Programmable Undervoltage Lockout (UVLO)
• Over-Current & Over-Temperature Protection
• Pre-Bias Output Start-Up
• Operating Temperature Range: –40°C to 85°C
• Enhanced Thermal Performance: 13.3°C/W
• Meets EN55022 Class B Emissions
– Integrated Shielded Inductor
APPLICATIONS
• Broadband & Communications Infrastructure
• Automated Test and Medical Equipment
• Compact PCI / PCI Express / PXI Express
• DSP and FPGA Point-of-Load Applications
DESCRIPTION
The LMZ31707 SIMPLE SWITCHER® power module is an easy-to-use integrated power solution that combines a 7-A DC/DC converter with power
MOSFETs, a shielded inductor, and passives into a low profile, QFN package. This total power solution allows as few as three external components and eliminates the loop compensation and magnetics part selection process.
The 10x10x4.3 mm QFN package is easy to solder onto a printed circuit board and allows a compact point-of-load design. Achieves greater than 95% efficiency and excellent power dissipation capability with a thermal impedance of 13.3°C/W.
The
LMZ31707 offers the flexibility and the feature-set of a discrete point-of-load design and is ideal for powering a wide range of ICs and systems.
Advanced packaging technology affords a robust and reliable power solution compatible with standard QFN mounting and testing techniques.
V
IN
C
IN
Figure 1. SIMPLIFIED APPLICATION
PVIN
VIN
ISHARE
VOUT
SENSE+
LMZ31707
SYNC_OUT
PWRGD
INH/UVLO
VADJ
SS/TR
RT/CLK
STSEL
AGND PGND
R
RT
V
OUT
C
OUT
R
SET
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
Eco-mode is a trademark of Texas Instruments.
3
SIMPLE SWITCHER is a registered trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LMZ31707
SLVSBV7A – JUNE 2013 – REVISED AUGUST 2013
ABSOLUTE MAXIMUM RATINGS
(1) www.ti.com
Over Operating Temperature Range (Unless Otherwise Noted)
Input Voltage
VIN, PVIN
INH/UVLO, PWRGD, RT/CLK, SENSE+
ILIM, VADJ, SS/TR, STSEL, SYNC_OUT, ISHARE, OCP_SEL
PH
Output Voltage PH 10ns Transient
VOUT
RT/CLK, INH/UVLO
Source Current
Sink Current
PH
PH
PVIN
PWRGD
Operating Junction Temperature
Storage Temperature
Mechanical Shock
Mechanical Vibration
Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted
Mil-STD-883D, Method 2007.2, 20-2000Hz
MIN
–0.3
–0.3
–0.3
–1.0
–3.0
–0.3
–0.1
–40
–65
MAX
20
6
3
20
UNIT
V
V
V
V
20 V
6 V
±100 µA current limit current limit
A
A current limit A
2 mA
125
(2)
°C
150 °C
1500 G
20
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) See the temperature derating curves in the Typical Characteristics section for thermal information.
RECOMMENDED OPERATING CONDITIONS
Over Operating Free-Air Temperature Range (Unless Otherwise Noted)
PV
V
IN
IN
V
OUT f
SW
Input Switching Voltage
Input Bias Voltage
Output Voltage
Switching Frequency
MIN
2.95
4.5
0.6
200
NOM MAX
17
17
5.5
1200
UNIT
V
V
V kHz
PACKAGE SPECIFICATIONS
LMZ31707
Weight
Flammability Meets UL 94 V-O
MTBF Calculated reliability Per Bellcore TR-332, 50% stress, T
A
= 40°C, ground benign
UNIT
1.45 grams
37.4 MHrs
Table 1. ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at
www.ti.com
.
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ELECTRICAL CHARACTERISTICS
Over –40°C to 85°C free-air temperature, PV
C
IN
IN
= V
= 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, C
IN
= 12 V, V
OUT
OUT
= 1.8 V, I
OUT
= 7 A,
= 4 x 47 µF ceramic (unless otherwise noted)
(1)
PARAMETER TEST CONDITIONS MIN
I
OUT
V
IN
PV
IN
Output current
Input bias voltage range
T
A
= 85°C, natural convection
Over output current range
0
4.5
2.95
(2)
UVLO
V
OUT(adj)
Input switching voltage range Over output current range
V
IN
Undervoltage lockout
Output voltage adjust range
V
IN
Increasing
V
IN
Decreasing
Over output current range
3.5
0.6
V
OUT
Set-point voltage tolerance
Temperature variation
Line regulation
T
A
= 25°C, I
OUT
= 0 A
–40°C ≤ T
A
≤ +85°C, I
OUT
= 0 A
Over input voltage range
TYP
4.0
3.85
±0.2%
±0.1%
η
Load regulation
Total output voltage variation
Efficiency
Output voltage ripple
I
I
Over output current range
Includes set-point, line, load, and temperature variation
P
O
VIN
= 4 A
P
VIN
O
= V
= V
= 4 A
IN
IN
= 12 V
= 5 V
V
OUT
= 5.0 V, f
SW
= 1 MHz
V
OUT
= 3.3 V, f
SW
= 750 kHz
V
OUT
= 2.5 V, f
SW
= 750 kHz
V
OUT
= 1.8 V, f
SW
= 500 kHz
V
OUT
= 1.2 V, f
SW
= 300 kHz
V
OUT
= 0.9 V, f
SW
= 250 kHz
V
OUT
= 0.6 V, f
SW
= 200 kHz
V
OUT
= 3.3 V, f
SW
= 750 kHz
V
OUT
= 2.5 V, f
SW
= 750 kHz
V
OUT
= 1.8 V, f
SW
= 500 kHz
V
OUT
= 1.2 V, f
SW
= 300 kHz
V
OUT
= 0.9 V, f
SW
= 250 kHz
V
OUT
= 0.6 V, f
SW
= 200 kHz
20 MHz bandwith
ILIM pin open
±0.2%
94 %
I
LIM
Current limit threshold
92 %
90 %
89 %
87 %
85 %
82 %
95 %
93 %
92 %
90 %
87 %
84 %
14
12
Transient response
ILIM pin to AGND
1.0 A/µs load step from
25 to 75% I
OUT(max)
Recovery time
VOUT over/undershoot
9 tbd tbd
V
INH
I
INH
I
I(stby)
Inhibit threshold voltage
INH Input current
INH Hysteresis current
Input standby current
Inhibit High Voltage
Inhibit Low Voltage
V
INH
< 1.1 V
V
INH
> 1.3 V
INH pin to AGND
1.3
-0.3
Power Good
PWRGD Thresholds
V
OUT rising
V
OUT falling
Good
Fault
Fault
Good
-1.15
-3.3
2
95%
108%
91%
104% f
SW
PWRGD Low Voltage
Switching frequency
I(PWRGD) = 0.5 mA
R
RT
= 169 k Ω 400 500
5.5
±1%
(4)
±1.5%
(4) open
(5)
1.1
10
MAX
7
17
17
(3)
4.5
0.3
600
UNIT
A
V
V
V
V
V
μA
μA
µA mV
P-P
A
A
µs mV
V kHz
(1) See the
section for more information for output voltages < 1.5 V.
(2) The minimum P
VIN
(3) The maximum PV
IN is 2.95 V or (V
OUT
+ 0.7 V), whichever is greater. See voltage is 17 V or (22 x V
OUT
), whichever is less. See
for more details.
for more details.
(4) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external R
SET resistor.
(5) This pin has an internal pull-up. If it is left open, the device operates when input power is applied. A small, low-leakage MOSFET is recommended for control. When the device is operating and no UVLO resistor divider is present on this pin, the open voltage is typically
2.9 V.
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ELECTRICAL CHARACTERISTICS (continued)
Over –40°C to 85°C free-air temperature, PV
C
IN
IN
= V
= 0.1 µF + 2 x 22 µF ceramic + 100 µF bulk, C
IN
= 12 V, V
OUT
OUT
= 1.8 V, I
OUT
= 7 A,
= 4 x 47 µF ceramic (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN
f
CLK
V
CLK-H
V
CLK-L
D
CLK
Synchronization frequency
CLK High-Level
CLK Low-Level
CLK Duty Cycle
CLK Control
200
2.0
20
Thermal Shutdown
Thermal shutdown
Thermal shutdown hysteresis
44
(6)
C
IN
External input capacitance
Ceramic
Non-ceramic
Ceramic 47
(7)
C
OUT
External output capacitance Non-ceramic
TYP
50
175
10
100
(6)
200
220
(7)
Equivalent series resistance (ESR)
MAX
1200
5.5
0.5
80
UNIT
kHz
V
V
%
°C
°C
µF
1500
5000
(8)
35
µF m Ω
(6) A minimum of 44 µF of external ceramic capacitance is required across the input (VIN and PVIN connected) for proper operation. An additional 100 µF of bulk capacitance is recommended. It is also recommended to place a 0.1 µF ceramic capacitor directly across the
PVIN and PGND pins of the device. Locate the input capacitance close to the device. When operating with split VIN and PVIN rails, place 4.7µF of ceramic capacitance directly at the VIN pin. See
for more details.
(7) The amount of required output capacitance varies depending on the output voltage (see
). The amount of required capacitance must include at least 1x 47µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See
and
more details.
(8) When using both ceramic and non-ceramic output capacitors, the combined maximum must not exceed 5000 µF. It may be necessary to increase the slow start time when turning on into the maximum capacitance. See the
section for information on adjusting the slow start time.
THERMAL INFORMATION
θ
JA
ψ
JT
ψ
JB
THERMAL METRIC
Junction-to-ambient thermal resistance
(2)
Junction-to-top characterization parameter
(1)
(3)
Junction-to-board characterization parameter
(4)
LMZ31707
RVQ42
42 PINS
13.3
1.6
5.3
UNIT
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (literature number SPRA953 ).
(2) The junction-to-ambient thermal resistance, θ
JA
, applies to devices soldered directly to a 100 mm x 100 mm double-sided PCB with
2 oz. copper and natural convection cooling. Additional airflow reduces θ
JA
(3) The junction-to-top characterization parameter, ψ
JT
.
, estimates the junction temperature, T
J
, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). T
J the temperature of the top of the device.
= ψ
JT
* Pdis + T
T
; where Pdis is the power dissipated in the device and T
T
(4) The junction-to-board characterization parameter, ψ
JB
, estimates the junction temperature, T
J
, of a device in a real system, using a procedure described in JESD51-2A (sections 6 and 7). T
J
= ψ
JB
* Pdis + T
B
; where Pdis is the power dissipated in the device and T
B the temperature of the board 1mm from the device.
is is
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OCP_SEL
ILIM
PWRGD
SENSE+
VADJ
SS/TR
STSEL
ISHARE
SYNC_OUT
RT/CLK
AGND
DEVICE INFORMATION
FUNCTIONAL BLOCK DIAGRAM
LMZ31707
SLVSBV7A – JUNE 2013 – REVISED AUGUST 2013
OCP
Shutdown
Logic
PWRGD
Logic
Thermal
Shutdown
VIN
UVLO
VREF
+
+
Comp
Current
Share
Power
Stage and
Control
Logic
Oscillator with PLL
INH/UVLO
VIN
PVIN
PH
VOUT
PGND
LMZ31707
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NAME
TERMINAL
NO.
2
AGND
23
PGND
20
21
31
32
33
VIN
PVIN
VOUT
PH
DNC
3
19
42
5
9
24
14
15
16
17
18
35
36
37
38
41
10
13
1
11
12
39
40
34
ISHARE 25
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Table 2. PIN DESCRIPTIONS
DESCRIPTION
Zero volt reference for the analog control circuit. These pins are not connected together internal to the device and must be connected to one another using an AGND plane of the PCB. These pins are associated with the internal analog ground (AGND) of the device. See Layout Recommendations.
This is the return current path for the power stage of the device. Connect these pins to the load and to the bypass capacitors associated with PVIN and VOUT.
Input bias voltage pin. Supplies the control circuitry of the power converter. Connect this pin to the input bias supply. Connect bypass capacitors between this pin and PGND.
Input switching voltage. Supplies voltage to the power switches of the converter. Connect these pins to the input supply. Connect bypass capacitors between these pins and PGND.
Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external bypass capacitors between these pins and PGND.
Phase switch node. These pins must be connected to one another using a small copper island under the device for thermal relief. Do not place any external component on these pins or tie them to a pin of another function.
OCP_SEL
ILIM
SYNC_OUT
PWRGD
RT/CLK
VADJ
SENSE+
4
22
26
27
6
7
8
Do Not Connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
Current share pin. Connect this pin to other LMZ31707 device's ISHARE pin when paralleling multple
LMZ31707 devices. When unused, treat this pin as a Do Not Connect (DNC) and leave it isolated from all other signals or ground.
Over current protection select pin. Leave this pin open for hiccup mode operation. Connect this pin to AGND for cycle-by-cycle operation. See
for more details.
Current limit pin. Leave this pin open for full current limit threshold. Connect this pin to AGND to reduce the current limit threshold by appoximately 3 A.
Synchronization output pin. Provides a 180° out-of-phase clock signal.
Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately
±6% out of regulation. A pull-up resistor is required.
This pin is connected to an internal frequency setting resistor which sets the default switching frequency. An external resistor can be connected from this pin to AGND to increase the frequency. This pin can also be used to synchronize to an external clock.
Connecting a resistor between this pin and AGND sets the output voltage.
Remote sense connection. This pin must be connected to VOUT at the load or at the device pins. Connect this pin to VOUT at the load for improved regulation.
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NAME
TERMINAL
NO.
SS/TR 28
STSEL
INH/UVLO
29
30
LMZ31707
SLVSBV7A – JUNE 2013 – REVISED AUGUST 2013
Table 2. PIN DESCRIPTIONS (continued)
DESCRIPTION
Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time.
A voltage applied to this pin allows for tracking and sequencing control.
Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave this pin open to enable the TR feature.
Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to control the INH function. A resistor divider between this pin, AGND, and PVIN/VIN sets the UVLO voltage.
RVQ PACKAGE
(TOP VIEW)
PVIN
AGND
VIN
OCP_SEL
DNC
ILIM
SYNC_OUT
PWRGD
DNC
PH
PVIN
1
40 39 38 37 36 35 34 33 32
31
2
3
4
5
6
7
8
9
10
41 VOUT
42 PH
11
12
13 14 15 16 17 18
19 20
30
29
28
27
26
25
24
23
22
21
PGND
INH/UVLO
STSEL
SS/TR
SENSE+
VADJ
ISHARE
DNC
AGND
RT/CLK
PGND
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100
90
80
TYPICAL CHARACTERISTICS (PVIN = VIN = 12 V)
(1) (2)
30
25
20
Vo = 5.0V, fsw = 1MHz
Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
70
60
50
40
0 1 2 3
Vo = 5.0V, fsw = 1MHz
Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
4 5 6
Output Current (A)
Figure 2. Efficiency vs. Output Current
7
C001
15
10
5
0 1 2 3 4
Output Current (A)
5 6
Figure 3. Voltage Ripple vs. Output Current
7
C004
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
Vo = 5.0V, fsw = 1MHz
Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
0.0
0 1 2 3 4 5 6
Output Current (A)
Figure 4. Power Dissipation vs. Output Current
7
C004
90
80
70
60
50
40
30
20
0
Airflow = 0 LFM
All Output Voltages
1 2 3 4 5
Output Current (A)
Figure 5. Safe Operating Area
6 7
C001
40
30
20
10
0
120
90
60
30
0
±
10 -30
±
20 -60
Gain
±
30 -90
Phase
±
40
1000 10k 100k
-120
Frequency (kHz)
Figure 6. V
OUT
= 1.8 V, I
OUT
= 7 A, C
OUT
= 200 µF ceramic, f
SW
= 500 kHz
(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to
Figure 2 , Figure 3 , and Figure 4 .
(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm, 4-layer PCB with 2 oz. copper.
Applies to
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100
90
80
TYPICAL CHARACTERISTICS (PVIN = VIN = 5 V)
(1) (2)
30
25
20
Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
Vo = 0.6V, fsw = 200kHz
70
60
50
40
0 1 2 3
Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
Vo = 0.6V, fsw = 200kHz
4 5 6
Output Current (A)
Figure 7. Efficiency vs. Output Current
7
C001
15
10
5
0 1 2 3 4 5 6
Output Current (A)
Figure 8. Voltage Ripple vs. Output Current
7
C004
3.0
2.5
2.0
1.5
1.0
Vo = 3.3V, fsw = 750kHz
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
Vo = 0.6V, fsw = 200kHz
0.5
0.0
0 1 2 3 4 5 6
Output Current (A)
Figure 9. Power Dissipation vs. Output Current
7
C004
90
80
70
60
50
40
30
20
0
Airflow = 0 LFM
All Output Voltages
1 2 3 4 5
Output Current (A)
Figure 10. Safe Operating Area
6 7
C001
40
30
20
10
0
120
90
60
30
0
±
10 -30
±
20 -60
Gain
±
30 -90
Phase
±
40
1000 10k 100k
-120
Frequency (kHz)
Figure 11. V
OUT
= 1.8 V, I
OUT
= 7 A, C
OUT
= 200 µF ceramic, f
SW
= 500 kHz
(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to
Figure 7 , Figure 8 , and Figure 9 .
(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm, 4-layer PCB with 2 oz. copper.
Applies to
.
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100
90
80
TYPICAL CHARACTERISTICS (PVIN = 3.3 V, VIN = 5 V)
(1) (2)
30
25
20
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
Vo = 0.6V, fsw = 200kHz
70
60
50
40
0 1 2 3
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
Vo = 0.6V, fsw = 200kHz
4 5 6
Output Current (A)
Figure 12. Efficiency vs. Output Current
7
C001
15
10
5
0 1 2 3 4 5 6
Output Current (A)
Figure 13. Voltage Ripple vs. Output Current
7
C004
3.0
2.5
2.0
1.5
1.0
Vo = 2.5V, fsw = 750kHz
Vo = 1.8V, fsw = 500kHz
Vo = 1.2V, fsw = 300kHz
Vo = 0.9V, fsw = 250kHz
Vo = 0.6V, fsw = 200kHz
0.5
0.0
0 1 2 3 4 5 6 7
Output Current (A)
Figure 14. Power Dissipation vs. Output Current
C004
90
80
70
60
50
40
30
20
0
Airflow = 0 LFM
All Output Voltages
1 2 3 4 5
Output Current (A)
Figure 15. Safe Operating Area
6 7
C001
40
30
20
10
0
120
90
60
30
0
±
10 -30
±
20 -60
Gain
±
30 -90
Phase
±
40
1000 10k 100k
-120
Frequency (kHz)
Figure 16. V
OUT
= 1.8 V, I
OUT
= 7 A, C
OUT
= 200 µF ceramic, f
SW
= 500 kHz
(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to
,
, and
(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm, 4-layer PCB with 2 oz. copper.
Applies to
.
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2.1
2.2
2.3
2.4
2.5
1.6
1.7
1.8
1.9
2.0
V
OUT
(V)
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
2.6
2.7
2.8
2.9
3.0
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APPLICATION INFORMATION
Adjusting the Output Voltage
The VADJ control sets the output voltage of the LMZ31707. The output voltage adjustment range is from 0.6V to
5.5V. The adjustment method requires the addition of R
SET
, which sets the output voltage, the connection of
SENSE+ to VOUT, and in some cases R
RT which sets the switching frequency. The R
SET resistor must be connected directly between the VADJ (pin 26) and AGND (pin 23). The SENSE+ pin (pin 27) must be connected to VOUT either at the load for improved regulation or at VOUT of the device. The R
RT resistor must be connected directly between the RT/CLK (pin 22) and AGND (pin 23).
gives the standard external R
SET resistor for a number of common bus voltages, along with the recommended R
RT resistor for that output voltage.
RESISTORS
R
SET
(k Ω)
R
RT
(k Ω)
Table 3. Standard R
SET
Resistor Values for Common Output Voltages
0.9
2.87
1000
1.0
2.15
1000
OUTPUT VOLTAGE V
OUT
(V)
1.2
1.8
2.5
1.43
487
0.715
169
0.453
90.9
3.3
0.316
90.9
5.0
0.196
63.4
For other output voltages, the value of the required resistor can either be calculated using the following formula, or simply selected from the range of values given in
1.43
R
SET
=
æ
ç
è
æ
è
V
OUT
0.6
ö
ø
-
1
ö
÷
ø
(1)
0.866
0.787
0.715
0.665
0.619
0.576
0.536
0.511
0.475
0.453
R
SET
(k Ω)
open
8.66
4.32
2.87
2.15
1.74
1.43
1.24
1.07
0.953
0.432
0.412
0.392
0.374
0.357
500
500
500
500
750
300
300
500
500
500
f
SW
(kHz)
200
200
200
250
250
250
300
300
300
300
750
750
750
750
750
Table 4. Standard R
SET
Resistor Values
169
169
169
169
90.9
487
487
169
169
169
R
RT
(k Ω)
OPEN
OPEN
OPEN
1000
1000
1000
487
487
487
487
90.9
90.9
90.9
90.9
90.9
4.6
4.7
4.8
4.9
5.0
4.1
4.2
4.3
4.4
4.5
V
OUT
(V)
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
5.1
5.2
5.3
5.4
5.5
0.243
0.237
0.232
0.226
0.221
0.215
0.210
0.205
0.200
0.196
R
SET
(k Ω)
0.348
0.332
0.316
0.309
0.294
0.287
0.280
0.267
0.261
0.255
0.191
0.187
0.182
0.178
0.174
63.4
63.4
63.4
63.4
63.4
63.4
63.4
63.4
63.4
63.4
R
RT
(k Ω)
90.9
90.9
90.9
90.9
90.9
90.9
90.9
90.9
90.9
90.9
63.4
63.4
63.4
63.4
63.4
1000
1000
1000
1000
1000
1000
1000
1000
1000
1000
f
SW
(kHz)
750
750
750
750
750
750
750
750
750
750
1000
1000
1000
1000
1000
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Capacitor Recommendations for the LMZ31707 Power Supply
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Capacitor Technologies
Electrolytic, Polymer-Electrolytic Capacitors
When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.
Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures are above 0°C.
Ceramic Capacitors
The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.
Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient response of the output.
Tantalum, Polymer-Tantalum Capacitors
Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended for power applications.
Input Capacitor
The LMZ31707 requires a minimum input capacitance of 44 μF of ceramic type. An additional 100 µF of nonceramic capacitance is recommended for applications with transient load requirements. The voltage rating of input capacitors must be greater than the maximum input voltage. At worst case, when operating at 50% duty cycle and maximum load, the combined ripple current rating of the input capacitors must be at least 3.5 Arms.
includes a preferred list of capacitors by vendor. It is also recommended to place a 0.1 µF ceramic capacitor directly across the PVIN and PGND pins of the device. When operating with split VIN and PVIN rails, place 4.7µF of ceramic capacitance directly at the VIN pin.
Output Capacitor
The required output capacitance is determined by the output voltage of the LMZ31707. See
for the amount of required capacitance. The effects of temperature and capacitor voltage rating must be considered when selecting capacitors to meet the minimum required capacitance. The required output capacitance can be comprised of all ceramic capacitors, or a combination of ceramic and bulk capacitors. The required capacitance must include at least one 47 µF ceramic. When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended in
are required. The required capacitance above the minimum is determined by actual transient deviation requirements.
includes a preferred list of capacitors by vendor.
MIN
0.6
0.8
1.2
3.0
4.0
Table 5. Required Output Capacitance
V
OUT
RANGE (V)
MINIMUM REQUIRED C
OUT
(µF)
MAX
< 0.8
< 1.2
< 3.0
< 4.0
5.5
(1) Minimum required must include at least one 47 µF ceramic capacitor.
500 µF
(1)
300 µF
(1)
200 µF
(1)
100 µF
(1)
47 µF ceramic
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VENDOR
Sanyo
Kemet
Sanyo
Sanyo
Sanyo
Kemet
Kemet
Sanyo
Sanyo
Murata
TDK
TDK
Murata
Murata
Panasonic
SERIES
X5R
X5R
X5R
X5R
X5R
EEH-ZA
POSCAP
T520
POSCAP
POSCAP
POSCAP
T530
T530
POSCAP
POSCAP
SLVSBV7A – JUNE 2013 – REVISED AUGUST 2013
Table 6. Recommended Input/Output Capacitors
(1)
PART NUMBER
GRM32ER61E226K
C3225X5R0J107M
C3225X5R0J476K
GRM32ER60J107M
GRM32ER60J476M
EEH-ZA1E101XP
16TQC68M
T520V107M010ASE025
10TPE220ML
6TPE100MI
2R5TPE220M7
T530D227M006ATE006
T530D337M006ATE010
2TPF330M6
6TPE330MFL
WORKING
VOLTAGE
(V)
CAPACITOR CHARACTERISTICS
CAPACITANCE
(µF)
ESR
(2)
(m Ω)
25
6.3
6.3
22
100
47
2
2
2
6.3
6.3
25
16
10
10
6.3
100
47
100
68
100
220
100
50
25
25
25
2
2
30
2.5
6.3
6.3
2.0
6.3
220
220
330
330
330
7
6
10
6
15
(1)
Capacitor Supplier Verification, RoHS, Lead-free and Material Details
Consult capacitor suppliers regarding availability, material composition, RoHS and lead-free status, and manufacturing process requirements for any capacitors identified in this table.
(2) Maximum ESR @ 100kHz, 25°C.
Transient Response
Table 7. Output Voltage Transient Response
C
IN1
= 3x 22 µF CERAMIC, C
IN2
= 100 µF POLYMER-TANTALUM
V
OUT
(V)
0.6
0.9
1.2
1.8
3.3
V
IN
(V)
5
12
5
12
5
12
5
12
5
12
C
OUT1
Ceramic
500 µF
500 µF
300 µF
300 µF
300 µF
300 µF
200 µF
200 µF
200 µF
200 µF
200 µF
200 µF
200 µF
200 µF
100 µF
100 µF
C
OUT2
BULK
220 µF
220 µF
220 µF
470 µF
220 µF
470 µF
220 µF
470 µF
220 µF
470 µF
220 µF
470 µF
220 µF
470 µF
220 µF
220 µF
VOLTAGE DEVIATION (mV)
2 A LOAD STEP, 3.5 A LOAD STEP,
(1 A/µs) (1 A/µs)
30
30
40
35
45
45
65
60
65
65
60
105
115
35
30
50
45
45
40
70
90
100
90
177
190
60
55
85
75
80
70
105
RECOVERY TIME
(µs)
95
95
100
100
100
100
110
90
90
95
95
110
120
120
130
150
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Transient Waveforms
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Figure 17. PVIN = 12V, VOUT = 1.2V, 3.5A Load
Step
Figure 18. PVIN = 12V, VOUT = 1.8V, 3.5A Load
Step
Figure 19. PVIN = 5V, VOUT = 0.9V, 2.5A Load Step Figure 20. PVIN = 5V, VOUT = 1.8V, 3.5A Load Step
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Application Schematics
V
IN
/ P
VIN
4.5 V to 17 V
+
C
IN1
100 µF
C
IN2
47 µF
C
IN3
0.1 µF
VIN
LMZ31707
SENSE+
PVIN VOUT
SYNC_OUT
PWRGD
INH/UVLO
ISHARE
RT/CLK
SS/TR
VADJ
STSEL AGND PGND
V
OUT
1.2 V
C
OUT1
2x 100 µF
+
C
OUT2
220 µF
R
SET
1.43 k
R
RT
487 k
Figure 21. Typical Schematic
PVIN = VIN = 4.5 V to 17 V, VOUT = 1.2 V
V
IN
/ P
VIN
4.5 V to 17 V
+
C
IN1
100 µF
C
IN2
47 µF
C
IN3
0.1 µF
VIN
LMZ31707
SENSE+
PVIN VOUT
SYNC_OUT
PWRGD
INH/UVLO
ISHARE
RT/CLK
SS/TR
VADJ
STSEL AGND PGND
V
OUT
3.3 V
C
OUT1
100 µF
+
C
OUT2
220 µF
R
SET
316
R
RT
90.9 k
Figure 22. Typical Schematic
PVIN = VIN = 4.5 V to 17 V, VOUT = 3.3 V
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P
VIN
3.3 V
+
V
IN
4.5 V to 17 V
C
IN3
4.7 µF
VIN
LMZ31707
SENSE+
PVIN VOUT
C
IN1
100 µF
C
IN2
47 µF
C
IN3
0.1 µF
SYNC_OUT
PWRGD
INH/UVLO
ISHARE
RT/CLK
SS/TR
VADJ
STSEL AGND PGND
V
OUT
1.0 V
C
OUT1
3x 100 µF
+
C
OUT2
220 µF
R
SET
2.15 k
R
RT
1 M
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Figure 23. Typical Schematic
PVIN = 3.3 V, VIN = 4.5 V to 17 V, VOUT = 1.0 V
VIN and PVIN Input Voltage
The LMZ31707 allows for a variety of applications by using the VIN and PVIN pins together or separately. The
VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the power converter system.
If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 17 V. If using the VIN pin separately from the PVIN pin, the VIN pin must be greater than 4.5 V, and the PVIN pin can range from as low as 2.95 V to 17 V. When operating from a split rail, it is recommended to supply VIN from 5 V to 12 V, for best performance. A voltage divider connected to the INH/UVLO pin can adjust either input voltage UVLO appropriately. See the
Programmable Undervoltage Lockout (UVLO)
section of this datasheet for more information.
3.3 V PVIN Operation
Applications operating from a PVIN of 3.3 V must provide at least 4.5 V for VIN. It is recommended to supply VIN from 5 V to 12 V, for best performance. See listeraure number SNVA692 for help creating 5 V from 3.3 V using a small, simple charge pump device.
Power Good (PWRGD)
The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 95% and 104% of the set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 k Ω and 100 kΩ to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once
VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the voltage on SENSE+ is lower than 91% or greater than 108% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input
UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.
SYNC_OUT
The LMZ31707 provides a 180° out-of-phase clock signal for applications requiring synchronization. The
SYNC_OUT pin produces a 50% duty cycle clock signal that is the same frequency as the device's switching frequency, but is 180° out of phase. Operating two devices 180° out of phase reduces input and output voltage ripple. The SYNC_OUT clock signal is compatible with other LMZ3 devices that have a CLK input.
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Parallel Operation
Up to six LMZ31707 devices can be paralleled for increased output current. Multiple connections must be made between the paralleled devices and the component selection is slightly different than for a stand-alone
LMZ31707 device. A typical LMZ31707 parallel schematic is shown in
Figure 24 . Refer to application note,
SNVA695 for information and design help when paralleling multiple LMZ31707 devices.
V
IN
= 12V
220µF
22µF
0.1µF
VIN
PVIN
LMZ31707
PWRGD
SENSE+
VOUT
V
O
= 1.8V
SYNC_OUT
RT/CLK
330µF
Sync Freq
500KHz
R
RT
169kΩ
STSEL
AGND
PGND
100µF
100µF
5V
Voltage
Supervisor
INH
Control
C
SH
C
SS
R
SET
715 Ω
22µF 0.1µF
R
RT
169kΩ
VIN
PVIN
SYNC_OUT
RT/CLK
LMZ31707
PWRGD
SENSE+
VOUT
STSEL
AGND
PGND
100µF
100µF
Figure 24. Typical LMZ31707 Parallel Schematic
Light Load Efficiency (LLE)
The LMZ31707 operates in pulse skip mode at light load currents to improve efficiency and decrease power dissipation by reducing switching and gate drive losses.
These pulses may cause the output voltage to rise when there is no load to discharge the energy. For output voltages < 1.5 V, a minimum load is required. The amount of required load can be determined by
. In most cases the minimum current drawn by the load circuit will be enough to satisfy this load. Applications requiring a load resistor to meet the minimum load, the added power dissipation will be ≤ 3.6 mW. A single 0402 size resistor across VOUT and PGND can be used.
(2)
When V
OUT
= 0.6 V and R
SET
= OPEN, the minimum load current is 600 µA.
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Power-Up Characteristics
When configured as shown in the front page schematic, the LMZ31707 produces a regulated output voltage following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input source.
shows the start-up waveforms for a LMZ31707, operating from a 5-V input (PVIN=VIN) and with the output voltage adjusted to 1.8 V.
shows the start-up waveforms for a LMZ31707 starting up into a pre-biased output voltage. The waveforms were measured with a 5-A constant current load.
Figure 25. Start-Up Waveforms Figure 26. Start-up into Pre-bias
Pre-Biased Start-Up
The LMZ31707 has been designed to prevent the low-side MOSFET from discharging a pre-biased output.
During pre-biased startup, the low-side MOSFET does not turn on until the high-side MOSFET has started switching. The high-side MOSFET does not start switching until the slow start voltage exceeds the voltage on the
VADJ pin. Refer to
.
Remote Sense
The SENSE+ pin must be connected to V
OUT at the load, or at the device pins.
Connecting the SENSE+ pin to V
OUT at the load improves the load regulation performance of the device by allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by the high output current flowing through the small amount of pin and trace resistance. This should be limited to a maximum of 300 mV.
NOTE
The remote sense feature is not designed to compensate for the forward drop of nonlinear or frequency dependent components that may be placed in series with the converter output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When these components are enclosed by the SENSE+ connection, they are effectively placed inside the regulation control loop, which can adversely affect the stability of the regulator.
Thermal Shutdown
The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds
175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C typically.
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Output On/Off Inhibit (INH)
The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low quiescent current state. The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device.
If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to interface with the pin. Using a voltage superviser to control the INH pin allows control of the turn-on and turn-off of the device as opposed to relying on the ramp up or down if the input voltage source.
shows the typical application of the inhibit function. Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, shown in
Figure 28 . If Q1 is turned off, the supply
executes a soft-start power-up sequence, as shown in
. A regulated output voltage is produced within
2 ms. The waveforms were measured with a 5-A constant current load.
INH
Control
Q1
INH/UVLO
AGND STSEL SS/TR
Figure 27. Typical Inhibit Control
Figure 28. Inhibit Turn-Off Figure 29. Inhibit Turn-On
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Slow Start (SS/TR)
Connecting the STSEL pin to AGND and leaving SS/TR pin open enables the internal SS capacitor with a slow start interval of approximately 1.2 ms. Adding additional capacitance between the SS pin and AGND increases the slow start time. Increasing the slow start time will reduce inrush current seen by the input source and reduce the current seen by the device when charging the output capacitors. To avoid the activation of current limit and ensure proper start-up, the SS capacitor may need to be increased when operating near the maximum output capacitance limit.
shows an additional SS capacitor connected to the SS/TR pin and the STSEL pin connected to AGND.
See
below for SS capacitor values and timing interval.
SS/TR
C
SS
(Optional)
AGND STSEL
Figure 30. Slow-Start Capacitor (C
SS
) and STSEL Connection
C
SS
(nF)
SS Time (msec)
Table 8. Slow-Start Capacitor Values and Slow-Start Time open
1.2
3.3
2.1
4.7
2.5
10
3.8
15
5.1
22
7.0
33
9.8
Overcurrent Protection
For protection against load faults, the LMZ31707 incorporates output overcurrent protection. The overcurrent protection mode can be selected using the OCP_SEL pin. Leaving the OCP_SEL pin open selects hiccup mode and connecting it to AGND selects cycle-by-cycle mode. In hiccup mode, applying a load that exceeds the regulator's overcurrent threshold causes the regulated output to shut down. Following shutdown, the module periodically attempts to recover by initiating a soft-start power-up as shown in
. This is described as a hiccup mode of operation, whereby the module continues in a cycle of successive shutdown and power up until the load fault is removed. During this period, the average current flowing into the fault is significantly reduced which reduces power dissipation. Once the fault is removed, the module automatically recovers and returns to normal operation as shown in
.
In cycle-by-cycle mode, applying a load that exceeds the regulator's overcurrent threshold limits the output current and reduces the output voltage as shown in
. During this period, the current flowing into the fault remains high causing the power dissipation to stay high as well. Once the overcurrent condition is removed, the output voltage returns to the set-point voltage as shown in
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Figure 31. Overcurrent Limiting (Hiccup) Figure 32. Removal of Overcurrent (Hiccup)
Figure 33. Overcurrent Limiting (Cycle-by-Cycle) Figure 34. Removal of Overcurrent (Cycle-by-
Cycle)
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Synchronization (CLK)
An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and
1200 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.5 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in
Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the
RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to
100 kHz first before returning to the switching frequency set by the RT resistor (R
RT
).
External Clock
200 kHz to 1200 kHz
RT/CLK
R
RT
AGND
Figure 35. RT/CLK Configuration
The synchronization frequency must be selected based on the output voltages of the devices being synchronized.
shows the allowable frequencies for a given range of output voltages. For the most efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires synchronizing three LMZ31707 devices with output voltages of 1.0 V, 1.2 V and 1.8 V, all powered from
PVIN = 12 V.
shows that all three output voltages should be synchronized to 300 kHz.
200
300
400
500
600
700
800
900
1000
1100
1200
Table 9. Synchronization Frequency vs Output Voltage
SYNCHRONIZATION
FREQUENCY (kHz)
1.1
1.4
1.6
1.9
2.1
2.4
2.7
2.9
3.2
PVIN = 12 V
V
OUT
RANGE (V)
MIN MAX
0.6
0.8
1.3
2.0
5.5
5.5
5.5
5.5
2.5
3.4
5.0
5.5
5.5
0.6
0.6
0.7
0.8
0.9
1.0
1.1
1.3
1.4
PVIN = 5 V
V
OUT
RANGE (V)
MIN MAX
0.6
0.6
1.5
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
4.3
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Sequencing (SS/TR)
Many of the common power supply sequencing methods can be implemented using the SS/TR, INH and
PWRGD pins. The sequential method is illustrated in
using two LMZ31707 devices. The PWRGD pin of the first device is coupled to the INH pin of the second device which enables the second power supply once the primary supply reaches regulation.
shows sequential turn-on waveforms of two LMZ31707 devices.
INH/UVLO
VOUT
STSEL
PWRGD
V
OUT1
INH/UVLO
VOUT
STSEL
PWRGD
V
OUT2
Figure 36. Sequencing Schematic Figure 37. Sequencing Waveforms
Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in
to the output of the power supply that needs to be tracked or to another voltage reference source. The tracking voltage must exceed 750mV before V
OUT2 of the V
OUT2 reaches its set-point voltage. The PWRGD output device may remain low if the tracking voltage does not exceed 1.4V.
shows simultaneous turn-on waveforms of two LMZ31707 devices. Use
and
to calculate the values of R1 and
R2.
R1 =
(
V
OUT2
´ 12.6
)
0.6
(3)
R2 =
0.6
´
R1
(
V
OUT2
0.6
)
(4)
V
OUT1
INH/UVLO
VOUT
STSEL SS/TR
V
OUT2
INH/UVLO
VOUT
STSEL SS/TR
R1
R2
Figure 38. Simultaneous Tracking Schematic
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Figure 39. Simultaneous Tracking Waveforms
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Programmable Undervoltage Lockout (UVLO)
The LMZ31707 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.5 V(max) with a typical hysteresis of 150 mV.
If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a combined VIN and PVIN, then the UVLO pin can be configured as shown in
or
lists standard values for R
UVLO1 and R
UVLO2 to adjust the VIN UVLO voltage up.
PVIN
VIN
R
UVLO1
R
UVLO2
INH/UVLO
PVIN
VIN
R
UVLO1
R
UVLO2
INH/UVLO
Figure 40. Adjustable VIN UVLO Figure 41. Adjustable VIN and PVIN Undervoltage
Lockout
VIN UVLO (V) 5.0
R
UVLO1
(k Ω)
68.1
R
UVLO2
(k
Ω)
21.5
Hysteresis (mV)
400
Table 10. Standard Resistor values for Adjusting VIN UVLO
5.5
68.1
18.7
415
6.0
68.1
16.9
430
6.5
68.1
15.4
450
7.0
68.1
14.0
465
7.5
68.1
13.0
480
8.0
68.1
12.1
500
8.5
68.1
11.3
515
9.0
68.1
10.5
530
9.5
68.1
9.76
550
10.0
68.1
9.31
565
For a split rail application, if a secondary UVLO on PVIN is required, VIN must be ≥ 4.5V.
shows the
PVIN UVLO configuration. Use
to select R
UVLO1 and R
UVLO2 for PVIN. If PVIN UVLO is set for less than
3.0 V, a 5.1-V zener diode should be added to clamp the voltage on the UVLO pin below 6 V.
> 4.5 V
VIN
PVIN
R
UVLO1
R
UVLO2
INH/UVLO
Figure 42. Adjustable PVIN Undervoltage Lockout, (VIN ≥4.5 V)
Table 11. Standard Resistor Values for Adjusting PVIN UVLO, (VIN ≥4.5 V)
PVIN UVLO (V)
R
UVLO1
(k Ω)
R
UVLO2
(k Ω)
Hysteresis (mV)
2.9
68.1
47.5
330
3.0
68.1
44.2
335
3.5
68.1
34.8
350
4.0
68.1
28.7
365
4.5
68.1
24.3
385
For higher PVIN UVLO voltages see
for resistor values
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Layout Considerations
To achieve optimal electrical and thermal performance, an optimized PCB layout is required.
thru
Figure 46 , shows a typical PCB layout. Some considerations for an optimized layout are:
• Use large copper areas for power planes (PVIN, VOUT, and PGND) to minimize conduction loss and thermal stress.
• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.
• Locate additional output capacitors between the ceramic capacitor and the load.
• Keep AGND and PGND separate from one another.
• Place R
SET
, R
RT
, and C
SS as close as possible to their respective pins.
• Use multiple vias to connect the power planes to internal layers.
Figure 43. Typical Top-Layer Layout Figure 44. Typical Layer-2 Layout
Figure 45. Typical Layer-3 Layout
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Figure 46. Typical Bottom-Layer Layout
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EMI
The LMZ31707 is compliant with EN55022 Class B radiated emissions.
and
show typical examples of radiated emissions plots for the LMZ31707 operating from 5V and 12V respectively. Both graphs include the plots of the antenna in the horizontal and vertical positions.
Figure 47. Radiated Emissions 5-V Input, 1.8-V
Output, 7-A Load (EN55022 Class B)
Figure 48. Radiated Emissions 12-V Input, 1.8-V
Output, 7-A Load (EN55022 Class B)
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Mar-2015
PACKAGING INFORMATION
Orderable Device
LMZ31707RVQR
Status
(1)
ACTIVE
Package Type Package
Drawing
Pins Package
Qty
B3QFN RVQ 42 500
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU
MSL Peak Temp
(3)
Level-3-260C-168 HR
Op Temp (°C)
-40 to 85
Device Marking
(4/5)
LMZ31707
LMZ31707RVQT ACTIVE B3QFN RVQ 42 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 85 LMZ31707
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
23-Mar-2015 www.ti.com
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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