SN74LVC244A Octal Buffer/Driver With 3-State Outputs 1 Features 2 Applications

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SN74LVC244A
SCAS414Z – NOVEMBER 1992 – REVISED JANUARY 2015
SN74LVC244A Octal Buffer/Driver With 3-State Outputs
1 Features
2 Applications
•
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•
1
•
•
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Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Specified From –40°C to 85°C and
–40°C to 125°C
Max tpd of 5.9 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Can Be Used as a Down Translator to Translate
Inputs From a Max of 5.5 V Down
to the VCC Level
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
Servers
LED Displays
Network Switches
Telecom Infrastructure
Motor Drivers
I/O Expanders
3 Description
These octal bus buffers are designed for 1.65-V to
3.6-V VCC operation. The ’LVC244A devices are
designed for asynchronous communication between
data buses.
Device Information(1)
PART NUMBER
SN74LVC244A
PACKAGE (PIN)
BODY SIZE
PDIP (20)
25.40 mm x 6.35 mm
SOP (20)
12.60 mm x 5.30 mm
SSOP (20)
7.50 mm x 5.30 mm
TVSOP (20)
5.00 mm x 4.40 mm
SOIC (20)
12.80 mm x 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC244A
SCAS414Z – NOVEMBER 1992 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
5
5
6
6
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics .........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1 Trademarks ........................................................... 12
13.2 Electrostatic Discharge Caution ............................ 12
13.3 Glossary ................................................................ 12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision Y (September 2010) to Revision Z
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Updated Features. .................................................................................................................................................................. 1
2
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6 Pin Configuration and Functions
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
VCC
20
2
1
20
2
19 2OE
3
18 1Y1
17 2A4
4
16 1Y2
15 2A3
5
6
14 1Y3
13 2A2
7
8
12 1Y4
9
GND
10
11
2A1
1
1OE
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
RGY PACKAGE
(TOP VIEW)
Pin Functions
PIN
NAME
DB, DGV,
DW, NS, PW,
and RGY
GQN or ZQN
1A1
2
A1
I
Input
1A2
4
B1
I
Input
1A3
6
C1
I
Input
1A4
8
D1
I
Input
1OE
1
A2
I
Output enable
1Y1
18
B4
O
Output
1Y2
16
C4
O
Output
1Y3
14
D4
O
Output
1Y4
12
E4
O
Output
2A1
11
E3
I
Input
2A2
13
D2
I
Input
2A3
15
C3
I
Input
2A4
17
B2
I
Input
2OE
19
A2
I
Output enable
2Y1
9
E2
O
Output
2Y2
7
D3
O
Output
2Y3
5
C2
O
Output
2Y4
3
B3
O
Output
GND
10
E1
—
Ground
VCC
20
A3
—
Power pin
TYPE
DESCRIPTION
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
DB package (4)
70
DGV package (4)
92
DW package (4)
θJA
Package thermal impedance
GQN or ZQN package
58
(4)
78
N package (4)
69
NS package (4)
60
PW package
(4)
83
RGY package (5)
Ptot
Power dissipation
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(5)
(6)
(7)
°C/W
37
TA = –40°C to 125°C (6) (7)
–65
500
mW
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
For the DW package: above 70°C the value of Ptot derates linearly with 8 mW/K.
For the DB, DGV, N, NS, and PW packages: above 60°C the value of Ptot derates linearly with 5.5 mW/K.
7.2 ESD Ratings
PARAMETER
V(ESD)
(1)
(2)
4
Electrostatic
discharge
DEFINITION
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over recommended operating free-air temperature range (unless otherwise noted) (1)
TA = 25°C
VCC Supply voltage
Operating
Data retention only
VIH
MIN
MAX
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.65
3.6
1.5
1.5
0.65 × VCC
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
2
VCC = 1.65 V to 1.95 V
Low-level
input voltage
VIL
VI
Input voltage
VO
Output voltage
High-level
output current
Low-level
output current
IOL
(1)
UNIT
V
V
0.35 × VCC
0.35 × VCC
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
0.7
0.7
VCC = 2.7 V to 3.6 V
0.8
0.8
0.8
V
0
5.5
0
5.5
0
5.5
V
0
VCC
0
VCC
0
VCC
V
VCC = 1.65 V
IOH
–40 TO 125°C
1.5
VCC = 1.65 V to 1.95 V
High-level
input voltage
–40 TO 85°C
–4
–4
–4
VCC = 2.3 V
–8
–8
–8
VCC = 2.7 V
–12
–12
–12
VCC = 3 V
–24
–24
–24
VCC = 1.65 V
4
4
4
VCC = 2.3 V
8
8
8
VCC = 2.7 V
12
12
12
VCC = 3 V
24
24
24
mA
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
SN74LVC244A
THERMAL METRIC (1)
DB (2)
DGV (2)
DW (2)
GQN or
ZQN (2)
78
N (2)
NS (2)
PW (2)
RGY (3)
61.6
90.1
114.7
50.3
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
108.1
128.7
90.9
RθJC(to
Junction-to-case(top) thermal resistance
70.2
43.7
55.3
46.5
56.4
48.4
58.4
RθJB
Junction-to-board thermal resistance
63.3
70.2
58.8
42.5
57.7
65.6
28.3
ψJT
Junction-to-top characterization
parameter
30.6
3.1
29.1
34.6
28.4
6.8
4.9
ψJB
Junction-to-board characterization
parameter
62.9
69.5
58.3
42.4
57.2
65.1
28.4
—
—
—
—
—
—
22.7
p)
RθJC(bo Junction-to-case(bottom) thermal
resistance
t)
(1)
(2)
(3)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC
II
TYP
MAX
MIN
–40 TO 125°C
MAX
MIN
1.65 V
to
3.6 V
VCC – 0.2
VCC – 0.2
VCC – 0.3
IOH = –4 mA
1.65 V
1.29
1.2
1.05
IOH = –8 mA
2.3 V
1.9
1.7
1.55
2.7 V
2.2
2.2
2.05
UNIT
MAX
V
3V
2.4
2.4
2.25
IOH = –24 mA
3V
2.3
2.2
2
IOL = 100 µA
1.65 V
to
3.6 V
0.1
0.2
IOL = 4 mA
1.65 V
0.24
0.45
0.6
IOL = 8 mA
2.3 V
0.3
0.7
0.75
IOL = 12 mA
2.7 V
0.4
0.4
0.6
IOL = 24 mA
3V
0.55
0.55
0.8
3.6 V
±1
±5
±20
µA
VI = 5.5 V or GND
0.3
V
Ioff
VI or VO = 5.5 V
0
±1
±10
±20
µA
IOZ
VO = 0 to 5.5 V
3.6 V
±1
±10
±20
µA
1
10
40
1
10
40
500
500
5000
ICC
VI = VCC or GND
IO = 0
3.6 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.7 V
to
3.6 V
Ci
VI = VCC or GND
3.3 V
4
pF
Co
VO = VCC or GND
3.3 V
5.5
pF
ΔICC
(1)
MIN
–40 TO 85°C
IOH = –100 µA
IOH = –12 mA
VOL
TA = 25°C
3.6 V ≤ VI ≤ 5.5 V (1)
µA
µA
This applies in the disabled state only.
7.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A
Y
VCC
OE
Y
Y
6
MAX
MIN
MAX
7
14.4
1
14.9
1
16.4
1
5.9
10.4
1
10.9
1
12.4
2.5 V ± 0.2 V
1
4.2
7.4
1
7.9
1
10
2.7 V
1
4.2
6.7
1
6.9
1
8.2
1.5
3.9
5.7
1.5
5.9
1.5
7.2
1.5 V
1
8.3
17.8
1
18.3
1
19.8
1.8 V ± 0.15 V
1
6.4
12.1
1
12.6
1
14.1
2.5 V ± 0.2 V
1
4.6
9.1
1
9.6
1
11.7
10.3
1
5
8.4
1
8.6
1
1.5
4.5
7.4
1.5
7.6
1.5
9.4
1.5 V
1
7.2
15.6
1
16.1
1
17.6
1.8 V ± 0.15 V
1
5.8
11.6
1
12.1
1
13.6
2.5 V ± 0.2 V
1
3.7
7.3
1
7.8
1
9.9
2.7 V
1
3.8
6.6
1
6.8
1
8.6
1.5
3.8
6.3
1.5
6.5
1.5
8
3.3 V ± 0.3 V
tsk(o)
MIN
1
2.7 V
OE
–40 TO 125°C
MAX
1.5 V
3.3 V ± 0.3 V
tdis
–40 TO 85°C
TYP
1.8 V ± 0.15 V
3.3 V ± 0.3 V
ten
TA = 25°C
MIN
3.3 V ± 0.3 V
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1
1.5
UNIT
ns
ns
ns
ns
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7.7 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
f = 10 MHz
Power dissipation capacitance per buffer/driver
Outputs disabled
f = 10 MHz
VCC
TYP
1.8 V
43
2.5 V
43
3.3 V
44
1.8 V
1
2.5 V
1
3.3 V
2
UNIT
pF
7.8 Typical Characteristics
10
14
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
10
8
6
4
One Output Switching
Four Outputs Switching
Eight Outputs Switching
8
6
4
2
2
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.5 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
2 × VCC
6V
6V
15 pF
30 pF
30 pF
50 pF
50 pF
2 kΩ
1 kΩ
500 Ω
500 Ω
500 Ω
0.1 V
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The LVC244A device is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs.
When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in
the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be
tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking
capability of the driver.
9.2 Functional Block Diagram
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.
9.3 Feature Description
•
•
Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8 V
Inputs accept voltage levels up to 5.5 V
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
SN74LVC244A is a high drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern. The inputs can accept voltages to 5.5 V at any valid VCC
making it ideal for down translation.
10.2 Typical Application
Regulated 3 V
SN74LVC244A
1OE
A1
uC or
System
Logic
VCC
Y1
uC
System Logic
LEDs
A4
Y4
GND
Figure 4. Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifcations, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above VCC.
10
Submit Documentation Feedback
Copyright © 1992–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC244A
SN74LVC244A
www.ti.com
SCAS414Z – NOVEMBER 1992 – REVISED JANUARY 2015
Typical Application (continued)
10.2.3 Application Curves
100
80
60
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
40
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OH – mA
I OL – mA
60
40
0
–20
–40
20
–60
0
–80
–20
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–100
–1
–0.5 0.0
VOL – V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH – V
Figure 5. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)
Figure 6. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
12.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
Submit Documentation Feedback
Copyright © 1992–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC244A
11
SN74LVC244A
SCAS414Z – NOVEMBER 1992 – REVISED JANUARY 2015
www.ti.com
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
12
Submit Documentation Feedback
Copyright © 1992–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC244A
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC244ADBLE
OBSOLETE
SSOP
DB
20
TBD
Call TI
Call TI
-40 to 125
SN74LVC244ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADBRE4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADGVRE4
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADGVRG4
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244ADWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244ADWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244AGQNR
OBSOLETE
BGA
MICROSTAR
JUNIOR
GQN
20
TBD
Call TI
Call TI
-40 to 85
LC244A
SN74LVC244AN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74LVC244AN
SN74LVC244ANE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74LVC244AN
SN74LVC244ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
10-Jun-2014
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC244ANSRE4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC244A
SN74LVC244APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
Call TI
-40 to 125
SN74LVC244APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWRG3
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWTE4
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244APWTG4
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC244A
SN74LVC244ARGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC244A
SN74LVC244ARGYRG4
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC244A
SN74LVC244AZQNR
ACTIVE
BGA
MICROSTAR
JUNIOR
ZQN
20
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
LC244A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC244A :
• Automotive: SN74LVC244A-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Mar-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74LVC244ADBR
SSOP
DB
20
2000
330.0
16.4
SN74LVC244ADGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC244ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LVC244ADWRG4
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LVC244ANSR
SO
NS
20
2000
330.0
24.4
9.0
13.0
2.4
4.0
24.0
Q1
SN74LVC244APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC244APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC244APWRG3
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC244APWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC244ARGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
ZQN
20
1000
330.0
12.4
3.3
4.3
1.6
8.0
12.0
Q1
SN74LVC244AZQNR
BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 1
8.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Mar-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC244ADBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74LVC244ADGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74LVC244ADWR
SOIC
DW
20
2000
364.0
361.0
36.0
SN74LVC244ADWRG4
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LVC244ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LVC244APWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LVC244APWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74LVC244APWRG3
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LVC244APWT
TSSOP
PW
20
250
367.0
367.0
38.0
SN74LVC244ARGYR
VQFN
RGY
20
3000
367.0
367.0
35.0
SN74LVC244AZQNR
BGA MICROSTAR
JUNIOR
ZQN
20
1000
338.1
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated

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