M29F080D
PRELIMINARY DATA
FEATURES SUMMARY
■
SUPPLY VOLTAGE
– V
CC
= 5V ±10% for PROGRAM, ERASE and
READ OPERATIONS
■
ACCESS TIME: 55, 70, 90ns
■
PROGRAMMING TIME
– 10µs per Byte typical
■
16 UNIFORM 64Kbyte MEMORY BLOCKS
■
PROGRAM/ERASE CONTROLLER
– Embedded Byte Program algorithms
■
ERASE SUSPEND and RESUME MODES
– Read and Program another Block during
Erase Suspend
■
UNLOCK BYPASS PROGRAM COMMAND
– Faster Production/Batch Programming
■
TEMPORARY BLOCK UNPROTECTION
MODE
■
COMMON FLASH INTERFACE
– 64 bit Security Code
■
LOW POWER CONSUMPTION
– Standby and Automatic Standby
■
100,000 PROGRAM/ERASE CYCLES per
BLOCK
■
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: F1h
Figure 1. Packages
TSOP40 (N)
10 x 20mm
SO44 (M)
April 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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M29F080D
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
CC
Supply Voltage (5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
V
SS
Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Special Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Protect and Chip Unprotect Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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M29F080D
Table 4. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 13
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 7. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 11. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 12. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Reset/Block Temporary Unprotect AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 22
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline . . . . . . . . . . . . . . . . 23
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data . . . . . . . . 23
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline. . . . . . . . . . . . . . . . 24
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data . . . . . . . . 24
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 14. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 15. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
APPENDIX A. BLOCK ADDRESS TABLE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 16. Block Addresses, M29F080D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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M29F080D
APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 17. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 18. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 19. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 20. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 21. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 22. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
APPENDIX C. BLOCK PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 23. Programmer Technique Bus Operations, BYTE = V
IH
or V
IL
. . . . . . . . . . . . . . . . . . . . . 31
Figure 14. Programmer Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 15. Programmer Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 16. In-System Equipment Group Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
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M29F080D
SUMMARY DESCRIPTION
The M29F080D is a 8 Mbit (1Mb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage 5V supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM.
The memory is divided into 16 uniform blocks of
64Kbytes (see Figure 5, Block Addresses) that can be erased independently so it is possible to preserve valid data while old data is erased.
Blocks can be protected in groups of 4 to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory.
They allow simple connection to most microprocessors, often without additional logic.
The memory is offered in TSOP40 (10 x 20mm) and
SO44 packages. Access times of 55, 70 and 90ns are available. The memory is supplied with all the bits erased (set to ’1’).
Figure 2. Logic Diagram
VCC
A0-A19
20
W
E
G
RP
M29F080D
8
DQ0-DQ7
RB
Table 1. Signal Names
A0-A19 Address Inputs
RP
RB
V
CC
V
SS
NC
DQ0-DQ7
E
G
W
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Supply Voltage
Ground
Not Connected Internally
VSS
AI06141
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M29F080D
Figure 3. TSOP Connections
A14
A13
A12
E
VCC
NC
RP
A19
A18
A17
A16
A15
A11
A10
A9
A8
A7
A6
A5
A4
1
10
11
M29F080D
20
40
31
30
21
NC
NC
W
G
RB
DQ7
DQ6
DQ5
DQ4
VCC
VSS
VSS
DQ3
DQ2
DQ1
DQ0
A0
A1
A2
A3
AI06142
Figure 4. SO Connections
A1
A0
DQ0
DQ1
DQ2
DQ3
VSS
VSS
A6
A5
A4
NC
NC
A3
A2
NC
RP
A11
A10
A9
A8
A7
M29F080D
37
36
35
34
33
32
31
44
43
42
41
40
39
38
26
25
24
23
30
29
28
27
12
13
14
8
9
10
11
6
7
4
5
1
2
3
15
16
17
18
19
20
21
22
W
G
RB
DQ7
DQ6
DQ5
DQ4
VCC
A17
A18
A19
NC
NC
NC
NC
VCC
E
A12
A13
A14
A15
A16
AI06143
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Figure 5. Block Addresses
M29F080D
Block Addresses
0FFFFFh
0F0000h
0EFFFFh
0E0000h
0DFFFFh
0D0000h
0CFFFFh
64 KByte
64 KByte
64 KByte
Total of 16
64 KByte Blocks
02FFFFh
020000h
01FFFFh
010000h
00FFFFh
000000h
64 KByte
64 KByte
64 KByte
Note: Also see Appendix A, Table 16 for a full listing of the Block Addresses.
M29F080D
AI06144
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M29F080D
SIGNAL DESCRIPTIONS
See Figure 2, Logic Diagram, and Table 1, Signal
Names, for a brief overview of the signals connected to this device.
Address Inputs (A0-A19). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the
Command Interface of the internal state machine.
Data Inputs/Outputs (DQ0-DQ7). The Data I/O outputs the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine.
Chip Enable (E). The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is
High, V
IH
, all other pins are ignored.
Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory.
Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.
Reset/Block Temporary Unprotect (RP). The
Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected.
A Hardware Reset is achieved by holding Reset/ t
Block Temporary Unprotect Low, V
IL
PLPX
, for at least
. After Reset/Block Temporary Unprotect goes High, V
IH
, the memory will be ready for Bus
Read and Bus Write operations after t
PHEL
or t
RHEL
, whichever occurs last. See the Ready/Busy
Output section, Table 13 and Figure 13, Reset/
Temporary Unprotect AC Characteristics for more details.
Holding RP at V
ID
will temporarily unprotect the protected Blocks in the memory. Program and
Erase operations on all blocks will be possible.
The transition from V
IH
to V
ID
must be slower than t
PHPHH
.
Ready/Busy Output (RB). The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations
Ready/Busy is Low, V
OL
. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 13 and Figure
13, Reset/Temporary Unprotect AC Characteristics.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy.
V
CC
Supply Voltage (5V). V
CC
provides the power supply for all operations (Read, Program and Erase).
The Command Interface is disabled when the V
CC
Supply Voltage is less than the Lockout Voltage,
V
LKO
. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/
Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid.
A 0.1µF capacitor should be connected between the V
CC
Supply Voltage pin and the V
SS
Ground pin to decouple the current surges from the power supply, see Figure 10, AC Measurement Load Circuit. The PCB track widths must be sufficient to carry the currents required during program and erase operations, I
CC3
.
V
SS
Ground. V
SS
is the reference for all voltage measurements.
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M29F080D
BUS OPERATIONS
There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See
Tables 2, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
Bus Read. Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, V
IL
, to Chip Enable and Output Enable and keeping Write Enable
High, V
IH
. The Data Inputs/Outputs will output the value, see Figure 10, Read Mode AC Waveforms, and Table 10, Read AC Characteristics, for details of when the output becomes valid.
Bus Write. Bus Write operations write to the
Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip
Enable or Write Enable, whichever occurs last.
The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, V
IH
, during the whole Bus
Write operation. See Figures 11 and 12, Write AC
Waveforms, and Tables 11 and 12, Write AC
Characteristics, for details of the timing requirements.
Output Disable. The Data Inputs/Outputs are in the high impedance state when Output Enable is
High, V
IH
.
Standby. When Chip Enable is High, V
IH
, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the
Standby Supply Current, I
CC2
, Chip Enable should
Table 2. Bus Operations
Operation E
Bus Read
Bus Write
Output Disable
Standby
Read Manufacturer
Code
V
IL
V
IL
X
V
IH
V
IL
Read Device Code
Note: X = V
IL
or V
IH
.
V
IL
G
V
IL
V
IH
V
IH
X
V
IL
V
IL
W
V
IH
V
IL
V
IH
X
V
IH
V
IH be held within V
CC
± 0.2V. For the Standby current level see Table 9, DC Characteristics.
During program or erase operations the memory will continue to use the Program/Erase Supply
Current, I
CC3
, for Program or Erase operations until the operation completes.
Automatic Standby. If CMOS levels (V
CC
± 0.2V) are used to drive the bus and the bus is inactive for
300ns or more the memory enters Automatic
Standby where the internal Supply Current is reduced to the Standby Supply Current, I
CC2
. The
Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
Special Bus Operations
Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications.
They require V
ID
to be applied to some pins.
Electronic Signature. The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory.
These codes can be read by applying the signals listed in Tables 2, Bus Operations.
Block Protection and Blocks Unprotection.
Blocks can be protected in groups of 4 against accidental Program or Erase. See Appendix A, Table
16, Block Addresses, for details of which blocks must be protected together as a group. Protected blocks can be unprotected to allow data to be changed.
There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. Block Protect and Chip Unprotect operations are described in Appendix C.
Address Inputs
A0-A19
Cell Address
Command Address
X
X
A0 = V
IL
, A1 = V
IL
, A9 = V
ID
, Others
V
IL
or V
IH
A0 = V
IH
, A1 = V
IL
,
A9 = V
ID
, Others V
IL
or V
IH
Data Inputs/Outputs
DQ7-DQ0
Data Output
Data Input
Hi-Z
Hi-Z
20h
F1h
9/36
M29F080D
COMMAND INTERFACE
All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus
Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security.
Refer to Table 3, Commands, in conjunction with the following text descriptions.
Read/Reset Command. The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status
Register. Either one or three Bus Write operations can be used to issue the Read/Reset command.
The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued while in
Erase Suspend.
Auto Select Command. The Auto Select command is used to read the Manufacturer Code, the
Device Code and the Block Protection Status.
Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/
Reset commands are accepted in Auto Select mode, all other commands are ignored.
From the Auto Select mode the Manufacturer
Code can be read using a Bus Read operation with A0 = V
IL
and A1 = V
IL
. The other address bits may be set to either V
IL
or V
IH
. The Manufacturer
Code for STMicroelectronics is 20h.
The Device Code can be read using a Bus Read operation with A0 = V
IH
and A1 = V
IL
. The other address bits may be set to either V
IL
or V
IH
. The
Device Code for the M29F080D F1h.
The Block Protection Status of each block can be read using a Bus Read operation with A0 = V
A1 = V
IH
IL
,
, and A12-A19 specifying the address of the block. The other address bits may be set to either V
IL
or V
IH
. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-
DQ7, otherwise 00h is output.
Program Command. The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.
If the address falls in a protected block then the
Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 4. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs.
See the section on the Status Register for more details.
After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
Unlock Bypass Command. The Unlock Bypass command is used in conjunction with the Unlock
Bypass Program command to program the memory. When the cycle time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass
Reset command. The memory can be read as if in
Read mode.
Unlock Bypass Program Command. The Unlock Bypass Program command can be used to program one address in the memory array at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass
Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior.
Unlock Bypass Reset Command. The Unlock
Bypass Reset command can be used to return to
Read/Reset mode from Unlock Bypass Mode.
Two Bus Write operations are required to issue the
Unlock Bypass Reset command. Read/Reset
10/36
command does not exit from Unlock Bypass
Mode.
Chip Erase Command. The Chip Erase command can be used to erase the entire chip. Six Bus
Write operations are required to issue the Chip
Erase Command and start the Program/Erase
Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase Suspend command. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 4. All Bus Read operations during the Chip Erase operation will output the Status
Register on the Data Inputs/Outputs. See the section on the Status Register for more details.
After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost.
Block Erase Command. The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected.
The Status Register can be read after the sixth
M29F080D
Bus Write operation. See the Status Register section for details on how to identify if the Program/
Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in
Table 4. All Bus Read operations during the Block
Erase operation will output the Status Register on the Data Inputs/Outputs. See the section on the
Status Register for more details.
After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode.
The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost.
Erase Suspend Command. The Erase Suspend
Command may be used to temporarily suspend a
Block Erase operation and return the memory to
Read mode. The command requires one Bus
Write operation.
The Program/Erase Controller will suspend within
15µs of the Erase Suspend Command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the
Erase is suspended immediately and will start immediately when the Erase Resume Command is issued. It is not possible to select any further blocks to erase after the Erase Resume.
11/36
M29F080D
During Erase Suspend it is possible to Read and
Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register.
It is also possible to issue the Auto Select, Read
CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted.
Erase Resume Command. The Erase Resume command must be used to restart the Program/
Erase Controller after an Erase Suspend. The device must be in Read Array mode before the Resume command will be accepted. An erase can be suspended and resumed more than once.
Read CFI Query Command. The Read CFI
Query Command is used to read data from the
Common Flash Interface (CFI) Memory Area. This command is valid when the device is in the Read
Array mode, or when the device is in Autoselected mode.
One Bus Write cycle is required to issue the Read
CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the Read Array mode or Autoselected mode). A second Read/
Reset command would be needed if the device is to be put in the Read Array mode from Autoselected mode.
See Appendix B, Tables 17, 18, 19, 20, 21 and 22 for details on the information contained in the
Common Flash Interface (CFI) memory area.
Block Protect and Chip Unprotect Com-
mands. Groups of blocks can be protected against accidental Program or Erase. The Protection Groups are shown in Appendix A, Table 16.
The whole chip can be unprotected to allow the data inside the blocks to be changed.
Block Protect and Chip Unprotect operations are described in Appendix C.
12/36
M29F080D
Table 3. Commands
Command
Read/Reset
Auto Select
Program
Unlock Bypass
Unlock Bypass
Program
Unlock Bypass Reset
Chip Erase
Block Erase
Erase Suspend
1
3
3
4
3
2
2
6
6+
1
Addr
1st
Data
X
555
555
555
555
X
X
555
555
X
F0
AA
AA
AA
AA
A0
90
AA
AA
B0
Addr
2AA
2AA
2AA
2AA
PA
X
2AA
2AA
2nd
Data
55
55
55
55
PD
00
55
55
Bus Write Operations
Addr
X
555
555
555
555
555
3rd
Data
F0
90
A0
20
80
80
Addr
PA
555
555
4th
Data
PD
AA
AA
Addr
2AA
2AA
5th
Data
55
55
Addr
555
BA
6th
Data
Erase Resume 1 X 30
Read CFI Query 1 55 98
Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal.
10
30
Table 4. Program, Erase Times and Program, Erase Endurance Cycles
Parameter Min
Typ
(1)
Typical after
100k W/E Cycles
(1)
12 Chip Erase
Block Erase (64 Kbytes)
Program (Byte)
Chip Program (Byte by Byte)
Program/Erase Cycles (per Block)
Note: 1. T
A
= 25°C, V
CC
= 5V.
100,000
12
0.8
10
12
Max
60
6
200
60
Unit
s s
µs s cycles
13/36
M29F080D
STATUS REGISTER
Bus Read operations from any address always read the Status Register during Program and
Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed.
The bits in the Status Register are summarized in
Table 5, Status Register Bits.
Data Polling Bit (DQ7). The Data Polling Bit can be used to identify whether the Program/Erase
Controller has successfully completed its operation or if it has responded to an Erase Suspend.
The Data Polling Bit is output on DQ7 when the
Status Register is read.
During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to
Read mode and Bus Read operations from the address just programmed output DQ7, not its complement.
During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of
DQ7. After successful completion of the Erase operation the memory returns to Read Mode.
In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase
Controller has suspended the Erase operation.
Figure 6, Data Polling Flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased.
Toggle Bit (DQ6). The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read.
During Program and Erase operations the Toggle
Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode.
During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the
Program/Erase Controller has suspended the
Erase operation.
If any attempt is made to erase a protected block, the operation is aborted, no error is signalled and
DQ6 toggles for approximately 100µs. If any attempt is made to program a protected block or a suspended block, the operation is aborted, no error is signalled and DQ6 toggles for approximately
1µs.
Figure 7, Data Toggle Flowchart, gives an example of how to use the Data Toggle Bit.
Error Bit (DQ5). The Error Bit can be used to identify errors detected by the Program/Erase
Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error
Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
Erase Timer Bit (DQ3). The Erase Timer Bit can be used to identify the start of Program/Erase
Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the
Program/Erase Controller starts the Erase Timer
Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The
Erase Timer Bit is output on DQ3 when the Status
Register is read.
Alternative Toggle Bit (DQ2). The Alternative
Toggle Bit can be used to monitor the Program/
Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the
Status Register is read.
During Chip Erase and Block Erase operations the
Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased.
Once the operation completes the memory returns to Read mode.
During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive
Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode.
After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to
’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly.
14/36
M29F080D
Table 5. Status Register Bits
Operation Address
Program
Program During Erase
Suspend
Program Error
Chip Erase
Block Erase before timeout
Any Address
Any Address
Any Address
Any Address
Erasing Block
Non-Erasing Block
Erasing Block
Block Erase
Erase Suspend
Non-Erasing Block
Erasing Block
Non-Erasing Block
Good Block Address
Erase Error
Faulty Block Address
Note: Unspecified data bits should be ignored.
Figure 6. Data Polling Flowchart
DQ7
DQ7
DQ7
DQ7
0
0
0
0
0
1
0
0
DQ6
Toggle
DQ5
0
DQ3
–
Toggle 0 –
Toggle
Toggle
Toggle
Toggle
Toggle
0
0
0
1
0
Toggle
No Toggle
0
0
Data read as normal
1
–
Toggle
Toggle
1
1
1
1
0
0
1
–
1
DQ2
–
–
–
Toggle
Toggle
No Toggle
Toggle
No Toggle
Toggle
No Toggle
Toggle
Figure 7. Data Toggle Flowchart
RB
0
0
0
1
1
0
0
0
0
0
0
0
START
START
READ
DQ5 & DQ6
READ DQ5 & DQ7 at VALID ADDRESS
READ DQ6
DQ7
=
DATA
NO
YES
NO
DQ5
= 1
YES
READ DQ7 at VALID ADDRESS
DQ6
=
TOGGLE
YES
NO
NO
DQ5
= 1
YES
READ DQ6
TWICE
DQ7
=
DATA
NO
YES
FAIL PASS
AI05278
DQ6
=
TOGGLE
YES
NO
FAIL PASS
AI05279
15/36
M29F080D
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality documents.
Table 6. Absolute Maximum Ratings
Symbol Parameter
T
BIAS
Temperature Under Bias
Min
–50
Max
125
T
STG
Storage Temperature
–65 150
V
IO
V
CC
Input or Output Voltage
Supply Voltage
(1)
–0.6
–0.6
V
CC
+ 0.6
6
V
ID
Identification Voltage –0.6
13.5
Note: 1. Minimum Voltage may undershoot to –2V or overshoot to V
CC
+2V during transition for a maximum of 20ns.
V
V
V
Unit
°C
°C
16/36
M29F080D
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived from tests performed under the Measurement
Conditions summarized in Table 7, Operating and
AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 7. Operating and AC Measurement Conditions
M29F080D
Parameter
V
CC
Supply Voltage
Ambient Operating Temperature
Load Capacitance (C
L
)
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
Min
4.5
– 40
30
0 to 3
1.5
Max
5.5
85
10
Min
4.5
– 40
Max
5.5
85
100
0.45 to 2.4
0.8 and 2.0
10
V
°C pF ns
V
V
Figure 8. AC Measurement I/O Waveform Figure 9. AC Measurement Load Circuit
1.3V
High Speed (55ns)
3V
VCC
1N914
1.5V
0V
3.3k
Ω
Standard (70, 90ns)
2.4V
DEVICE
UNDER
TEST
CL
OUT
0.45V
2.0V
0.8V
AI05276
0.1µF
CL includes JIG capacitance
AI05277
Table 8. Device Capacitance
Symbol Parameter
C
IN
Input Capacitance
C
OUT
Output Capacitance
Note: Sampled only, not 100% tested.
Test Condition
V
IN
= 0V
V
OUT
= 0V
Min Max
6
12
Unit
pF pF
17/36
M29F080D
Table 9. DC Characteristics
Symbol Parameter
I
LI
I
LO
I
CC1
I
CC2
Input Leakage Current
Output Leakage Current
Supply Current (Read)
Supply Current (Standby) TTL
I
CC3
Supply Current (Standby) CMOS
I
CC4
(1)
Supply Current (Program/Erase)
V
IL
V
IH
V
OL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
V
OH
Output High Voltage CMOS
V
ID
I
ID
Identification Voltage
Identification Current
V
LKO
(1)
Program/Erase Lockout Supply
Voltage
Note: 1. Sampled only, not 100% tested.
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
E = V
IL
, G = V
IH
, f = 6MHz
E = V
IH
E = V
CC
± 0.2V,
RP = V
CC
±0.2V
Program/Erase
Controller active
I
I
I
OL
OH
OH
= 5.8mA
= –2.5mA
= –100µA
A9 = V
ID
Min
–0.5
2
2.4
V
CC
– 0.4
11.5
3.2
Max
±1
±1
20
2
150
20
0.8
V
CC
+ 0.5
0.45
12.5
100
4.2
mA
V
V
V
V
V
V
µA
V
Unit
µA
µA mA mA
µA
18/36
M29F080D
Figure 10. Read AC Waveforms
A0-A19
E
G tAVQV tELQV tELQX tGLQX tGLQV tAVAV
VALID tAXQX tEHQZ tEHQX
DQ0-DQ7 tGHQX tGHQZ
VALID
AI06145
Table 10. Read AC Characteristics
Symbol Alt Parameter Test Condition
t t
AVAV
AVQV t t
RC
ACC
Address Valid to Next Address Valid
Address Valid to Output Valid
E = V
IL
,
G = V
IL
E = V
IL
,
G = V
IL t
ELQX
(1) t
ELQV t
GLQX
(1) t
GLQV t
EHQZ
(1) t
GHQZ
(1) t t t t t t
LZ
CE
OLZ
OE
HZ
DF
Chip Enable Low to Output Transition
Chip Enable Low to Output Valid
Output Enable Low to Output Transition
Output Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z t
EHQX t
GHQX t
AXQX t
OH
Chip Enable, Output Enable or Address
Transition to Output Transition
Note: 1. Sampled only, not 100% tested.
G = V
G = V
IL
IL
E = V
IL
E = V
IL
G = V
IL
E = V
IL
Min
Max
Min
Min
Max
Min
Max
Max
Max
55
0
55
0
30
18
18
55
M29F080D
70/ 90
55 70
70
0
70
0
30
20
20
0 0
Unit
ns ns ns ns ns ns ns ns ns
19/36
M29F080D
Figure 11. Write AC Waveforms, Write Enable Controlled
A0-A19 tAVAV
VALID tAVWL tWLAX tWHEH
E tELWL tWHGL
G tGHWL tWLWH
W tWHWL tWHDX
DQ0-DQ7 tDVWH
VALID
VCC
RB tVCHEL tWHRL
Table 11. Write AC Characteristics, Write Enable Controlled
Symbol Alt Parameter
t
AVAV t
ELWL t
WLWH t
DVWH t
WHDX t
WHEH t t
WC t
CS t
WP t
DS t
DH
CH
Address Valid to Next Address Valid
Chip Enable Low to Write Enable Low
Write Enable Low to Write Enable High
Input Valid to Write Enable High
Write Enable High to Input Transition
Write Enable High to Chip Enable High t
WHWL t
AVWL t
WLAX t
GHWL t
WHGL t
WPH t t
AS
AH
Write Enable High to Write Enable Low
Address Valid to Write Enable Low
Write Enable Low to Address Transition
Output Enable High to Write Enable Low t
OEH
Write Enable High to Output Enable Low t
WHRL
(1) t
BUSY
Program/Erase Valid to RB Low t
VCHEL t
VCS
V
CC
High to Chip Enable Low
Note: 1. Sampled only, not 100% tested.
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
20/36
20
0
45
0
0
0
0
45
45
55
M29F080D
70/ 90
55
0
70
0
0
0
45
45
20
0
45
0
0
30
50
30
50
AI06146
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
µs
Figure 12. Write AC Waveforms, Chip Enable Controlled
A0-A19 tAVAV
VALID tAVEL
W tWLEL
G tGHEL tELEH
E tELAX tEHWH tEHGL tEHEL tEHDX
DQ0-DQ7 tDVEH
VALID
VCC
RB tVCHWL tEHRL
Table 12. Write AC Characteristics, Chip Enable Controlled
Symbol Alt Parameter
t
AVAV t
WLEL t
ELEH t
DVEH t
EHDX t
EHWH t t
WC t
WS t
CP t
DS t
DH
WH
Address Valid to Next Address Valid
Write Enable Low to Chip Enable Low
Chip Enable Low to Chip Enable High
Input Valid to Chip Enable High
Chip Enable High to Input Transition
Chip Enable High to Write Enable High t
EHEL t
AVEL t
ELAX t
GHEL t
EHGL t t
CPH t
AS
AH
Chip Enable High to Chip Enable Low
Address Valid to Chip Enable Low
Chip Enable Low to Address Transition
Output Enable High Chip Enable Low t
OEH
Chip Enable High to Output Enable Low t
EHRL
(1) t
BUSY
Program/Erase Valid to RB Low t
VCHWL t
VCS
V
CC
High to Write Enable Low
Note: 1. Sampled only, not 100% tested.
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
Max
Min
20
0
45
0
0
0
0
45
45
55
M29F080D
70/ 90
55
0
70
0
0
0
45
45
20
0
45
0
0
30
50
30
50
M29F080D
AI06147
Unit
ns ns ns ns ns ns ns ns ns ns ns ns
µs
21/36
M29F080D
Figure 13. Reset/Block Temporary Unprotect AC Waveforms
W, E, G
RB
RP tPLPX tPHWL, tPHEL, tPHGL tRHWL, tRHEL, tRHGL tPHPHH tPLYH
AI02931B
Table 13. Reset/Block Temporary Unprotect AC Characteristics
Symbol Alt Parameter
t
PHWL
(1) t
PHEL t
PHGL
(1) t
RHWL
(1) t
RHEL
(1) t
RHGL
(1) t
PLPX t
PLYH
(1) t t t t
RH
RB
RP
READY
RP High to Write Enable Low, Chip Enable Low,
Output Enable Low
RB High to Write Enable Low, Chip Enable Low,
Output Enable Low
RP Pulse Width
RP Low to Read Mode t
PHPHH
(1) t
VIDR
RP Rise Time to V
Note: 1. Sampled only, not 100% tested.
ID
Min
Min
Min
Max
Min
0
500
10
500
55
M29F080D
70/ 90
50 50
Unit
ns
0
500
10
500 ns ns
µs ns
22/36
M29F080D
PACKAGE MECHANICAL
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Outline
1 N
A2 e
E
N/2
D1
D
DIE
TSOP-a
C
B
A
CP
A1
α
L
Note: Drawing is not to scale.
TSOP40 – 40 lead Plastic Thin Small Outline, 10 x 20mm, Package Mechanical Data millimeters
Symbol inches
Typ Min Max Typ Min
C
D
D1
A
A1
A2
B
E e
L
α
N
CP
0.500
0.050
0.950
0.170
0.100
19.800
18.300
9.900
–
0.500
0°
40
1.200
0.150
1.050
0.270
0.210
20.200
18.500
10.100
–
0.700
5°
0.100
0.0197
0.0020
0.0374
0.0067
0.0039
0.7795
0.7205
0.3898
–
0.0197
0°
40
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
0.3976
–
0.0276
5°
0.0039
23/36
M29F080D
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Outline
b
D e
N
A2
CP
E EH
1
A
C
A1
α
L
SO-d
Note: Drawing is not to scale.
D e
HE
L
N
α
C
CP
E
A1
A2 b
SO44 – 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data millimeters
Symbol inches
Typ Min Max Typ Min
A 2.80
2.30
0.40
0.15
13.30
28.20
1.27
16.00
0.80
0.10
2.20
0.35
0.10
13.20
28.00
–
15.75
2.40
0.50
0.20
0.08
13.50
28.40
–
16.25
0.0906
0.0157
0.0059
0.5236
1.1102
0.0500
0.6299
0.0315
0.0039
0.0866
0.0138
0.0039
0.5197
1.1024
–
0.6201
44
8
44
Max
0.1102
0.0945
0.0197
0.0079
0.0030
0.5315
1.1181
–
0.6398
8
24/36
M29F080D
PART NUMBERING
Table 14. Ordering Information Scheme
Example:
M29F080D
55 N 1 T
Device Type
M29
Operating Voltage
F = V
CC
= 5V ± 10%
Device Function
080D = 8 Mbit (1Mb x8), Uniform Block
Speed
55 = 55 ns
70 = 70 ns
90 = 90 ns
Package
N = TSOP40: 10 x 20 mm
M = SO44
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you.
REVISION HISTORY
Table 15. Document Revision History
Date
03-Dec-2001
05-Apr-2002
Version
-01
-02
Revision Details
First Issue
Description of Ready/Busy signal clarified (and Figure 13 modified)
Clarified allowable commands during block erase
Clarified the mode the device returns to in the CFI Read Query command section
25/36
M29F080D
APPENDIX A. BLOCK ADDRESS TABLE
Table 16. Block Addresses, M29F080D
#
Size,
KByte
Address Range Protection Group
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
6
5
4
8
7
1
0
3
2
12
11
10
9
15
14
13
0F0000h-0FFFFFh
0E0000h-0EFFFFh
0D0000h-0DFFFFh
0C0000h-0CFFFFh
0B0000h-0BFFFFh
0A0000h-0AFFFFh
090000h-09FFFFh
080000h-08FFFFh
070000h-07FFFFh
060000h-06FFFFh
050000h-05FFFFh
040000h-04FFFFh
030000h-03FFFFh
020000h-02FFFFh
010000h-01FFFFh
000000h-00FFFFh
3
2
1
0
26/36
M29F080D
APPENDIX B. COMMON FLASH INTERFACE (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary.
When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 17, 18, 19, 20, 21 and 22 show the addresses used to retrieve the data.
The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 22, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command to return to Read mode.
Table 17. Query Structure Overview
Address Sub-section Name
10h CFI Query Identification String
1Bh
27h
40h
System Interface Information
Device Geometry Definition
Primary Algorithm-specific Extended Query table
61h Security Code Area
Note: Query data are always presented on the lowest order data outputs.
Description
Command set ID and algorithm data offset
Device timing & voltage information
Flash device layout
Additional information specific to the Primary
Algorithm (optional)
64 bit unique device number
Table 18. CFI Query Identification String
Address Data
10h
11h
51h
52h
Description
Query Unique ASCII String "QRY"
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
59h
02h
00h
40h
00h
00h
00h
00h
00h
Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm
Address for Primary Algorithm extended Query table (see Table 20)
Alternate Vendor Command Set and Control Interface ID Code second vendor
- specified algorithm supported
Address for Alternate Algorithm extended Query table
Value
"Q"
"R"
"Y"
AMD
Compatible
P = 40h
NA
NA
27/36
M29F080D
Table 19. CFI Query System Interface Information
Address Data Description
1Bh
1Ch
45h
55h
V
CC
Logic Supply Minimum Program/Erase voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV
V
CC
Logic Supply Maximum Program/Erase voltage bit 7 to 4 bit 3 to 0
BCD value in volts
BCD value in 100 mV
1Dh
1Eh
1Fh
20h
21h
22h
23h
00h
00h
04h
00h
0Ah
00h
04h
V
PP
[Programming] Supply Minimum Program/Erase voltage
00h not supported
V
PP
[Programming] Supply Maximum Program/Erase voltage
00h not supported
Typical timeout per single byte program = 2 n
µs
Typical timeout for minimum size write buffer program = 2 n
µs
Typical timeout per individual block erase = 2 n
ms
Typical timeout for full chip erase = 2 n
ms
Maximum timeout for byte program = 2 n
times typical
24h
25h
00h
03h
Maximum timeout for write buffer program = 2 n
times typical
Maximum timeout per individual block erase = 2 n
times typical
26h 00h
Maximum timeout for chip erase = 2 n
times typical
Note: 1. Not supported in the CFI
Value
4.5V
5.5V
NA
NA
16µs
NA
1s see note (1)
256µs
NA
8s see note (1)
28/36
M29F080D
Table 20. Device Geometry Definition
Address
27h
Data
14h
Description
Device Size = 2 n
in number of bytes
28h
29h
2Ah
2Bh
00h
00h
00h
00h
Flash Device Interface Code description
Maximum number of bytes in multi-byte program or page = 2 n
2Ch
2Dh
2Eh
2Fh
30h
01h
0Fh
00h
00h
01h
Number of Erase Block Regions within the device.
It specifies the number of regions within the device containing contiguous
Erase Blocks of the same size.
Region 1 Information
Number of identical size erase block = 000Fh+1
Region 1 Information
Block size in Region 1 = 0100h * 256 byte
Value
1 MByte x8 only
Async.
NA
1
16
64 Kbyte
29/36
M29F080D
Table 21. Primary Algorithm-Specific Extended Query Table
Address Data Description
40h
41h
50h
52h Primary Algorithm extended Query table unique ASCII string “PRI”
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
49h
31h
30h
00h
02h
04h
01h
04h
00h
00h
00h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
Block Protection
00 = not supported, x = number of blocks per group
Temporary Block Unprotect
00 = not supported, 01 = supported
Block Protect /Unprotect
04 = M29W400B mode
Simultaneous Operations, 00 = not supported
Burst Mode, 00 = not supported, 01 = supported
Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word
Table 22. Security Code Area
Address
61h
62h
63h
64h
65h
66h
67h
68h
Data
XX
XX
XX
XX
XX
XX
XX
XX
64 bit: unique device number
Description
2
4 yes
4
No
No
No
Value
"P"
"R"
"I"
"1"
"0"
Yes
30/36
M29F080D
APPENDIX C. BLOCK PROTECTION
Block protection can be used to prevent any operation from modifying the data stored in the memory. The blocks are protected in groups, refer to
Appendix A, Table 16 for details of the Protection
Groups. Once protected, Program and Erase operations within the protected group fail to change the data.
There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section.
To protect the Extended Block issue the Enter Extended Block command and then use either the
Programmer or In-System technique. Once protected issue the Exit Extended Block command to return to read mode. The Extended Block protection is irreversible, once protected the protection cannot be undone.
Programmer Technique
The Programmer technique uses high (V
ID
) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment.
To protect a group of blocks follow the flowchart in
Figure 14, Programmer Equipment Block Protect
Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all groups can be unprotected at the same time. To unprotect the chip follow Figure 15, Programmer
Equipment Chip Unprotect Flowchart. Table 23,
Table 23. Programmer Technique Bus Operations, BYTE = V
IH
or V
IL
Operation E G W
Address Inputs
A0-A19
Block (Group)
Protect
(1)
V
IL
V
ID
V
IL
Pulse
A9 = V
ID
, A12-A19 Block Address
Others = X
Chip Unprotect
Block (Group)
Protection Verify
V
V
ID
IL
V
V
ID
IL
V
IL
Pulse
V
IH
A9 = V
ID
, A12 = V
IH
, A15 = V
IH
Others = X
A0 = V
IL
, A1 = V
IH
, A6 = V
IL
, A9 = V
ID
,
A12-A19 Block Address
Others = X
Block (Group)
Unprotection Verify
V
IL
V
IL
V
IH
A0 = V
IL
, A1 = V
IH
, A6 = V
IH
, A9 = V
ID
,
A12-A19 Block Address
Others = X
Note: 1. Block Protection Groups are shown in Appendix A, Table 16.
Programmer Technique Bus Operations, gives a summary of each operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end.
Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
In-System Technique
The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the memory has been fitted to the system.
To protect a group of blocks follow the flowchart in
Figure 16, In-System Block Protect Flowchart. To unprotect the whole chip it is necessary to protect all of the groups first, then all the groups can be unprotected at the same time. To unprotect the chip follow Figure 17, In-System Chip Unprotect
Flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing.
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
X
X
Pass = XX01h
Retry = XX00h
Retry = XX01h
Pass = XX00h
31/36
M29F080D
Figure 14. Programmer Equipment Group Protect Flowchart
START
ADDRESS = GROUP ADDRESS
W = VIH n = 0
G, A9 = VID,
E = VIL
Wait 4µs
W = VIL
Wait 100µs
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
DATA
=
01h
YES
NO
A9 = VIH
E, G = VIH
PASS
++n
= 25
YES
NO
A9 = VIH
E, G = VIH
FAIL
Note: Block Protection Groups are shown in Appendix A, Table 16.
32/36
AI05574
Figure 15. Programmer Equipment Chip Unprotect Flowchart
START
PROTECT ALL GROUPS n = 0
CURRENT GROUP = 0
NO ++n
= 1000
YES
A9 = VIH
E, G = VIH
FAIL
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Wait 4µs
W = VIL
Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1, A6 = VIH
E = VIL
Wait 4µs
G = VIL
Wait 60ns
Read DATA
INCREMENT
CURRENT GROUP
NO
DATA
=
00h
YES
LAST
GROUP
NO
YES
A9 = VIH
E, G = VIH
PASS
AI05575
M29F080D
Note: Block Protection Groups are shown in Appendix A, Table 16.
33/36
M29F080D
Figure 16. In-System Equipment Group Protect Flowchart
START n = 0
RP = VID
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 100µs
WRITE 40h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 4µs
READ DATA
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
DATA
=
01h
YES
NO
RP = VIH
ISSUE READ/RESET
COMMAND
PASS
++n
= 25
YES
RP = VIH
NO
ISSUE READ/RESET
COMMAND
FAIL
Note: Block Protection Groups are shown in Appendix A, Table 16.
34/36
AI05576
M29F080D
Figure 17. In-System Equipment Chip Unprotect Flowchart
NO
++n
= 1000
YES
RP = VIH
ISSUE READ/RESET
COMMAND
FAIL
START
PROTECT ALL GROUPS n = 0
CURRENT GROUP = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
WRITE 40h
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
Wait 4µs
READ DATA
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
NO
DATA
=
00h
YES
INCREMENT
CURRENT GROUP
LAST
GROUP
NO
YES
RP = VIH
ISSUE READ/RESET
COMMAND
PASS
AI05577
Note: Block Protection Groups are shown in Appendix A, Table 16.
35/36
M29F080D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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All other names are the property of their respective owners
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36/36
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