ETHERNET TRANSCEIVERS TLK1211RCP FEATURES

ETHERNET TRANSCEIVERS TLK1211RCP FEATURES

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ETHERNET TRANSCEIVERS

Check for Samples: TLK1211RCP

SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011

1

FEATURES

2

0.6-Gbps to 1.3-Gbps Serializer/Deserializer

Low Power Consumption

<

250 mW (typ) at

1.25 Gbps

Fast Relock Times Less Than 256 ns (Typ)

Suitable for EPON/GEPON Applications

LVPECL Compatible Differential I/O on High

Speed Interface

Single Monolithic PLL Design

Support For 10-Bit Interface or Reduced

Interface 5-Bit DDR (Double Data Rate)

Clocking

Receiver Differential Input Thresholds 200 mV

Minimum

IEEE 802.3 Gigabit Ethernet Compliant

ANSI X3.230-1994 (FC-PH) Fibre Channel

Compliant

Advanced 0.25-

μ

m CMOS Technology

No External Filter Capacitors Required

Comprehensive Suite of Built-In Testability

IEEE 1149.1 JTAG Support

2.5-V Supply Voltage for Lowest Power

Operation

3.3-V Tolerant on LVTTL Inputs

Hot Plug Protection

64-Pin VQFP With Thermally Enhanced

Package ( PowerPAD

)

CPRI Data Rate Compatible (614 Mbps,

1.22 Gbps)

Industrial Temperature Range

Supported:

40

°

C to 85

°

C

TD6

VDD

TD7

TD8

TD9

GND

MODESEL

PRBSEN

GND

TD0

TD1

TD2

VDD

TD3

TD4

TD5

9

10

11

12

6

7

8

4

5

2

3

1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

47

46

45

44

43

42

41

40

39

38

13

14

15

16

17 18 19

37

36

35

34

20 21 22 23 24 25 26 27 28 29 30 31 32

33

RD4

RD5

RD6

VDD

RD7

RD8

RD9

GND

JTDI

SYNC/PASS

GND

RD0

RD1

RD2

VDD

RD3

DESCRIPTION

The TLK1211RCP gigabit ethernet transceiver provides for ultrahigh-speed, full-duplex, point-to-point data transmissions. This device is based on the timing requirements of the 10-bit interface specification by the IEEE

802.3 gigabit ethernet specification and is also compliant with the ANSI X3.230-1994 (FC-PH) fibre channel standard. The device supports data rates from 0.6 Gbps to 1.3 Gbps.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2006 – 2011, Texas Instruments Incorporated

TLK1211RCP

SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

DESCRIPTION CONTINUED

The primary application of the transceiver is to provide building blocks for point-to-point baseband data transmission over controlled impedance media of 50 Ω . The transmission media can be printed-circuit board traces, copper cables, or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The transceiver performs the data serialization, deserialization, and clock extraction functions for a physical layer interface device. The transceiver operates at 1.25 Gbps (typical), providing up to 1 Gbps of data bandwidth over a copper or optical media interface.

The transceiver supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing double data rate (DDR) clocking. In the TBI mode the serializer/deserializer (SERDES) accepts 10-bit wide 8b/10b parallel encoded data bytes. The parallel data bytes are serialized and transmitted differentially at PECL compatible voltage levels. The SERDES extracts clock information from the input serial stream and deserializes the data, outputting a parallel 10-bit data byte.

In the DDR mode the parallel interface accepts 5-bit wide 8b/10b encoded data aligned on both the rising and falling edges of the reference clock. The data is clocked most significant bit first (bits 0 – 4 of the 8b/10b encoded data) on the rising edge of the clock and the least significant bits (bits 5 – 9 of the 8b/10b encoded data) are clocked on the falling edge of the clock.

The transceiver provides a comprehensive series of built-in tests for self-test purposes including loopback and pseudorandom binary sequence (PRBS) generation and verification. An IEEE 1149.1 JTAG port is also supported.

The transceiver is housed in a high-performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the device PowerPAD be soldered to the thermal land on the board.

The transceiver is characterized for operation from – 40 ° C to 85 ° C.

The transceiver uses a 2.5-V supply. The I/O section is 3.3-V compatible. With a 2.5-V supply the chipset is very power-efficient, dissipating less than 250 mW typical power when operating at 1.25 Gbps.

The transceiver is designed to be hot plug capable. A power-on reset causes RBC0, RBC1, the parallel output signal terminals, TXP, and TXN to be held in a high-impedance state.

Differences Between TLK1211RCP and TNETE2201

The TLK1211RCP transceiver is the functional equivalent of the TNETE2201. There are several differences between the devices as noted below. See

Figure 12

in the Application Information section for an example of a typical application circuit.

• The V

CC is 2.5 V for the TLK1211RCP vs 3.3 V for TNETE2201.

• The PLL filter capacitors on terminals 16, 17, 48, and 49 of the TNETE2201 are no longer required. The

TLK1211RCP uses these terminals to provide added test capabilities. The capacitors, if present, do not affect the operation of the device.

• No pulldown resistors are required on the TXP/TXN outputs.

• TLK1211RCP has faster re-lock time compared to the TLK1201A and TNETE2201B.

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SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011

T

A

Table 1. AVAILABLE OPTIONS

(1)

– 40 ° C to 85 ° C

PACKAGE

PLASTIC QUAD FLAT PACK (RCP)

TLK1211RCP

(1) For the most current package and ordering information, see the

Package Option Addendum at the end of this document, or see the

TI website at www.ti.com

.

BLOCK DIAGRAM

PRBSEN

LOOPEN

TD(0-9)

PRBS

Generator

10 Bit

Registers

2:1

MUX

Parallel to

Serial

TXP

TXN

Clock

Phase Generator

REFCLK

MODESEL

ENABLE

TESTEN

RBC1

RBC0

SYNC/PASS

Control

Logic

PRBS

Verification

Interpolator and

Clock Extraction

Clock

2:1

MUX

Clock

RD(0-9)

Serial to Parallel and

Comma Detect

2:1

MUX

Data

RXP

RXN

LOS

SYNCEN

RBCMODE

JTMS

JTRSTN

JTDI

TCK

JTAG

Control

Register

JTDO

I/O DESCRIPTION

Terminal Functions

TERMINAL

NAME NO.

SIGNAL

MODESEL 15

LOS 26

I

P/D

(1)

O

Mode select. This terminal selects between the 10-bit interface and a reduced 5-bit DDR interface. When low, the 10-bit interface (TBI) is selected. When pulled high, the 5-bit DDR mode is selected. The default mode is the TBI.

Loss of signal. Indicates a loss of signal on the high-speed differential inputs RXP and RXN.

If the magnitude of RXP-RXN > 150 mV, then LOS = 1 which is a valid input signal.

If the magnitude of RXP-RXN > 50 mV and < 150 mV, then LOS is undefined.

If the magnitude of RXP-RXN < 50 mV, then LOS = 0 which is a loss of signal.

Note: Above LOS conditions are specified only for Input Common Mode Voltage (RXP+RXN)/2 ≥

1.25V

(1) P/D = Internal pulldown

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Terminal Functions (continued)

TERMINAL

NAME NO.

RBCMODE 32

I/O DESCRIPTION

RBC0

RBC1

RD0 – RD9

REFCLK

RXP

RXN

SYNCEN

SYNC/PASS

TD0 – TD9

TXP

TXN

31

30

45, 44,

43, 41,

40, 39,

38, 36,

35, 34

22

54

52

24

47

2-4, 6-9,

11-13

62

61

www.ti.com

I

P/D

O

O

I

(1)

Receive clock mode select. When RBCMODE and MODESEL are low, half-rate clocks are output on RBC0 and RBC1. When MODESEL is low and RBCMODE is high, a full baud-rate clock is output on RBC0 and RBC1 is held low. When MODESEL is high, RBCMODE is ignored and a full baud-rate clock is output on RBC0 and RBC1 is held low.

Receive byte clock. RBC0 and RBC1 are recovered clocks used for synchronizing the 10-bit output data on RD0 – RD9. The operation of these clocks is dependent upon the receive clock mode selected.

In the half-rate mode, the 10-bit output data words are valid on the rising edges of RBC0 and

RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous detect. The clocks are always expanded during data realignment and never slivered or truncated.

RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.

In the normal rate mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned to the rising edge.

In the DDR mode, only RBC0 is valid and operates at 1/10th the serial data rate. Data is aligned on both the rising and falling edges.

Receive data. When in TBI mode (MODESEL = low), these outputs carry 10-bit parallel data output from the transceiver to the protocol layer. The data is referenced to terminals RBC0 and

RBC1, depending on the receive clock mode selected. RD0 is the first bit received. When in the

DDR mode (MODESEL = high), only RD0 – RD4 are valid. RD5 – RD9 are held low. The 5-bit parallel data is clocked out of the transceiver on the rising edge of RBC0.

Reference clock. REFCLK is an external input clock that synchronizes the receiver and transmitter interface (60 MHz to 130 MHz). The transmitter uses this clock to register the input data (TD0 – TD9) for serialization. In the TBI mode that data is registered on the rising edge of

REFCLK.

In the DDR mode, the data is registered on both the rising and falling edges of REFCLK with the most significant bits aligned on the rising edge of REFCLK.

PECL I Differential input receive. RXP and RXN together are the differential serial input interface from a copper or an optical I/F module.

I

P/U

(2)

Synchronous function enable. When SYNCEN is high, the internal synchronization function is activated. When this function is activated, the transceiver detects the K28.5 comma character

(0011111 negative beginning disparity) in the serial data stream and realigns data on byte boundaries if required. When SYNCEN is low, serial input data is unframed in RD0 – RD9.

O

I

PECL

O

Synchronous detect. The SYNC output is asserted high upon detection of the comma pattern in the serial data path. SYNC pulses are output only when SYNCEN is activated (asserted high). In

PRBS test mode (PRBSEN = high), SYNC/PASS outputs the status of the PRBS test results

(high = pass).

Transmit data. When in the TBI mode (MODESEL = low) these inputs carry 10-bit parallel data output from a protocol device to the transceiver for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit.

When in the DDR mode (MODESEL = high) only TD0 – TD4 are valid. The 5-bit parallel data is clocked into the transceiver on the rising and falling edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit.

Differential output transmit. TXP and TXN are differential serial outputs that interface to a copper or an optical I/F module. TXP and TXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low.

TEST

ENABLE

JTDI

28

48

I

P/U

(2)

When this terminal is low, the device is disabled for Iddq testing. RD0 – RD9, RBCn, TXP, and

TXN are high impedance. The pullup and pulldown resistors on any input are disabled. When

ENABLE is high, the device operates normally.

Test data input. IEEE1149.1 (JTAG)

JTDO

JTMS

JTRSTN

27

55

56

I

P/U

(2)

O

I

P/U

(2)

I

P/U

(2)

Test data output. IEEE1149.1 (JTAG)

Test mode select. IEEE1149.1 (JTAG)

Reset signal. IEEE1149.1 (JTAG)

(2) P/U = Internal pullup

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Terminal Functions (continued)

TERMINAL

NAME NO.

LOOPEN 19

I/O DESCRIPTION

PRBSEN 16

P/D

I

I

P/D

(3)

(3)

Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active.

PRBS enable. When PRBSEN is high, the PRBS generation circuitry is enabled. The PRBS verification circuit in the receive side is also enabled. A PRBS signal can be fed to the receive inputs and checked for errors, that are reported by the SYNC/PASS terminal indicating low.

Test clock. IEEE1149.1 (JTAG)

Manufacturing test terminal

TCK

TESTEN

49

17

I

I

P/D

(3)

POWER

VDD

VDDA

5, 10,

20, 23,

29, 37,

42, 50,

63

53, 57,

59, 60

18 VDDPLL

GROUND

GND

GNDA

GNDPLL

1, 14,

21,25,

33, 46

51, 58

64

(3) P/D = Internal pulldown

Supply

Supply

Supply

Digital logic power. Provides power for all digital circuitry and digital I/O buffers.

Analog power. VDDA provides power for the high-speed analog circuits, receiver, and transmitter

PLL power. Provides power for the PLL circuitry. This terminal requires additional filtering.

Ground Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.

Ground Analog ground. GNDA provides a ground for the high-speed analog circuits RX and TX.

Ground PLL ground. Provides a ground for the PLL circuitry.

DETAILED DESCRIPTION

Data Transmission

This device supports both the defined 10-bit interface (TBI) and a reduced 5-bit interface utilizing DDR clocking.

When MODESEL is low, the TBI mode is selected. When MODESEL is high, the DDR mode is selected.

In the TBI mode, the transmitter portion registers incoming 10-bit wide data words (8b/10b encoded data,

TD0 – TD9) on the rising edge of REFCLK. The REFCLK is also used by the serializer, which multiplies the clock by a factor of 10, providing a signal that is fed to the shift register. The 8b/10b encoded data is transmitted sequentially bits 0 through 9 over the differential high-speed I/O channel.

In the DDR mode, the transmitter accepts 5-bit wide 8b/10b encoded data on pins TD0 – TD4. In this mode, data is aligned to both the rising and falling edges of REFCLK. The data is then formed into a 10-bit wide word and sent to the serializer. The rising edge REFCLK clocks in bits 0 – 4, and the falling edge of REFCLK clocks in bits

5 – 9. Bit 0 is the first bit transmitted.

Transmission Latency

Data transmission latency is defined as the delay from the initial 10-bit word load to the serial transmission of bit

9. The minimum latency in TBI mode is 20 bit times. The maximum latency in TBI mode is 22 bit times. The minimum latency in DDR mode is 30 bit times, and maximum latency in DDR mode is 32 bit times.

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Measured 10-Bits Next 10-Bit Code b7 b8 b9 b0 b1 b2 b3 t d(Tx latency)

TD(0−9)

10-Bit Code

REFCLK

Figure 1. Transmitter Latency Full Rate Mode

Data Reception

The receiver portion deserializes the differential serial data. The serial data is retimed based on an interpolated clock generated from the reference clock. The serial data is then aligned to the 10-bit word boundaries and presented to the protocol controller along with receive byte clocks (RBC0 and RBC1).

Receiver Clock Select Mode

There are two modes of operation for the parallel bus: 1) the 10-bit (TBI) mode and 2) 5-bit (DDR) mode. When in TBI mode, there are two user-selectable clock modes that are controlled by the RBCMODE terminal: 1) full-rate clock on RBC0 and 2) half-rate clocks on RBC0 and RBC1. When in the DDR mode, only a full-rate clock is available on RBC0; see

Table 2 .

Table 2. Mode Selection

MODESEL

0

0

1

1

RBCMODE

0

1

0

1

MODE

TBI half-rate

TBI full-rate

DDR

DDR

RECEIVE BYTE

CLOCK

30 – 65 MHz

60 – 130 MHz

60 – 130 MHz

60 – 130 MHz

In the half-rate mode, two receive byte clocks (RBC0 and RBC1) are 180 degrees out of phase and operate at one-half the data rate. The clocks are generated by dividing down the recovered clock. The received data is output with respect to the two receive byte clocks (RBC0 and RBC1) allowing a protocol device to clock the parallel bytes using the RBC0 and RBC1 rising edges. The outputs to the protocol device, byte 0 of the received data is valid on the rising edge of RBC1. See the timing diagram shown in

Figure 2 .

t d(S)

RBC0 t d(S)

RBC1 t d(H)

SYNC

RD(0-9) t d(H)

K28.5

DXX.X

DXX.X

DXX.X

K28.5

DXX.X

Figure 2. Synchronous Timing Characteristics Waveforms (TBI Half-Rate Mode)

In the normal-rate mode, only RBC0 is used and operates at full data rate (that is, 1.25-Gbps data rate produces a 125-MHz clock). The received data is output with respect to the rising edge of RBC0. RBC1 is low in this mode. See the timing diagram shown in

Figure 3

.

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RBC0 t d(S) t d(H)

SYNC

RD(0-9)

K28.5

DXX.X

DXX.X

DXX.X

K28.5

DXX.X

Figure 3. Synchronous Timing Characteristics Waveforms (TBI Full-Rate Mode)

In the double data rate mode, the receiver presents the data on both the rising and falling edges of RBC0. RBC1 is low impedance. The data is clocked bit 0 first, and aligned to the rising edge of RBC0. See the timing diagram shown in

Figure 4

.

t d(S)

RBC0 t d(H) t d(S) t d(H)

SYNC

RD(0-4)

K28.5

K28.5

Bits 0-4 Bits 5-9

DXX.X

DXX.X

DXX.X

DXX.X

DXX.X

DXX.X

K28.5

K28.5

DXX.X

Figure 4. Synchronous Timing Characteristics Waveforms (DDR Mode)

The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset. The received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, ± 0.02% (200

PPM) for proper operation (see the recommended operating tables).

Receiver Word Alignment

This device uses the IEEE 802.3 gigabit ethernet defined 10-bit K28.5 character (comma character) word alignment scheme. The following sections explain how this scheme works and how it realigns itself.

Comma Character on Expected Boundary

This device provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial input data to the 7-bit synchronization pattern. The K28.5 character is defined by 8-bit/10-bit coding scheme as a pattern consisting of 0011111010 (a negative number beginning with disparity) with the 7 MSBs (0011111), referred to as the comma character. The K28.5 character was implemented specifically for aligning data words.

As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is properly aligned and data realignment is not required.

Figure 2

shows the timing characteristics of RBC0, RBC1, SYNC, and RD0 – RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1.)

Comma Character Not on Expected Boundary

If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in

Figure 5

. The

RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. With this design, the maximum stretch that occurs is 20 bit times. This occurs during a worst case scenario when the K28.5 is aligned to the falling edge of RBC1 instead of the rising edge.

Figure 5

shows the timing characteristics of the data realignment.

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Max Receive

Path Latency

INPUT DATA

31 Bit

Times

K28.5

DXX.X

DXX.X

30 Bit

Times (Max)

K28.5

DXX.X

DXX.X

DXX.X

K28.5

www.ti.com

RBC0

RBC1

RD(0-9)

Worst Case

Misaligned K28.5

DXX.X

DXX.X

K28.5

Corrupt Data

DXX.X

DXX.X

Misalignment Corrected

K28.5

DXX.X

DXX.X

DXX.X

K28.5

SYNC

Figure 5. Word Realignment Timing Characteristics Waveforms

Systems that do not require framed data may disable byte alignment by tying SYNCEN low.

When a SYNC character is detected, the SYNC signal is brought high and is aligned with the K28.5 character.

The duration of the SYNC pulse is equal to the duration of the data when in TBI mode. When in DDR mode the

SYNC pulse is present for the entire RBC0 period.

Data Reception Latency

The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word with RD0 received as first bit. The minimum latency in TBI mode is 18 bit times, and the maximum latency is 24 bit times. The minimum latency in DDR mode is 17 bit times and maximum latency is 23 bit times.

RXP, RXN

10-Bit Code b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 t d(Rx latency)

RD(0−9) 10-Bit Code

RBC0

Figure 6. Receiver Latency - TBI Normal Mode Shown

Loss of Signal Detection

This device has a loss-of-signal (LOS) detection circuit for conditions where the incoming signal no longer has sufficient voltage level to keep the clock recovery circuit in lock. The LOS is intended to be an indication of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of signal coding health. Under a PRBS serial input pattern, LOS is high for signal amplitudes greater than 150 mV. The

LOS is low for all amplitudes below 50 mV. Between 50 mV and 150 mV, LOS is undetermined.

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Testability

The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable function allows for all circuitry to be disabled so that an Iddq test can be performed. The PRBS function also allows for a BIST (built-in self test). The terminal setting, TESTEN high, enables the test mode. The terminal

TESTEN has an internal pulldown resistor, so it defaults to normal operation. The TESTEN is only used for factory testing, and is not intended for end-user control.

Loopback Testing

The transceiver can provide a self-test function by enabling (setting LOOPEN to high level) the internal loopback path. Enabling this function causes serial transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. The external differential output is held in a high-impedance state during the loopback testing.

Enable Function

When held low, ENABLE disables all quiescent power in both the analog and digital circuitry. This allows an ultralow-power idle state when the link is not active.

PRBS Function

This device has a built-in 2

7

– 1 PRBS function. When the PRBSEN control bit is set high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel transmitter input bus. Data from the normal parallel input source is ignored during PRBS test mode. The PRBS pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a bit error rate tester (BERT) or to the receiver of another TLK1211RCP. Since the PRBS is not really random and is really a predetermined sequence of 1s and 0s, the data can be captured and checked for errors by a BERT. This device also has a built-in BERT function on the receiver side that is enabled by PRBSEN. It can receive a PRBS pattern and check for errors, and then reports the errors by forcing the SYNC/PASS terminal low. When PRBS is enabled,

RBCMODE is ignored. MODESEL must be low for the PRBS verifier to function correctly. The PRBS testing supports two modes (normal and latched), which are controlled by the SYNCEN input. When SYNCEN is low, the result of the PRBS bit error rate test is passed to the SYNC/PASS terminal. When SYNCEN is high the result of the PRBS verification is latched on the SYNC/PASS output (that is, a single failure forces SYNC/PASS to remain low).

JTAG

The TLK1211 supports an IEEE1149.1 JTAG function while maintaining compatibility with the industry standard

64 pin QFP package footprint. In this way, the TLK1211 installed on a board layout that was designed for the industry standard footprint such as for the TNETE2201B. (Provided the supply voltage can be programmed from the older 3.3 V to 2.5 V.) The JTAG pins on the TLK1211 are chosen to either be on the ‘ vender-unique ’ pins of the industry standard footprint, or are on pins that were previously power or ground. The TRSTN pin has been placed on pin 56, which is a ground on the industry standard footprint. In this way, a TLK1211 installed onto the older footprint has the JTAG tap controller held in reset, and thus disabled. If the JTAG function is desired, then the 5 JTAG pins TRSTN, TMS, TCK, TDI, and TDO can be used in the usual manner for a JTAG function. If the

JTAG function is not desired, then connecting TRSTN to ground is recommended. TMS and TDI have internal pullup resistors, and can thus be left unconnected if not used. TDO is an output and should be left unconnected if JTAG is not used. TCK does not have an internal pullup, and can be tied to GND or PWR if not used, but with

TRSTN low, this input is not used, and thus can be left unconnected.

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ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

DD

(see

(2)

)

Input voltage range at TTL terminals, V

I

Input voltage range at any other terminal

Storage temperature, T stg

Electrostatic discharge

Characterized free-air operating temperature range

TLK1211RCP

– 0.3 V to 3 V

– 0.5 V to 4 V

– 0.3 V to V

DD

+0.3 V

– 65 ° C to 150 ° C

CDM: 1 kV, HBM:4 kV

– 40 ° C to 85 ° C TLK1211RCP

(1) Stresses beyond those listed under “ absolute maximum ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “ recommended operating conditions ” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

DISSIPATION RATING TABLE

PACKAGE

RCP64

(2)

RCP64

(3)

RCP64

(4)

T

A

≤ 25 ° C

POWER RATING

5.25 W

3.17 W

2.01 W

OPERATING FACTOR

(1)

ABOVE T

A

= 25

°

C

46.58 mW/ ° C

23.70 mW/ ° C

13.19 mW/ ° C

(1) This is the inverse of the traditional junction-to-ambient thermal resistance (R

θ JA

).

(2) 2 oz. Trace and copper pad with solder

(3) 2 oz. Trace and copper pad without solder

(4) Standard JEDEC high-K board

PARAMETER

R

θ JA

Junction-to-free-air thermal resistance

R

θ JC

Junction-to-case-thermal resistance

Table 3. Thermal Characteristics

TEST CONDITION

Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land

Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land

Board-mounted, no air flow, JEDEC test board

Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land

Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land

Board-mounted, no air flow, JEDEC test board

MIN

T

A

= 70 ° C

POWER RATING

2.89 W

1.74 W

1.11 W

TYP MAX UNIT

21.47

42.2

75.83

0.38

0.38

7.8

° C/W

° C/W

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RECOMMENDED OPERATING CONDITIONS

SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011

Supply voltage, V

DD

, V

DD(A)

Total supply current, I

DD

, I

DD(A)

Total power dissipation, P

D

Total shutdown current, I

DD

, I

DD(A)

Startup lock time, PLL

Operating free-air temperature, T

A

Frequency = 1.25 Gbps, PRBS pattern

Frequency = 1.25 Gbps, PRBS pattern

Enable = 0, V

DD(A)

, V

DD

= 2.7 V

V

DD

, V

DD(A)

= 2.5 V, EN ↑ to PLL acquire

TLK1211RCP

REFERENCE CLOCK (REFCLK) TIMING REQUIREMENTS

over recommended operating conditions (unless otherwise noted)

PARAMETER

Frequency

Frequency

Accuracy

Duty cycle

Jitter

Minimum data rate

Maximum data rate

TEST CONDITIONS

TLK1211RCP

Random plus deterministic

MIN

TYP – 0.01%

TYP – 0.01%

100

40%

TTL ELECTRICAL CHARACTERISTICS

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

C

IN over recommended operating conditions (unless otherwise noted)

PARAMETER

High-level output voltage

Low-level output voltage

High-level input voltage

Low-level input voltage

High-level Input current

Low-level Input current

Input capacitance

I

OH

= – 400 μ A

I

OL

= 1 mA

TEST CONDITIONS

V

DD

= 2.3 V, V

IN

= 2 V

V

DD

= 2.3 V, V

IN

= 0.4 V

TYP

60

130

MIN NOM MAX UNIT

2.3

2.5

2.7

V

95

238

113

305 mA mW

-40

1 mA

500

85

μ

° s

C

50%

MAX UNIT

TYP+0.01%

MHz

TYP+0.01%

100 ppm

60%

40 ps

V

DD

MIN TYP MAX UNIT

– 0.2

2.3

GND 0.25

0.5

V

V

1.7

3.6

0.8

V

V

40

– 40

4

μ A

μ A pF

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SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011

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TRANSMITTER/RECEIVER CHARACTERISTICS

V

OD

V

(cm)

PARAMETER

V

OD

= |TxD-TxN|

Transmit common mode voltage range

R t

= 50 Ω

R t

= 50 Ω

TEST CONDITIONS

Receiver input voltage requirement,

V

ID

= |RxP - RxN|

Receiver common mode voltage range, (RxP

+ RxN)/2

I lkg(R)

C

I

Receiver input leakage current

Receiver input capacitance t

(TJ) t

(DJ) t r

, t f

Serial data total jitter (peak-to-peak)

Serial data deterministic jitter (peak-to-peak)

Differential signal rise, fall time (20% to 80%)

Serial data jitter tolerance minimum required eye opening, (per IEEE-802.3 specification at

1.25Gbps and per CPRI 2.0 specification at

614.4Mbps)

Differential output jitter, Random + deterministic, PRBS pattern,

R

ω

= 125 MHz

Differential output jitter, Random + deterministic, PRBS pattern,

R

ω

= 106.25 MHz

Differential output jitter, PRBS pattern,

R

ω

= 125 MHz

R

L

= 50 Ω , C and

Figure 7

L

= 5 pF, See

Figure 8

Differential input jitter, Random + deterministic, R

ω

= 125 MHz

Differential input jitter, Random + .4 UI deterministic, R

ω

= 61.44MHz

Receiver data acquisition lock time from powerup t d(Tx latency)

Data re-lock time from application of valid input data stream

Tx latency

.75 UI jitter closure with random data

@ 1.25 Gbps

.20 UI jitter closure with 01010.. data

@ 1.25Gbps

See

Figure 1

t d(Rx latency)

Rx latency

TBI modes

DDR mode

TBI modes

DDR mode

TBI mode

DDR mode

TBI mode

DDR mode

See

Figure 6

600 – 620 Mbps

600 – 620 Mbps

1228.8 Mbps

1228.8 Mbps

(1) UI = serial bit time

MIN TYP MAX UNIT

(1)

600 800 1100 mV

1000 1250 1400 mV

200

1000 1250 2250

-350

100

0.25

0.34

TX+

80%

50%

20% t f

V

V t r

TX−

80%

50%

20% t r

V

V

VOD t f

80%

20%

0 V

1V

−1V

Figure 7. Differential and Common-Mode Output Voltage Definitions

18

17

19

18

20

30

18

17

2

1600

350

0.24

0.2

0.10

250

500

256

128

21

22

23

23

22

32

24

23 mV mV

μ A pF

UI

UI

UI ps

UI

UI

μ s ns ns

UI

UI

12

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C

L

5 pF

50

50

C

L

5 pF

Figure 8. Transmitter Test Setup

LVTTL OUTPUT SWITCHING CHARACTERISTICS

over recommended operating conditions (unless otherwise noted) t r t f t r(RBC) t f(RBC) t su(D1) t h(D1) t su(D2) t h(D2) t su(D3) t h(D3)

PARAMETER

Clock rise time

Clock fall time

Data rise time

Data fall time

Data setup time (RD0 – RD9), Data valid prior to RBC0 rising

Data hold time (RD0 – RD9), Data valid after RBC0 rising

Data setup time (RD0 – RD4)

Data hold time (RD0 – RD4)

Data setup time (RD0 – RD9)

Data hold time (RD0 – RD9)

TEST CONDITIONS

80% to 20% output voltage, C = 5 pF (see

Figure 9

)

TBI normal mode, (see

Figure 3 )

TBI normal mode, (see

Figure 3 )

DDR mode, R

ω

= 125 MHz, (see

Figure 4 )

DDR mode, R

ω

= 125 MHz, (see

Figure 4 )

TBI half-rate mode, R

ω

= 125 MHz, (see

Figure 2 )

TBI half-rate mode, R

ω

= 125 MHz, (see

Figure 2 )

2

2

0.8

2.5

1.5

MIN TYP

0.3

0.3

0.3

0.3

2.5

MAX UNIT

1.5

1.5

ns

1.5

1.5

ns ns ns ns ns ns ns

CLOCK

1.4 V t r t f

DATA

80%

50%

20% t f

2 V

0.8 V t r

Figure 9. TTL Data I/O Valid Levels for AC Measurement

TRANSMITTER TIMING REQUIREMENTS

over recommended operating conditions (unless otherwise noted) t su(D4) t h(D4) t su(D5) t h(D5) t r

, t f

PARAMETER

Data setup time (TD0 – TD9)

Data hold time (TD0 – TD9)

Data setup time (TD0

TD9)

Data hold time (TD0 – TD9)

TD[0,9] data rise and fall time

TBI modes

DDR modes

See

Figure 9

TEST CONDITIONS MIN TYP MAX UNIT

1.6

ns

0.8

0.7

0.5

ns

2 ns

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SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011

APPLICATION INFORMATION

www.ti.com

8B/10B TRANSMISSION CODE

The PCS maps GMII signals into 10-bit code groups and vice versa, using an 8b/10b block coding scheme. The

PCS uses the transmission code to improve the transmission characteristics of information to be transferred across the link. The encoding defined by the transmission code ensures that sufficient transitions are present in the PHY bit stream to make clock recovery possible in the receiver. Such encoding also greatly increases the likelihood of detecting any single or multiple bit errors that may occur during transmission and reception of information. The 8b/10b transmission code specified for use has a high-transition density, is run length limited, and is dc-balanced. The transition density of the 8b/10b symbols range from 3 to 8 transitions per symbol. The definition of the 8b/10b transmission code is specified in IEEE 802.3 gigabit ethernet and ANSI X3.230-1994

(FC-PH), clause 11.

The 8b/10b transmission code uses letter notation describing the bits of an unencoded information octet. The bit notation of A,B,C,D,E,F,G,H for an unencoded information octet is used in the description of the 8b/10b transmission code-groups, where A is the LSB. Each valid code group has been given a name using the following convention: /Dx.y/ for the 256 valid data code-groups and /Kx.y/ for the special control code-groups, where y is the decimal value of bits EDCBA and x is the decimal value of bits HGF (noted as K < HGF.EDCBA

> ).

Thus, an octet value of FE representing a code-group value of K30.7 would be represented in bit notation as 111

11110.

V

DD

TXP Z

O

RXP

5 k

7.5 k

Z

O

GND

VDD

+

_

Z

O

Z

O

5 k

TXN

Transmitter Media

RXN

7.5 k

GND

Receiver

Figure 10. High-Speed I/O Directly-Coupled Mode

TXP

TXN

Z

O

Z

O

Z

O

Z

O

RXP

V

DD

5 k

7.5 k

GND

VDD

5 k

RXN

7.5 k

GND

Receiver Transmitter Media

Figure 11. High-Speed I/O AC-Coupled Mode

+

_

14

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Host

Protocol

Device

JTAG

Controller

10

10

2

TLK1211RCP

SLLS658D – SEPTEMBER 2006 – REVISED APRIL 2011

2.5 V

5 Ω at 100 MHz

2.5 V

VDD VDDA

GND

GNDA

17

TESTEN

TLK1211

TD0-TD9

22

REFCLK

16

PRBSEN

19

LOOPEN

24

SYNCEN

47

SYNC/PASS

RD0-RD9

18

VDDPLL

GNDPLL

64

TXP

TXN

62

61

RBC0-RBC1

28

ENABLE

26

LOS

32

RBCMODE

15

MODESEL

49

TCK

55

JTMS

48

JTDI

56

JTRSTN

27

JTDO

RXP

RXN

54

R

R

52 t t

0.01 µF

50 Ω

50 Ω

Controlled Impedance

Transmission Line

Controlled Impedance

Transmission Line

Controlled Impedance

Transmission Line

Controlled Impedance

Transmission Line

Figure 12. Typical Application Circuit (AC mode)

DESIGNING WITH PowerPAD

The TLK1211RCP is housed in a high-performance, thermally enhanced, 64-pin VQFP (RCP64) PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the

PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. Therefore, if not implementing PowerPAD PCB features, the use of solder masks (or other assembly techniques) may be required to prevent any inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package. It is strongly recommended that the PowerPAD be soldered to the thermal land. The recommended convention, however, is to not run any etches or signal vias under the device, but to have only a grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the minimum size required for the keepout area for the 64-pin PFP PowerPAD package is 8 mm × 8 mm.

It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the

PowerPAD package. The thermal land varies in size depending on the PowerPAD package being used, the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may or may not contain numerous thermal vias depending on PCB construction.

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Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD

Thermally Enhanced Package Application Report, TI literature number SLMA002 , available via the TI Web pages beginning at URL: http://www.ti.com

.

Figure 13. Example of a Thermal Land

For the TLK1211RCP, this thermal land must be grounded to the low-impedance ground plane of the device.

This improves not only thermal performance but also the electrical grounding of the device. It is also recommended that the device ground terminal landing pads be connected directly to the grounded thermal land.

The land size must be as large as possible without shorting device signal terminals. The thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques.

While the thermal land may be electrically floated and configured to remove heat to an external heat sink, it is recommended that the thermal land be connected to the low-impedance ground plane for the device. More information may be obtained from the TI application note PHY Layout, TI literature number SLLA020 .

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PACKAGE OPTION ADDENDUM

www.ti.com

31-Mar-2011

PACKAGING INFORMATION

Orderable Device

Status

(1) Package Type Package

Drawing

Pins Package Qty

Eco Plan

(2) Lead/

Ball Finish

MSL Peak Temp

(3) Samples

(Requires Login)

TLK1211RCP ACTIVE HVQFP RCP 64 160 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

TLK1211RCPG4 ACTIVE HVQFP RCP 64 160 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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