SERVICE MANUAL

CDX-605

US Model

MICROFILM

Model Name Using Similar Mechanism

CD Drive Mechanism Type

Optical Pick-up Name

CDX-505RF

MG-250C-137

KSS-521A/J2N

System

Frequency response

Wow and flutter

Signal-to-noise ratio

Outputs

Current drain

Operating temperature

Dimensions

Mass

Power requirement

Supplied accessories

SPECIFICATIONS

Compact disc digital audio system

10 – 20,000 Hz

Below the measurable limit

94 dB

BUS control output (8 pins)

Analog audio output (RCA pin)

800 mA (during CD playback)

800 mA (during loading or ejecting a disc)

– 10

°

C to + 55

°

C (14

°

F to 131

°

F)

Approx. 262

×

90

×

181.5 mm

(10 3 /

8

×

3 5 /

8

×

7 1 /

4

in.) (w/h/d) not incl. projecting parts and controls

Approx. 2.1 kg (4 lb 10 oz)

12 V DC car battery

(negative ground)

Disc magazine (1)

Parts for installation and connections

(1 set)

Design and specifications subject to change without notice.

COMPACT DISC CHANGER

7-3.

SCHEMATIC DIAGRAM – RF Section – •

See page 17 for Waveforms.

•

See page 31 for IC Block Diagrams.

(Page 27)

CDX-605

– 21 – – 22 –

CDX-605

7-6.

SCHEMATIC DIAGRAM – MAIN Section (1/2) – •

See page 17 for Waveforms.

•

See page 31 for IC Block Diagrams.

(Page 22)

– 27 – – 28 –

7-7.

SCHEMATIC DIAGRAM – MAIN Section (2/2) – •

See page 17 for Waveforms.

•

See page 31 for IC Block Diagrams.

CDX-605

– 29 – – 30 –

CDX-605

• IC Block Diagrams

IC11 CXA1992BR (RF BOARD)

FE_BIAS

F

E

EI

VEE

TEO

LPFI

40

41

42

43

44

45

46

VEE

TEI 47

ATSC

TZC

48

49

–

+

–

+

ATSC

WINDOW

COMP.

–

+

TZC COMP.

TDFCT 50

VCC

VC 51 –

+

FZC 52

VCC

+

–

FZC COMP.

VEE

39

PD2 IV

AMP

PD1 IV

AMP

38

VCC

37

VEE

APC

36 35

VEE

LASER POWER CONTROL

34 33

–

+

RF SUMMING

AMP

+

–

–

+

–

+

F IV AMP

–

+

E IV AMP

VCC FE AMP

VEE

+

–

+

–

FO. BIAS

WINDOW

COMP.

+

–

+

–

+

–

E-F BALANCE

WINDOW COMP.

+

–

+

–

+

–

TRK. GAIN

WINDOW COMP.

FOK

FOH

FOL

TGH

TGL

BALH

BALL

ATSC

TZC

FZC

DFCT

TM1

DFCT

TG1

FOCUS

TRACKING

PHASE COMPENSATION

PHASE COMPENSATION

–

+

1 2 3

FS4

4 5 6 7

32

VEE

LEVEL S

VEE

VCC

MIRR

FS2

DFCTO

FS1

8

VCC

VEE

31

VCC

VEE

30

IIL DATA REGISTER

INPUT SHIFT REGISTER

ADDRESS DECODER

SENS SELECTOR

OUTPUT DECODER

IFB1-6

BAL1-4

TOG1-4

Charge up

9

FS1-4

VCC

DFCT

IIL

↓

TTL

TG1-2 TM1-7 PS1-4

TG2

10

TM7

29

FSET

11

28

12

27

IIL

↓

TTL

TTL

↓

IIL

ISET

VCC

26

25

24

23

22

21

20

19

18

17

SENS2

SENS1

C. OUT

XRST

DATA

XLT

CLK

LOCK

VCC

ISET

VCC VCC

TM4 TM6

16 SL_O

15 SL_M

TM3

VEE VEE

TM5

+

–

TM2

14 SL_P

13

IC52 BA6287F (RF BOARD)

IC301 BA6287F (MAIN BOARD)

OUT1 1

VM 2

VCC 3

TSD

DRIVER DRIVER

CONTROL LOGIC

POWER

SAVE

FIN 4

8 GND

7 OUT2

6 VREF

5 RIN

IC101 CXD2530Q (MAIN BOARD)

TES7

NC

VSS

XVDD

XTAI

XTAO

XVSS

VSS

NC

TES8

NC

VDD

NC

VSS

VDD

NC 84

85

86

87

88

89

81

82

83

VSS

NC

NC

XRST

96

97

98

99

100

90

91

92

93

94

95

80 79 78 77 76 75 74 73 72

TIMING

LOGIC

EFM

DEMODULATOR

SUB CODE

PROCESSOR

CPU

INTERFACE

71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

ERROR

CORRECTOR

16K RAM

SERVO

AUTO

SEQUENCER

D / A

INTERFACE

DIGITAL OUT

DIGITAL CLV

ASYMMETRY

CORRECTOR

DIGITAL

PLL

OSC

CLOCK

GENERATOR

50

49

LRCK

WDCK

48

47

46

45

44

43

42

41

40

ASYE

ASYO

ASYI

BIAS

RF

AVDD

CLTV

AVSS

FILI

39

38

37

36

FILO

PCO

VCTL

V16M

35

34

33

32

31

VCKI

VPCO1

VPCO2

TES1

TES0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

– 31 – – 32 –

IC102 SM5852FS-E2 (MAIN BOARD)

LRCI

BCKI

DI

1

2

3

INPUT

INTERFACE

SYSTEM

CLOCK

DIGITAL

SIGNAL

PROCESSOR

CLK

VSS

4

5

RSTN 6

TESTN 7

MUTEN 8

SEQUENTIAL

CONTROL

MUTE

CONTROL

OUTPUT

INTERFACE

MODE

CONTROL

16

15

14

13

DB/DS

MOD2

MOD1

OPT

12 VDD

11

10

9

LRCO

BCKO

DOUT

IC204 BA8272F-E2 (MAIN BOARD)

14 13 12 11 10 9 8

1 2 3 4 5 6

RESET

SWITCH

7

IC401 TC9464FN-EL (MAIN BOARD)

24 23 22 21 20 19 18

INTERFACE

CIRCUIT

MICROCOMPUTER

INTERFACE

CIRCUIT

17 16 15 14 13

OSC

DIGITAL FILTER CIRCUIT

ATTENUATOR OPERATIONAL CIRCUIT

DEEMPHASIS FILTER CIRCUIT

D∆ MODULATION CIRCUIT

TEST

CIRCUIT

OUTPUT

CIRCUIT

ANALOG

FILTER

TIMING

GENERATOR

OUTPUT

CIRCUIT

ANALOG

FILTER

1 2 3 4 5 6 7 8 9 10 11 12

– 33 –

7-8.

IC PIN FUNCTION DESCRIPTION

•

MAIN BOARD IC302 CXP84124-078Q (SYSTEM CONTROLLER)

Pin No.

Pin Name I/O

1

2

3

4

LIM.SW

BUSON

EJECT

LOAD1

I

I

I

I

Function

Sled limit in detect switch (SW1) input terminal

“L”: When the optical pick-up is inner position

Bus on/off control signal input from the SONY bus interface (IC204) “H”: bus on

Eject switch (SW303) input terminal “H” active

Save end detect switch (SW12) input terminal

“L”: When completion of the disc chucking operation

5

6

7

8

9

10

11

12

13

14

15 to 23

24

25 to 29

30

39

40

41

42

43

44

45

46, 47

48

49

35

36

37

38

31

32

33

34

LOAD2

A.MUTE

EMPH

CH.R

CH.F

—

ELV.R

ELV.ON

CD RST

CDON

—

AUTO ON/OFF

—

RESET

EHS

H.TEMP

—

MODE1

MODE2

MODE3

—

SCK

SI

EXTAL

XTAL

VSS

TX

TEX

AVSS

AVREF

ATRIBT

MCK

I

O

Chucking end detect switch (SW11) input terminal

“L”: When completion of the disc chucking operation

O Audio line muting on/off control signal output terminal “H”: muting on

O Emphasis mode output to the D/A converter (IC401) “L”: emphasis on

Motor drive signal (save direction) output to the chucking motor drive (IC52)

“H” active *1

O

Motor drive signal (load chucking direction) output to the chucking motor drive (IC52)

“H” active *1

O Not used (open)

O

Motor drive signal (elevator down direction) output to the elevator motor drive (IC301)

“L” active *2

O Mechanism deck section power supply on/off control signal output “H”: power on

O

System reset signal output to the CXA1992AR (IC11), CXD2530Q (IC101) and SM5852FS

(IC102) “L”: reset

O D/A converter and servo section power supply on/off control signal output “H”: power on

O Not used (open)

I

Setting terminal for the automatic adjustment “L”: automatic adjustment, “H”: manual adjustement (solder across the BP302 terminal) Normally: fixed at “L”

O Not used (open)

I

System reset signal input from the reset signal generator (IC202) and SONY bus interface

(IC204) “L”: reset

For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”

Main system clock input terminal (8 MHz) I

O Main system clock output terminal (8 MHz)

— Ground terminal

O Sub system clock output terminal Not used (open)

I Sub system clock input terminal Not used (fixed at “L”)

— Ground terminal (for A/D converter)

I Reference voltage (+5V) input terminal (for A/D converter)

I

I

I

Selection input of the custom file, D-BASS, etc.

Input of signal for the fine adjustment (linear position sensor adjustment; RV301) of elevator position (A/D input)

Elevator height position detect input from the RV302 (elevator height sensor) (A/D input)

I

I

I High temperature sensor input terminal Not used (open)

O Not used (open)

O D-BASS control signal output to the SM5852FS (IC102)

O D-BASS control signal output to the SM5852FS (IC102)

O D-BASS control signal output Not used (open)

O Not used (open)

Serial data transfer clock signal input from the SONY bus interface (IC204)

Serial data input from the SONY bus interface (IC204)

– 34 –

62

63

64

59

60

61

65

66

67

68

69

70

71

72

73

74

75

76

77 to 80

Pin No.

50

51

52

53

54

55

56

57

58

—

MAG.SW

BUCHECK

W.UP

C.OUT

EEDATA

EECLK

EEINIT

—

SINGLE

FOK

GFS

SENS1

VDD

NC (VDD)

CDCLK

CDXLT

CDDATA

—

Pin Name

SO

SQCLK

SUBQ

—

—

MGLK

SCOR

SENS2

PWM

I/O

O

O

I

O

I

I

I

I

O

Function

Serial data output to the SONY bus interface (IC204)

Subcode Q data reading clock signal output to the CXD2530Q (IC101)

Subcode Q data input from the CXD2530Q (IC101)

Not used (open)

Not used (fixed at “H”)

Magazine eject operation completion detect switch (SW301) input terminal

“L”: eject completed

Subcode sync (S0+S1) detection signal input from the CXD2530Q (IC101)

Internal status signal (sense signal) input from the CXA1992AR (IC11)

Motor drive signal (elevator up direction) output to the elevator motor drive (IC301)

“L” active *2

O

I

O

O

I

I

Not used (open)

Magazine in/out detect switch (SW302) input terminal “L”: magazine detected

Battery detection signal input terminal “H”: battery on

I

I

Bus on or eject switch (SW303) input terminal “H”: bus on or eject switch pushing

Track number count signal input from the CXA1992AR (IC11)

I/O Two-way data bus with the EEPROM Not used (open)

Serial clock signal output to the EEPROM Not used (open)

Initialize signal input for the EEPROM “H”: format Fixed at “L” in this set

Not used (open)

I

Setting terminal for the single disc/multiple discs mode

“L”: single mode, “H”: multiple discs mode (fixed at “H”)

O

O

O

O

I

I

Focus OK signal input from the CXA1992AR (IC11) “L”: NG, “H”: OK

Guard frame sync signal input from the CXD2530Q (IC101) “L”: NG, “H”: OK

I Internal status signal (sense signal) input from the CXD2530Q (IC101)

— Power supply terminal (+5V)

— Connected to the power supply (+5V)

Serial data transfer clock signal output to the CXD2530Q (IC101)

Serial data latch pulse signal output to the CXD2530Q (IC101)

Serial data output to the CXD2530Q (IC101)

Not used (open)

*1 chucking motor (M103) control

Mode

STOP

Terminal

CH.F (pin 9)

CH.R (pin 8)

“L”

“L”

LOAD

CHUCKING

“H”

“L”

SAVE

“L”

“H”

BRAKE

“H”

“H”

*2 elevator motor (M104) control

Mode

STOP

Terminal

PWM (pin %•)

ELV.R (pin !¡)

“H”

“H”

ELEVATOR

UP

“L”

“H”

ELEVATOR

DOWN

“H”

“L”

BRAKE

“L”

“L”

– 35 –