MAX16056–MAX16059 125nA Supervisory Circuits with Capacitor- Adjustable Reset and Watchdog Timeouts General Description

MAX16056–MAX16059 125nA Supervisory Circuits with Capacitor- Adjustable Reset and Watchdog Timeouts General Description

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

General Description

The MAX16056–MAX16059 are ultra-low-current 125nA

(typ) microprocessor (µP) supervisory circuits that monitor a single system supply voltage. These devices assert an active-low reset signal whenever the V

CC supply voltage drops below the factory-trimmed reset threshold, manual reset is pulled low, or the watchdog timer runs out (MAX16056/MAX16058). The reset output remains asserted for an adjustable reset timeout period after V

CC rises above the reset threshold. Factorytrimmed reset threshold voltages are offered from

1.575V to 4.625V in approximately 100mV increments

(see Table 1).

These devices feature adjustable reset and watchdog timeout using external capacitors. The MAX16056/

MAX16058 contain a watchdog timer with a watchdog select input (WDS) that multiplies the watchdog timeout period by 128. The MAX16057/MAX16059 do not have the watchdog feature.

The MAX16056–MAX16059 are available in either pushpull or open-drain output-type configurations (see the

Ordering Information). These devices are fully specified over the -40°C to +125°C automotive temperature range.

The MAX16056/MAX16058 are available in the 8-pin

TDFN package, and the MAX16057/MAX16059 are available in the 6-pin TDFN package.

Applications

Portable/Battery-Powered Equipment

PDAs/Cell Phones

MP3 Players/Pagers

Glucose Monitors/Patient Monitors

Metering/HVAC

Typical Operating Circuit appears at end of data sheet.

TOP VIEW

V

CC

8

WDS

7

WDI SRT

6 5

Features

o Ultra-Low 125nA (typ) Supply Current o 1.1V to 5.5V Operating Supply Range o Factory-Set Reset Threshold Options from 1.575V

to 4.625V in Approximately 100mV Increments

o Capacitor-Adjustable Reset Timeout o Capacitor-Adjustable Watchdog Timeout

(MAX16056/MAX16058)

o Watchdog Timer Capacitor Open Detect Function o Optional Watchdog Disable Function

(MAX16056/MAX16058)

o Manual Reset Input o Guaranteed RESET Valid for V

CC

1.1V

o Push-Pull or Open-Drain RESET Output Options o Power-Supply Transient Immunity o Small, 3mm x 3mm TDFN Package

Ordering Information

PART

PIN-

PACKAGE

RESET

OUTPUT

WATCH-

DOG

TIMER

MAX16056ATA_ _+T 8 TDFN-EP*

MAX16057ATT_ _+T 6 TDFN-EP*

Push-Pull

Push-Pull

MAX16058ATA_ _+T 8 TDFN-EP* Open-Drain

MAX16059ATT_ _+T 6 TDFN-EP* Open-Drain

Yes

No

Yes

No

Note: All devices are specified over the -40°C to +125°C operating temperature range.

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

*EP = Exposed pad.

“_ _” represents the two number suffix needed when ordering the reset threshold voltage value (see Table 1).

Standard versions and their package top marks are shown in

Table 3 at the end of data sheet.

Pin Configurations

V

CC

6

N.C.

5

SRT

4

MAX16056

MAX16058

EP

1 2 3

RESET GND SWT

TDFN

4

MR

MAX16057

MAX16059

EP

1 2

RESET GND

TDFN

3

MR

*CONNECT EXPOSED PAD TO GND.

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

19-4686; Rev 2; 4/13

2

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

ABSOLUTE MAXIMUM RATINGS

V

CC to GND ..............................................................-0.3V to +6V

SRT, SWT, WDS, MR, WDI, to GND ...........-0.3V to (V

CC

RESET (Push-Pull) to GND .........................-0.3V to (V

CC

+ 0.3V)

+ 0.3V)

RESET (Open-Drain) to GND ...................................-0.3V to +6V

Input Current (all pins) .................................................... ±20mA

Output Current (RESET) ................................................. ±20mA

Continuous Power Dissipation (T

A

= +70°C)

6-Pin TDFN (derate 23.8mW/°C above +70°C) .........1905mW

8-Pin TDFN (derate 24.4mW/°C above +70°C) .........1951mW

Junction-to-Ambient Thermal Resistance (

θ

JA

) (Note 1)

6-Pin TDFN ...................................................................42°C/W

8-Pin TDFN ...................................................................41°C/W

Junction-to-Case Thermal Resistance (

θ

JC

) (Note 1)

6-Pin TDFN .....................................................................9°C/W

8-Pin TDFN .....................................................................8°C/W

Operating Temperature Range .........................-40°C to +125°C

Storage Temperature Range .............................-65°C to +150°C

Junction Temperature .....................................................+150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to

www.maximintegrated.com/thermal-tutorial

.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(V

CC

= 1.2V to 5.5V, T

A

= T

MIN to T

MAX

, unless otherwise noted. Typical values are at V

CC

= 3.3V, T

A

= +25°C.) (Note 2)

PARAMETER SYMBOL TYP

Supply Voltage

Supply Current

V

CC

I

CC

CONDITIONS

T

A

= 0°C to +125°C

T

A

= -40°C to 0°C

V

CC

= 5.0V, T

A

=

-40°C to +85°C

V

CC

> V

TH

+ 150mV, no load, reset output deasserted (Note 3)

V

CC

= 3.3V, T

A

=

-40°C to +85°C

V

CC

= 1.8V, T

A

=

-40°C to +85°C

V

CC

= 5.0V, T

A

=

-40°C to +125°C

V

CC

= 3.3V, T

A

=

-40°C to +125°C

V

CC

= 1.8V, T

A

=

-40°C to +125°C

V

CC

< V

TH

, no load, reset output asserted

MIN

1.1

1.2

142

132

125

142

132

125

7

MAX

5.5

5.5

210

185

175

430

415

400

V

CC

Reset Threshold

Hysteresis

V

CC

to Reset Delay

Reset Timeout Period

V

TH

V

HYST t

RD t

RP

T

A

= +25°C

V

CC

falling (see Table 1)

T

A

= -40°C to

+125°C

V

CC

rising

V

CC

falling from (V

TH

+ 100mV) to

(V

TH

- 100mV) at 10mV/µs

C

SRT

= 2700pF (Note 4)

V

TH

-

1.5%

V

TH

-

2.5%

10.5

0.5

80

14.18

15

V

TH

+

1.5%

V

TH

+

2.5%

17.0

UNITS

V nA

µA

V

%

µs ms

Maxim Integrated

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

ELECTRICAL CHARACTERISTICS (continued)

(V

CC

= 1.2V to 5.5V, T

A

= T

MIN to T

MAX

, unless otherwise noted. Typical values are at V

CC

= 3.3V, T

A

= +25°C.) (Note 2)

PARAMETER

SRT Ramp Current

SRT Ramp Threshold

Watchdog Timeout Clock Period

SWT Ramp Current

SWT Ramp Threshold

RESET Output Voltage

SYMBOL CONDITIONS

t

I

RAMP1

V

S RT

= 0V to V

R AM P 1

,

V

C C

= 1.6V to 5V

T

A

= -40°C to

+125°C

T

A

= +25°C

V

RAMP1

V

CC

= 1.6V to 5V (V

RAMP

rising)

WDPER

T

A

= +25°C

T

A

= -40°C to +125°C

I

RAMP2

V

S WT

= 0V to V

RAM P 2

V

C C

= 1.6V to 5V

,

T

A

= -40°C to

+125°C

T

A

= +25°C

V

RAMP2

V

CC

= 1.6V to 5V (V

RAMP2

rising)

V

CC

≥ 1.0V, I

SINK

= 50µA

V

OL

V

CC

≥ 2.7V, I

SINK

= 1.2mA

V

CC

≥ 4.5V, I

SINK

= 3.2mA

V

CC

≥ 1.8V,

I

SOURCE

= 200µA

V

OH

MAX16056/MAX16057

V

CC

≥ 2.25V,

I

SOURCE

= 500µA

V

CC

≥ 4.5V,

I

SOURCE

= 800µA

I

LKG

V

CC

> V

TH

, reset not asserted, V

RESET

=

5.5V (MAX16058/MAX16059)

MIN

197

210 270

1.173

1.235

1.297

5

3.5

197

210

0.8 x

V

CC

0.8 x

V

CC

0.8 x

V

CC

TYP

240

240

6.4

6.4

240

240

MAX

282

8

9.5

282

270

1.173

1.235

1.297

0.3

0.3

0.4

RESET Output-Leakage Current,

Open Drain

1.0

V

IH

0.7 x

V

CC

Input-Logic Levels

V

IL

0.3 x

V

CC

MR Minimum Pulse Width

MR Glitch Rejection

MR to RESET Delay

WDI Minimum Pulse Width

Input Leakage Current t t

MPW

MRD

(Note 5)

MR, WDI, WDS is connected to GND or V

CC

1

150

-100

200

250

+100

Note 2: Devices are production tested at T

A

= +25°C. Specifications over temperature limits are guaranteed by design.

Note 3: WDI input period is 1s with t

RISE and t

FALL

< 50ns.

Note 4: Worst case of SRT ramp current and voltage is used to guarantee minimum and maximum limits.

Note 5: Guaranteed by design, not production tested.

UNITS

nA

V ms nA

V

V

µA

V

µs ns ns ns nA

Maxim Integrated

3

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Typical Operating Characteristics

(V

CC

= 2.5V, T

A

= +25°C, unless otherwise noted.)

4

10.0

1.0

T

A

= +125

NC

SUPPLY CURRENT vs. SUPPLY VOLTAGE

V

TH

= 2.23V

T

A

= -40

NC

T

A

= +85

NC

T

A

= +25

NC

0.1

1.0 1.5 2.0 2.5 3.0

3.5 4.0 4.5 5.0

V

CC

(V)

NORMALIZED RESET TIMEOUT PERIOD vs. TEMPERATURE

5.5

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

-40 -25 -10 5 20 35 50 65 80

TEMPERATURE (

NC)

95 110 125

NORMALIZED RESET THRESHOLD

VOLTAGE vs. TEMPERATURE

1.020

1.015

1.010

1.005

1.000

0.995

0.990

0.985

0.980

-40 -25 -10 5 20 35 50 65

TEMPERATURE (

NC)

80 95 110 125

350

300

250

SUPPLY CURRENT vs. TEMPERATURE

RESET IS NOT ASSERTED

V

TH

= 1.575V

V

CC

= 5.5V

V

CC

= 3.3V

200

150

100

50

V

CC

= 2.5V

V

CC

= 1.8V

0

-40 -25 -10 5 20 35 50 65

TEMPERATURE (

NC)

80 95 110 125

NORMALIZED WATCHDOG

TIMEOUT PERIOD vs. TEMPERATURE

1.05

1.04

1.03

1.02

1.01

1.00

0.99

0.98

0.97

0.96

0.95

-40 -25 -10 5 20 35 50 65 80

TEMPERATURE (

NC)

95 110 125

1000

100

10

RESET TIMEOUT PERIOD vs. C

SRT

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

0 50 100 150

C

SRT

(nF)

200 250 300

MAXIMUM V

CC

TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE

RESET OCCURS ABOVE THIS LINE

1

10

V

CC

FALLING FROM V

TH

+ 100mV

100

RESET THRESHOLD OVERDRIVE (mV)

1000

V

CC

TO RESET DELAY vs. TEMPERATURE

120

110

100

V

CC

= V

TH

+ 100mV TO V

TH

- 100mV

90

80

70

60

50

-40 -25 -10 5 20 35 50 65

TEMPERATURE (

NC)

80 95 110 125

Maxim Integrated

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Typical Operating Characteristics (continued)

(V

CC

= 2.5V, T

A

= +25°C, unless otherwise noted.)

0.30

0.25

0.20

0.15

0.10

0.05

RESET OUTPUT-LOW VOLTAGE

V

CC

= 1.8V

vs. SINK CURRENT

V

CC

= 2.5V

V

CC

= 3.3V

0

0 0.5

1.0

1.5

2.0

2.5

3.0

I

SINK

(mA)

3.5

4.0

4.5

5.0

MANUAL RESET DELAY vs. TEMPERATURE

270

268

266

264

262

260

258

256

254

252

250

-40 -25 -10 5 20 35 50 65 80

TEMPERATURE (

NC)

95 110 125

RESET OUTPUT-HIGH VOLTAGE vs. SOURCE CURRENT

0.20

0.15

0.10

0.05

0

0

0.50

0.45

0.40

0.35

0.30

0.25

V

CC

= 1.8V

V

CC

= 2.5V

V

CC

= 3.3V

0.1

0.2 0.3 0.4 0.5

0.6 0.7

I

SOURCE

(mA)

0.8

0.9

1.0

SUPPLY CURRENT vs. WATCHDOG

SWITCHING FREQUENCY

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.01

0.1

1 10 100 1000

WATCHDOG SWITCHING FREQUENCY (kHz)

10,000

MANUAL RESET DELAY

MAX16056 toc13

200ns/div

MR

1V/div

RESET

1V/div

RESET SINK CAPABILITY vs. SUPPLY VOLTAGE

5

4

3

2

1

10

9

8

7

6

0

0

V

RESET

= 0.3V

0.5

1.0

1.5

2.0

2.5

V

CC

(V)

3.0

3.5

4.0

RESET SOURCE CAPABILITY vs. SUPPLY VOLTAGE

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2.0

V

RESET

= 0.8 x V

CC

2.5

3.0

3.5

4.0

V

CC

(V)

4.5

5.0

5.5

_______________________________________________________________________________________________________ 5

5

6

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Pin Description

MAX16056/

MAX16058

PIN

MAX16057/

MAX16059

NAME

1

2

3

1

2

FUNCTION

RESET

GND

SWT

Push-Pull or Open-Drain Reset Output. RESET asserts whenever V

CC

drops below the selected reset threshold voltage (V

TH

) or manual reset is pulled low. RESET remains low for the reset timeout period after all reset conditions are deasserted, and then goes high.

The watchdog timer triggers a reset pulse (t

RP

) whenever a watchdog fault occurs

(MAX16056/MAX16058).

Ground

Watchdog Timeout Input. Connect a capacitor between SWT and GND to set the basic watchdog timeout period (t

WD

). Determine the period by the formula t

WD

= Floor[C

SWT

x

5.15 x 10

6

/6.4ms] x 6.4ms + 3.2ms (Note 6) with t

WD

in seconds and C

SWT

in Farads, or use Table 2. Extend the basic watchdog timeout period by using the WDS input. Connect

SWT to ground to disable the watchdog timer function. The value of the capacitor must be between 2275pF and 0.54µF to have a valid watchdog timeout period.

4

5

6

7

3

4

MR

SRT

WDI

WDS

8 6 V

CC

5

N.C.

EP

Note 6: Floor: take the integral value.

Manual-Reset Input. Drive MR low to manually reset the device. RESET remains asserted for the reset timeout period after MR is released. There is no internal pullup on MR. MR must not be left unconnected. Connect MR to V

CC

if not used.

Reset Timeout Input. Connect a capacitor from SRT to GND to select the reset timeout period. Determine the period as follows: t

RP

= 5.15 x 10

6 x C

SRT

with t

RP

in seconds and

C

SRT

in Farads, or use Table 2. The value of the capacitor must be between 39pF and

4.7µF.

Watchdog Input. A falling transition must occur on WDI within the selected watchdog timeout period or a reset pulse occurs. The watchdog timer clears when a falling transition occurs on WDI or whenever RESET is asserted. Connect SWT to ground to disable the watchdog timer function.

Watchdog Select Input. WDS selects the watchdog timeout mode. Connect WDS to ground to select normal mode. The watchdog timeout period is t

WD

. Connect WDS to V

CC to select extended mode, multiplying the basic timeout period (t

WD

) by a factor of 128. A change in the state of WDS clears the watchdog timer.

Supply Voltage. V

CC

is the power-supply input and the input for fixed threshold V

CC monitor. For noisy systems, bypass V

CC

with a 0.1µF capacitor to GND.

No Connection. Not internally connected.

Exposed Pad. Connect EP to GND or leave unconnected.

Maxim Integrated

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Detailed Description

The MAX16056–MAX16059 are ultra-low-current 125nA

(typ) µP supervisory circuits that monitor a single system supply voltage. These devices assert an active-low reset signal whenever the V

CC supply voltage drops below the factory-trimmed reset threshold, manual reset is pulled low, or the watchdog timer runs out

(MAX16056/MAX16058). The reset output remains asserted for an adjustable reset timeout period after

V

CC rises above the reset threshold. The reset and watchdog delay periods are adjustable using external capacitors.

RESET Output

The MAX16056–MAX16059 µP supervisory circuits assert a reset to prevent code-execution errors during powerup, power-down, and brownout conditions. The reset output is guaranteed to be valid for V

CC down to 1.1V.

When V

CC falls below the reset threshold, the RESET output asserts low. Once V

CC exceeds the reset threshold plus the hysteresis, an internal timer keeps the reset output asserted for the capacitor-adjusted reset timeout period (t

RP

), then after this interval the reset output deasserts (see Figure 1). The reset function features immunity to power-supply voltage transients.

Manual-Reset Input (MR)

Many µP-based products require manual-reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. The MAX16056–

MAX16059 feature an MR input. A logic-low on MR asserts a reset. RESET remains asserted while MR is low and for the timeout period, t

RP

, after MR returns high. Connect MR to V

CC if unused. MR can be driven with CMOS logic levels or with open-drain/collector outputs (with a pullup resistor). Connect a normally open momentary switch from MR to GND and a resistor from

MR to V

CC to implement a manual-reset function; external debounce circuitry is not required. If MR is driven by long cables or the device is used in a noisy environment, connect a 0.1µF capacitor from MR to GND to provide additional noise immunity.

Watchdog Timer

The MAX16056/MAX16058’s watchdog timer circuitry monitors the µP’s activity. If the µP does not toggle

(high-to-low) the watchdog input (WDI) within the capacitor-adjustable watchdog timeout period (t

WD

RESET asserts for the reset timeout period (t

RP

),

). The internal watchdog timer is cleared by: 1) any event that asserts RESET, by 2) a falling transition at WDI (that can detect pulses as short as 150ns) or by 3) a transition (high-to-low or low-to-high) at WDS. While reset is asserted, the watchdog timer remains cleared and does not count. As soon as reset deasserts, the watchdog timer resumes counting.

There are two modes of watchdog operation, normal mode and extended mode. In normal mode (Figure 2), the watchdog timeout period is determined by the value of the capacitor connected between SWT and ground. In extended mode (Figure 3), the watchdog timeout period is multiplied by 128. For example, in extended mode, a 0.33µF capacitor gives a watchdog timeout period of 217s (see Table 2). To disable the watchdog timer function, connect SWT to ground.

When V

CC ramps above V

TH

+ V

HYST

, the value of the external SWT capacitor is sampled after RESET goes high. When sampling is finished, the capacitor value is stored in the device and is used to set watchdog timeout. If RESET goes low before sampling is finished, the device interrupts sampling, and sampling is restarted when RESET goes high again.

If the external SWT capacitor is less than 470pF, the sampling result sets the watchdog timeout to zero. This causes the watchdog to assert RESET continuously after sampling is finished. If a PCB manufacturing defect caused the connection to C

SWT to be broken, the capacitance is very low and RESET is continuously asserted. If the external SWT capacitor is greater than

0.47µF, the sampling result sets the watchdog timeout to be infinite, disabling the watchdog function.

Maxim Integrated

7

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

V

TH

+ V

HYST

V

CC t

RP t

MRD

RESET

MR

Figure 1. RESET Timing Relationship

V

CC

WDI

0V

V

CC

RESET

0V

NORMAL MODE (WDS = GND) t

WD

Figure 2. Watchdog Timing Diagram, Normal Mode, WDS = GND

V

CC

WDI t

WD

x 128

0V

V

CC

RESET

0V

EXTENDED MODE (WDS = V

CC

)

Figure 3. Watchdog Timing Diagram, Extended Mode, WDS = V

CC

8 t

MPW t

RP t

RP t

RP

V

TH t

RD

Maxim Integrated

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Applications Information

Selecting the Reset Timeout Capacitor

The reset timeout period is adjustable to accommodate a variety of µP applications. To adjust the reset timeout period (t

RP

), connect a capacitor (C

SRT

) between SRT and ground. The reset timeout capacitor is calculated as follows:

C

SRT

= t

RP

/(5.15 x 10

6

) with t

RP in seconds and C

SRT in Farads.

C

SRT must be a low-leakage (< 10nA) type capacitor. A ceramic capacitor with low temperature coefficient dielectric (i.e., X7R) is recommended.

Selecting Watchdog Timeout Capacitor

The watchdog timeout period is adjustable to accommodate a variety of µP applications. With this feature, the watchdog timeout can be optimized for software execution. The programmer can determine how often the watchdog timer should be serviced. Adjust the watchdog timeout period (t

WD

) by connecting a capacitor (C

SWT

) between SWT and GND. For normal mode operation, calculate the watchdog timeout as follows: t

WD

= Floor[C

SWT x 5.15 x 10

6

/6.4ms] x 6.4ms + 3.2ms

with t

WD in seconds and C

SWT in Farads.

(Floor: take the integral value) (Figures 2 and 3)

The maximum t

WD is 296s. If the capacitor sets t

WD greater than the 296s, t

WD

= infinite and the watchdog timer is disabled.

C

SWT must be a low-leakage (< 10nA) type capacitor.

A ceramic capacitor with low temperature coefficient dielectric (i.e., X7R) is recommended.

Watchdog Timeout Accuracy

The watchdog timeout period is affected by the SWT ramp current (I

RAMP2

) accuracy, the SWT ramp threshold (V

RAMP2

) and the watchdog timeout clock period

(t

WDPER

). In the equation above, the constant 5.15 x

10

6 is equal to V

RAMP2

/I

RAMP2

, and 6.4ms equals the watchdog timeout clock period. Calculate the timeout accuracy by substituting the minimum, typical, and maximum values into the equation.

For example, if C

SWT

= 100nF. t

WDMIN

= Floor[100 x 10

-9 x 1.173/(282 x 10

3.5ms + 0.5 x 3.2ms = 141.7ms

-9

)/9.5ms] x t

WDNOM

= Floor[100 x 10

-9 x 1.235/(240 x 10 x 6.4ms + 0.5 x 6.4ms = 515.2ms

-9

)/6.4ms] t

WDMAX

= Floor[100 x 10

-9 x 1.297/(197 x 10 x 9.5ms + 0.5 x 9.5ms = 1790.75ms

-9

)/3.5ms]

Transient Immunity

For applications with higher slew rates on V

CC during power-up, additional bypass capacitance may be required.

The MAX16056–MAX16059 are relatively immune to short-duration supply voltage transients, or glitches on

V

CC

. The Maximum V

CC

Transient Duration vs. Reset

Threshold Overdrive graph in the

Typical Operating

Characteristics shows this transient immunity. The area below the curve of the graph is the region where these devices typically do not generate a reset pulse. This graph was generated using a falling pulse applied to

V

CC

, starting 100mV above the actual reset threshold

(V

TH

) and ending below this threshold (reset threshold overdrive). As the magnitude of the transient increases, the maximum allowable pulse width decreases.

Typically, a 100mV V

CC transient duration of 40µs or less does not cause a reset.

Using the MAX16056–MAX16059 for

Reducing System Power Consumption

Using the RESET output to control an external p-channel

MOSFET to control the on-time of a power supply can result in lower system power consumption in systems that can be regularly put to sleep. By tying the WDI input to ground, the RESET output becomes a low-frequency clock output. When RESET is low, the MOSFET is turned on and power is applied to the system. When RESET is high, the MOSFET is turned off and no power is consumed by the system. This effectively reduces the shutdown current of the system to zero (Figure 4).

Maxim Integrated

9

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

BAT

1M

Ω

0.1

μF

MANUAL

POWER-ON

VCC

MR

MAX16056

C

SWT

SWT

C

SRT

SRT GND WDS

RESET

WDI

0.1

μF

V

CC1

μP

V

CC

RESET

V

CC1 t

RP t

WD

Figure 4. Using MAX16056–MAX16059 to Reduce System Power Consumption t

RP

10

Maxim Integrated

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Interfacing to Other Voltages for Logic Compatibility

The open-drain RESET output can be used to interface to a µP with other logic levels. The open-drain output is connected to a voltage from 0V to 5.5V as shown in

Figure 5. Generally, the pullup resistor connected to

RESET connects to the supply voltage that is being monitored at the device’s V

CC input. However, some systems use the open-drain output to level-shift from the supervisor’s monitored supply to another supply voltage. As the supervisor’s V

CC decreases, so does the device’s ability to sink current at RESET.

Ensuring a Valid RESET Down to V

CC

= 0V

(Push-Pull RESET)

When V

CC falls below 1.1V, the current-sinking capability of RESET decreases drastically. The high-impedance CMOS logic inputs connected to RESET can drift to undetermined voltages. This presents no problems in most applications, since most µPs and other circuitry do not operate with V

CC below 1.1V. In those applications where RESET must be valid down to 0, add a pulldown resistor between the MAX16056/MAX16057 push-pull RESET output and GND. The resistor sinks any stray leakage currents, holding RESET low (Figure

6). Choose a pulldown resistor that accommodates leakages, such that RESET is not significantly loaded and is capable of pulling to GND. The external pulldown cannot be used with the open-drain RESET output of the MAX16058/MAX16059.

3.3V

5V

V

CC

MAX16058

MAX16059

RESET

V

CC

100k

Ω

RESET

μP

V

CC

MAX16056

MAX16057

RESET

GND

V

CC

2M

Ω

GND

Figure 5. Interfacing with Other Voltage Levels

GND

Figure 6. Ensuring RESET Valid to VCC = GND

Maxim Integrated

11

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Table 1. Threshold Suffix Guide

SUFFIX

33

32

31

26

25

24

23

30

29

28

27

225

22

42

41

40

39

46

45

44

43

38

37

36

35

34

18

17

16

21

20

19

3.218

3.120

2.998

2.925

2.852

2.730

2.633

2.559

2.438

2.340

2.255

2.180

2.133

2.048

1.950

1.853

1.755

1.623

1.536

MIN

4.509

4.388

4.266

4.193

4.095

3.998

3.900

3.802

3.705

3.608

3.510

3.413

3.315

V

CC

THRESHOLD FALLING (V)

TYP

4.625

4.500

4.375

4.300

4.200

4.100

4.000

3.900

3.800

3.700

3.600

3.500

3.400

3.300

3.200

3.075

3.000

2.925

2.800

2.700

2.625

2.500

2.400

2.313

2.235

2.188

2.100

2.000

1.900

1.800

1.665

1.575

3.383

3.280

3.152

3.075

2.998

2.870

2.768

2.691

2.563

2.460

2.371

2.290

2.243

2.153

2.050

1.948

1.845

1.707

1.614

MAX

4.741

4.613

4.484

4.408

4.305

4.203

4.100

3.998

3.895

3.793

3.690

3.588

3.485

12

Maxim Integrated

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Table 2. Capacitor Selection Guide

CAPACITANCE (pF)

82

100

120

150

39

47

56

68

180

220

270

330

390

470

560

680

820

1000

1200

1500

1800

2200

2700

3300

3900

4700

5600

6800

8200

10,000

12,000

15,000

18,000

t

RP

(ms)

Not recommended

14.18

16.99

20.1

24.21

28.84

35.00

42.23

51.5

61.8

77.25

92.7

t

WD

(ms)

Indeterminate

(0, 9.6, or 16)

16

16

22.4

22.4

28.8

35.2

41.6

54.4

60.8

80

92.8

t

WD

x 128 (ms)

0

(no capacitor is connected)

Indeterminate

(0, 1228.8, or 1636)

1641

1641

2460

2460

3280

4099

4918

6556

7376

9833

11,472

Maxim Integrated

13

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Table 2. Capacitor Selection Guide (continued)

CAPACITANCE (pF)

22,000

27,000

33,000

39,000

47,000

56,000

68,000

82,000

100,000

120,000

150,000

180,000

220,000

270,000

330,000

390,000

470,000

680,000

820,000

1,000,000

1,500,000

2,200,000

3,300,000

4,700,000

772.5

927

1133

1390.5

1699.5

2008.5

2420.5

3502

4223

5150

7725

11,330

16,995

24,205

t

RP

(ms)

113.3

139.05

169.95

200.85

242.05

288.4

350.2

422.3

515

618

t

WD

(ms)

112

137.6

169.6

201.6

240

291.2

348.8

419.2

515.2

617.6

771.2

924.8

1129.6

1392

1699.2

2006.4

2416

Indeterminate

(may be infinite and watchdog is disabled)

Infinite

(watchdog is disabled)

t

WD

x 128 (ms)

13,929

17,206

21,302

25,398

30,313

36,867

44,240

53,251

65,539

78,646

98,307

117,968

144,182

177,769

217,091

256,412

308,841

14

Maxim Integrated

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Table 3. Standard Versions

PART

MAX16056ATA17+

MAX16056ATA23+

MAX16056ATA26+

MAX16056ATA29+

MAX16056ATA31+

MAX16056ATA46+

MAX16057ATT17+

MAX16057ATT23+

MAX16057ATT26+

MAX16057ATT29+

MAX16057ATT31+

MAX16057ATT46+

MAX16058ATA16+

MAX16058ATA22+

MAX16058ATA26+

MAX16058ATA29+

MAX16058ATA31+

MAX16058ATA44+

MAX16059ATT16+

MAX16059ATT22+

MAX16059ATT26+

MAX16059ATT29+

MAX16059ATT31+

MAX16059ATT44+

AUC

AUD

BLF

BLG

BLH

BLI

BLJ

BLK

ATW

ATX

ATY

ATZ

AUA

AUB

TOP MARK

BKZ

BLA

BLB

BLC

BLD

BLE

ATQ

ATR

ATS

ATT

Maxim Integrated

15

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

Typical Operating Circuit

BAT

1M

Ω

0.1

μF

MANUAL

RESET

VCC

MR

MAX16056

C

SWT

SWT

C

SRT

SRT GND WDS

RESET

WDI

VCC

μP

PROCESS: BiCMOS

Chip Information

Package Information

For the latest package outline information and land patterns (footprints), go to

www.maximintegrated.com/packages

. Note that a

“+”, “#”, or “-” in the package code indicates RoHS status only.

Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

8 TDFN-EP

6 TDFN-EP

PACKAGE

CODE

T833-2

T633-2

OUTLINE

NO.

21-0137

21-0137

LAND

PATTERN NO.

90-0059

90-0058

16

Maxim Integrated

2

MAX16056–MAX16059

125nA Supervisory Circuits with Capacitor-

Adjustable Reset and Watchdog Timeouts

REVISION

NUMBER

REVISION

DATE

4/13

DESCRIPTION

Removed Automotive Infotainment from Applications sections

Revision History

PAGES

CHANGED

2, 3, 15

1

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________

17

© 2013 Maxim Integrated Products, Inc.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

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