SP6203/6205 Low Noise, 300mA and 500mA CMOS LDO Regulators FEATURES

SP6203/6205 Low Noise, 300mA and 500mA CMOS LDO Regulators FEATURES
®
SP6203/6205
SP6203/6205
Solved by
TM
Low Noise,
Noise, 300mA
300mAand
and500mA
500mACMOS
CMOSLDO
LDORegulators
Regulators
Low
FEATURES
■ Very Low Dropout Voltage: 0.61 PMOS Pass
Device
■ Accurate Output Voltage: 2% over Temperature
■ Guaranteed 500mA Output Current: SP6205
■ Ultra Low Noise Output: 2µVRMS with 0nF
Bypass
■ Unconditionally Stable with 2.2µF Ceramic
■ Low Quiescent Current: 45µA
■ Very Low Ground Current: 350µA at 500 mA
■ Power-Saving Shutdown Mode: < µA
■ Fast Turn-On and Turn-Off: 60µS
■ Fast Transient Response
■ Current Limit and Thermal Shutdown Protection
■ Very Good Load/Line Regulation: 0.0/0.04%
■ Excellent PSRR: 6dB < kHz
■ Industry Standard SOT-23-5 and Small pin
2X3 DFN Package
■ Fixed Output Voltages: 2.5V, 2.V, 2.V,
2.5V, 3.0V and 3.3V
■ Adjustable Output Available
FIXED
VOUT
BYP
2
GND
3
EN
4
SP6203
SP6205
8 Pin DFN
ADJUSTABLE
VOUT
ADJ NC
NC
6
NC
GND
3
5
VIN
EN
4
2
SP6203
SP6205
8 Pin DFN
VOUT
NC
6
NC
5
VIN
Now Available in Lead Free Packaging
APPLICATIONS
■ Cellular / GSM Phones
■ Laptop / Palmtop Computers
■ Battery-Powered Systems
■ Pagers
■ Medical Devices
■ MP3/CD Players
■ Digital Still Cameras
DESCRIPTION
The SP6203/6205 are ultra low noise CMOS LDOs with very low dropout and ground current. The noise
performance is achieved by means of an external bypass capacitor without sacrificing turn-on and turn-off
speed critical to portable applications. Extremely stable and easy to use, these devices offer excellent PSRR
and Line/Load regulation. Target applications include battery-powered equipment such as portable and
wireless products. Regulators' ground current increases only slightly in dropout. Fast turn-on/turn-off enable
control and an internal 301 pull down on output allows quick discharge of output even under no load
conditions. Both LDOs are protected with current limit and thermal shutdown.
Both LDOs are available in fixed & adjustable output voltage versions and come in an industry standard
SOT-23 5-pin and small 2X3 pin DFN packages. For SC-0 00mA CMOS LDO, SP623 is available.
TYPICAL APPLICATION CIRCUIT
VIN
CIN
2.2µF
EN
Date: 12/14/06
2//05
2
SP6203
SP6205
3
5-Pin
FIXED
VIN
VOUT
5
1
CIN
2.2µF
COUT
2.2µF Ceramic
EN
4
BYP
1
COUT
2.2µF Ceramic
2
SP6203
SP6205
3
5-Pin
ADJUSTABLE
SP6203/SP6205
LowLow
Noise,
300300
andand
500mA
CMOS
LDOLDO
Regulators
SP6203/6205
Noise,
500mA
CMOS
Regulators
VOUT
5
4
ADJ
2006 Sipex Corporation
© Copyright 2005
OPERATING RATINGS
ABSOLUTE MAXIMUM RATINGS
Input Voltage (V IN )...........................................+2.V to +5.5V
Enable Input Voltage (V EN)...........................................0 to 5.5V
Junction Temperature (TJ)...........................................-40°C to +25°C
Thermal Resistance, SOT-23-5 (eJA)...........................................Note Thermal Resistance, SOT-23-6 (eJA)...........................................Note Supply Input Voltage (VIN)..........................................................-2V to 6V
Output Voltage (VOUT).....................................................-0.6V to VIN +V
Enable Input Voltage (VEN)........................................................-2V to 6V
Power Dissipation (PD)......................................Internally Limited, Note Lead Temperature (soldering 5s)...........................................+260°C
Storage Temperature.....................................................-65°C to +50°C
Junction Temperature..........................................................+50°C
Remark: The device is not guaranteed to function outside its operating rating.
These are stress ratings only and functional operation of the device at these
ratings or any other above those indicated in the operation sections of the
specifications below is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
ELECTRICAL SPECIFICATIONS
Unless otherwise specified: VIN=VOUT + 0.5V to 6V, COUT = 2.2µF ceramic, CIN = 2.2µF, IOUT =00µA,
-40°C < T < 25°C. The z denotes the specifications which apply over full operating temperature range -40°C to
+25°C, unless otherwise specified.
PARAMETER
Input Voltage
Output Voltage Accuracy
Output Voltage
Temperature Coefficient, Note2
Reference Voltage
Line Regulation
Load Regulation, Note 3
MIN
-2
.225
Ground Pin Current, Note 5
0.33
0.55
Thermal Shutdown Junction
Temperature
Thermal Shutdown Hysteresis
Power Supply Rejection Ratio
Output Noise Voltage, Note 6
Date: 12/14/06
Date: 2//05
UNITS
V
%
ppm/°C
z
z
z
CONDITIONS
.25
0.04
0.0
0.3
0.06
60
20
0
300
45
0
5
235
350
0.0
0.50
0.5
0
.25
0.3
0.3
0.5
V
%/V
%
z
Adjustable version only
6VOUT (VIN below 6V)
IOUT = 0.mA to 300mA (SP6203)
IOUT = 0.mA to 500mA (SP6205)
IOUT = 0.mA
IOUT = 00mA
IOUT = 200mA
IOUT = 300mA (SP6203)
IOUT = 500mA (SP6205)
IOUT = 0.mA (IQUIESCENT)
IOUT = 00mA
IOUT = 200mA
IOUT = 300mA (SP6203)
IOUT = 500mA (SP6205)
VEN < 0.4V (shutdown)
VOUT = ZeroV (SP6203)
VOUT = ZeroV (SP6205)
Regulator Turns off
300
500
00
330
40
0.
.4
mV
µA
µA
A
z
z
z
z
z
z
°C
2
6
50
630
2
50
0.05
25
Thermal Regulation, Note Wake-Up Time (TWU), Note (from shutdown mode)
Turn-On Time (TON), Note (from shutdown mode)
Turn-Off Time (TOFF),
Output Discharge Resistance
Enable Input Logic Low Voltage
Enable Input Logic High Voltage
MAX
6
+2
50
Dropout Voltage for VOUT > 3.0V,
Note 4
Shutdown Supply Current
Current Limit
TYP
°C
dB
5
µVRMS
50
%/W
µs
60
20
µs
00
5
30
250
25
µs
0.4
1
V
V
.6
z
z
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators
2
Variation from specified VOUT
6VOUT/6T
Regulator turns on again at 5°C
f ) kHz
CBYP = 0nF, IOUT = 0.mA
CBYP = 0nF, IOUT =300mA
CBYP = 0nF, IOUT = 0.mA
CBYP = 0nF, IOUT = 300mA
6VOUT/6PD
VIN * 4V, Note 0
IOUT = 30mA
VIN * 4V, Note 0
IOUT = 30mA
IOUT = 0.mA, VIN * 4V, Note 0
IOUT = 300mA, VIN * 4V, Note 0
No Load
Regulator Shutdown
Regulator Enabled
© Copyright 2006 Sipex Corporation
© Copyright 2005 Sipex Corporation
ELECTRICAL SPECIFICATIONS NOTES
Note 1: Maximum power dissipation can be calculated using the formula: PD = (TJ(max) - TA) / eJA, where TJ(max) is
the junction temperature, TA is the ambient temperature and eJA is the junction-to-ambient thermal resistance. eJC
is 6°C/W for this package. Exceeding the maximum allowable power dissipation will result in excessive die
temperature and the regulator will go into thermal shutdown mode. eJA is 191°C/W for SOT-23-5, and is 59°C/W
for the -pin DFN. A part mounted on a PC board will deliver improved thermal performance based upon copper
surface area.
Note 2: Output voltage temperature coefficient is defined as the worst case voltage change divided by the total
temperature range.
Note 3: Regulation is measured at constant junction temperature using low duty cycle pulse testing. Changes in
output voltage due to heating effects are covered by the thermal regulation specification.
Note 4: Dropout-voltage is defined as the input to output differential at which the output voltage drops 2% below its
nominal value measured at V differential.
Note 5: Ground pin current is the regulator quiescent current. The total current drawn from the supply is the sum of
the load current plus the ground pin current.
Note 6: Output noise voltage is defined within a certain bandwidth, namely 0Hz < BW < 00kHz. An external
bypass cap (0nF) from reference output (BYP pin) to ground significantly reduces noise at output.
Note 7: Thermal regulation is defined as the change in output voltage at a time “t” after a change in power
dissipation is applied, excluding load and line regulation effects. Specifications are for a 300mA load pulse at VIN =
6V for t = ms.
Note 8: The wake-up time (TWU) is defined as the time it takes for the output to start rising after enable is brought
high.
Note 9: The total turn-on time is called the settling time (TS), which is defined as the condition when both the
output and the bypass node are within 2% of their fully enabled values when released from shutdown.
Note 10: For output voltage versions requiring VIN to be lower than 4V, timing (TON & TOFF) increases slightly.
FUNCTIONAL DIAGRAM
VOUT
VIN
VOUT
VIN
EN
EN
bandgap .25V
reference
bandgap .25V
reference
R
BYP
current limit
&
thermal shutdown
ADJ
current limit
&
thermal shutdown
Cbyp
(optional)
GND
GND
Low Noise Fixed Regulator - 5 Pin
Date: 12/14/06
Date: 2//05
R2
Low Noise Adjustable Regulator - 5 Pin
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators
3
© Copyright 2006 Sipex Corporation
© Copyright 2005 Sipex Corporation
PIN DESCRIPTION
5 PIN OPTION
PIN NUMBER
NAME
FUNCTION
VIN
2
GND
3
EN
Enable/Shutdown (Logic high = enable, logic
low = shutdown)
4 (Fixed)
BYP
Reference bypass input for ultra-quiet operation.
Connecting a 0nF cap on this pin reduces
output noise.
4 (adj.)
ADJ
Adjustable (Input): Adjustable regulator feedback input. Connect to a resistive voltagedivider network.
5
VOUT
Regulator Output Voltage
Power Supply Input
Ground Terminal
PINOUT 5 PIN SOT-23
EN GND VIN
2
1
3
EN GND VIN
3
2
1
SIPEX
SIPEX
4
5
4
5
BYP
VOUT
ADJ
VOUT
Fixed Voltage Regulator
Date:
Date: 12/14/06
2//05
Adjustable Voltage Regulator
SP6203/SP6205
Low Low
Noise,
300 300
and and
500mA
CMOS
LDOLDO
Regulators
SP6203/6205
Noise,
500mA
CMOS
Regulators
4
©
© Copyright
Copyright 2006
2005 Sipex
Sipex Corporation
Corporation
PIN DESCRIPTION
8 PIN OPTION
PIN DFN
PIN NUMBER
PIN CONFIGURATION
NAME
FUNCTION
(fixed)
VOUT
Regulator Output Voltage. Connect to Pin VOUT.
(Adj)
ADJ
Adjustable (Input): Adjustable regulator feedback input. Connect to a resistive voltagedivider network.
2(fixed)
BYP
Reference bypass input for ultra-quiet operation.
Connecting a 0nF cap on this pin reduces
output noise.
2(Adj)
NC
No Connect
3
GND
4
EN
Enable/Shutdown (Logic high = enable, logic
low = shutdown)
5
VIN
Power Supply Input
6
NC
No Connect
NC
No Connect
VOUT
Ground
Regulator Output VoltageA
PINOUT 8 PIN DFN
FIXED
VOUT
BYP
2
GND
3
EN
4
Date: 2//05
Date: 12/14/06
SP6203
SP6205
8 Pin DFN
ADJUSTABLE
VOUT
ADJ NC
NC
2
6
NC
GND
3
5
VIN
EN
4
SP6203
SP6205
8 Pin DFN
SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
5
VOUT
NC
6
NC
5
VIN
© Copyright 2005 Sipex Corporation
© Copyright 2006 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS
VOUT
VOUT
IO (200mA/DIV)
VEN
Current Limit
Turn on Time, RLOAD = 501 (60mA)
VOUT
VOUT
VEN
VEN
Turn off Time, RLOAD = 30K (0.1mA)
Turn off Time, RLOAD = 61 (500mA)
VOUT (AC)
VOUT (AC)
VIN
IOUT
Load Regulation, IO = 100µA ~ 500mA
Date: 12/14/06
2//05
Line Regulation, Line Step from 4V to 6V, IO = 1mA
SP6203/6205
Noise,
500mA
CMOS
Regulators
SP6203/SP6205
LowLow
Noise,
300 300
and and
500mA
CMOS
LDOLDO
Regulators
6
© Copyright 2005
2006 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS: Continued
VIN
VEN
VOUT
VOUT
VIN = 3.5V, IO = 500mA
BYP
Start Up Waveform, VIN = 3.5V, IO = 500mA
Start Up Waveform, Slow VIN , No Load
VIN
VIN
VOUT
VOUT
BYP
BYP
Start Up Waveform, Slow VIN , 500mA Output Load
Start Up Waveform, Slow VIN , COUT=1000µF, IO=0mA
VIN
VIN
VOUT
VOUT
BYP
BYP
Start Up Waveform, Slow VIN, COUT=1000µF, IO=500mA
Date: 12/14/06
2//05
Fast VIN , No Load
SP6203/6205
Noise,
500mA
CMOS
Regulators
SP6203/SP6205
LowLow
Noise,
300 300
and and
500mA
CMOS
LDOLDO
Regulators
© Copyright 2005
2006 Sipex Corporation
TYPICAL PERFORMANCE CHARACTERISTICS: Continued
VIN
VOUT
BYP
Fast VIN , 500mA Output Load
Fast VIN = 1000µF Output Load
VIN
VOUT
BYP
Fast VIN , COUT=1000µF, IO=500mA
Output Noise (uVrms), Cbyp = 10nF
Output Noise (uVrms), Cbyp = open
000
Noise (uVrms)
Noise (uVrms)
50
40
30
20
0
00
600
400
200
0
0
0.
0
00
0.
000
0
00
000
Output current (mA)
Output current (mA)
Date:
2//05
Date: 12/14/06
SP6203/6205
Noise,
500mA
CMOS
Regulators
SP6203/SP6205
LowLow
Noise,
300300
andand
500mA
CMOS
LDOLDO
Regulators
©©Copyright
Copyright2005
2006Sipex
SipexCorporation
Corporation
THEORY OF OPERATION
General Overview
Output Capacitor
The SP6203/6205 is intended for applications
where very low dropout voltage, low supply
current and low output noise are critical, even
with high load conditions (500mA maximum).
Unlike bipolar regulators, the SP6203/6205
(CMOS LDO) supply current increases only
slightly with load current.
The SP6203/6205 contains an internal bandgap
reference which is fed into the inverting input of
the LDO-amplifier. The output voltage is then
set by means of a resistor divider and compared
to the bandgap reference voltage. The error
LDO-amplifier drives the gate of a P-channel
MOSFET pass device that has a RDS(ON) of 0.61
at 500mA producing a 300mV drop at the output.
Furthermore, the SP6203/6205 has its own current limit circuitry (500mA/850mA) to ensure
that the output current will not damage the
device during output short, overload or start-up.
Also, the SP6203/6205 includes thermal shutdown circuitry to turn off the device when the
junction temperature exceeds 170°C and it remains off until the temperature drops by 12°C.
An output capacitor is required between VOUT
and GND to prevent oscillation. A 2.2µF output
capacitor is recommended.
Larger values make the chip more stable which
means an improvement of the regulator’s transient response. Also, when operating from other
sources than batteries, supply-noise rejection
can be improved by increasing the value of the
input and output capacitors and using passive
filtering techniques.
For a lower output current, a smaller output
capacitance can be chosen.
Finally, the output capacitor should have an
effective series resistance (ESR) of 0.51 or less.
Therefore, the use of good quality ceramic or
tantalum capacitors is advised.
Bypass Capacitor
A bypass pin (BYP) is provided to decouple the
bandgap reference. A 10nF external capacitor
connected from BYP to GND reduces noise
present on the internal reference, which in turn
significantly reduces output noise and also improves power supply rejection. Note that the
minimum value of COUT must be increased to
maintain stability when the bypass capacitor is
used because CBYP reduces the regulator phase
margin. If output noise is not a concern, this
input may be left unconnected. Larger capacitor
values may be used to further improve power
supply rejection, but result in a longer time
period (slower turn on) to settle output voltage
when power is initially applied.
Enable/Shutdown Operation
The SP6203/6205 is turned off by pulling the
VEN pin below 0.4V and turned on by pulling it
above 1.6V.
If this enable/shutdown feature is not required,
it should be tied directly to the input supply
voltage to keep the regulator output on at all
time.
While in shutdown, VOUT quickly falls to zero
(turn-off time is dependent on load conditions
and output capacitance on VOUT) and power
consumption drops nearly to zero.
No Load Stability
The SP6203/6205 will remain stable and in
regulation with no external load (other than the
internal voltage driver) unlike many other voltage regulators. This is especially important in
CMOS RAM battery back-up applications.
Input Capacitor
A small capacitor of 2.2µF is required from VIN
to GND if a battery is used as the power
source. Any good quality electrolytic, ceramic
or tantalum capacitor may be used at the input.
Date:
Date:12/14/06
2//05
SP6203/SP6205
Low Low
Noise,
300 and
CMOS
LDO LDO
Regulators
SP6203/6205
Noise,
300 500mA
and 500mA
CMOS
Regulators
©©Copyright
Copyright2006
2005Sipex
SipexCorporation
Corporation
THEORY OF OPERATION: Continued
TJ(max) is the maximum junction temperature of
the die and is 125°C. TA is the ambient temperature. eJA is the junction-to-ambient thermal resistance for the regulator and is layout dependent. The SOT-23-5 package has a eJA of
approximately 256°C/W for minimum PCB
copper footprint area.
This results in a maximum power dissipation of:
PD(max) = [(125°C - 25°C)/(191°C/W)] = 523mW
Turn On Time
The turn on response is split up in two separate
response categories: the wake up time (TWU)
and the settlling time (TS). The wake up time is
defined as the time it takes for the output to rise
to 2% of its total value after being released from
shutdown (EN > 0.4V). The settling time is
defined as the condition where the output reaches
98% of its total value after being released from
shutdown. The latter is also called the turn on
time and is dependent on the output capacitor, a
little bit on load and, if present, on a bypass
capacitor.
The actual power dissipation of the regulator
circuit can be determined using one simple
equation:
PD = (VIN - VOUT) * IOUT + VIN * IGND
t(s) = T(on)
VENABLE
To prevent the device from entering thermal
shutdown. maximum power dissipation can not
be exceeded.
Substituting PD(max) for PD and solving for the
operating conditions that are critical to the application will give the maximum operating conditions for the regulator circuit. For example, if
we are operating the SP6203 3.0V at room
temperature, with a minimum footprint layout
and and output current of 300mA, the maximum
input voltage can be determined, based on the
equation below. Ground pin current can be taken
from the electrical specifications table (0.23mA
at 300mA).
390mW = (VIN-3.0V) * 300mA + VIN *0.23mA
%
2%
VOUT
t(wu)
Turn Off Time
The turn off time is defined as the condition
where the output voltage drops about 66% (e) of
its total value. 5e to 7e is the constant where the
output voltage drops nearly to zero. There will
always be a small voltage drop in shutdown
because of the switch unless we short-circuit it.
The turn off time of the output voltage is dependent on load conditions, output capacitance on
VOUT (time constant o = RLCL) and also on the
difference in voltage between input and output.
After calculations, we find that the maximum
input voltage of a 3.0V application at 300mA of
output current in a SOT-23-5 package is 4.7V.
Thermal Considerations
The SP6203/6205 is designed to provide 300/
500 mA of continuous current in a tiny package.
Maximum power dissipation can be calculated
based on the output current and the voltage drop
across the part. To determine the maximum
power dissipation of the package, use the junction-to-ambient thermal resistance of the device
and the following basic equation:
So if the intend is to operate a 5V output version
from a 6V supply at 300mA load and at a 25°C
ambient temperature, then the actual total power
dissipation will be:
PD=([6V-5V]*[300mA])+(6V*0.23mA)=301.4mW
This is well below the 523mW package maximum. Therefore, the regulator can be used.
PD = (TJ(max) - TA) / eJA
Date:
Date: 12/14/06
2//05
SP6203/SP6205
Low Low
Noise,
300 300
and and
500mA
CMOS
LDOLDO
Regulators
SP6203/6205
Noise,
500mA
CMOS
Regulators
10
0
©
© Copyright
Copyright 2006
2005 Sipex
Sipex Corporation
Corporation
THEORY OF OPERATION: Continued
Note that the regulator cannot always be used at
its maximum current rating. For example, in a
5V input to 3.0V output application at an ambient temperature of 25°C and operating at the full
500mA (IGND = 0.355mA) load, the regulator is
limited to a much lower load current, determined by the following equation:
Layout Considerations
The primary path of heat conduction out of the
package is via the package leads. Therefore,
careful considerations have to be taken into
account:
1) Attaching the part to a larger copper footprint
will enable better heat transfer from the device,
especially on PCB’s where there are internal
ground and power planes.
523mW = ( [5V-3V]*[ Iload(max)]) +(5V*0.350mA)
After calculation, we find that in such an application (SP6205) the regulator is limited to
260.6mA. Doing the same calculations for the
300mA LDO (SP6203) will limit the regulator’s
output current to 260.9mA.
2) Place the input, output and bypass capacitors
close to the device for optimal transient response and device behavior.
3) Connect all ground connections directly to
the ground plane. In case there’s no ground
plane, connect to a common local ground point
before connecting to board ground.
Also, taking advantage of the very low dropout
voltage characteristics of the SP6203/6205,
power dissipation can be reduced by using the
lowest possible input voltage to minimize the
input-to-output drop.
Such layouts will provide a much better thermal
conductivity (lower eJA) for, a higher maximum
allowable power dissipation limit.
Adjustable Regulator Applications
The SP6203/6205 can be adjusted to a specific
output voltage by using two external resistors
(see functional diagram). The resistors set the
output voltage based on the following equation:
VOUT = VREF *(R1/R2 + 1)
Resistor values are not critical because ADJ
(adjust) has a high input impedance, but for best
performance use resistors of 470K1 or less. A
bypass capacitor from ADJ to VOUT provides
improved noise performance.
Dual-Supply Operation
When used in dual supply systems where the
regulator load is returned to a negative supply,
the output voltage must be diode clamped to
ground.
Date: 12/14/06
Date: 2//05
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators
11
© Copyright 2006 Sipex Corporation
© Copyright 2005 Sipex Corporation
Date: 12/14/06
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
12
© Copyright 2006 Sipex Corporation
Date: 12/14/06
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
13
© Copyright 2006 Sipex Corporation
ORDERING INFORMATION
Part Number
SP6203EM5-1-8
SP6203EM5-1-8/TR
SP6203EM5-2-5
SP6203EM5-2-5/TR
SP6203EM5-2-7
SP6203EM5-2-7/TR
SP6203EM5-2-8
SP6203EM5-2-8/TR
SP6203EM5-2-85
SP6203EM5-2-85/TR
SP6203EM5-3-0
SP6203EM5-3-0/TR
SP6203EM5-3-3
SP6203EM5-3-3/TR
SP6203EM5
SP6203EM5 /TR
SP6203ER-1-8
SP6203ER-1-8/TR
SP6203ER-2-5
SP6203ER-2-5/TR
SP6203ER-2-7
SP6203ER-2-7/TR
SP6203ER-2-8
SP6203ER-2-8/TR
SP6203ER-2-85
SP6203ER-2-85/TR
SP6203ER-3-0
SP6203ER-3-0/TR
SP6203ER-3-3
SP6203ER-3-3/TR
SP6203ER
SP6203ER /TR
Top
Marking
Temperature
Range
Voltage
Option
Package
Type
N2WW
N2WW
L2WW
L2WW
G2WW
G2WW
Q3WW
Q3WW
H2WW
H2WW
M2WW
M2WW
J2WW
J2WW
Q2WW
Q2WW
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
2.5V
2.5V
2.5V
2.5V
2.7V
2.7V
2.8V
2.8V
2.85V
2.85V
3.0V
3.0V
3.3V
3.3V
ADJ
ADJ
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
620318YWW
620318YWW
620325YWW
620325YWW
620327YWW
620327YWW
620328YWW
620328YWW
620385YWW
620385YWW
620330YWW
620330YWW
620333YWW
620333YWW
6203ERYWW
6203ERYWW
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
2.5V
2.5V
2.5V
2.5V
2.7V
2.7V
2.8V
2.8V
2.85V
2.85V
3.0V
3.0V
3.3V
3.3V
ADJ
ADJ
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6203ER-ADJ/TR = standard; SP6203ER-L-ADJ/TR = lead free.
/TR = Tape and Reel.
Pack quantity is 2,500 for SOT-23 and 3,000 for DFN.
TOP MARKING note: "WW" for SOT-23 package is datecode Work Week. "YWW for DFN package is
datecode Year & Work Week. Lead Free SOT-23 packages can be identified by a Bar "|" to the left of the standard
Top Marking. Lead Free DFN packages can be identified by a Bar "__" under the standard Top Marking.
Sipex Corporation
Corporation
ANALOG EXCELLENCE
Date: 2//05
Date: 12/14/06
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 5035
TEL: (40) 34-500
FAX: (40) 35-600
Sipex Corporation reserves the right to make changes to any products
described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither
does it convey any license under its patent rights nor the rights of others.
SP6203/6205 Low Noise, 300 and 500mA CMOS LDO Regulators
SP6203/SP6205 Low Noise, 300 and 500mA CMOS LDO Regulators
4
14
© Copyright 2005 Sipex Corporation
© Copyright 2006 Sipex Corporation
Part Number
SP6205EM5-1-8
SP6205EM5-1-8/TR
SP6205EM5-2-5
SP6205EM5-2-5/TR
SP6205EM5-2-7
SP6205EM5-2-7/TR
SP6205EM5-2-8
SP6205EM5-2-8/TR
SP6205EM5-2-85
SP6205EM5-2-85/TR
SP6205EM5-3-0
SP6205EM5-3-0/TR
SP6205EM5-3-3
SP6205EM5-3-3/TR
SP6205EM5
SP6205EM5 /TR
SP6205ER-1-8
SP6205ER-1-8/TR
SP6205ER-2-5
SP6205ER-2-5/TR
SP6205ER-2-7
SP6205ER-2-7/TR
SP6205ER-2-8
SP6205ER-2-8/TR
SP6205ER-2-85
SP6205ER-2-85/TR
SP6205ER-3-0
SP6205ER-3-0/TR
SP6205ER-3-3
SP6205ER-3-3/TR
SP6205ER
SP6205ER /TR
Top
Marking
Temperature
Range
X2WW
X2WW
V2WW
V2WW
R2WW
R2WW
E3WW
E3WW
S2WW
S2WW
W2WW
W2WW
T2WW
T2WW
A3WW
A3WW
520518YWW
520518YWW
520525YWW
520525YWW
520527YWW
520527YWW
520528YWW
520528YWW
520585YWW
520585YWW
520530YWW
520530YWW
520533YWW
520533YWW
5205ERYWW
5205ERYWW
ORDERING INFORMATION
Voltage
Option
Package
Type
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
2.5V
2.5V
2.5V
2.5V
2.7V
2.7V
2.8V
2.8V
2.85V
2.85V
3.0V
3.0V
3.3V
3.3V
ADJ
ADJ
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
5 Pin SOT-23
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
-40˚C to +125˚C
2.5V
2.5V
2.5V
2.5V
2.7V
2.7V
2.8V
2.8V
2.85V
2.85V
3.0V
3.0V
3.3V
3.3V
ADJ
ADJ
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
8 Pin DFN
Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6205ER-ADJ/TR = standard; SP6205ER-L-ADJ/TR = lead free.
/TR = Tape and Reel.
Pack quantity is 2,500 for SOT-23 and 3,000 for DFN.
TOP MARKING note: "WW" for SOT-23 package is datecode Work Week. "YWW for DFN package is
datecode Year & Work Week. Lead Free SOT-23 packages can be identified by a Bar "|" to the left of the standard
Top Marking. Lead Free DFN packages can be identified by a Bar "__" under the standard Top Marking.
Sipex Corporation
Solved by
Corporation
ANALOG EXCELLENCE
TM
Date:
12/14/06
Date:
2//05
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 5035
TEL: (40) 34-500
FAX: (40) 35-600
Sipex Corporation reserves the right to make changes to any products
described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither
does it convey any license under its patent rights nor the rights of others.
SP6203/SP6205
Low Noise,
300 and
CMOSCMOS
LDO Regulators
SP6203/6205
Low Noise,
300500mA
and 500mA
LDO Regulators
15
5
©©
Copyright
2006
Sipex
Corporation
Copyright
2005
Sipex
Corporation
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