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Programmable real time network emulator
Scottis, Marios George, M.S.
The University of Arizona, 1993
UMI
300 N. Zeeb Rd.
Ann Arbor, MI 48106
PROGRAMMABLE REAL TIME
NETWORK EMULATOR
by
Marios George Scottis
A Thesis Submitted to the Faculty of the
DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING
In Partial Fulfillment of the Requirements
For the Degree of
MASTER OF SCIENCE
WITH A MAJOR IN ELECTRICAL ENGINEERING
In the Graduate College
THE UNIVERSITY OF ARIZONA
19 9 3
2
STATEMENT BY AUTHOR
This thesis has been submitted in partial fulfillment of requirements for an
advanced degree at The University of Arizona and is deposited in the University Library to
be made available to borrowers under rules of the Library.
Brief quotations from this thesis are allowable without special permission,
provided that accurate acknowledgment of source is made. Requests for permission for
extended quotation from or reproduction of this manuscript in whole or in part may be
granted by the head of the major department or the Dean of the Graduate College when in
his or her judgment the proposed use of the material is in the interests of scholarship. In all
other instances, however, permission must be obtained from the author.
SIGNED:
l/Cf
APPROVAL BY THESIS DIRECTOR
This thesis has been approved on the date shown below:
Ming-Kang Liu
Assistant Professor of
Electrical and Computer Engineering
Date
3
ACKNOWLEDGMENTS
I would like to thank my graduate advisor Dr. Ming-Kang Liu for his guidance and
encouragement that made this thesis possible. I would also like to thank my committee's
members Dr. Frederick Hill and Dr. Jo Dale Carothers for their interest in my work.
Secondly I would like to take the opportunity and express my sincere thanks to the
manager of Pricilab Ltd., Nicosia-Cyprus Mr. Christodoulos Maimaris for manufacturing
the Printed Circuit Boards used in this thesis free.
Finally but most of all, I would like to thank my parents for their financial and
moral support which help me throughout my work.
4
To my parents,
George and Leto
5
TABLE OF CONTENTS
LIST OF FIGURES
7
LIST OF TABLES
9
ABSTRACT
10
1. BACKGROUND
1.0 Introduction
1.0.1 Circuit Switching Networks
1.0.2 Packet Switching Networks
1.1 Motivation
1.2 Issues
1.3 Approach
1.4 Thesis Organization
2. NETWORK EMULATOR DESIGN
2.0 Introduction
2.1 General Overview
2.2 Data Format
2.3 Memory Buffer
2.4 Data And Memory Control
2.4.1 Serial To Parallel Converter
2.4.2 Parallel To Serial Converter
2.4.3 Packet Activity Detection Circuit
2.4.4 Packets In Memory Counter
2.4.5 Memory Read Circuit
2.5 Computer Interface
2.6 Control Logic
2.7 Packet Delay/Loss Circuit
2.8 Implementation
11
11
12
14
17
19
20
21
22
22
22
25
27
31
33
37
41
42
44
48
48
53
55
6
TABLE OF CONTENTS - Continued
3. EMULATOR PROGRAMMING
3.0 Introduction
3.1 Bit Rate And Frame Size
3.1.1 Setting The Frame Size
3.2 Statistics
3.2.1 Download The Data
4. EMULATOR TESTING
4.0 Introduction
4.1 Testing Set Up
4.2 Results
5. CONCLUSIONS AND FUTURE WORK
5.0 Introduction
5.1 Future Work
REFERENCES
57
57
57
58
59
61
63
63
63
65
73
73
74
76
7
LIST OF FIGURES
1.1
Integrated Digital Network
13
1.2
Digital Hierarchy
14
1.3
Packet Switching Network
15
1.4
Transmission Of Packets
16
1.5
Video Compression And Communication Over Networks
18
1.6
Example Of Incoming And Outgoing Frames
20
2.1
Block Diagram
23
2.2
Timing Signals
25
2.3
Data Structure
26
2.4
An SRAM Implementation for First-In-First-Out Memory Buffer
28
2.5
Functional Block Diagram
29
2.6
Asynchronous Read And Write
31
2.7
Data And Memoiy Control Block Diagram
32
2.8
Serial To Parallel Converter Block Diagram
34
2.9
Timing Signals For The Serial To Parallel Converter
35
2.10 Write Control Signal
36
2.11 Parallel To Serial Converter Block Diagram
38
2.12 Timing Signals For The Parallel To Serial Converter
39
2.13 Read Control Signal
40
8
LIST OF FIGURES - Continued
2.14 Packet Activity Detection Circuit With An Active Packet
41
2.15 Packet Activity Detection Circuit With An Empty Packet
42
2.16 Write And Read Cycles
43
2.17 Memory Read Block Diagram
45
2.18 Memory Read Circuit Timing Signals (With FIFO Not Empty)
46
2.19 Memory Read Circuit Timing Signals (With FIFO Empty)
47
2.20 Computer Interface Block Diagram
49
2.21 Control Logic Block Diagram
52
2.22 Packet Loss/Delay Block Diagram
54
3.1
Position Of The DIP Switches
59
3.2
Flowchart For Downloading The Data
62
4.1
Testing Set Up
64
4.2
Transmitted Data
66
4.3
Received Data
68
4.4
Logic Analyzer (General View)
70
4.5
Logic Analyzer (Time Slot 2)
71
4.6
Logic Analyzer (Time Slot 4)
72
9
LIST OF TABLES
2.1
8255A Address Map
49
4.1
Packet Loss/Delay Statistics
67
10
ABSTRACT
The tremendous development of the digital video technology on data compression
made the idea of video communications over computer networks a reality. This project
helps in the study of these compression techniques.
To understand the video transmission performance over a packet switching
network, we designed and implemented a programmable real time network emulator. The
proposed emulator will be used in the study of new compression algorithms and help in
their evaluation over different networks. The emulator was tested and found to operate
successfully. Some directions in which the emulator can be expanded are also proposed
11
CHAPTER 1
BACKGROUND
1.0 Introduction
The need of communication dates back to the ancient times in which many
techniques such as smokes, sound signals, reflected sun light, and fire beacons during the
night were used. To transmit more information over longer distance, more advanced
techniques of communications have been developed. Over the last few decades, the
telecommunication technology has built a worldwide telecommunication network available
to the general public. This worldwide telecommunication infrastructure is believed to be
one of the greatest achievements in the recent human history. One primary objective of the
worldwide network was to provide voice services. Today, it is used for a variety of
services such as data transfer, credit verification, bank transactions, airline reservations,
and home shopping.
In the past, networks were developed to meet the transport characteristics of
different types of traffic. According to the geographic size, there are Local Area Networks
(LANs), Metropolitan Area Networks (MANs), and Long-Haul Networks. According to
the way traffic is switched, there are two types of networks; circuit switching networks
and packet switching networks.
12
1.0.1 Circuit Switching Networks
Circuit switching networks were designed originally for voice traffic. In their first
version, voice channels were set up through a series of circuit switches upon call requests.
To carry multiple voice channels over one physical transmission line, analog transmission
techniques based on Frequency Division Multiplexing (FDM) were used. As digital
transmission technology was introduced in 1960's, voice signals were digitized and
transmitted in bits. A time
domain multiplexing technique called Time Division
Multiplexing (TDM) was used to transmit multiple digital voice channels over the same
transmission line. The first digital system introduced by AT&T in the North America is
called the T-carrier system (T stands for Time or TDM). It has a multiplexing hierarchy
from low bits to high bit rates. Figures 1.1 and 1.2 illustrate an Integrated Digital Network
(IDN) and the digital hierarchy respectively.
In Figure 1.2, we see the lowest bit rate of the digital signals is 64Kb/s, which is
capable of carrying one Pulse Code Modulation (PCM) voice channel. This lowest bit rate
digital signal is called Digital Signal 0 (DSO). In the first level of multiplexing, 24 DSO
streams are multiplexed into one DS1 signal, which has a rate of 1.544Mb/s. Four of these
DS1 streams can be multiplexed into a higher speed digital signal DS2, seven of which can
be multiplexed into a DS3 stream at a bit rate of 44.736Mb/s. This DS3 rate is the highest
rate practically used in the North America, although there is an even higher rate digital
signal DS4 which multiplexes six DS3 signals and has a rate of 274.176Mb/s.
As mentioned earlier, a DS1 signal has 24 PCM channels. These 24 channels are
multiplexed in bytes. That is, 24 bytes with one byte each from the 24 DSO channels are
13
interleaved in the time domain. These 24 bytes plus one framing bit form one TDM frame.
In TDM, each byte in the frame is called one time slot. Therefore, one time slot carries on
a PCM voice channel. When a call request is received, an open time slot needs to be found
to carry the voice. Once the time slot is allocated, it will be used in every frame for the
same voice conversation. Therefore, this is equivalent to a dedicated circuit switched link
and guarantees no interruptions. This is an important characteristic of circuit switching.
DIGITAL
swrrcH
Figure 1.1:
DIGITAL
HIERARCHY
Integrated Digital Network.
DIGITAL
SWITCH
14
64Kbfe
1544MW»
6.312Mty>
44.736MW«
DS2
i
Z74.176HVi
Figure 1.2:
Digital Hierarchy.
1.0.2 Packet Switching Networks
Different from circuit switching networks, packet switching networks were
designed originally for data traffic. In packet switching information is transmitted via
"packets", which consist of the header and information payload. The header contains
information for touting and source identification. The payload carries data to be
transmitted. When a packet is sent to the network, it is switched according to the address
information. In computer communications, data generated is usually random and bursty.
As a result, packets are generated only when there is data to transmit. In this case, packet
switching becomes an attractive choice since there are no lines or time slots dedicated for
each connection. Figure 1.3 shows a typical packet switching network.
15
COMPUTERS
GATEWAY
NODE
COMPUTER 1
COMPUTER 4
COMPUTER 2
Figure 1.3:
Packet Switching Network.
As illustrated in Figure 1.3, a packet switching network consists of switching
nodes which are connected by constant rate links. In practice, these links can be DSO
(64Kb/s) channels borrowed from existing circuit switching networks, or dedicated DS1
lines. Each switching node routes incoming packets according to their final destinations.
Therefore, packet switching can be also described as store-and-forward. There is a special
kind of nodes called gateways, which perform packet conversion between two different
networks.
16
One of the main advantages of the packet switching networks is the pipelining
effect which is illustrated in Figure 1.4. Lets assume that in Figure 1.3 computer 2 needs
to send data to computer 3. There are multiple routes that packets might follow. One
such route is through nodes D, E, F and B. As soon as the first packet enters the link
between nodes E and F the second packet can be transmitted from node D to node E and
so forth. This means that two or more packets might be in the network at the same time
heading for computer 3. Thus, pipelining effect increases the efficiency of the network.
Packet delay
fkckstl
Jbcketl
•
D
Figure 1.4:
E
Transmission Of Packets.
F
B
17
One problem in packet switching is the random delay. Since there is no dedicated
line allocated for a given connection as in the case of circuit switching, a packet sent to the
network may find traffic congestion. That is, there can be more packets that need to be
transmitted over a given link than the link capacity. As a result, the packet can be either
lost or has to wait in the buffer of the switching node. As an example assume that
computer 1 needs to talk to computer 4. A possible route is through nodes A, B, and F,
through the gateway, and finally through nodes G, H and I. If now the link between the
nodes B and F is fully occupied by the traffic between computers 2 and 3, packets from
computer 1 will have difficulty to go through. On the other hand, if there is no traffic on
the link, the packet can be switched immediately. Therefore, transmission delay in a packet
switching network is not a constant and highly depends on the network traffic intensity.
1.1 Motivation
Video communication has been a dream for many people. Video communications
such as video telephony, teleconference, and interactive video over personal computers
have been actively pursued over the last two decades. Recently, the low bit rate digital
video compression technology has been made possible. Recent standards on low bit rate
video such as the CCITT H.261, MPEG and JPEG have been proposed [l]-[3].
These low bit rate video compression standards have one common characteristic.
That is, they are designed for a fixed bit rate transmission channel. In other words, they
are designed for transmission in circuit switching networks. Since we have more and more
18
access to computers and packet switching networks, it is desirable to transmit video data
over a packet switching network.
Video communication over a packet switching network is illustrated in Figure 1.5.
First, an analog video signal is digitized by an analog to digital converter. The digital
output is send to an encoder for data compression. The compressed signal is packetized
and sent to the network. On the receiver side, the received packet is depacketized and
decoded. The final decompressed output is sent to a digital to analog converter to get the
original video signal. If a computer monitor is used, the decompressed output can be sent
to the computer directly for display.
PAczrraiTiox
WD
•ITVOU
nnnci
TnaumUterSUe1
NETWORK
Reconfbuctad
Decompnasd
L/<Oi
VBTWOIK
DITMFACB
AID PACKET
DBTBCTOt
JtecetoerSide
Figure 1.5:
Video Compression And Communication Over Networks.
19
1.2 Issues
As mentioned earlier, one important characteristic of packet switching is the
random transmission delay. When there are too many packets stored in a buffer,
subsequently incoming packets will be lost. In data communications, random delay is in
general not a problem, and lost packets can be recovered from re-transmission. For real­
time video communication, however, random delay and packet loss can become significant
problems. Since the video signal is continuous in time and has no time for re-transmission,
random packet delay and packet loss can significantly degrade the quality of video
transmission.
Therefore, to overcome the delay and loss problems, we need to develop new
compression algorithms. Since the performance of new algorithms can depend on the
packet switching network used, we need to perform real time transmission over a given
network to evaluate the performance of a given network. This can be time consuming and
expensive. An alternative way is to develop a programmable real-time network emulator.
The network emulator is used to emulate a real packet switching network illustrated in
Figure 1.5. With the programmability, we can easily study the transmission performance
over different switching networks. Since it is also real-time, we can evaluate performance
quickly and direcdy.
20
1.3 Approach
The basic idea to implement a real-time network emulator is illustrated in Figure
1.6. Each incoming packet sent to the emulator can be dropped or not according to the
programmed pattern. If it is not dropped, a programmed delay determines how long it will
stay in the buffer before it is sent out. In this approach, we can use given traffic statistics
to emulate the packet loss and random delay of the target packet switching network.
Programmed to
be dropped
A | Bitfrgr
Frame header
Figure 1.6:
Time slot carrying a packet LJ An empty time slot
Example Of Incoming And Outgoing Frames.
(a) Incoming data
(b) Outgoing data
•
(b)
21
1.4 Thesis Organization
In the remaining of this thesis, detailed design of the programmable real-time
network emulator is explained in Chapter 2. Chapter 3 explains how to program the
emulator, and Chapter 4 shows some experimental results. Finally chapter 5 gives the
conclusion and addresses future work.
22
CHAPTER 2
NETWORK EMULATOR DESIGN
2.0 Introduction
As mentioned in Chapter One, one primary objective of this thesis was to build a
real-time programmable network emulator for a packet switching network such as
Ethernet, Fiber Distributed Data Interface (FDDI), frame relays, and BroadbandISDN/ATM networks. In the design, programmability was one of the most challenging
parts. In addition, to meet the high speed requirement for real-time transmission, high
speed logic components such as the Fairchild Advance Schottky TTL (FAST) series were
used. The FAST series facilitates high switching speeds (typical in the range of 80115MHz), small propagation delays (~3ns), large fan-out capability (>50), superior noise
margins, and low power consumption [4].
2.1 General Overview
In this section, we first explain the overall emulator design. The functional block
diagram of the emulator is illustrated in Figure 2.1. As shown, the emulator consists of
23
(1) the memory buffer section, (2) the data and memory control section, (3) the computer
interface section, (4) the control logic section and (5) the packet delay-loss section.
FRAME 0
FRAME IN
CONTROL LOGIC
CLOCK 01
CLOCK IN
PACKET
LOSS/DELAY
lou.
MEMORY AND DATA
CONTROL
DATA IN
COMPUTER
INTERFACE
MEMORY BUFFER
Emulator
HOST COMPUTER
Figure 2.1: Block Diagram.
DATA OUT
24
Under normal operation, external data DATA_IN is first sent to the memory and
data control section. The purpose of the memory and data control is to manipulate the
data flow for packet loss and delay control. To do this, it receives control signals from the
control logic section (framing timing etc.) and the packet delay and loss signals from the
packet delay/loss section. From these signals, it generates the write and read cycles for the
memory buffer section. The data read back from the memory buffer is sent out by the
DAT A OUT signal from the memory and data control section.
The primary function of the control logic section is to generate the necessary
timing signals for the system It receives the external FRAME IN and CLOCKJN signals
for frame timing and bit timing. From these signals it generates signals to indicate the
beginning of each frame and time slot
The packet loss/delay section receives user programming commands through the
computer interface. In other words, this section uses the input packet loss and delay
information to generate the packet loss and delay signals for the memory and data control
section.
To provide the user programmability, the computer interface is another important
pan of the system. It initializes the emulator and transfers the delay and loss data from the
computer to the packet delay/loss section.
The computer that controls the emulator is located at the bottom of the block
diagram. The probability distributions for the packet loss and delay are pie-generated by
the computer and then downloaded to the emulator.
25
As noted from the block diagram, the input signals to the emulator include not
only the data itself but also the frame timing and bit timing. Inclusion of these timing
signals is to simplify the design by avoiding the bit timing and frame timing recovery. Since
the transceivers and emulator are all local during emulation, the inclusion of these signals
is not a problem. Figure 2.2 illustrates the timing signals used in the emulator. The
beginning of each frame is indicated by the rising edge of the frame signal. Both, the frame
and data signals are synchronous to the bit clock signal.
^nnnrLrinnju^ARfinju^m »
(b)
J
1
Figure 2.2:
(c)
Timing Signals.
(a) Clock signal
(b) Frame signal
(c) Typical data
2.2 Data Format
Each frame of the input DATAJN signal to the emulator is assumed to have a
certain number of time slots of identical size. Each time slot is used to carry one packet. In
this thesis, we specifically consider emulation for B-ISDN/ATM (Asynchronous Transfer
Mode) since it is likely to be used for future broadband services [5].
26
The ATM packet size is 53 Octets from the CCITT recommendation [6]. The first
5 Octets in the packet are used for the header, and the remaining 48 Octets are the
information field or payload. Figure 2.3c shows a typical packet structure. The header is
divided into fields. There are the generic flow control field (4 bits), the virtual path field
identifier (8 bits), the virtual channel field identifier (16 bits), the payload-type field (2 bits)
Frame N-4 Frame N-3
Frame N-2
Frame N-1
Time Slot 2
Time Slot n
Frame
header
424 bits
Packet header
Active/idle bit
1 = Time slot carries a packet
0 = Time slot carries no data
Figure 2.3:
Frame N+1
Data Structure.
(a) Alternative frames
(b) A typical frame with n number of time slots
(c) A typical packet
27
the loss priority indicator (1 bit), the reserve field, (1 bit), and the header checksum
sequence (8 bits).
For the emulation purpose, the emulator does not examine the header bits except
the 51*1 bit, which is used to determine if the slot carries an active ATM packet or not (see
Figure 2.2c). If this active/idle bit is one, it indicates that the slot carries an active packet.
If the active/idle bit is zero, the slot carries no data. The active/idle bit is set by the
packetization circuit in Figure 1.5. When there are enough data to fill a packet, the
active/idle bit is set to one and a packet is sent to the network. On the other hand, if there
are not enough data to fill a packet, the active/idle bit is set to zero, and an empty packet
is transmitted.
A frame has a number of slots for ATM packets as illustrated Figure 2.2b. The
frame length is set at 125(is. Because of the fixed frame size in time, the number of time
slots in each frame depends on the bit rate. For example, at a bit rate of lOOMb/s, each
frame has 12,500 bits (=100Mb/s times 125|i.s). Since each time slot has 424 bits, one
frame in this case can carry 29 time slots, which represents 12,296 bits out of the total
12,500 bits. The remaining 204 bits are used for the frame header (see Figure 1.2b).
2.3 Memory Buffer
The incoming packets are stored and retrieved in a first-in-first-out
(FIFO)
sequence. One way to implement this is to use a Static RAM (SRAM) as illustrated in
Figure 2.4. An address generator and additional control logic are needed to read and write
28
the data. In this implementation, since the data bus is used for both read and write, the
control circuit must prevent simultaneous write and read and provide isolation between
the input and the output data lines.
Data out
Data in
ADDRESS
GENERATOR
kt&rm
STATIC
RAM
bat
W
1
I
CONTROL
LOGIC
H
Figure 2.4:
w
I
An SRAM Implementation for First-In-First-Out Memory Buffer.
29
An alternative approach to simplify the control circuit implementation is to use
commercially available FIFO memory chips. These chips have internal control logic to
handle asynchronous read and write. FIFO memory chips are available from manufactures
such as Motorola, National Semiconductors, and Micron Technology. The FIFO chip we
used is the MT52C9020-25 from Micron Technology . The MT52C9020-25 is a 2Kx9
FIFO with access time of only 25 nsec. Its functional block diagram is given in Figure 2.5.
It is based on the low-power CMOS technology and employs a true dual port with dual
write and read pointers to handle the internal addressing. This dual port pointer design
allows data to be written to and read from the FIFO asynchronously and independently.
R-
READ
CONTROL
T
READ ADDRESS POINTER
2048 x 9 BIT
DUAL PORT
MEMORY
D1-D9
Q1-Q9
©m
WRITE ADDRESS POINTER
XI
W -
WRITE
CONTROL
FURTRS"
Figure 2.5:
RESET
LOGIC
Functional Block Diagram.
EXPAND
LOGIC
I
FLAG
LOGIC
+-XO/HF
-• EF
-• FF
30
The signal levels of the chip are fully TTL compatible. The chip has also empty, halffull, and
full flags to signal buffer occupancy, and has provisions for depth and/or
width expansion [7].
The trade-off of using FIFO memory is the cost. It is generally much more
expensive than ordinary SRAMs. The price for the same capacity can be five to eight times
higher than that of SRAM's. When the memory size is small as in our case, this higher
cost is compensated by the external control circuit required for addressing SRAM's.
Before using the FIFO, the RESET (/?s) pin must be taken LOW in order to
initialize the read and write pointers and the flags. Data can be read from the FIFO from
the Q1-Q9 pins by taking the read strobe (/?) pin LOW and the FIFO occupancy is non
zero. The read access time is tA after the falling edge of R (see Figure 2.6). If the FIFO is
empty, any attempted reads are prohibited and the output pins will stay inactive (high
impedance).
Data can be written into the FIFO by taking the write strobe (w) LOW and the
FIFO is not full. The write cycle starts at the falling edge of W and data on D1-D9 pins
will be latched on the following rising edge of W (see Figure 2.6). If the FIFO is full, any
attempted writes are prohibited and the data will be lost.
In the current design, four MT52C9020 chips are cascaded to have a total size of 8
Kbytes. For the ATM cell size of 53 bytes, this FIFO size can store up to 154 packets.
31
DATA OUT (1)
VALID
/
\
D1.D9
DATA IN (1)
VALID
\
/
DATA OUT (2)
VALID
/ DATA IN (2)
\
VALID
• UNDEFINED
Figure 2.6:
Asynchronous Read And Write.
tA=Access time
tRC=Read cycle time
t^^Write cycle time
2.4 Data And Memory Control
The data and memory control section is the heart of the emulator. As mentioned
earlier, its mission is to manage the data flow, introduce packet loss and delay, and control
the read/write strobes of the memory buffer. The block diagram of this section is shown in
Figure 2.7. It consists of serial to parallel conversion, parallel to serial conversion, packet
"B
3
Si
«-J
U
B
T1ATA1N
D. DATA OUT
CLOCK
DATA IN
Write enable signal ^
SERIAL
TO
PARALLEL
CONVERTER
PARALLEL
TO
SERIAL
CONVERTER
htrinwl
CLOCK
a.
£
a
2
I
w
8
*•
D
s
9
End of picket+5
DIVIDE
BY 8
COUNTER
PACKET
ACTIVITY
DETECTION
CIRCUIT
MEMORY
READ
CIRCUIT
Ion
Memory
enable
signal
Multiple control signals
see ten
Memoiy
PACKETS
IN MEMORY
COUNTER
Multiple control signals
see text
empty
T
DATA AND MEMORY CONTROL CIRCUIT
S>
33
activity detection, packets in memory counter, memory read circuit, and other control
logic. These components are discussed below.
2.4.1 Serial To Parallel Converter
On the top left side of the block diagram is the serial to parallel converter. The
input data is serial to parallel convened for two reasons. First, to transmit high speed data,
parallel data can reduce the speed requirement for the memory buffer. For a bit rate of
lOOMb/s, the read and write cycles must be within 10 nsec if data is stored and forwarded
serially (see Figure 2.6). Therefore, the access time must be in the range of 5 to 7 nsec.
However, the fastest FIFO available has an access time of 25 nsec, which gives a transfer
rate of at most 40Mb/s. If we use serial to parallel conversion, the transfer rate can be
multiplied by the degree of parallelism. In the current design, the parallel bus is 8 bits.
With 25 nsec access time, we can have up to 320 Mb/s transfer rate.
Another reason to use serial to parallel conversion is to reduce the cost of the
emulator. The FIFO chip we are using has a 9-bit input/output data bus. If serial to parallel
conversion is not used, only one of the nine bits was to be used, which wastes almost 90%
of the FIFO's capacity. On the other hand, with serial to parallel conversion used, eight of
the nine bits are used. This dramatically reduces the number of FIFO chips required
resulting in a more compact design and at a lower cost.
Figure 2.8 shows the block diagram for the serial to parallel converter, which
consists of a shift register, a D-Flip Flop, and a divide by 8 counter. The serial input data
34
and the inverse of the input clock (CLK) are applied to the shift register. The parallel
output of the shift register is connected to the input of the D-latch. The shift register shifts
on the rising edge of its clock signal. Therefore the input data will be shifted on the middle
of each data bit. Every eight bits a pulse latches the data to the output of the D-latch. The
data remain in the latch until the next set of data is latched. This serial to parallel
conversion provides enough time for the memory control circuit to store the data into
the FIFO (see Figure 2.9f). The signal that shifts the data to the output of the D-latch
comes from the divide by eight counter.
Serial Data Input
SHIFT REGISTER
Inverse of input clock (CLK)
Write enable
DIVIDE BY 8
COUNTER
D-LATCH
To the FIFO
Data Input
Figure 2.8:
Serial To Parallel Converter Block Diagram.
35
H
One write cycle
jiARjijmnjTim
i
•
•
i
^
i
i
w
(c)
(d)
DEEta
Wnte into the FIFO
Data latched to the
D-latch output
Figure 2.9:
(e)
(0
Data corresponding
to the previous byte
Timing Signals For The Serial To Parallel Converter.
(a)
(b)
(c)
(d)
(e)
(f)
Input clock signal
Inverse clock signal
Typical data
Clock pulse to the D-latch
Output of D-latch
Write control signal
The serial to parallel conversion is enabled by the control logic at the end of every
frame header, and is disabled again one byte after the end of the frame. This process
allows conversion for only the packets not the frame header. Because of the conversion,
there is one byte delay in storing the data to the memory buffer. Hence, the first byte of
the packet is sent to the FIFO during the second byte of the packet (see Figure 2.10a). To
prevent invalid data stored during the first byte of the first packet in each frame, a sccond
signal that is also generated by the control logic is used to prohibit data loading to the
buffer at the first write cycle of the first packet. Similarly, the 53r^ byte of the last packet
36
in each frame is written into the FIFO one byte after the end of the frame (see Figure
2.10b).
ft
•
ft
•# •
(a)
Byte 1 is written
into the FIFO
•• »
1 *
1
•
• • 1 11
'
s
a
ft ft
«
«
m
ft
1
1 11 • •
i
—•
i
'V
Frame header
Byte 53 is written
into the FIFO
Packet earring real data
Figure 2.10: Write Control Signal.
(a) Moving from the frame header to the first packet in the frame
(b) Moving from the last packet in the frame to the frame header of the next frame.
37
2.4.2 Parallel To Serial Converter
When data is read back from the FIFO, we need to perform parallel to serial
conversion to get the serial data out. In this process, data in the FIFO is first read out byte
by byte. The block diagram of the parallel to serial converter is shown in Figure 2.11 and
is consisted of a D-latch, a shift register, a flip-flop, a decoder, and a divide by eight
counter. The decoder is connected to the output of the divide by eight counter and it
generates the required control pulses for the operation of the converter. After parallel data
appears on the FIFO's output bus, a pulse latches diem on the D-latch. The output of the
D-latch is connected to the parallel input of the shift register. The mode selection input of
the shift register is connected to the output of the D flip-flop. Depending on the level of
the mode selected, the shift register operates either in the parallel load or the shift mode. If
the mode selection input is HIGH, the shift register operates in the parallel load mode and if
the mode input is LOW, it operates in the shift mode. To load the parallel data to the shift
register, a pulse generated by the decoder sets the flip-flop output HIGH, which forces the
shift register to load the parallel data appeared on the D-latch output. After one bit clock,
the flip-flop is reset and sends a LOW signal to the shift register, which changes the shift
register to the shift mode (see Figure 2.12e). Following this are seven clock cycles which
shift seven internal bits of the register to the right. In the next cycle, the next byte on the
FIFO's output bus is loaded to the shift register and the same sequence repeats.
38
Prom FIFO
Data output
Inverse of input clock (CLK)
Bead enable
DIVIDE BY 8
COUNTER
D-LATCH
DECODER
> SHIFT REGISTER
Mode
CLK
CLR
FLIP-FLOP
Figure 2.11: Parallel To Serial Converter Block Diagram.
39
One read cycle
JTRTLTLJmJTJlJlJlJ^^
•
i
•
i
«
i
i
•
(e)
Read from the FIFO
Data latched to the
D-lalch output
Data loaded to
shift register
Beset flip-flop
(shift register
works in the
shift right mode)
Figure 2.12: Timing Signals For The Parallel To Serial Converter.
(a)
(b)
(c)
(d)
(e)
(f)
Input clock signal
Inverse clock
Clock pulse D-latch
Clock pulse flip-flop
Reset flip-flop
Load data to the shift register when is high. Shift register works in the shift right
mode when is LOW
As in the case of serial to parallel conversion, because of one byte delay in the
conversion, the first read cycle for each packet comes one byte before the beginning of the
packet (see Figure 2.13a). In the same way, the 53rc* byte in the packet must be read from
40
the FIFO one byte before the end of the packet. For the last packet in the firame, we have
the similar situation (see Figure 2.13b).
•
mi
iHI
£
•••
(a)
ri_n__ni__rTL_r
7
Byte 1 is read
from the FIFO
Byte S3 is read
from the FIFO
Frame header
IPacket earring real data
Figure 2.13: Read Control Signal.
(a) Moving from the frame header to the first packet in the firame
(b) Moving from the last packet in the firame to the frame header of the next firame.
41
2.4.3 Packet Activity Detection Circuit
As mentioned in Section 2.2, each time slot has its S^1 bit to indicate if it carries an
active packet. The activity detection circuit is used to read this bit and detects if the slot is
active (see Figure 2.3). If the active/idle bit is one, meaning that the packet carries real
data, the output of the activity detection circuit goes
HIGH,
allowing the packet to be
stored into the FIFO (see Figure 2.14). One bit before the end of the packet a pulse resets
the activity detection circuit and its output goes
output of the activity detection circuit remains
LOW.
LOW,
If the active/idle bit is zero, the
inhibiting any write attempts into the
FIFO until the next packet arrives (see Figure 2.15).
JTjTJTJTJTJTJTJTJTiTJTJTJTJTJTJTJTjlJTJT- <•>
(b)
~L
(c)
t
Packet starts
here
5
in the
time »ktjs ONE
t
Output goes
HIGH
Figure 2.14: Packet Activity Detection Circuit With An Active Packet
(a) Clock signal
(b) Typical data with the 5th bit in the packet header HIGH
(c) Output of the packet activity detection circuit
42
(a)
1
1i
i
i
i
t
Packet starts
here
5 i&jnthe
tima akt is ZERO
1
(b)
(c)
t
Output remains
LOW
Figure 2.15: Packet Activity Detection Circuit With An Empty Packet
(a) Clock signal
(b) Typical data with the 5^ bit in the packet header LOW
(c) Output of the packet activity detection circuit
2.4.4 Packets In Memory Counter
If the average packet arrival rate is higher than the packet departure rate, the
memory buffer will become overflowed. In the current implementation, the buffer can hold
up to 154 packets (8 Kbytes/53 bytes). When the 155^ packet arrives, there is an
overflow. We can solve this problem in two ways.
The first way is to program the loss and delay statistics in a way that guarantees no
buffer overflow. This will require additional check and modification from the traffic
statistics given. A second way is to use a hardware method. A counter can be used to
count the total number of packets currently in the FIFO and inhibits any write attempts
after the 154th packet until there is a packet read from the buffer. This counter is called
packets-in-memory counter and is shown in Figure 2.7, below the FIFO memory.
43
The packets-in-memory counter is also used to inhibit any read attempts when the
buffer is empty until a complete packet is stored into the buffer. We have seen before that
due to serial to parallel conversion and then back from parallel to serial, the read control
signal leads the write control signal by two cycles (see Figure 2.16). If now the buffer is
empty and the packets in memory counter does not inhibit any read attempts, a read cycle
will be sent to the FIFO even though the FIFO is empty. As a result, invalid data will
appear at the emulator output. In addition to this, after the first write cycle, the buffer will
not be empty, and the next read cycle will read the new data at the wrong timing (not in
alignment with the slot timing). Therefore, by inhibiting the read cycles when the buffer is
empty for the entire packet period, the problem is eliminated. Also, this makes sure that
invalid data will not appear on the emulator output.
- -
\
L ..
I
l
Packet starts
here
I
Buffer is not
empty after
this point
Figure 2.16: Write And Read Cycles.
(a) Write control signal
(b) Read control signal
JTT (b)
If the packets in
memory circuit is
not used, this will
read the new data in
the FIFO, and data
will be shifted out
starting fromtjys^
—
point
44
2.4.5 Memory Read Circuit
The memory read circuit controls the read strobe of the FIFO and its block
diagram is shown in Figure 2.17. The memory read circuit consists of a divide-by-8
counter, a decoder, two flip-flops and three
AND
gates. The output Q of flip-flop_2
controls the read strobe input of the FIFO memory and the output Q of flip-flop_l
controls the clear (CLR) input of flip-flop_2. During the emulator initialization, the output
of flip-flop_l (Q) and flip-flop_2 (q) are reset to zero and one respectively. Therefore the
initial state of the read control signal is one.
The purpose of using flip-flop_l and
AND
gates 1 and 2 is to inhibit any read
attempts when the FIFO memory is empty. This prevents invalid data at the emulator
output. A pulse that comes 8 bits before the end of the time slot resets flip-flop_l through
AND
gate 2 and its output goes to ZERO (see Figure 2.18c and Figure 2.19c). If the FIFO
memory is not empty, a second pulse will set flip-flop_l and its output will go HIGH (see
Figure 2.18d and e). On the other hand, if the FIFO memory is empty this pulse will be
inhibited by
AND gate 1 and the output of flip-flop_l will
stay LOW for the whole time slot
(see Figure 2.19d and e).
The decoder is connected to the output of the divide-by-8 counter and sets and
resets flip-flop_2 every 8 bits. If the output of flip-flop_l is HIGH meaning that the FIFO
memory is not empty, a pulse will set the Q output of flip-flop_2 LOW on the falling edge
of the second clock cycle (see Figure 2.18f). On the rising edge of the last clock cycle, a
pulse resets flip-flop_2 and its output goes back to
sequence repeats until the whole packet is read.
HIGH
(see Figure 2.18g). The same
45
If now the FIFO memory is empty the output of flip-flop_2 will be forced to stay
HIGH
because its clear (CLR) input will be held LOW. In this case any read attempts will
be inhibited.
Flip-Flop 2
Inverie of input dock (CLK)
Read enable
Flip-Flop 1
rffOwrtT
>CLK
BnJ »f Tin. RW .1
CLK
RndiifTiniiifllati-S
Delay
=e>
Muter Rent
Figure 2.17: Memory Read Block Diagram.
Q
46
^
One read cycle
^
la)
_rmjiJTJTJTruTJi4iJTJT^^
•
*
i
*
nj^jruruiUTU^
•
—n
i
|
i
>
®
•
»
j
1
(c)
j
j
(d)
•
n
*
(e)
u
u
"Lf
u
U
(f)
(g)
(h)
Time slot >
starts here
Figure 2.18: Memory Read Circuit Timing Signals (With FIFO Not Empty).
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
Input clock signal
Inverse clock signal
End of time slot - 8 pulse
End of time slot - 7 pulse
Output of flip-flop 1 (goes HIGH)
Flip-flop 2 sets on the rising edge
Flip-flop 2 resets
Read control signal
47
One read cycle
<
•
i
1I
I
1
•
I
n
! n
i
i
:
u
u
:•
U
u
u
«
Time slot >
starts here
Figure 2.19: Memory Read Circuit Timing Signals (With FIFO Empty).
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
Input clock signal
Inverse clock signal
End of time slot - 8 pulse
End of time slot - 7 pulse
Output of flip-flop 1 (stays LOW)
Flip-flop 2 does not set on the rising edge
Flip-flop 2 resets
Read control signal
48
2.5 Computer Interface
The computer interface is based on the Intel's 8255A PIO (Programmable Input
Output). The 8255A is a general purpose programmable I/O device designed to be fully
compatible with the Intel microprocessors. It can be configured as three 8-bits ports or
two 8-bit ports and two 4-bit ports. Each port can be configured for input, output or bi­
directional operation. The configuration can be programmed by software, thus eliminating
external logic required for interfacing 82S5A to other devices.
Figure 2.20 shows the block diagram of the computer interface. The 8255A is
shown on the right. A buffer is used between the data buses of the computer and 82S5A.
This use of a buffer is a good practice to protect the computer when something goes
wrong. A simple decoder is used for addressing 82SSA. According to the IBM Technical
Reference Manual [8], we use the address 300Hex as the first V0 address for the 8255A.
The address map of the 8255A is shown in Table 2.1.
2.6 Control Logic
The block diagram of the control logic section is shown in Figure 2.21 and its main
function is to generate necessary timing and control signals for the emulator. The control
logic monitors the incoming data to detect the beginning of each frame and time slot.
During the time that the packet loss and delay data are downloaded, the control logic sets
the emulator in the idle state until all the data are transferred. It is very important for the
11
PS
u
ad,
Df
ad,
E-«
f| «
O
.J
m
8255A
bd
(
bd,
S
CO
03
w
Q
O
PS
C D,
Q
1 § n
Figure 2.20: Computer Interface Block Diagram.
Operation
Address
Port A
300Hex
Port B
301Hex
Port C
302Hex
Command Word+
303Hex
Table 2.1:
+
82SSA Address Map.
The command word is a command that is sent by the system software in order to initialize the 82SSA.
50
emulator to start operating on the rising edge of the frame signal because its operation
depends on a chain of cascaded delay and counter modules that count the pulses of the
input clock signal in order to locate the beginning of each frame and time slot. The first
frame detection circuit takes care of that. After the emulator is initialized, it keeps the
emulator idled until the first frame arrives.
The first module in the chain is the delay-by-(L-8). This module introduces a delay
equal to the frame header length (L) minus 8 bits. The delay-by-(L-8) module consists of
three cascaded decade counters by which we can preset the initial value by changing a
twelve-selector DIP (Dual-In-Line-Package) switch (four selectors for each decade
counter). The initial value is used to determine the frame header length. Its value is smaller
than the frame header by 8 to account for the parallel to serial conversion delay. As soon
as a rising edge of the frame signal is detected, these counters start to count down. When
zero is reached the output of the delay-by-(L-8) module goes to zero and enables the
parallel-to-serial converter. At the same time its internal counters re-load their initial value.
The length of the delay-by-(L-8) module can be set for any number between 0 and 999.
When the delay-by-(L-8) goes to zero, the second delay module in the chain is
enabled. This is the delay-by-8 and its purpose is to find the end of the frame header.
When the end of the frame header is reached, it enables the serial-to-parallel converter and
the next delay module in the chain which is also a delay-by-8. The function of this delay is
to inhibit the first write cycle of the first packet for the reason we mentioned earlier.
On the bottom left side of the block diagram is the divide-by-424 counter with a
decoder connected to its output. The divide-by-424 counter is also enabled by the delay-
51
by-(L-8) and has the same length as the time slot. Its purpose is to generate a variety of
control signals. Such signals include the signals that synchronize the packet loss and delay
signals with the incoming packets, the signals that increase and decrease the packets in
memory counter, the signal that resets the packet activity circuit, and the signals that
controls the packet delay circuit. There are more than 15 control signals generated from
this control logic section.
The last counter in the chain is the divide-by-n counter and is also of a variable
length. Its length is the same as the number of the time slots in the frame (n). It operates in
the same way as the delay-by-(L-8) module does, but in this case we have only two
internal decade counters with an eight-selector DIP switch. Therefore the length of this
counter can be set from 0 to 99. The purpose of the divide-by-n counter is to indicate the
end of the frame.
The divide-by-n counter indicates the end of the frame 8 bits before the actual end
of the frame. This gives enough time for the reset circuits to reset the delay-by-(L-8)
module. The output of the delay-by-(L-8) goes
HIGH and
the parallel-to-serial converter is
disabled. After 16 bits the reset circuit resets the two delay-by-8 modules and the serial-toparallel converter is also disabled. In the meanwhile the next frame has been detected and
the same cycle repeats.
2?
Read enable signal ^
Frame header
<3
K)
N>
write enable signal
9
Delay
by L-8
module
9
5
Delay
by 8
module
Delay
by 8
module
Clock input signal
0
W
Matter reset
Frame input gjgnal
1
g
<s
First frame
detection
Reset Circuits
Divide
byn
counter
Note: L=headerlenght
n=number of packets per frame
Divide
by 424
counter
Decodera
jrigtak
to
53
2.7 Packet Delay/Loss Circuit
The packet delay/loss circuit is responsible for generating the delay and loss
signals used by the data and memory circuit. Figure 2.22 shows the block diagram of the
packet delay/loss circuit In the delay/loss circuit, two 128K static RAMs are used to store
the statistics for the loss and delay. The RAM chip we used is the MCM6226 by
Motorola. The MCM6226 is a static RAM organized as 131,072 words of 8-bits. Its static
design eliminates the need of external circuitry for refreshing. It is also fully TTL
compatible and has a low access time (25ns).
Addressing of the RAM chips is handled by two identical address generators, one
for each RAM chip. The address generator controls the 17 address input lines of the
MCM6226. After initialization of the emulator, the address generator is reset to zero.
When a pulse is applied to the clock input of the address generator, its output increases by
one and advances the access to the memory by one byte. On the 131,073th clock pulse,
the address generator resets and the whole cycle repeats. This means we can program
delay and loss for up to 131,072 packets. When the program delay and loss data are used
to control the delay and loss of each packet, the loss data are repetitively used for every
131,072 time slots. On the other hand, the delay data are repetitively used for every
131,072 outgoing packets (that is, those incoming active packets that have been stored in
the buffer). Therefore, the address generator for the RAM that controls packet loss
advances much faster than the one that controls the delay. This is the main reason of
using two address generators. Is to ensure independence of the packet loss and packet
delay statistics.
54
MatwrButt
RatC-DO
HraciranMikmiiMffiM
DELAY
CIRCUIT
^ 128 K
STATIC
BAM
Pt
WR
Endof Ackst-12
>CIK
EbitC-Dl
RntB-Dl
>CLK
n
%
128 K
STATIC
RAM S."
Figure 2.22: Packet Loss/Delay Block Diagram.
55
The I/O ports of 8255A are also shown in the block diagram. Port A of 8255A is
configured as a bi-directional port for transferring data from the computer to the RAM
chips, and back to the computer for verification purposes. Seven bits of Port A are used
for the delay data and one is used for the loss data. These seven bits for the delay data
allows a maximum delay of 127 time slots that can be programmed. As mentioned earlier,
the FIFO buffer can hold up to 154 packets. Therefore, it is sufficient to store
instantaneous large delay packets.
Port B of 8255A is used for controlling the write and read strobes of the two
RAMs. Port C is used for initializing the emulator and for generating the pulse that
advances the address generators when the data are downloaded to the RAMs. The
procedure for downloading the data to the emulator will be explained in more detail in
Chapter 3.
2.8 Implementation
To meet the high speed transmission requirement the emulator was built on a
Printed Circuit Board (PCB). The design was done on a PC by using a drafting program
for PCB layouts. In order to minimize the size of the PCB and consequently the length of
the tracks, five different PCBs were designed. Each one carries a major part of the
emulator design. These boards are:
•
The Logic Control Board
•
The Data And Memory Control Board
56
•
The Packet Loss Board
•
The Packet Delay Board
•
The Computer Interface Board
High quality connectors were used for the interconnections among the circuit
boards, and the lengths of wires were minimized. In addition, gold plated IC sockets were
used to ensure perfect contact between IC pins and the sockets. Furthermore, decoupling
capacitors were placed closed to the power pin of the chips. The emulator needs +5 Volts
to operate and takes its power from the host computer.
57
CHAPTER 3
EMULATOR PROGRAMMING
3.0 Introduction
Chapter Two has discussed the design of the emulator and described the hardware
aspect of programming the packet loss and delay. In this chapter we discuss the software
aspect of programming the emulator. As we are going to see, programming the emulator
is straightforward. In addition to programming the packet loss and delay, we can also
program the transmission bit rate. In other words, the programming can be divided into
the following two parts.
•
Bit rate
•
Programming the statistics for the packet loss and delay
3.1 Bit Rate And Frame Size
Before we even turn on the emulator and start loading the loss and delay data
to the emulator, we must first set the right bit rate. In the current design, the frame size is
58
fixed at 125|is and the packet size is fixed at 53 bytes. Therefore, by programming
different transmission bit rates, we can accommodate different number of slots in a frame.
If the number of time slots per frame is (n) and the header length is (L), the user can use
the following formulas to calculate n and L for a given bit rate.
n = INT
L = (Bit
(Bit
Rate)*\25\is
424
Rate)* 125jis—n*424
[3.1]
[3.2]
where:
Bit rate is the transmission bit rate, that is the rate of the bit timing.
3.1.1 Setting The Frame Size
We mentioned in Section 2.6 that the emulator has two DIP switches for setting
the frame header length and the number of time slots per frame. These DIP switches are
located on the data and memory control board as shown in Figure 3.1. The DIP switch
on the top right side (SW1) has twelve selectors (SW1-1 to SW1-12) and the second
DIP switch (SW2) has eight selectors (SW2-1 to SW2-8). SW1 is for setting the header
length and SW2 is for the setting number of time slots per frame. After both n and L are
determined, the user can use the tables that are provided with the emulator and set both
DIP switches for the desirable bit rate.
59
SWl
1
-1
SWl
SW2-1
1
SW2
Memory and data control board
Figure 3.1:
Position Of The DIP Switches
3.2 Statistics
To program the loss and delay statistics of the emulator, we need to have a
software driver. In the current implementation a small program was written to test if the
emulator functions properly. The emulator programming is implemented in two steps. In
the first step, the program generates the packet loss and delay statistics according to a
certain probability distribution. The type of the probability distributions is determined by
the user from two choices. The first choice is to create a custom distribution. The user can
specify the delay and the loss probability for each individual packet. The other choice is to
create a uniform distribution. The user can specify the minimum and maximum delay. In
addition the user can specify the loss probability in percentage, that is how many of the
incoming time slots will be discard. In both choices the delay must be between 1 and 127.
Anything else will not be accepted by the program. Also for the custom distribution the
60
loss data must be 0 for drop or 1 for pass. Anything else will be also discarded by the
program.
It is relative easy to modify the existing program in order to add any other
distribution. Unfortunately computers can generate only uniform distributions. Therefore
the future user must design an algorithm for converting the uniform distribution to the
distribution of his/hers desired. There are many books already written on this subject
In the second step, the data are transferred from the host computer to the
emulator. The program creates a single number for the packet delay and loss together.
This number is calculated from the following equation.
Number = 128-(Delay] + 128x[LossJ
[3.3]
where:
Delay is the packet delay in time slots
Loss is the packet loss (l=pass, 0=drop)
We mentioned in Section 2.7 that the size for the packet delay and loss data can be
at the maximum 131,072. If the generated data is less than this maximum number the
program will give a warning to the user if he/she wants to continue. If the answer is yes
any data after the end of the data file will be invalid. There is no way to get the buffer
overflowed because the program does not allow creation of data more than this maximum
size.
61
3.2.1 Download The Data
Figure 3.2 illustrates the flowchart of down loading the delay and loss data to the
emulator. The first step is to initialize the 82SSA. A command word is sent to the chip at
address 303Hex to specify the use of its three ports as discussed in the previous chapter.
After the 8255 is initialized, the Master Reset (8255A Port C-DO) is set LOW until all data
are transferred. This prevents any control signals coming form the control logic section to
interfere with the data transfer. After this, both address generators are reset and the
first byte of data is sent to Port A. After the data appears on Port A, the write strobe
input of both RAMs is taken momentarily
LOW
and data are written into the first
address location. From the write strobe, a pulse is sent to the address generators and
their memory location advances by one. The same procedure
continues until all
data are transferred. After the transfer is completed, the address generators are reset, the
read strobe input is forced to go LOW and the Master Reset is taken HIGH. The emulator
is now ready for emulation.
62
START
INITIALIZE 8255
Master Resets LOW
RESET ADDRESS
GENERATORS
PORT A = DATA
Write Strobe Input
IS TAKEN LOW
AND THEN HIGH
SEND A PULSE TO
THE ADDRESS
GENERATORS
THIS THE \NO
LAST
JT
k DATA?
YES
Read Strobe = LOW
Master Reset = HIGH
END
Figure 3.2:
Flowchart For Downloading The Data.
63
CHAPTER 4
NETWORK EMULATOR TESTING
4.0 Introduction
In the previous chapters, we have discussed in detail the design and programming
of the network emulator. Although every part of the emulator was simulated on a
computer before it was built, a real test is necessary to verify that the emulator meets all
design specifications. This chapter explains the testing and discusses some experimental
results.
4.1 Testing Set Up
For simple and flexible testing we use a computer to generate the necessary timing
and data signals. As illustrated in Figure 4.1, the testbed consists of a test computer and a
computer interface. The computer interface is identical to the one used in the network
emulator. That is, an 82SS I/O chip is used. In this case, Port A is configured as an output
port with output lines Aj, A2 and A3 used as DATAJN, FRAMEJN and CLOCKJN
for the emulator input. Port B is configured as an input Port with Bj, B2 and B3 for
64
DATA_OUT, FRAME_OUT and CLOCK_OUT, respectively. A simple program that
controls the computer interface was also written.
Al
A2
M.
WO
P-.«
Bl
£ M.
M
DATA.IN
FRAME,IN
CLOCK.IN
DATA.OUT
FRAME.OUT
CLOCK.OUT
g
{-J *
hH
TEST COMPUTER
EMULATOR
Testbed
HOST COMPUTER
Figure 4.1:
Testing Set Up.
65
The program reads a pre-written data file and forwards it to port Aj. The data
file has a certain number of lines of 53 characters, with each line representing an ATM
cell. The program reads
the file
character by character and converts each ASCII
character into a binary number, which is sent out to port Aj At the same time, the
program generates the frame timing and clock timing. After a bit is sent out, the
program reads the state of port B and stores the data into an output file. After all the data
in the file are sent out, the program analyzes the output file to extract the data. The
program then converts the received data into characters and displays them on the monitor
screen.
Figure 4.2 shows the transmitted data, i.e. content of the data file. In this example
file, 20 time slots were generated, with 50% of them being active ATM cells. The slots
canying active cells are indicated by the greater sign ">" as their first character. In the
example file, time slots 1, 2, 6, 7, 8, 9, 11, 14, 15, 19 and 20 were set to carry active
packets. The remaining time slots were set to carry no data. In the test, we set two time
slots per frame for simplicity, and the frame header had a length of 74 bits. Table 4.1
shows the statistics used for the packet loss and packet delay. From Table 4.1, we can
see that packets 1, 4, 7 were programmed to be dropped. In addition, packets 2, 3, 5, 6,
8,9,10 and 11 were programmed to have a delay of 2,2,1,3,2,3,2 and 1 respectively.
4.2 Results
The received data from the emulator is shown in Figure 4.3. We can see that
packets 1, 4 and 7 were dropped as programmed. We can also notice that packet 2 is
66
received at time slot 4, which means a delay of two slots. Similarly, packets 3, S, 6, 8, 9,
10 and 11 arrive at time slots 8,9,12,16,19,21,22, which means delays of 2, 1, 3, 2,
3,2, and 1, respectively. These data are consistent with what programmed. Therefore, we
see that the emulator functions properly.
Note that packet 8 appears on time slot 16, two time slots after it entered the FIFO
(time slot 14). Therefore depending on the FIFO occupancy delay works in a different
Transmitted Data
OOOOOOOOOl11111111122222222223333333333444444444«pS5
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
#1 :
«2 :
413 :
#4 :
415 :
416 :
#7 :
418 :
418 :
#10:
4111:
4112:
4113:
4114:
4115:
4116:
4117:
4118:
#19:
#20:
> This is
> This is
This is
This is
This is
> This is
> This is
> This is
> This is
This is
> This is
This is
This is
> This is
> This is
This is
This is
This is
> This is
> This is
slot # 1.
slot • 2.
slot • 3.
slot • 4.
slot 41 5.
slot • 6.
slot • 7.
slot 41 8.
slot • 8.
slot 41 10.
slot 41 11.
slot 41 12.
slot • 13.
slot 41 14.
slot 41 15.
slot 41 18.
slot 41 17.
slot 41 18.
slot 41 18.
slot « 20.
Carrias
Carrias
Carrias
Carries
Carrias
Carries
Carrias
Carrias
Carrias
Carrias
Carries
Carries
Carries
Carries
Carrias
Carries
Carries
Carries
Carries
Carries
packat • 1.
packat • 2.
no packat.
no packat.
no packat.
packet • 3.
packat • 4.
packat 41 5.
packat • 6.
no packat.
packet I 7.
no packat.
no packet.
packet • 8.
packat • 8.
no packet.
no packet.
no packet.
packat 41 10.
packet • 11.
Press any kew to continue
Figure 4.2:
Transmitted Data.
and
and
and
and
and
end
and
and
and
and
end
and
end
end
and
end
end
end
and
end
Loss
Delay
1
0
2
2
1
2
3
0
1
4
0
3
5
1
2
6
1
3
7
0
2
8
1
1
9
1
1
10
1
1
11
0
1
12
0
1
13
0
1
14
1
1
15
1
1
16
1
1
17
1
1
18
0
1
19
1
1
20
1
1
Table 4.1:
Packet Loss/Delay Statistics.
68
Received Data
00000000011
1
o
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
Slot
*1
<12
«3
#4
115
me
»7
<18
«8
mo
<»ii
tt12
*13
*14
<115
<116
<117
<>18
*18
«20
•21
#22
12222222222333333333344444444445555
O
O
O
O
>
This is slot tt
2. Carries packet
»
2.
end
>
>
This is slot *
This is slot <1
6. Carrias packet tt
8. Carries packet tt
3.
5.
end
end
» This is slot
•
8. Carrias packet tt
6.
end
>
This is slot
»
14. Carrias packet tt
8.
end
>
This is slot tt 15. Carries packet tt
8.
end
>
>
This is slot
This is slot
Carrias packet tt 10.
Carries packet tt 11.
end
end
• 19.
• 20.
Pr«m» any kau to cont inua
Figure 4.3:
Transmitted Data.
way. For example, if the FIFO occupancy is not zero at the time the packet enters the
FIFO its delay will count from the time that the last packet leaves the FIFO. On the other
hand, if the FIFO occupancy is zero the delay will count from the same time slot that the
packet originally appears.
69
A timing diagram from a logic analyzer that shows all signals is also shown in
Figure 4.4. These signals are: (1) CLOCK_IN, (2), FRAME_IN, (3) DATA_IN, (4)
CLOCK_OUT, (5) FRAME_OUT, (6) DATA_OUT, and some internal signals such as
(7) Loss, (8) Delay, (9) Write Strobe and (10) Read Strobe.
From this timing diagram, we see that the loss signal is LOW for time slots 1, 3,
4 and 7 as it was programmed (see Table 4.1). For time slot 5, we can see that
although the loss signal is
HIGH,
the write strobe is inactive because the time slot
carries no data. On the other hand side, the write strobe is active for time slot 2,
storing packet 2 in the FIFO. Figure 4.5 shows a zoom-in for time slot 2. In this figure, we
can see that the write strobe consists of 53 write attempts for the 53 bytes in the
packet. Also we can see that there is one byte delay for the first and the last byte in the
packet as explained in Section 2.4.1.
During the time that no packets are coming out from the emulator, DATA_OUT
stays LOW. It is forced LOW by hardware to make sure that only valid data can appear on
the emulator output.
Figure 4.6 shows a zoom-in for time slot 4 where the first packet is read from
the FIFO. Similar to Figure 4.5, we have 53 read attempts. Also due to one byte delay,
the first and last read attempts come one byte before the beginning and end of the time
slot.
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Display IININO 24 CH
Uolti/Bl
Bo^uirc ONCE
Uolt2/Bl
Baoleup Data NO
File fl-T=
Ur it* weimry NO
Utility
Exit
Nova CURSOR B
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CLK IN
Bl_B8
FRflNK IN
DRTR IN
Btja ifjupfiurj
11
CLK OUT
rRflHE OUT BljBS
DflTR OUT Bl_86
LOSS
DELRV
B1JB8
B1_B9
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SLOT N
Bt_15
SLOT H»1 Bt IB
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1 1 ' Slot 1 ' Slot 2 I' Slot 3 ' Slot 4
Slot 9 !Slot 10'
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Clock
INTERNAL
Rat*
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NO
Display TIMII10 24 CH
Rewire ONCE
Backup Data NO
Urit* WHtiru NO
Exit
? Help
CLK IN
B1_00
FRRHE IN Bl_01
DflTB IN
B1JB2
CLK OUT
FRHHI OUT
DATA OUT
LOSS
DELAY
B1 Trt
B1
xxxxxxxx
Triaser Logio TRUE
XXXXXXXX XXXXXX1X
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Uo!«2/Bl
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Hove CURSOR B
I42B47
R-l- 0177.5m
B-I» ®377.7h»
B-T« l2N.2m
B1_M
B1JBS
Bi_JW
B1J8
B1JB9
URITE
REdO
Bl_lt
Bl_12
FRRME
SLOT N
SLOT N*1
B1.M
Bl_15
B1.1S
The first Write Cycle
comes one byte after
the beginning of the
packet
The last Write Cycle
comes one byte after
the end of the packet
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Clock
INTERNRL
10KHZ lflOu*
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NO
Display TIMING 24 CH
Roquire ONCE
Backup Data NO
Urite wenorw NO
Exit
? Help
CLK IN
Bl_08
nm IN B1JB1
DRTR IN
B1JB2
CLK OUT
B1JB4
FRRNE OUT Bl_06
DRTR OUT Bl_06
LOSS
DELR*
Bl_08
URITE
RERD
Bl_ll
Bl_12
FRRHE
SLOT N
SLOT N»1
Bl_14
Bl_15
Bl_16
i
B1 Trigger
xxxxxxxx xxxxxxxx xxxexxxx xxxxxxxx
B1 Search
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
Trigger Logic TRUE
R=00348
Uoltl/Bl
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Uolt2/Bl
•01.4SU
File
Utilitu
Howe CURSOR B
B>02163
T=«0045
R-B= •184.1ns
fl-T- Mt30.3ns
B-T- 0214.4ns
"•in m i
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inim^—
B1_B9
fir* Read Cyclc
One Byte Before
The Start of Tie
Packet
Last Read Cyclc
One Byte Before
The End of The
Packet
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N)
73
CHAPTER 5
CONCLUSIONS AND FUTURE WORK
5.0 Introduction
A packet switching network has a random transmission delay and possible packet
loss for each packet. The loss can be caused by transmission errors in the packet headers
or by collisions in random multiple access. In general, the statistics of transmission delay
and packet loss are highly network dependent. In other words, each network has its
own transmission characteristics.
To emulate an arbitrary packet switching network, the
network emulator
discussed can be programmed with given delay and loss statistics. The user can flexibly
program packet loss according to a certain probability distribution and random delay
according to another distribution. These distributions can be customized or can be any
one of the known distributions such as Poisson, exponential, normal, or uniform. In
the current implementation, an IBM compatible computer is used to generate the statistics
and download them to the emulator.
74
The emulator was tested and found to be functional. The test was performed
using real data at a bit rate determined by the test computer. Although the test bit rate is
low, the emulator is expected to function properly at much higher bit rates. This is
because high speed components have been carefully used and the emulator was built on
a PCB. Our conservative prediction is that the emulator should function properly up to
40Mb/s.
5.1 Future Work
To apply the emulator for various real networks, there are several directions for
future expansion.
•
The first direction is to improve the design so we can use the emulator for higher
speed networks. An optimum speed will be the 150 Mb/s for SONET STS-3.
•
A second direction is to modify the circuit to introduce random or burst errors at
a given BER (Bit Rate Error). Modification from the current implementation
should be simple. We need to build a random generator where we can introduce a
BER up to lO-9.
•
Another direction is to find a way of modeling a practical network from which we
can get the real statistics. This can be done by counting the inter-arrival times from
real transmission. From these real data, we can model the network and generate
the packet loss and packet delay data.
75
Based on the network emulator, we plan to design a programmable real time
video codec. With this programmability, we can study new coding algorithms and
evaluate their performance together with the network emulator. In other words,
we can design the best algorithm for a given network.
76
REFERENCES
[1]
International Standards Organization / International Electrotechnical Commission
DIS 10918-1, "Digital Compression And Coding Of Continues-Tone Still Images"
, Jan. 2, 1992.
[2]
International Standards Organization CD 11172-2, "Coding Of Moving Pictures
And Associated Audio - Part 2", Nov., 1991.
[3]
CCITT Working Party XV/4 on Coding for Visual Telephony, "Draft Revision
For Recommendation H261", Consultative Committee for Telegraphy and
Telephony, Document XV-R 37-E, Aug. 1990.
[4]
Fairchild, "FAST series", data book, 1982.
[5]
John P. Cosmas, "Characterization of Video Codes as Autoregressive Moving
Average Processes and Related Queueing System PerformanceIEEE Journal on
Selected Areas in Communications, Vol 9, No. 3, April 1991.
[6]
CCITT Study Group XVIII Subworking Part 8/1 ATM, "Meeting Report of
Subworking Part 8/1 ATM", Temporary Document, 14-E Question 2/XVm,
Geneva, June 1989.
[7]
Micron Technology Inc., "MOS Data Book", 1991.
[8]
IBM, "Technical Reference Personal Computer AT', 1985.
[9]
Thomas L. Floyd, "Digital Fundamentals", Charles E. Merrill Publishing
Company, 1977.
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