$viewer_title

 SLCS132C − MARCH 1997 − REVISED MAY 1997
D Ultra-Fast Operation . . . 10 ns (typ)
D Low Positive Supply Current
D AND PW PACKAGE
(TOP VIEW)
12.7 mA (Typ)
D Operates From a Single 5-V Supply or From
D
D
D
D
D
D
a Split ± 5-V Supply
Complementary Outputs
Input Common-Mode Voltage Includes
Negative Rail
Low Offset Voltage
No Minimum Slew Rate Requirement
Output Latch Capability
Functional Replacement to the LT1116
VCC+
IN +
IN −
VCC−
8
2
7
3
6
4
5
IN +
Q OUT
Q OUT
IN −
The TL3116 is a pin-for-pin functional replacement for the LT1116 comparator, offering
high-speed operation but consuming much less
power.
AVAILABLE OPTIONS
PACKAGED DEVICES
TSSOP
(PW)
0°C to 70°C
TL3116CD
TL3116CPWLE
−40°C to 85°C
TL3116ID
TL3116IPWLE
CHIP
FORM‡
(Y)
POSITIVE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
ÎÎÎÎÎ
ÎÎÎÎÎ
15
14
I CC − Positive Supply Current − mA
The TL3116 is an ultra-fast comparator designed
to interface directly to TTL logic while operating
from either a single 5-V power supply or dual
± 5-V supplies. The input common-mode voltage
extends to the negative rail for ground sensing
applications. It features extremely tight offset
voltage and high gain for precision applications. It
has complementary outputs that can be latched
using the LATCH ENABLE terminal. Figure 1
shows the positive supply current of the
comparator. The TL3116 only requires 12.7 mA
(typical) to achieve a propagation delay of 10 ns.
SMALL
OUTLINE†
(D)
Q OUT
Q OUT
GND
LATCH ENABLE
symbol (each comparator)
description
TA
1
VCC = ± 5 V
13
12
11
10
9
8
7
6
5
−50
−25
0
25
50
75
100
125
TA − Free-Air Temperature − °C
TL3116Y
Figure 1
—
† The PW packages are available left-ended taped and reeled only.
‡ Chip forms are tested at TA = 25°C only.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1997, Texas Instruments Incorporated
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,-) (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SLCS132C − MARCH 1997 − REVISED MAY 1997
TL3116Y chip information
This chip, when properly assembled, displays characteristics similar to the TL3116C. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
VCC+
(1)
(5)
(1)
(1)
LATCH ENABLE
(8)
(1)
IN+
(7)
IN−
(2)
(2)
+
(3)
−
(8)
Q OUT
(7)
Q OUT
(4)
(6)
VCC −
GND
55
(6)
CHIP THICKNESS: 10 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
(3)
(6)
(5)
(4)
TJ max = 150°C
TOLERANCES ARE ± 10%.
(6)
ALL DIMENSIONS ARE IN MILS.
TERMINALS 1 AND 6 CAN BE
CONNECTED TO MULTIPLE PADS.
63
COMPONENT COUNT
2
Bipolars
53
MOSFETs
49
Resistors
46
Capacitors
14
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• DALLAS, TEXAS 75265
SLCS132C − MARCH 1997 − REVISED MAY 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 7 V to 7 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI (LATCH ENABLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground.
2. Differential voltages are at IN+ with respect to IN −.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
D
725 mW
5.8 mW/°C
464 mW
PW
525 mW
4.2 mW/°C
336 mW
DERATING FACTOR
ABOVE TA = 25°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TA = 70°C
POWER RATING
3
SLCS132C − MARCH 1997 − REVISED MAY 1997
electrical characteristics at specified operating free-air temperature, VDD = ±5 V, VLE = 0 (unless
otherwise noted)
TEST CONDITIONS†
PARAMETER
TL3116C
MIN
TYP‡
MAX
TA = 25°C
TA = full range
0.5
MIN
3
TL3116I
TYP‡
0.5
MAX
3
VIO
Input offset voltage
αVIO
Temperature coefficient
of input offset voltage
Input offset current
TA = 25°C
TA = full range
0.1
IIO
Input bias current
TA = 25°C
TA = full range
0.7
IIB
Common-mode input
voltage range
VDD = ± 5 V
VDD = 5 V
−5
2.5
−5
2.5
VICR
0
2.5
0
2.5
CMRR
Common-mode rejection
ratio
− 5 ≤ VIC ≤ 2.5 V
75
100
75
100
Positive supply: 4.6 V ≤ +VDD ≤ 5.4 V,
TA = 25°C
60
80
60
80
kSVR
Supply-voltage rejection
ratio
Negative supply: − 7 V ≤ −VDD ≤ − 2 V,
TA = 25°C
80
100
80
100
VOL
VOH
Low-level output voltage
High-level output voltage
3.5
Negative supply current
VIL
Low-level input voltage
(LATCH ENABLE)
VIH
High-level input voltage
(LATCH ENABLE)
IIL
Low-level input current
(LATCH ENABLE)
0.1
1.1
0.7
µA
A
µA
A
V
dB
dB
V+ ≤ 4.6 V,
I(sink) = 10 mA,
TA = 25°C
V+ ≤ 4.6 V,
V+ ≤ 4.6 V,
TA = 25°C
IO = 1 mA,
3.6
3.9
3.6
3.9
V+ ≤ 4.6 V,
TA = 25°C
IO = 10 mA,
3.4
3.8
3.4
3.8
400
600
400
600
mV
750
750
V
12.7
14.7
−2.6
12.7
2
VLE = 0
mA
0.8
2
0
• DALLAS, TEXAS 75265
15
−3
0.8
POST OFFICE BOX 655303
1.1
1.5
I(sink) = 4 mA,
TA = 25°C
TA = full range
0.2
0.35
1.2
VLE = 2 V
24
† Full range for the TL3116C is TA = 0°C to 70°C. Full range for the TL3116I is TA = − 40°C to 85°C.
‡ All typical values are measures with TA = 25°C.
4
0.2
mV
µV/°C
−2.8
0.3
Positive supply current
ICC
3.5
−2.5
UNIT
V
V
1
0
1
µA
39
24
45
µA
SLCS132C − MARCH 1997 − REVISED MAY 1997
switching characteristics, VDD = ±5 V, VLE = 0
tpd1
tsk(p)
Propagation delay time‡
Pulse skew (|tpd+ − tpd−|)
TL3116C
TEST CONDITIONS†
PARAMETER
MIN
TL3116I
TYP
MAX
MIN
TYP
MAX
∆VI = 100 mV,
VOD = 5 mV
TA = 25°C
TA = full range
9.9
12
9.9
12
9.9
14
9.9
15
∆VI = 100 mV,
VOD = 20 mV
TA = 25°C
TA = full range
8.2
10.3
8.2
10.3
8.2
12.7
8.2
13.7
∆VI = 100 mV,
TA = 25°C
VOD = 5 mV,
0.5
0.5
UNIT
ns
ns
tsu
Setup time, LATCH ENABLE
3.4
3.4
ns
† Full range for the TL3116C is 0°C to 70°C. Full range for the TL3116I is − 40°C to 85°C.
‡ tpd1 cannot be measured in automatic handling equipment with low values of overdrive. The TL3116 is 100% tested with a 1-V step and 500-mV
overdrive at TA = 25°C only. Correlation tests have shown that tpd1 limits given can be ensured with this test, if additional dc tests are performed
to ensure that all internal bias conditions are correct. For low overdrive conditions, VOS is added to the overdrive.
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
ICC
ICC
tpd
Positive supply current
Negative supply current
Propagation delay time
vs Input voltage
2
vs Frequency
3
vs Free-air temperature
4
vs Free-air temperature
5
vs Overdrive voltage
6
vs Supply voltage
7
vs Input impedance
8
vs Load capacitance
9
vs Free-air temperature
10
VIC
VIT
Common-mode input voltage
vs Free-air temperature
11
Input threshold voltage (LATCH ENABLE)
vs Free-air temperature
12
vs Output source current
13
VO
Output voltage
vs Output sink current
14
II
Input current (LATCH ENABLE)
vs Input voltage
15
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5
SLCS132C − MARCH 1997 − REVISED MAY 1997
TYPICAL CHARACTERISTICS
POSITIVE SUPPLY CURRENT
vs
FREQUENCY
POSITIVE SUPPLY CURRENT
vs
INPUT VOLTAGE
I CC − Positive Supply Current − mA
18
16
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
24
VCC = ± 5 V
TA = 25°C
22
I CC − Positive Supply Current − mA
20
14
TA = 85°C
12
TA = 25°C
10
TA = − 40°C
8
6
4
20
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC = ± 5 V
TA = 25°C
TA = 85°C
18
TA = 25°C
16
14
TA = − 40°C
12
2
10
0
1
2
3
4
5
6
VI − Input Voltage − V
7
101
0
8
f − Frequency − MHz
Figure 2
Figure 3
POSITIVE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
I CC − Positive Supply Current − mA
14
NEGATIVE SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
ÎÎÎÎÎ
0
VCC = ± 5 V
ÎÎÎÎ
ÎÎÎÎ
VCC = ± 5 V
I CC − Negative Supply Current − mA
15
102
13
12
11
10
9
8
7
− 0.5
−1
− 1.5
−2
− 2.5
6
5
−50
−25
0
25
50
75
100
125
−3
−50
−25
TA − Free-Air Temperature − °C
Figure 4
6
0
25
Figure 5
POST OFFICE BOX 655303
50
75
TA − Free-Air Temperature − °C
• DALLAS, TEXAS 75265
100
125
SLCS132C − MARCH 1997 − REVISED MAY 1997
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
OVERDRIVE VOLTAGE
PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
12
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
12
10
VCC = ± 5 V
TA = 25°C
t pd − Propagation Delay Time − ns
t pd − Propagation Delay Time − ns
VCC = ± 5 V
TA = 25°C
8
6
4
2
0
0
10
20
40
30
10
8
6
4
2
0
4.4
50
4.6
4.8
Overdrive Voltage − mV
Figure 6
ÎÎÎÎÎ
ÎÎÎÎÎ
t pd − Propagation Delay Time − ns
t pd − Propagation Delay Time − ns
14
Stepsize = 100 mV
VCC = ± 5 V
TA = 25°C
14
12
5 mV
10
20 mV
8
6
4
12
tPDHL
tPDLH
10
8
6
4
0
50
100
150
200
250
300
0
ÎÎÎÎÎ
ÎÎÎÎÎ
VCC = ± 5 V
TA = 25°C
2
2
0
5.6
PROPAGATION DELAY TIME
vs
LOAD CAPACITANCE
20
16
5.4
Figure 7
PROPAGATION DELAY TIME
vs
INPUT IMPEDANCE
18
5.2
5
VCC − Supply Voltage − V
0
10
ZI − Input Impedance − Ω
20
30
40
50
CL − Load Capacitance − pF
Figure 8
Figure 9
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SLCS132C − MARCH 1997 − REVISED MAY 1997
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
COMMON-MODE INPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
ÎÎÎÎÎ
25
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
6
VCC = 5 V (Upper Limit)
VCC = ± 5 V (Upper Limit)
VIC − Common-Mode Input Voltage − V
t pd − Propagation Delay Time − ns
VCC = ± 5 V
20
15
Rising Edge
10
Falling Edge
5
4
2
ÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎ
0
VCC = 5 V (Lower Limit)
−2
ÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎ
−4
VCC = ± 5 V (Lower Limit)
0
− 50
− 25
0
25
50
75
100
TA − Free-Air Temperature − °C
−6
− 50
125
− 25
75
100
0
25
50
TA − Free-Air Temperature − °C
Figure 10
Figure 11
OUTPUT VOLTAGE
vs
OUTPUT SOURCE CURRENT
ÎÎÎÎ
ÎÎÎÎ
1.8
1.6
1.4
1.2
1
0.8
0.6
4.6
4.4
TA = − 40°C
3.8
3.6
3.2
3
150
0
5
10
Figure 13
POST OFFICE BOX 655303
15
IO(source) − Output Source Current − mA
Figure 12
8
TA = 25°C
4
0.2
0
25
50
75
100 125
TA − Free-Air Temperature − °C
TA = 85°C
4.2
3.4
−25
VCC = ± 5 V
TA = 25°C
4.8
0.4
0
−50
ÎÎÎÎÎ
ÎÎÎÎÎ
5
VCC = ± 5 V
VO − Output Voltage − V
VIT − Input Threshold Voltage (LATCH ENABLE) − V
INPUT THRESHOLD VOLTAGE (LATCH ENABLE)
vs
FREE-AIR TEMPERATURE
2
125
• DALLAS, TEXAS 75265
20
SLCS132C − MARCH 1997 − REVISED MAY 1997
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
OUTPUT SINK CURRENT
1.8
VO − Output Voltage − V
1.6
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
1.4
1.2
TA = 25°C
1
TA = − 40°C
0.8
0.6
TA = 85°C
0.4
0.2
0
0
15
10
IO(sink) − Output Sink Current − mA
5
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
30
VCC = ± 5 V
TA = 25°C
I I − Input Current (LATCH ENABLE) − µ A
2
INPUT CURRENT (LATCH ENABLE)
vs
INPUT VOLTAGE
20
25
VCC = ± 5 V
TA = 25°C
20
15
10
5
0
−5
− 10
− 15
− 20
− 0.5
Figure 14
0
0.5
1
VI − Input Voltage − V
1.5
2
Figure 15
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• DALLAS, TEXAS 75265
9
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL3116CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3116C
TL3116CDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3116C
TL3116CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
3116C
TL3116CPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T3116
TL3116CPWLE
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
TL3116CPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T3116
TL3116ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3116I
TL3116IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3116I
TL3116IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3116I
TL3116IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
3116I
TL3116IPW
ACTIVE
TSSOP
PW
8
150
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z3116
TL3116IPWLE
OBSOLETE
TSSOP
PW
8
TBD
Call TI
Call TI
TL3116IPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z3116
TL3116IPWRG4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
Z3116
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TL3116CDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL3116IDR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL3116CDR
SOIC
D
8
2500
367.0
367.0
38.0
TL3116IDR
SOIC
D
8
2500
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
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EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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