CURRENT MODE PWM CONTROLLER UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5

CURRENT MODE PWM CONTROLLER UC1842/3/4/5 UC2842/3/4/5 UC3842/3/4/5

www.ti.com

UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

CURRENT MODE PWM CONTROLLER

FEATURES

Optimized For Off-line and DC-to-DC

Converters

Low Start-Up Current (<1 mA)

Automatic Feed Forward Compensation

Pulse-by-Pulse Current Limiting

Enhanced Load Response Characteristics

Under-Voltage Lockout With Hysteresis

Double Pulse Suppression

High Current Totem Pole Output

Internally Trimmed Bandgap Reference

500-kHz Operation

Low R

O

Error Amp

DESCRIPTION

The UC1842/3/4/5 family of control devices provides the necessary features to implement off-line or dc-to-dc fixed frequency current mode control schemes with a minimal external parts count.

Internally implemented circuits include under-voltage lockout featuring start up current less than 1 mA, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a PWM comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. The output stage, suitable for driving N-Channel MOSFETs, is low in the off state.

Differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. The UC1842 and UC1844 have UVLO thresholds of 16 V

ON and 10 V

OFF

, ideally suited to off-line applications. The corresponding thresholds for the UC1843 and UC1845 are 8.4 V and 7.6 V.

The UC1842 and UC1843 can operate to duty cycles approaching 100%. A range of zero to 50% is obtained by the UC1844 and UC1845 by the addition of an internal toggle flip flop which blanks the output off every other clock cycle.

BLOCK DIAGRAM

V cc

7 12

UVLO

34 V

S/R

5 V

REF

GROUND

5 9

2.50 V

VREF

Good

Logic

Internal

BIAS

4 7

OSC

R

T

/C

T

Error

Amp

2R

S

V

FB

2 3

R

R

COMP 1 1

1 V

CURRENT

SENSE

COMPARATOR

CURRENT

SENSE

Note 1:

Note 2:

A/B

3 5

A = DIL−8 Pin Number. B = SO−14 and CFP−14 Pin Number.

Toggle flip flop used only in 1844 and 1845.

T

PWM

LATCH

8 14

V

REF

5 V

50 mA

7

V

C

11

6 10

OUTPUT

5 8

POWER

GROUND

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 1997–2007, Texas Instruments Incorporated

2

UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

ABSOLUTE MAXIMUM RATINGS

(1) www.ti.com

Supply voltage

Low impedance source

I

CC

< 30 mA

Output current

Output energy (capacitive load)

Analog inputs (Pins 2, 3)

Error amp output sink current

Power dissipation

Storage temperature range

Junction temperature range

Lead temperature (soldering, 10 seconds)

T

A

25

°

C (DIL-8)

T

A

25

°

C (SOIC-14)

T

A

25

°

C (SOIC-8)

UNIT

30 V

Self Limiting

±

1 A

5

µ

J

–0.3 V to 6.3 V

10 mA

1 W

725 mW

650 mW

–65

°

C to 150

°

C

–55

°

C to 150

°

C

300

°

C

(1) All voltages are with respect to Pin 5. All currents are positive into the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages.

COMP

NC

V

FB

NC

I

SENSE

NC

R

T

/C

T

CONNECTION DIAGRAMS

DIL-8, SOIC-8

N or J PACKAGE, D8 PACKAGE

(TOP VIEW)

PLCC-20

Q PACKAGE

(TOP VIEW)

COMP

V

FB

I

SENSE

R

T

/C

T

1

2

3

4

8

7

6

5

V

REF

V

CC

OUTPUT

GROUND

SOIC-14, CFP-14

D or W PACKAGE

(TOP VIEW)

6

7

4

5

1

2

3

14

13

12

11

10

9

8

V

REF

NC

V

CC

V

C

OUTPUT

GROUND

PWR GND

NC

V

FB

NC

I

SENSE

NC

6

7

4

5

8

3 2 1 20 19

9 10 11 12 13

18

17

16

15

14

V

CC

V

C

NC

OUTPUT

NC

NC − No internal connection

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www.ti.com

UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

DIL-8

SOIC-8

SOIC-14

CFP-14

PLCC-20

PACKAGE

J

N

D8

D14

W

Q

θ

28

JC

(1)

25

42

35

5.49

°

C/W

34

θ

JA

125-160

110

(2)

84-160

(2)

50-120

(2)

175.4C/W

43-75

(2)

(1)

θ

JC data values stated were derived from MIL-STD-1835B.

(2) Specified

θ

JA

(junction to ambient) is for devices mounted to 5 in

2

FR4 PC board with one ounce copper where noted. When resistance range is given, lower values are for 5 in

2

. Test PWB was 0.062 in thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace widths for non-power packages with 100 x 100-mil probe land area at the end of each trace.

DISSIPATION RATINGS

PACKAGE

W

T

A

25

°

C

POWER RATING

700 mW

DERATING FACTOR

ABOVE T

A

25

°

C

5.5 mW/

°

C

T

A

70

°

C

POWER RATING

452 mW

T

A

85

°

CPO

WER RATING

370 mW

T

A

125

°

C

POWER RATING

150 mW

ELECTRICAL CHARACTERISTICS

Unless otherwise stated, these specifications apply for –55

°

C

T

A

125

°

C for the UC184X; –40

°

C

T

A

85

°

C for the

UC284X; 0

°

C

T

A

70

°

C for the 384X; V

CC

= 15 V

(1)

; R

T

= 10 k

; C

T

= 3.3 nF, T

A

= T

J

.

PARAMETER TEST CONDITIONS

UC1842/3/4/5

UC2842/3/4/5

MIN

UC3842/3/4/5

TYP MAX MIN TYP MAX

UNIT

REFERENCE SECTION

Output Voltage

Line Regulation

Load Regulation

Temp. Stability

Total Output Variation

Output Noise Voltage

Long Term Stability

Output Short Circuit

OSCILLATOR SECTION

Initial Accuracy

Voltage Stability

Temp. Stability

Amplitude

T

J

= 25

°

C, I

O

= 1 mA

12

V

IN

25 V

1

I

0

20 mA

See

(2) (3)

Line, load, tempature

(2)

10 Hz

≤ f

10 kHz, T

J

= 25

°

C

(2)

T

A

= 125

°

C, 1000 Hrs

(2)

T

J

= 25

°

C

(4)

12

V

CC

25 V

T

MIN

T

A

T

MAX

(2)

V

PIN

4 peak-to-peak

(2)

4.95

4.9

–30

47

5.00

5.05

4.90

6 20

6

0.2

25

0.4

5.1

4.82

50

5 25

–100 –180 –30

52

0.2%

5%

1.7

57

1%

47

5.00

5.10

6

6

0.2

50

5

20

V mV

25

0.4

mV/

°

C

5.18

25

V

µ

V mV

–100 –180 mA

52

0.2%

5%

1.7

57

1% kHz

V

(1) Adjust V

CC above the start threshold before setting at 15 V.

(2) These parameters, although specified, are not 100% tested in production.

(3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:

Temp Stability

+

V

REF

(max)

TJ(max)

*

*

VREF (min)

TJ (min)

V

REF(max) and V

REF(min) are the maximum and minimum reference voltages measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.

(4) Output frequency equals oscillator frequency for the UC1842 and UC1843.

Output frequency is one half oscillator frequency for the UC1844 and UC1845.

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3

4

UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007 www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated, these specifications apply for –55

°

C

T

A

125

°

C for the UC184X; –40

°

C

T

A

85

°

C for the

UC284X; 0

°

C

T

A

70

°

C for the 384X; V

CC

= 15 V; R

T

= 10 k

; C

T

= 3.3 nF, T

A

= T

J

.

PARAMETER TEST CONDITIONS

UC1842/3/4/5

UC2842/3/4/5

MIN

UC3842/3/4/5

TYP MAX MIN TYP MAX

UNIT

ERROR AMP SECTION

Input Voltage V

PIN 1

= 2.5 V

Input Bias Current

A

VOL

Unity Gain Bandwidth

PSRR

Output Sink Current

Output Source Current

V

OUT

High

V

OUT

Low

CURRENT SENSE SECTION

2

V

O

4 V

T

J

= 25

°

C

(5)

12

V

CC

25 V

V

PIN 2

= 2.7 V, V

PIN 1

= 1.1 V

V

V

PIN 2

PIN 2

= 2.3 V, V

PIN 1

= 2.3 V, R

L

V

PIN 2

= 2.7 V, R

L

= 5 V

= 15 k

Ω to ground

= 15 k

Ω to Pin 8

Gain

Maximum Input Signal

PSRR

Input Bias Current

See

(6) (7)

V

PIN 1

= 5 V

(6)

12

V

CC

25 V

(5) (6)

Delay to Output

OUTPUT SECTION

V

PIN 3

= 0 V to 2 V

(5)

Output Low Level

I

SINK

= 20 mA

I

SINK

= 200 mA

I

SOURCE

= 20 mA

Output High Level

Rise Time

Fall Time

I

SOURCE

= 200 mA

T

J

= 25°C, C

L

= 1 nF

T

J

= 25

°

C, C

L

= 1nF

(5)

(5)

UNDER-VOLTAGE LOCKOUT SECTION

X842/4

Start Threshold

X843/5

Min. Operating Voltage After

Turn On

X842/4

X843/5

PWM SECTION

Maximum Duty Cycle

X842/3

X844/5

Minimum Duty Cycle

TOTAL STANDBY CURRENT

Start-Up Current

Operating Supply Current

V

CC

Zener Voltager I

V

PIN 2

CC

= V

PIN 3

= 25 mA

= 0 V

2.45

65

0.7

60

2

–0.5

5

2.85

0.9

13

12

15

7.8

9

7.0

95%

46%

30

0.1

1.5

13.5

13.5

50

50

70

6

–0.8

6

0.7

2.50

2.55

2.42

–0.3

–1

90

1

65

0.7

60

2

–0.5

5

1.1

16

8.4

10

7.6

70

–2

150

3 3.15

2.85

1 1.1

0.9

–10

300

0.5

11

34

0.4

2.2

150

150

1

17

13

12

17 14.5

9.0

7.8

11

8.2

8.5

7.0

97% 100% 95%

48% 50% 47%

0%

30

0.1

1.5

13.5

13.5

50

50

2.50

2.58

–0.3

–2

90

1

70

6

–0.8

6

0.7

1.1

70

–2

150

3 3.15

1 1.1

–10

300

16 17.5

8.4

9.0

10 11.5

7.6

8.2

97% 100%

48% 50%

0%

0.5

11

34

0.4

2.2

150

150

1

17

V

µ

A dB

MHz dB mA

V

V/V

V dB

µ

A ns

V ns

V mA

V

(5) These parameters, although specified, are not 100% tested in production.

(6) Parameter measured at trip point of latch with V

PIN 2

(7) Gain defined as:

A

+

D VPIN 1

D VPIN 3

, 0 v

VPIN 3 v

0.8 V

= 0.

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UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007 www.ti.com

ERROR AMP CONFIGURATION

Error amp can source or sink up to 0.5 mA.

2.5 V

0.5 mA

+

Z

I

Z

F

V

FB

2

COMP

1

_

UNDER-VOLTAGE LOCKOUT

During under-voltage lock-out, the output drive is biased to sink minor amounts of current. Pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents.

V

CC

V

CC

7 ON/OFF Command to REST of IC

V

ON

V

OFF

UC1842

UC1844

16 V

10 V

UC1843

UC1845

8.4 V

7.6 V

<17 mA

<1 mA

V

OFF

V

ON

CURRENT SENSE CIRCUIT

A small RC filter may be required to suppress switch transients.

ERROR

AMP

2R

I

S

R

R

R

S

C

5

1

COMP

3

CURRENT

SENSE

GND

5

Peak Current (I

S

) is Determined By The Formula

I

SMAX

,1.0 V

RS

1 V

CURRENT

SENSE

COMPARATOR

V

CC

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5

6

UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

OSCILLATOR SECTION

V

REF

8

R

T

30

Deadtime vs C

T

(R

T

>5 k

W

)

R

T

/C

T

4

10

C

T

GROUND

5

For R

T

> 5 K f ~

1.72

R

T

C

T t d

3

1

0.3

1 2.2

4.7

10 22 47 100

C

T

− nF

OUTPUT SATURATION CHARACTERISTICS

4

V

CC

= 15 V

100

Timing Resistance vs Frequency

30

10 www.ti.com

3

100 1 k 10 k 100 k f − Frequency − Hz

1 M

3

T

A

= 25

°

C

T

A

= −55

°

C

2

1

SOURCE SAT

(V

CC −

V

OH)

SINK SAT (V

OL

)

0

.01

.02

.03 .04 .05

.07 .1

.2

.3 .4 .5

.7

1

Output Current, Source or Sink − A

ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE

80

60

40

20

0

Av

10 100 1 k 10 k

f − Frequency − Hz

100 k 1 M 10 M

θ

0

−45

−90

−135

−180

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UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

OPEN-LOOP LABORATORY FIXTURE

High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypas capacitors should be conected close to pin 5 in a single point ground. The transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3.

V

REF

R1

4.7 k

W

2N2222

100 k

W

UC1842

A V

CC

1

COMP

V

REF

8

0.1

m

F

1 k

W

ERROR AMP

ADJUST

4.7 k

W

5 k

W

I

SENSE

ADJUST

2 V

FB

3

I

SENSE

V

CC

7

OUTPUT 6

0.1

m

F

1 k

W

1 W

OUTPUT

4 R

T

/ C

T

GROUND

5

GROUND

C

T

SHUTDOWN TECHNIQUES

Shutdown of the UC1842 can be accomplished by two methods; either raise pin 3 above 1 V or pull pin 1 below a voltage two diode drops above ground. Either method causses the output of the PWM comparator to be high

(refer to block diagram). The PWM latch is reset dominant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR which will be reset by cycling V this pint the reference turns off, allowing the SCR to reset.

CC below the lower UVLO threshold. At

1 k

W

8

V

REF

1

COMP

SHUTDOWN

SHUTDOWN

330

W

500

W

3

I

SENSE

To Current

SENSE RESISTOR

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7

8

UC1842/3/4/5

UC2842/3/4/5

UC3842/3/4/5

SLUS223C – APRIL 1997 – REVISED JUNE 2007

OFFLINE FLYBACK REGULATOR

R1

5

1 W

117 VAC

VARO

VM 68

C1

250

µ

F

250 V

R2

56 k

2 W

R12

4.7 k

2 W

C9

3300 pF

600 V

N

P

D4

1N3613

R4

4.7 k

R3

20 k

D2

1N3612

D3

1N3612

2

1

7

R5 150 k

C14

C5

0.01

µ

F

100 pF

8

R6

10 k

C6

0.0022

µ

F

4

UC3844

5

6

3

C2

100

µ

F

25 V

22

C3

µ

F

USD1120

R9

68

3 W

R7

22

R8

1 k

C7

470 pF

C4

47

µ

F

25 V

R13

20 k

NC

T1

Q1

UFN833

R10

0.55

1 W

D6

U9D946

N5

C10

4700

µ

F

10 V

D7

UF81002

N12

N12

D8

UES1002

L1

C12

2200

µ

F

16 V

C13

2200

µ

F

16 V

C11

4700

µ

F

10 V

www.ti.com

C8

680 pF

600 V

D8

1N3613

R11

2.7 k

2 W

+6 V

COM

+12 V

±

12 V COM

−12 V

Power Supply Specifications

1. Input Voltages a.

5VAC to 130VA (50 Hz/60 Hz)

2. Line Isolation: 3750 V

3. Switchng Frequency: 40 kHz

4. Efficiency at Full Load 70%

5. Output Voltage: a.

+5 V,

±

5%; 1A to 4A load

Ripple voltage: 50 mV P-P Max b.

+12 V,

±

3%; 0.1A to 0.3A load

Ripple voltage: 100 mV P-P Max c.

–12 V,

±

3%; 0.1A to 0.3A load

Ripple voltage: 100 mV P-P Max

SLOPE COMPENSATION

A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%.

V

REF

8

0.1

m

F

R

T

R

T

/ C

T

4

UC1842/3

I

SENSE

3

C

T

R1

R2

C

I

SENSE

R

SENSE

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PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device

5962-8670401PA

Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

CDIP JG 8 1

Eco Plan

(2)

TBD

5962-8670401VPA ACTIVE CDIP JG 8 1 TBD

5962-8670401VXA ACTIVE LCCC FK 20 1 TBD

5962-8670401XA

5962-8670402PA

5962-8670402XA

5962-8670403PA

5962-8670403VPA

5962-8670403VXA

5962-8670403XA

5962-8670404DA

5962-8670404PA

5962-8670404VPA

ACTIVE LCCC

ACTIVE

ACTIVE

CDIP

LCCC

ACTIVE

ACTIVE

ACTIVE

CDIP

CDIP

LCCC

ACTIVE LCCC

ACTIVE

ACTIVE

ACTIVE

CFP

CDIP

CDIP

FK 20 1

JG

FK

8

20

1

1

JG

JG

FK

8

8

20

1

1

1

FK 20 1

W

JG

JG

14

8

8

1

1

1

8-Nov-2014

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

Lead/Ball Finish

(6)

A42

A42

POST-PLATE

POST-PLATE

A42

POST-PLATE

A42

A42

POST-PLATE

POST-PLATE

A42

A42

A42

MSL Peak Temp

(3)

N / A for Pkg Type

Op Temp (°C)

-55 to 125

N / A for Pkg Type -55 to 125

N / A for Pkg Type -55 to 125

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

Device Marking

(4/5)

8670401PA

UC1842

8670401VPA

UC1842

5962-

8670401VXA

UC1842L

QMLV

5962-

8670401XA

UC1842L/

883B

8670402PA

UC1843

5962-

8670402XA

UC1843L/

883B

8670403PA

UC1844

8670403VPA

UC1844

5962-

8670403VXA

UC1844L

QMLV

5962-

8670403XA

UC1844L/

883B

5962-8670404DA

UC1845W/883B

8670404PA

UC1845

8670404VPA

UC1845

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device

5962-8670404VXA

5962-8670404XA

UC1842J

UC1842J883B

UC1842L883B

UC1842W

UC1843J

UC1843J883B

UC1843L

UC1843L883B

UC1843W

UC1844J

UC1844J883B

UC1844L883B

UC1845J

Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

LCCC FK 20 1

Eco Plan

(2)

TBD

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

LCCC

CDIP

CDIP

LCCC

CFP

CDIP

CDIP

LCCC

LCCC

CFP

CDIP

CDIP

LCCC

CDIP

FK

JG

JG

FK

W

JG

JG

FK

FK

W

JG

JG

FK

JG

20

8

8

20

14

8

8

20

20

14

8

8

20

8

1

1

1

1

1

1

1

1

1

1

1

1

1

1

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

TBD

8-Nov-2014

Lead/Ball Finish

(6)

POST-PLATE

POST-PLATE

A42

A42

POST-PLATE

A42

A42

A42

POST-PLATE

POST-PLATE

A42

A42

A42

POST-PLATE

A42

MSL Peak Temp

(3)

N / A for Pkg Type

Op Temp (°C)

-55 to 125

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

-55 to 125

8670402PA

UC1843

UC1843L

5962-

8670402XA

UC1843L/

883B

UC1843W

UC1844J

8670403PA

UC1844

5962-

8670403XA

UC1844L/

883B

UC1845J

Device Marking

(4/5)

5962-

8670404VXA

UC1845L

QMLV

5962-

8670404XA

UC1845L/

883B

UC1842J

8670401PA

UC1842

5962-

8670401XA

UC1842L/

883B

UC1842W

UC1843J

Addendum-Page 2

Samples

PACKAGE OPTION ADDENDUM

UC1845W

UC1845W883B

UC2842D

UC2842D8

UC2842D8G4

UC2842D8TR

UC2842D8TRG4

UC2842DG4

UC2842DTR

UC2842J

UC2842N

UC2842NG4

UC2843D

UC2843D8

UC2843D8G4 www.ti.com

Orderable Device

UC1845J883B

UC1845L

UC1845L883B

8-Nov-2014

SOIC

SOIC

SOIC

SOIC

SOIC

CDIP

PDIP

PDIP

CFP

CFP

SOIC

SOIC

SOIC

SOIC

SOIC

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

OBSOLETE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

CDIP JG 8 1

ACTIVE

ACTIVE

LCCC

LCCC

FK

FK

20

20

1

1

Eco Plan

(2)

TBD

TBD

TBD

D

D

D

D

D

JG

P

P

D

D

W

W

D

D

D

14

14

14

8

8

14

8

8

14

8

8

14

8

8

8

1

1

TBD

TBD

50

75

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

75 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

TBD

50

50

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

50

75

75

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Addendum-Page 3

A42

A42

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Call TI

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Lead/Ball Finish

(6)

A42

POST-PLATE

POST-PLATE

MSL Peak Temp

(3)

N / A for Pkg Type

Op Temp (°C)

-55 to 125

N / A for Pkg Type

N / A for Pkg Type

-55 to 125

-55 to 125

N / A for Pkg Type

N / A for Pkg Type

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Call TI

N / A for Pkg Type

N / A for Pkg Type

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

-55 to 125

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

Device Marking

(4/5)

8670404PA

UC1845

UC1845L

5962-

8670404XA

UC1845L/

883B

UC1845W

5962-8670404DA

UC1845W/883B

UC2842D

UC2842

D8

UC2842

D8

UC2842

D8

UC2842

D8

UC2842D

UC2842D

UC2842N

UC2842N

UC2843D

UC2843

D8

UC2843

D8

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device

UC2843D8TR

UC2843D8TRG4

UC2843DG4

UC2843DTR

UC2843DTRG4

UC2843J

UC2843N

UC2843NG4

UC2844D

UC2844D8

UC2844D8G4

UC2844D8TR

UC2844D8TRG4

UC2844DG4

UC2844DTR

UC2844DTRG4

UC2844N

UC2844NG4

8-Nov-2014

Status

(1)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

OBSOLETE

ACTIVE

ACTIVE

Package Type Package

Drawing

SOIC

SOIC

SOIC

SOIC

D

D

D

D

Pins Package

8

8

14

14

Qty

Eco Plan

(2)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

SOIC D 14

CDIP

PDIP

PDIP

JG

P

P

8

8

8

2500 Green (RoHS

& no Sb/Br)

TBD

50

50

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

ACTIVE SOIC D 14

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

PDIP

PDIP

D

D

D

D

D

D

D

P

P

8

8

8

8

14

14

14

8

8

50

75

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

75 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50

50

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Lead/Ball Finish

(6)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Call TI

CU NIPDAU

CU NIPDAU

MSL Peak Temp

(3)

Level-1-260C-UNLIM

Op Temp (°C)

-40 to 85

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

-40 to 85

-40 to 85

-40 to 85

Level-1-260C-UNLIM

Call TI

N / A for Pkg Type

N / A for Pkg Type

-40 to 85

-40 to 85

-40 to 85

-40 to 85

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

N / A for Pkg Type

N / A for Pkg Type

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

-40 to 85

UC2843N

UC2843N

UC2844D

UC2844

D8

UC2844

D8

UC2844

D8

UC2844

D8

UC2844D

UC2844D

UC2844D

UC2844N

UC2844N

Device Marking

(4/5)

UC2843

D8

UC2843

D8

UC2843D

UC2843D

UC2843D

Samples

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device

UC2845D

UC2845D8

UC2845D8G4

UC2845D8TR

UC2845D8TRG4

UC2845DG4

UC2845DTR

UC2845DTRG4

UC2845J

UC2845N

UC2845NG4

UC3842D

UC3842D8

UC3842D8G4

UC3842D8TR

UC3842D8TRG4

UC3842DG4

UC3842DTR

8-Nov-2014

Status

(1)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

OBSOLETE

ACTIVE

ACTIVE

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

SOIC

SOIC

SOIC

SOIC

D

D

D

D

14

8

8

8

50

75

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

75 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

SOIC D 8

SOIC

SOIC

SOIC

CDIP

PDIP

PDIP

SOIC

D

D

D

JG

P

P

D

14

14

14

8

8

8

14

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50

50

50

TBD

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

D

D

D

D

D

D

8

8

8

8

14

14

75

75

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

Call TI

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Lead/Ball Finish

(6)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

MSL Peak Temp

(3)

Level-1-260C-UNLIM

Op Temp (°C)

-40 to 85

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

-40 to 85

-40 to 85

-40 to 85

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

-40 to 85

-40 to 85

-40 to 85

-40 to 85

Call TI

N / A for Pkg Type

N / A for Pkg Type

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

-40 to 85

-40 to 85

-40 to 85

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

UC2845N

UC2845N

UC3842D

UC3842

D8

UC3842

D8

UC3842

D8

UC3842

D8

UC3842D

UC3842D

Device Marking

(4/5)

UC2845D

UC2845

D8

UC2845

D8

UC2845

D8

UC2845

D8

UC2845D

UC2845D

UC2845D

Samples

Addendum-Page 5

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device

UC3842N

UC3842NG4

UC3843D

UC3843D8

UC3843D8G4

UC3843D8TR

UC3843D8TRG4

UC3843DG4

UC3843DTR

UC3843DTRG4

UC3843N

UC3843NG4

UC3843QTR

UC3844D

UC3844D8

UC3844D8G4

UC3844D8TR

UC3844D8TRG4

8-Nov-2014

Status

(1)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

OBSOLETE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

PDIP

PDIP

SOIC

SOIC

P

P

D

D

8

8

14

8

50

50

50

75

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

SOIC D 8

SOIC

SOIC

SOIC

SOIC

SOIC

PDIP

PDIP

D

D

D

D

D

P

P

8

8

14

14

14

8

8

75 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

PLCC

SOIC

SOIC

SOIC

SOIC

SOIC

FN

D

D

D

D

D

20

14

8

8

8

8

50

75

75

TBD

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Call TI

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Lead/Ball Finish

(6)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

MSL Peak Temp

(3)

N / A for Pkg Type

Op Temp (°C)

0 to 70

N / A for Pkg Type

Level-1-260C-UNLIM

Level-1-260C-UNLIM

0 to 70

0 to 70

0 to 70

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

0 to 70

0 to 70

0 to 70

0 to 70

Level-1-260C-UNLIM

Level-1-260C-UNLIM

N / A for Pkg Type

N / A for Pkg Type

Call TI

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

Device Marking

(4/5)

UC3842N

UC3842N

UC3843D

UC3843

D8

UC3843

D8

UC3843

D8

UC3843

D8

UC3843D

UC3843D

UC3843D

UC3843N

UC3843N

UC3844D

UC3844

D8

UC3844

D8

UC3844

D8

UC3844

D8

Samples

Addendum-Page 6

PACKAGE OPTION ADDENDUM

www.ti.com

8-Nov-2014

Orderable Device

UC3844DG4

UC3844DTR

UC3844DTRG4

UC3844N

UC3844NG4

UC3845AJ

Status

(1)

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

Package Type Package

Drawing

SOIC

SOIC

D

D

Pins Package

14

14

Qty

Eco Plan

(2)

50 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

SOIC

PDIP

D

P

14

8

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

PDIP

CDIP

P

JG

8

8

50

1

Green (RoHS

& no Sb/Br)

TBD

Lead/Ball Finish

(6)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

A42

MSL Peak Temp

(3)

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

N / A for Pkg Type

N / A for Pkg Type

N / A for Pkg Type

Op Temp (°C)

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

UC3845D

UC3845D8

UC3845D8G4

UC3845D8TR

UC3845D8TRG4

UC3845DG4

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

ACTIVE

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

D

D

D

D

D

D

14

8

8

8

8

14

50

75

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

75 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

CU NIPDAU

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

Level-1-260C-UNLIM

UC3845DTR

UC3845DTRG4

UC3845N

ACTIVE

ACTIVE

ACTIVE

SOIC

SOIC

PDIP

D

D

P

14

14

8

2500 Green (RoHS

& no Sb/Br)

2500 Green (RoHS

& no Sb/Br)

50 Green (RoHS

& no Sb/Br)

CU NIPDAU

CU NIPDAU

CU NIPDAU

Level-1-260C-UNLIM

Level-1-260C-UNLIM

N / A for Pkg Type

UC3845NG4 ACTIVE PDIP P 8 50 Green (RoHS

& no Sb/Br)

CU NIPDAU N / A for Pkg Type

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

0 to 70

Device Marking

(4/5)

UC3844D

UC3844D

UC3844D

UC3844N

UC3844N

UC3845AJ

UC3845D

UC3845

D8

UC3845

D8

UC3845

D8

UC3845

D8

UC3845D

UC3845D

UC3845D

UC3845N

UC3845N

Addendum-Page 7

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

8-Nov-2014

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UC1842, UC1842-SP, UC1843, UC1844, UC1844-SP, UC1845, UC1845-SP, UC3842, UC3843, UC3844, UC3845, UC3845AM :

Catalog: UC3842 , UC1842 , UC3843 , UC3844 , UC1844 , UC3845 , UC1845 , UC3842M , UC3845A

Military: UC1842 , UC1843 , UC1844 , UC1845

• Space: UC1842-SP , UC1843-SP , UC1844-SP , UC1845-SP

NOTE: Qualified Version Definitions:

Addendum-Page 8

www.ti.com

Catalog - TI's standard catalog product

Military - QML certified for Military and Defense Applications

Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

PACKAGE OPTION ADDENDUM

8-Nov-2014

Addendum-Page 9

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

19-Mar-2008

*All dimensions are nominal

Device

UC2842D8TR

UC2842DTR

UC2843D8TR

UC2843DTR

UC2844D8TR

UC2844DTR

UC2845D8TR

UC2845DTR

UC3842D8TR

UC3842DTR

UC3843D8TR

UC3843DTR

UC3844D8TR

UC3844DTR

UC3845D8TR

UC3845DTR

Package

Type

Package

Drawing

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

Pins

8

14

8

14

8

14

8

14

8

14

8

14

8

14

8

14

SPQ

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

330.0

330.0

330.0

330.0

330.0

330.0

330.0

330.0

330.0

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

12.4

330.0

330.0

16.4

12.4

330.0

330.0

330.0

330.0

16.4

12.4

16.4

12.4

16.4

12.4

16.4

12.4

16.4

12.4

16.4

12.4

16.4

A0 (mm)

6.5

6.4

6.5

6.4

6.5

6.5

6.4

6.5

6.4

6.4

6.5

6.4

6.5

6.4

6.5

6.4

B0 (mm)

9.0

5.2

9.0

5.2

9.0

9.0

5.2

9.0

5.2

5.2

9.0

5.2

9.0

5.2

9.0

5.2

K0 (mm) P1

(mm)

W

(mm)

Pin1

Quadrant

2.1

2.1

2.1

2.1

2.1

2.1

2.1

2.1

2.1

2.1

2.1

2.1

2.1

2.1

2.1

2.1

8.0

8.0

8.0

8.0

8.0

8.0

8.0

8.0

8.0

8.0

8.0

8.0

8.0

8.0

8.0

8.0

16.0

12.0

16.0

12.0

16.0

12.0

16.0

12.0

16.0

12.0

16.0

12.0

16.0

12.0

16.0

12.0

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Q1

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

19-Mar-2008

*All dimensions are nominal

Device

UC2842D8TR

UC2842DTR

UC2843D8TR

UC2843DTR

UC2844D8TR

UC2844DTR

UC2845D8TR

UC2845DTR

UC3842D8TR

UC3842DTR

UC3843D8TR

UC3843DTR

UC3844D8TR

UC3844DTR

UC3845D8TR

UC3845DTR

Package Type Package Drawing Pins

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

SOIC

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

D

8

14

8

14

8

8

14

8

14

14

8

14

14

8

14

8

SPQ

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

2500

Length (mm) Width (mm) Height (mm)

340.5

333.2

340.5

333.2

340.5

333.2

340.5

333.2

340.5

333.2

340.5

333.2

340.5

333.2

340.5

333.2

338.1

345.9

338.1

345.9

338.1

345.9

338.1

345.9

338.1

345.9

338.1

345.9

338.1

345.9

338.1

345.9

20.6

28.6

20.6

28.6

20.6

28.6

20.6

28.6

20.6

28.6

20.6

28.6

20.6

28.6

20.6

28.6

Pack Materials-Page 2

JG (R-GDIP-T8)

0.063 (1,60)

0.015 (0,38)

0.100 (2,54)

8

0.400 (10,16)

0.355 (9,00)

5

1

0.280 (7,11)

0.245 (6,22)

4

0.065 (1,65)

0.045 (1,14)

0.020 (0,51) MIN

0.200 (5,08) MAX

Seating Plane

0.130 (3,30) MIN

0.023 (0,58)

0.015 (0,38)

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

CERAMIC DUAL-IN-LINE

0.310 (7,87)

0.290 (7,37)

0

°

–15

°

0.014 (0,36)

0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

MECHANICAL DATA

MPLC004A – OCTOBER 1994

PLASTIC J-LEADED CHIP CARRIER FN (S-PQCC-J**)

20 PIN SHOWN

3

D

D1

1 19

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

0.032 (0,81)

0.026 (0,66)

4 18

D2 / E2

E E1

D2 / E2

8 14

9 13

0.050 (1,27)

0.008 (0,20) NOM

0.021 (0,53)

0.013 (0,33)

0.007 (0,18)

M

NO. OF

PINS

**

52

68

84

20

28

44

D / E D1 / E1 D2 / E2

MIN MAX MIN MAX MIN MAX

0.385 (9,78)

0.485 (12,32)

0.395 (10,03)

0.495 (12,57)

0.350 (8,89)

0.450 (11,43)

0.356 (9,04)

0.456 (11,58)

0.685 (17,40)

0.785 (19,94)

0.695 (17,65)

0.795 (20,19)

0.650 (16,51)

0.750 (19,05)

0.656 (16,66)

0.756 (19,20)

0.985 (25,02)

1.185 (30,10)

0.995 (25,27)

1.195 (30,35)

0.950 (24,13)

1.150 (29,21)

0.958 (24,33)

1.158 (29,41)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.441 (11,20)

0.541 (13,74)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.469 (11,91)

0.569 (14,45)

4040005 / B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

1

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