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bq24640
SLUSA44A – MARCH 2010 – REVISED JULY 2015
bq24640 High-Efficiency Synchronous Switched-Mode Super Capacitor Charger
1 Features
2 Applications
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
Charge Super Capacitor Pack From 2.1 V to 26 V
CC/CV Charge Profile From 0 V Without
Precharge
600-kHz NMOS-NMOS Synchronous Buck
Controller
Over 90% Efficiency for up to 10-A Charge
Current
5-V to 28-V VCC Input Voltage Range
Accuracy
– ±0.5% Charge Voltage Regulation
– ±3% Charge Current Regulation
High Integration
– Internal Loop Compensation
– Internal Digital Soft Start
Safety
– Input Overvoltage Protection
– Capacitor Temperature Sensing Hot and Cold
Charge Suspend
– Thermal Shutdown
Status Outputs
– Adapter Present
– Charger Operation Status
Charge Enable Pin
30-ns Driver Dead Time and 99.5% Maximum
Effective Duty Cycle
Automatic Sleep Mode for Low Power
Consumption
– <15-µA Off-State Super Capacitor Discharge
Current
– <1.5-mA Off-State Input Quiescent Current
•
Memory Backup Systems
Industrial UPS Systems and Power Transient
Buffering
Bridge Power to Buffer the Battery
3 Description
The bq24640 device is a highly integrated switchedmode super capacitor charge controller. The device
offers a constant-frequency synchronous PWM
controller with high accuracy charge current, voltage
regulation, and charge status monitoring.
The bq24640 charges a super capacitor in two
phases: constant current and constant voltage
(CC/CV). The device can charge super capacitors
from 0 V with current set on the ISET pin. When the
super capacitor voltage reaches the programmed
target voltage, charge current begins tapering down.
The bq24640 enters a low-current sleep mode
(<15 μA) when the input voltage falls below the
output capacitor voltage.
The bq24640 has an input CE pin to enable and
disable charge, and the STAT and PG output pins
report charge and adapter status. The TS pin on the
bq24640 monitors the temperature of the capacitor
and suspends charge during hot and cold conditions.
Device Information(1)
PART NUMBER
bq24640
PACKAGE
VQFN (16)
BODY SIZE (NOM)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
ADAPTER
CE
VREF
HIDRV
ISET
bq24640
STAT
PH
LODRV
Super
Cap
ADAPTER
PG
VREF
SRP
SRN
VFB
TS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24640
SLUSA44A – MARCH 2010 – REVISED JULY 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
4
4
5
5
5
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 10
7.1 Overview ................................................................. 10
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 17
9 Power Supply Recommendations...................... 21
10 Layout................................................................... 21
10.1 Layout Guidelines ................................................. 21
10.2 Layout Examples................................................... 22
11 Device and Documentation Support ................. 23
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
23
23
23
23
23
23
12 Mechanical, Packaging, and Orderable
Information ........................................................... 23
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2010) to Revision A
•
2
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
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5 Pin Configuration and Functions
BTST
HIDRV
PH
LODRV
RVA Package
16-Pin VQFN With Exposed Thermal Pad
Top View
16
15
14
13
REGN
CE 2
11
GND
STAT 3
10
SRP
TS 4
9
SRN
6
7
8
VFB
PG
5
ISET
12
VREF
VCC 1
Pin Functions
PIN
TYPE (1)
DESCRIPTION
NAME
NO.
BTST
16
P
PWM high-side driver positive supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST.
CE
2
I
Charge enable, active HIGH logic input. HI enables charge, and LO disables charge. Connect to pullup rail
with 10-kΩ resistor. It has an internal 1-MΩ pulldown resistor.
GND
11
P
Low-current sensitive analog/digital ground. On PCB layout, connect with thermal pad underneath the IC.
HIDRV
15
O
PWM high-side driver output. Connect to the gate of the high-side N-channel power MOSFET with a short
trace.
ISET
7
I
ICHG =
LODRV
13
O
PWM low-side driver output. Connect to the gate of the low-side N-channel power MOSFET with a short
trace.
PG
5
O
Open-drain active-low adapter status output. Connect to pullup rail through LED and 10-kΩ resistor. The LED
turns on when a valid is detected, and off in the sleep mode.
PH
14
P
Switching node, charge current output inductor connection. Connect the 0.1-μF bootstrap capacitor from PH
to BTST.
REGN
12
P
PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to GND pin
close to the IC. Use for low-side driver and high-side driver bootstrap voltage by small signal Schottky diode
from REGN to BTST.
SRN
9
I
Charge current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from SRN pin to GND for
common-mode filtering.
SRP
10
P/I
Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to
provide differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to GND for commonmode filtering.
STAT
3
O
Open-drain charge status output to indicate various charger operation. Connect to the pullup rail through the
LED and 10-kΩ (see Table 4).
TS
4
I
Temperature qualification voltage input for negative temperature coefficient thermistor. Program the hot and
cold temperature window with a resistor-divider from VREF to TS to GND. Recommend SEMITEC 103AT-2
10-kΩ thermister.
Charge current set point. The voltage is set through a voltage divider from VREF to ISET and to GND.
(1)
VISET
20 ´ RSR
P - Power, I - Input, O - Output
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
VCC
1
P
IC power positive supply. Connect through a 10-Ω resistor to the cathode of input diode. Place a 1-μF ceramic
capacitor from VCC to GND and place it as close as possible to IC to filter out the noise.
VFB
8
I
Charge voltage analog feedback adjustment. Connect a resistor divider from output to VFB to GND to adjust
the output voltage. The internal regulation limit is 2.1V.
VREF
6
P
3.3-V reference voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This
voltage could be used for programming charge current regulation on ISET and for thermal threshold on TS. It
can be used as the pullup rail of STAT, and PG.
—
Exposed pad beneath the IC. Always solder thermal pad to the board, and have vias on the thermal pad
plane star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal
pad to dissipate the heat.
Thermal pad
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC, SRP, SRN, STAT, PG, CE
MIN
MAX
–0.3
33
–2
33
PH
Voltage
(2)
Maximum
difference voltage
Temperature
(1)
(2)
(3)
VFB
(3)
–0.3
16
REGN, LODRV, TS
–0.3
7
BTST, HIDRV with respect to GND
–0.3
39
VREF, ISET
–0.3
3.6
–0.5
0.5
Junction, TJ
–40
155
Storage, Tstg
–55
155
SRP–SRN
UNIT
V
V
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult the
Package Option Addendum at the end of the data sheet for thermal limitations and considerations.
Must have a series resistor between output to VFB if output voltage is expected to be greater than 16 V. Usually the resistor-divider top
resistor will take care of this.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
4
Electrostatic discharge
(1)
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±2000
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC, SRP, SRN, STAT, PG, CE
PH
Voltage
(with respect to GND)
MIN
MAX
–0.3
28
–2
30
VFB
–0.3
14
REGN, LODRV, TS
–0.3
6.5
BTST, HIDRV with respect to GND
–0.3
34
ISET
–0.3
3.3
VREF
Maximum difference voltage
UNIT
V
3.3
SRP–SRN
Junction temperature, TJ
–0.2
0.2
V
0
125
°C
6.4 Thermal Information
bq24640
THERMAL METRIC (1)
RVA (VQFN)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
43.8
°C/W
RθJC(top)
Junction-to-case(top) thermal resistance
81
°C/W
RθJB
Junction-to-board thermal resistance
16
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
15.77
°C/W
RθJC(bot)
Junction-to-case(bottom) thermal resistance
4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
5 V ≤ V(VCC) ≤ 28 V, 0°C < T < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VVCC_OP
VCC input voltage operating range
5
28
V
15
µA
QUIESCENT CURRENTS
IOUT
Total output discharge current (sum
of currents into VCC, BTST, PH,
SRP, SRN, VFB), VFB ≤ 2.1V
VUVLO < VVCC < VSRN (sleep mode)
VVCC > VSRN, VVCC > VUVLO,
CE = LOW
IAC
VVCC > VSRN, VVCC > VVCCLOWV,
Adapter supply current into VCC pin CE = HIGH, charge done
VVCC > VSRN, VVCC > VVCCLOWV,
CE = HIGH, Charging, Qg_total = 20 nC,
VVCC = 20 V
1
1.5
2
5
mA
25
CHARGE VOLTAGE REGULATION
VFB
Feedback regulation voltage
2.1
Charge voltage regulation accuracy
IVFB
Leakage current into VFB pin
V
TJ = 0°C to 85°C
–0.5%
0.5%
TJ = –40°C to 125°C
–0.7%
0.7%
VFB = 2.1 V
100
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Electrical Characteristics (continued)
5 V ≤ V(VCC) ≤ 28 V, 0°C < T < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT REGULATION
VISET1
ISET voltage range
VIREG_CHG
SRP-SRN current sense voltage
range
2
VIREG_CHG = VSRP – VSRN
KISET1
Charge current set factor (amps of
charge current per volt on ISET pin)
RSENSE = 10 mΩ
100
5
VIREG_CHG = 40 mV
Charge current regulation accuracy
IISET
Leakage current into ISET pin
–3%
V
mV
A/V
3%
VIREG_CHG = 20 mV
–5%
5%
VIREG_CHG = 5 mV
–25%
25%
VIREG_CHG = 1.5 mV
–50%
50%
VISET1 = 2 V
100
nA
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
VUVLO
AC undervoltage rising threshold
VUVLO_HYS
AC undervoltage hysteresis, falling
Measure on VCC
3.65
3.85
4
350
V
mV
VCC LOWV COMPARATOR
VLOWV_FALL
Falling threshold, disable charge
VLOWV_RISE
Rising threshold, resume charge
Measure on VCC
4.1
V
4.35
4.5
V
100
150
mV
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP
_FALL
Sleep falling threshold
VVCC – VSRN to enter sleep mdoe
40
Sleep hysteresis
500
mV
Sleep rising delay
VCC falling below SRN, Delay to pull up PG
1
µs
Sleep falling delay
VCC rising above SRN, Delay to pull down
PG
30
ms
Sleep rising shutdown deglitch
VCC falling below SRN, Delay to enter sleep
mode
100
ms
Sleep falling powerup deglitch
VCC rising above SRN, Delay to exit sleep
mode
30
ms
VSLEEP_HYS
OUT OVERVOLTAGE COMPARATOR
VOV_RISE
Overvoltage rising threshold
As percentage of VVFB
104%
VOV_FALL
Overvoltage falling threshold
As percentage of VVFB
102%
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV
AC overvoltage rising threshold
VACOV_HYS
AC overvoltage falling hysteresis
Measured on VCC
31
32
33
V
1
V
AC overvoltage rising deglitch
Delay to disable charge
1
ms
AC overvoltage falling deglitch
Delay to resume charge
1
ms
Temperature Increasing
145
°C
15
°C
Thermal shutdown rising deglitch
Temperature Increasing
100
µs
Thermal shutdown falling deglitch
Temperature Decreasing
10
ms
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising
temperature
TSHUT_HYS
Thermal shutdown hysteresis
THERMISTOR COMPARATOR
VLTF
Cold temperature rising threshold
As percentage to VVREF
VLTF_HYS
Rising hysteresis
As percentage to VVREF
72.5% 73.5% 74.5%
0.2%
VHTF
Hot temperature rising threshold
As percentage to VVREF
36.4%
VTCO
Cutoff temperature rising threshold
As percentage to VVREF
33.7% 34.4% 35.1%
Deglitch time for temperature out-ofVTS < VLTF, or VTS < VTCO, or VTS < VHTF
range detection
6
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0.4%
0.6%
37% 37.6%
400
ms
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Electrical Characteristics (continued)
5 V ≤ V(VCC) ≤ 28 V, 0°C < T < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Deglitch time for temperature invalid-range detection
MIN
VTS > VLTF – VLTF_HYS or VTS >VTCO, or VTS
> VHTF
TYP
MAX
UNIT
20
ms
45.5
mV
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
Charge overcurrent rising threshold
VOC
Current rising, in nonsynchronous mode,
measure on V(SRP-SRN), VSRP < 2 V
Current rising, as percentage of V(IREG_CHG),
in synchronous mode, VSRP > 2.2 V
160%
Charge overcurrent threshold floor
Minimum OCP threshold in synchronous
mode, measure on V(SRP-SRN), VSRP > 2.2 V
50
mV
Charge overcurrent threshold ceiling
Maximum OCP threshold in synchronous
mode, measure on V(SRP-SRN), VSRP > 2.2 V
180
mV
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET
Charge undercurrent falling
threshold
Switch from CCM to DCM, VSRP > 2.2 V
1
5
9
mV
LOW CHARGE CURRENT COMPARATOR
VLC
Low charge current (average) falling
threshold to force into
Measure V(SRP-SRN)
nonsynchronous mode
1.25
mV
VLC_HYS
Low charge current rising hysteresis
1.25
mV
VLC_DEG
Deglitch on both edges
1
µs
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VVCC > VUVLO (0–35 mA load)
IVREF_LIM
VREF current limit
VVREF = 0 V, VVCC > VUVLO
3.267
35
3.3
3.333
V
mA
REGN REGULATOR
VREGN_REG
REGN regulator voltage
VVCC > 10 V, CE = HIGH (0–40 mA load)
5.7
IREGN_LIM
REGN current limit
VREGN = 0 V, VVCC > VUVLO, CE = HIGH
40
6
6.3
V
mA
PWM HIGH-SIDE DRIVER (HIDRV)
RDS_HI_ON
High-side driver (HSD) turnon
resistance
VBTST – VPH = 5.5 V
3.3
6
Ω
RDS_HI_OFF
High-side driver turnoff resistance
VBTST – VPH = 5.5 V
1
1.3
Ω
VBTST_REFRESH
Bootstrap refresh comparator
threshold voltage
VBTST – VPH when low side refresh pulse
is requested
4
4.2
V
PWM LOW-SIDE DRIVER (LODRV)
RDS_LO_ON
Low-side driver (LSD) turnon
resistance
RDS_LO_OFF
Low-side driver turnoff resistance
4.1
7
Ω
1
1.4
Ω
PWM DRIVERS TIMING
Driver Dead-Time
Dead time when switching between LSD and
HSD, no load at LSD and HSD
PWM ramp height
As percentage of VCC
30
ns
PWM OSCILLATOR
VRAMP_HEIGHT
PWM switching frequency
7%
510
600
690
kHz
INTERNAL SOFT START (8 STEPS TO REGULATION CURRENT ICHG)
Soft start steps
Soft start step time
8
step
1.6
ms
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Electrical Characteristics (continued)
5 V ≤ V(VCC) ≤ 28 V, 0°C < T < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC IO PIN CHARACTERISTICS (CE, STAT, PG)
VIN_LO
CE input low threshold voltage
VIN_HI
CE input high threshold voltage
0.8
VBIAS_CE
CE input bias current
VCE = 3.3 nV (CE has internal 1-MΩ
pulldown resistor)
VOUT_LO
STAT, PG output low saturation
voltage
IOUT_HI
Leakage current
2.1
V
V
6
μA
Sink current = 5 mA
0.5
V
V = 32 V
1.2
μA
6.6 Typical Characteristics
Table 1. Table of Graphs
FIGURES
Power Up (VREF, REGN, PG)
Figure 1
Charge Enable and Disable
Figure 2
Current Soft Start (CE = HIGH)
Figure 3
Continuous Conduction Mode Switching Waveform
Figure 5
Discontinuous Conduction Mode Switching Waveform
Figure 6
Charge Profile
Figure 7
VCC
CE
VREF
REGN
PH
STAT
PG
IOUT
Figure 2. Charge Enable and Disable
Figure 1. Power Up
8
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CE
PH
REGN
LODRV
PH
CE
IOUT
IOUT
Figure 4. Charge Stops on CE LOW
Figure 3. Current Soft Start (CE = HIGH)
PH
HIDRV
PH
LODRV
LODRV
IL
IL
Figure 5. Continuous Conduction Mode
Figure 6. Discontinuous Conduction Mode
VCC
STAT
VOUT
IOUT
Figure 7. Charge Profile
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7 Detailed Description
7.1 Overview
The bq24640 device is a stand-alone, integrated super capacitor charger. The device employs a switched-mode
synchronous buck PWM controller with constant switching frequency.
Charging begins in one of two phases (depending upon super capacitor voltage): constant current (fast-charge
current regulation), and constant voltage (fast-charge voltage regulation). Constant current can be configured
through the ISET pin, allowing for flexibility in the super capacitor charging profile. During charging, the
integrated fault monitors of the device, such as output overvoltage protection (VOV_RISE), thermal shutdown
(internal TSHUT and TS pin), and input voltage protection (VACOV and VUVLO), ensure super capacitor safety.
The bq24640 has two status pins (STAT and PG) to indicate the charging status and input voltage (AC adapter)
status. These pins can be used to drive LEDs or communicate with a host processor.
VOREG
(PROG)
ICHARGE
(PROG)
Constant Current
Constant Voltage
Taper Current
Time
Figure 8. Typical Charging Profile
10
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7.2 Functional Block Diagram
VREF
bq24640
VOLTAGE
REFERENCE
VREF
3.3V
LDO
VCC
-
SRN+100mV
+
SLEEP
UVLO
VCC
VCC
-
VUVLO
+
SLEEP
UVLO
VCC
CE
FBO
1M
COMP
ERROR
AMPLIFIER
EAI
-
PWM
+
+
VREG
BTST
CE
+
1V
VFB
EAO
LEVEL
SHIFTER
20uA
SRP
SRP-SRN
+
SYNCH
PH
+
20X
-
PWM
CONTROL
LOGIC
+
V(SRP-SRN)
HIDRV
OUT_OVP
5 mV +
-
SRN
BTST
_+
PH
20uA
VCC
6V LDO
REFRESH
-
CE
4V
CHARGE
REGN
+
LODRV
V(SRP-SRN)
-
160% X ISET
+
CHG_OCP
GND
8mA
CHARGE
IC Tj
+
145 degC
-
STAT
TSHUT
STAT
ISET
VFB
-
104% X VREG
+
VCC
+
OUT_OVP
STATE
MACHINE
LOGIC
PG
PG
ACOV
VREF
VACOV +LTF
+
TS
SUSPEND
HTF
+
-
TCO
+
-
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7.3 Feature Description
7.3.1 Output Voltage Regulation
The bq24640 uses a high-accuracy voltage regulator for the charging voltage. The charge voltage is
programmed through a resistor-divider from the output to ground, with the midpoint tied to the VFB pin. The
voltage at the VFB pin is regulated to 2.1 V, giving Equation 1 for the regulation voltage:
R2 ù
é
VOUT = 2.1V ´ ê1 +
R1 úû
ë
where
•
R2 is connected from VFB to the output, and R1 is connected from VFB to GND.
(1)
7.3.2 Output Current Regulation
The ISET input sets the maximum charging current. Output current is sensed by resistor RSR connected between
SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 10-mΩ sense
resistor, the maximum charging current is 10 A. The equation for charge current is:
VISET
ICHARGE =
20 ´ R SR
(2)
The input voltage range of ISET is from 0 V to 2 V. The SRP and SRN pins are used to sense voltage across
RSR with default value of 10 mΩ. However, resistors of other values can also be used. A larger sense resistor will
give a larger sense voltage and a higher regulation accuracy, but this comes at the expense of higher conduction
loss.
7.3.3 Power Up
The bq24640 uses a sleep comparator to determine if the source of power on the VCC pin is a valid supply to
charge the capacitor. If the VCC voltage is above the UVLO threshold and greater than the SRN voltage, and all
other conditions are met, bq24640 will then start to charge (see Enable and Disable Charging). If the SRN
voltage is greater than VCC, the bq24640 enters a low quiescent current sleep mode to minimize current drain
from the capacitor (<15 µA).
If VCC is below the UVLO threshold, the device is disabled.
7.3.4 Enable and Disable Charging
The following conditions have to be valid before charge is enabled:
• CE is HIGH.
• The device is not in undervoltage lockout (UVLO) mode and not in VCCLOWV.
• The device is not in sleep mode (that is, VCC > SRN).
• The VCC voltage is lower than the AC overvoltage threshold (VCC < VACOV).
• 30-ms delay is complete after initial power up.
• The REGN LDO and VREF LDO voltages are at the correct levels.
• Thermal shutdown (TSHUT) is not valid.
• TS fault is not detected.
One of the following conditions will stop ongoing charging:
• CE is LOW.
• Adapter is removed, thus causing the device to enter VCCLOWV.
• The device is in sleep mode (that is, VCC < SRN).
• Adapter is over voltage.
• The REGN or VREF LDOs voltage are not valid.
• TSHUT IC temperature threshold is reached.
• TS voltage goes out of range indicating the temperature is too hot or too cold.
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Feature Description (continued)
7.3.5 Automatic Internal Soft-Start Charger Current
The charger automatically soft starts the charger regulation current to ensure there is no overshoot or stress on
the output capacitor. The soft start consists of stepping up the charge regulation current into 8 evenly divided
steps up to the programmed charge current. Each step lasts around 1.6 ms, for a typical rise time of 13 ms. No
external components are needed for this function.
7.3.6 Converter Operation
The synchronous buck PWM converter uses a fixed-frequency voltage mode with feed-forward control scheme. A
type III compensation network allows using ceramic capacitors at the output of the converter. The compensation
input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The
feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output
(EAO). The LC output filter is selected to give a resonant frequency of 12 kHz to 17 kHz, where resonant
frequency, fo, is given by:
1
¦o =
2p L o Co
(3)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty-cycle of the
converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop
compensation. The ramp is offset in order to allow zero percent duty-cycle when the EAO signal is below the
ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100% duty-cycle
PWM request. Internal gate drive logic allows achieving 99.98% duty-cycle while ensuring the N-channel upper
device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2 V for more
than 3 cycles, then the high-side N-channel power MOSFET is turned off and the low-side N-channel power
MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side driver
returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again due to leakage
current discharging the BTST capacitor below the 4.2 V, and the reset pulse is issued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
output voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region.
7.3.7 Synchronous and Nonsynchronous Operation
The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current
for a 10-mΩ sense resistor). During synchronous mode, the internal gate drive logic ensures there is breakbefore-make complimentary switching to prevent shoot-through currents. During the 30-ns dead time where both
FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having the low-side
FET turnon keeps the power dissipation low, and allows safely charging at high currents. During synchronous
mode the inductor current is always flowing and converter operates in continuous conduction mode (CCM),
creating a fixed two-pole system.
The charger operates in nonsynchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor
current on 10-mΩ sense resistor). The charger is forced into nonsynchronous mode when the super capacitor
voltage is lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV (125 mA on 10-mΩ
sense resistor).
During nonsynchronous operation, the body-diode of lower-side MOSFET can conduct the positive inductor
current after the high-side N-channel power MOSFET turns off. When the load current decreases and the
inductor current drops to zero, the body diode will be naturally turned off and the inductor current will become
discontinuous. This mode is called Discontinuous Conduction Mode (DCM). During DCM, the low-side N-channel
power MOSFET will turn on when the bootstrap capacitor voltage drops below 4.2 V, then the low-side power
MOSFET will turn off and stay off until the beginning of the next cycle, where the high-side power MOSFET is
turned on again. The low-side MOSFET on-time is required to ensure the bootstrap capacitor is always
recharged and able to keep the high-side power MOSFET on during the next cycle.
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Feature Description (continued)
At very low currents during nonsynchronous operation, there may be a small amount of negative inductor current
during the recharge pulse. The charge must be low enough to be absorbed by the input capacitance. Whenever
the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on, and the low-side
MOSFET does not turn on (only recharge pulse) either, and there is almost no discharge from the output.
During the DCM mode the loop response automatically changes and has a single-pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.
7.3.8 Input Overvoltage Protection (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. When the adapter voltage
reaches the ACOV threshold, charge is disabled.
7.3.9 Output Overvoltage Protection
The converter will not allow the high-side FET to turn-on until the output voltage goes below 102% of the
regulation voltage. This allows one-cycle response to an overvoltage condition – such as occurs when the load is
removed. An 8-mA current sink from SRP-SRN to GND is on during charge and allows discharging the output
capacitors.
7.3.10 Cycle-by-Cycle Charge Overcurrent Protection
The charger has a secondary cycle-to-cycle overcurrent protection. The charger monitors the charge current, and
prevents the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off
when the overcurrent is detected, and automatically resumes when the current falls below the overcurrent
threshold.
7.3.11 Thermal Shutdown Protection
The VQFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C.
7.3.12 Temperature Qualification
The controller continuously monitors load temperature by measuring the voltage between the TS pin and GND. A
negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this voltage.
The controller compares this voltage against its internal thresholds to determine if charging is allowed. To initiate
a charge cycle, the temperature must be within the V(LTF) to V(HTF) thresholds. If temperature is outside of this
range, the controller suspends charge and waits until the temperature is within the V(LTF) to V(HTF) range.
During the charge cycle the temperature must be within the V(LTF) to V(TCO) thresholds. If temperature is
outside of this range, the controller suspends charge and waits until the temperature is within the V(LTF) to
V(HTF) range. The controller suspends charge by turning off the PWM charge FETs. If the TS function is not
required, R9 and R10 can be the same value so the voltage on TS is 1.65 V with VREF as the reference supply.
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Feature Description (continued)
VREF
VREF
CHARGE SUSPENDED
CHARGE SUSPENDED
VLTF
VLTFH
VLTF
VLTFH
TEMPERATURE RANGE
TO INITIATE CHARGE
TEMPERATURE RANGE
DURING A CHARGE
CYCLE
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
GND
GND
Figure 9. TS Pin, Thermistor Sense Thresholds
Assuming a 103AT NTC thermistor is selector, the value RT1 and RT2 can be determined by using the following
equations:
æ 1
1 ö
VVREF ´ RTHCOLD ´ RTHHOT ´ ç
÷
VLTF
VTCO ø
è
RT2 =
æV
ö
æV
ö
RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷
V
V
è LTF
ø
è TCO
ø
(4)
VVREF
- 1
VLTF
RT1 =
1
1
+
RT2
RTHCOLD
(5)
VREF
bq24640
RT 1
TS
RT 2
RTH
103 AT
Figure 10. TS Resistor Network
7.3.13 CE (Charge Enable)
The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables
charge, provided all the other conditions for charge are met (see Enabling and Disabling Charge). A high-tolow transition on this pin also resets all timers and fault conditions. There is an internal 1-MΩ pulldown resistor
on the CE pin, so if CE is floated the charge will not turn on.
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Feature Description (continued)
7.3.14
PG Output
The open-drain PG (power good) output indicates when the VCC voltage is present. The open-drain FET turns
on whenever bq24640 is not in UVLO mode and not in sleep mode (that is, V(VCC) > V(SRN) and V(VCC) >
V(UVLO)). The PG pin can be used to drive an LED or communicate to the host processor.
7.3.15 Charge Status Outputs
The open-drain STAT output indicates various charger operations as shown in Table 2. These status pins can be
used to drive LEDs or communicate with the host processor.
NOTE
OFF indicates that the open-drain transistor is turned off.
Table 2. STAT Pin Definition
CHARGE STATE
STAT
CE high
ON
Sleep mode
OFF
Charge Suspend (TS), Input or Output Overvoltage, CE low
Blinking
7.4 Device Functional Modes
7.4.1 Constant Current Mode
If the super capacitor voltage is less than the programmed target voltage (that is, VFB pin is less than VFB) when
charging is enabled, then charging will resume in constant current mode. In this mode, the super capacitor
charge current will be constant and regulated as per the ISET and current sense resistor (between SRP and
SRN) settings.
7.4.2 Constant Voltage Mode
When the super capacitor voltage is between the target charge voltage and OVP condition (that is, VFB ≤ VFB pin
< VOV_RISE), then the device will be in constant voltage mode. In this mode, the super capacitor voltage will be
constant and regulated as per the VFB setting while the charge current will taper down.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The bq24640 super capacitor charger is ideal for high current charging (up to 10 A). The bq24640EVM
evaluation module is a complete charge module for evaluating the bq24640. The application curves were taken
using the bq24640EVM. Refer to the EVM user's guide (SLUU410) for EVM information.
8.2 Typical Application
D2
MBRS540T3
Adapter
R6: 10 W
R 11
2W
C2
2.2 mF
Temp
S ensing
C8
10 m F
C 7: 1 mF
C4
1 mF
R7
100 kW
R9
9.31 kW
VREF
CE
VCC
REGN
ISET
BTST
R 5: 100 W
HIDRV
TS
C1
0.1 m F
R8
22.1 kW
R10
10k
(SEMITEC 430 kW
103AT - 2)
PH
C5:1 mF
D1
BAT54
Q4
C6
0. 1 mF
LODRV
GND
Adapter
RSR
10m W
SiS412DN
Q5
L: 6.8 µ H
SiS412DN
STAT
R1 3 :10 kW
C9
10 m F
Super C apacitor
C12
10mF
C10
0.1 m F
R2
300 kW
SRP
R1 4:10 kW
C1 1: 0.1 µ F
PG
Cff
22 pF
R1
105 kW
SRN
bq24640
C13
10 mF
VFB
PwrPad
VIN = 19 V, VOUT = 8.1 V, Icharge = 3 A, Temperature range 0–45°C
Figure 11. Typical Application Schematic
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
AC adapter voltage (VIN)
19 V
Battery charge voltage
8.1 V
Battery charge current (during constant current phase)
3A
8.2.2 Detailed Design Procedure
8.2.2.1 Inductor Selection
The bq24640 has a 600-kHz switching frequency to allow the use of small inductor and capacitor values. The
inductor saturation current must be higher than the charging current (ICHG) plus half the ripple current
(IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE
(6)
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The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT / VIN), switching frequency (fs),
and inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
¦s ´ L
(7)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in
the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a
practical design.
8.2.2.2 Input Capacitor
Input capacitor must have enough ripple current rating to absorb input switching ripple current. The worst-case
RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at
50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50%
and can be estimated by the following equation:
ICIN = ICHG ´
D × (1 - D)
(8)
Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and must be placed
to the drain of the high-side MOSFET and source of the low-side MOSFET as close as possible. Voltage rating
of the capacitor must be higher than normal input voltage level. A 25-V rating or higher capacitor is preferred for
20-V input voltage. The 20-μF capacitance is suggested for typical of 3-A to 4-A charging current.
8.2.2.3 Output Capacitor
Output capacitor also must have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given:
I
ICO UT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3
(9)
The output capacitor voltage ripple can be calculated as follows:
2
æ
ö
VOUT
1
ΔVO =
V
ç
÷
2 ç OUT
VIN ÷ø
8LC¦ s è
(10)
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The bq24640 has internal loop compensator. To get good loop stability, the resonant frequency of the output
inductor and output capacitor must be designed from 12 kHz to 17 kHz. The preferred ceramic capacitor is 25 V
or higher rating, X7R or X5R.
8.2.2.4 Power MOSFETs Selection
Two external N-channel MOSFETs are used for a synchronous switching charger. The gate drivers are internally
integrated into the IC with 6 V of gate drive voltage. 30-V or higher voltage rating MOSFETs are preferred for 20V input voltage and 40-V or higher rating MOSFETs are preferred for 20-V to 28-V input voltage.
Figure-of-merit (FOM) is usually used for selecting proper MOSFET based on a tradeoff between the conduction
loss and switching loss. For top side MOSFET, FOM is defined as the product of the ON-resistance of the
MOSFET, RDS(ON), and the gate-to-drain charge, QGD. For bottom-side MOSFET, FOM is defined as the product
of the ON-resistance of the MOSFET, RDS(ON), and the total gate charge, QG.
FOM top = RDS(on) ´ QGD ; FOM bottom = RDS(on) ´ QG
(11)
The lower the FOM value, the lower the total power loss. Usually lower RDS(ON) has higher cost with the same
package size.
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The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle
(D=VOUT/VIN), charging current (ICHG), ON-resistance of the MOSFET (RDS(ON)), input voltage (VIN), switching
frequency (F), turnon time (ton), and turnoff time (toff):
1
Ptop = D ´ ICHG2 ´ RDS(on) +
´ VIN ´ ICHG ´ (t on + t off ) ´ fS
2
(12)
The first item represents the conduction loss. Usually MOSFET RDS(ON) increases by 50% with 100ºC junction
temperature rise. The second term represents the switching loss. The MOSFET turnon and turnoff times are
given by:
Q
Q
ton = SW , toff = SW
Ion
Ioff
where
•
•
•
QSW is the switching charge
Ion is the turn-on gate driving current
IOFF is the turn-off gate driving current.
(13)
If the switching charge is not given in MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD) and
gate-to-source charge (QGS):
1
QSW = QGD +
´ QGS
2
(14)
Gate driving current total can be estimated by REGN voltage (VREGN), MOSFET plateau voltage (VPLT), total
turnon gate resistance (RON) and turnoff gate resistance ROFF) of the gate driver:
VREGN - Vplt
Vplt
Ion =
, Ioff =
R on
R off
(15)
The conduction loss of the bottom-side MOSFET is calculated with Equation 16 when it operates in synchronous
continuous conduction mode:
Pbottom = (1 - D) ´ ICHG 2 ´ RDS(on)
(16)
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into nonsynchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET will be turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result all the freewheeling current goes through the body-diode of the bottom-side MOSFET. The maximum
charging current in nonsynchronous mode can be up to 0.9 A (0.5 A typical) for a 10-mΩ charging currentsensing resistor considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or
body diode capable of carrying the maximum nonsynchronous mode charging current.
MOSFET gate driver power loss contributes to the dominant losses on controller IC, when the buck converter is
switching. Choosing the MOSFET with a small Qg_total will reduce the IC power loss to avoid thermal shutdown.
PICLoss_driver = VIN ´ Qg_total ´ fS
where
•
Qg_total is the total gate charge for both upper and lower MOSFET at 6-V VREGN.
(17)
8.2.2.5 Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a secondorder system. The voltage spike at VCC pin may be beyond IC maximum voltage rating and damage IC. The
input filter must be carefully designed and tested to prevent an overvoltage event on VCC pin.
There are several methods to damping or limit the overvoltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the over voltage spike well below the IC maximum pin
voltage rating. A high current capability TVS Zener diode can also limit the overvoltage level to an IC safe level.
However these two solutions may not have low cost or small size.
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A cost effective and small size solution is shown in Figure 12. The R1 and C1 are composed of a damping RC
network to damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used
for reverse-voltage protection for VCC pin. C2 is the VCC pin decoupling capacitor and must be placed as close
as possible to the VCC pin. The R2 and C2 form a damping RC network to further protect the IC from high dv/dt
and high-voltage spike. C2 value must be less than C1 value so R1 can dominant the equivalent ESR value to
get enough damping effect for hot plug-in. R1 and R2 package must be sized enough to handle inrush current
power loss according to resistor manufacturer’s datasheet. The filter components value must always be verified
with real application and minor adjustments may must fit in the real application circuit.
D1
Adapter
Connector
R2 (1206)
4.7 - 30 W
R1 (2010)
2W
VCC pin
C1
2.2 mF
C2
0.1 - 1 mF
Figure 12. Input Filter
8.2.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines
The bq24640 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant
frequency, fo, is approximately 12 kHz to 17 kHz. Table 4 provides a summary of typical LC components for
various charge currents.
See Inductor Selection for information on controlling ripple current.
Table 4. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current
CHARGE CURRENT
Output Inductor Lo
2A
4A
6A
8A
10 A
10 µH
6.8 µH
4.7 µH
3.3 µH
3.3 µH
Output Capacitor Co
15 µF
20 µF
30 µF
40 µF
40 µF
Sense Resistor
10 mΩ
10 mΩ
10 mΩ
10 mΩ
10 mΩ
Table 5. Component List for Typical System Circuit of Figure 11
PART DESIGNATOR
QTY
DESCRIPTION
Q4, Q5
2
N-channel MOSFET, 30 V, 12 A, PowerPAK 1212-8, Vishay-Siliconix, Sis412DN
D1
1
Diode, Dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C
D2
1
Schottky Diode, 40 V, 5 A, SMC, ON Semiconductor, MBRS540T3
D3, D4
2
LED Diode, Green, 2.1 V, 10 mΩ, Vishay-Dale, WSL2010R0100F
RSR
1
Sense Resistor, 10 mΩ, 1%, 1 W, 2010, Vishay-Dale, WSL2010R0100F
L
1
Inductor, 6.8 μH, 5.5 A, Vishay-Dale IHLP2525CZ
C8, C9, C12, C13
4
Capacitor, Ceramic, 10 μF, 35 V, 20%, X7R
C4, C5
2
Capacitor, Ceramic, 1 μF, 16 V, 10%, X7R
C7
1
Capacitor, Ceramic, 1 μF, 50 V, 10%, X7R
C1, C6, C11
3
Capacitor, Ceramic, 0.1 μF, 16 V, 10%, X7R
C2
1
Capacitor, Ceramic, 2.2 μF, 50 V, 10%, X7R
Cff
1
Capacitor, Ceramic, 22 pF, 35 V, 10%, X7R
C10
1
Capacitor, Ceramic, 0.1 μF, 35 V, 10%, X7R
R1
1
Resistor, Chip, 105 kΩ, 1/16 W, 0.5%
R2
1
Resistor, Chip, 300 kΩ, 1/16 W, 0.5%
R7
1
Resistor, Chip, 100 kΩ, 1/16 W, 0.5%
R8
1
Resistor, Chip, 22.1 kΩ, 1/16 W, 0.5%
R9
1
Resistor, Chip, 9.31 kΩ, 1/16 W, 1%
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Table 5. Component List for Typical System Circuit of Figure 11 (continued)
PART DESIGNATOR
QTY
DESCRIPTION
R10
1
Resistor, Chip, 430 kΩ, 1/16 W, 1%
R11
1
Resistor, Chip, 2 Ω, 1 W, 5%
R13, R14
2
Resistor, Chip, 100 kΩ, 1/16 W, 5%
R5
1
Resistor, Chip, 100 Ω, 1/16 W, 0.5%
R6
1
Resistor, Chip, 10 Ω, 0.25 W, 5%
8.2.3 Application Curves
VIN: 19 V
VCAP: 8 V
ICHG = 3 A
VIN: 19 V
Figure 13. Continuous Conduction Mode
VCAP: 8 V
ICHG = 3 A
Figure 14. Battery Charging Soft Start
(by Asserting CE Low to High)
9 Power Supply Recommendations
For proper operation of bq24640, VCC must be from 5 V to 28 V. To begin charging, VCC must be higher than
SRN by at least 500 mV (otherwise, the device will be in sleep mode). TI recommends an input voltage of at
least 1.5 V to 2 V higher than the super capacitor voltage, taking into consideration the DC losses in the highside FET (Rdson), inductor (DCR), the input diode drop, and current-sense resistor (between SRP and SRN).
Power limit for the input supply must be greater than the maximum power required for super capacitor charging.
10 Layout
10.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize high frequency current path loop (see Figure 15) is important to prevent electrical and
magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper
layout. Layout PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to switching MOSFET supply and ground connections and use
the shortest copper trace connection. These parts must be placed on the same layer of PCB instead of on
different layers and using vias to make this connection.
2. The IC must be placed close to the switching MOSFET gate terminals and keep the gate drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching MOSFETs.
3. Place the inductor input terminal to switching MOSFET output terminal as close as possible. Minimize the
copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging current sensing resistor must be placed right next to the inductor output. Route the sense leads
connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area)
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Layout Guidelines (continued)
and do not route the sense leads through a high-current path (see Figure 15 for Kelvin connection for best
current accuracy). Place decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route analog ground separately from power ground and use single ground connection to tie charger power
ground to charger analog ground. Just beneath the IC, use analog ground copper pour, but avoid power pins
to reduce inductive and capacitive noise coupling. Connect analog ground to GND pin using thermal pad as
the single ground connection point to connect analog ground and power ground together, or use a 0-Ω
resistor to tie analog ground to power ground (thermal pad must tie to analog ground in this case). A starconnection under thermal pad is highly recommended.
8. It is critical to solder the exposed thermal pad on the backside of the IC package to the PCB ground. Ensure
that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
9. Decoupling capacitors must be placed next to the IC pins and make trace connection as short as possible.
10. All via size and number should be enough for a given current path.
Refer to the EVM design (SLUU410) for the recommended component placement with trace and via locations.
For the QFN information, refer to Quad Flatpack No-Lead Logic Packages (SCBA017) and QFN/SON PCB
Attachment Application Report (SLUA271).
10.2 Layout Examples
L1
SW
R1
V OUT
High
Frequency
V IN
Current
C1
Path
C2
PGND
C3
Super
Capacitor
Figure 15. High-Frequency Current Path
Charge Current Direction
R SNS
To Inductor
To Capacitor and Output
Current Sensing Direction
To SRP and SRN pin
Figure 16. Sensing Resistor PCB Layout
22
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SLUSA44A – MARCH 2010 – REVISED JULY 2015
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
• bq24600/20/40 EVM (HPA421) Multi Cell Synchronous Switch-Mode Charger, SLUU410
• Quad Flatpack No-Lead Logic Packages, SCBA017
• QFN/SON PCB Attachment, SLUA271
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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23
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24640RVAR
ACTIVE
VQFN
RVA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OGA
BQ24640RVAT
ACTIVE
VQFN
RVA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OGA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24640RVAR
VQFN
RVA
16
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
BQ24640RVAR
VQFN
RVA
16
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
BQ24640RVAT
VQFN
RVA
16
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
BQ24640RVAT
VQFN
RVA
16
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-May-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24640RVAR
VQFN
RVA
16
3000
367.0
367.0
35.0
BQ24640RVAR
VQFN
RVA
16
3000
367.0
367.0
35.0
BQ24640RVAT
VQFN
RVA
16
250
210.0
185.0
35.0
BQ24640RVAT
VQFN
RVA
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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