CPM/CPU INTERACTION

CPM/CPU INTERACTION
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CPM/CPU INTERACTION
• Host Commands from CPU
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⋅ Change state of SCC Channel
⋅ Initialize SCC Channel
⋅ Consist of microcode routines which change state
of microcode or SCC state machine.
• Buffer Descriptors
⋅ Give RISC data to transmit.
⋅ Tell RISC where to store received data.
⋅ Report transmit or receive errors.
• Event Registers
⋅ Hardware or microcode generated events
⋅ Can generate an interrupt to the CPU
• Configuration Registers
⋅ Determine the operation mode of the SCC
⋅ Generate Clocking
⋅ Determine the Physical Interface
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SCC
PARAMETER RAM
Address
Base + $00
Base + $02
Base + $04
Base + $05
Base + $06
Base + $08
Base + $0C
Base + $10
Base + $12
Base + $14
Base + $18
Base + $1C
Base + $20
Base + $22
Base + $24
Base + $28
Base + $2C
Name
RBASE
TBASE
RFCR
TFCR
MRBLR
RSTATE
R_PTR
RBPTR
R_CNT
RTEMP
TSTATE
T_PTR
TBPTR
T_CNT
TTEMP
R_CRC
T_CRC
Function
The DPRAM location of the first RBD
The DPRAM location of the first TBD
Function Code for Receive DMA
Function Code for Transmit DMA
Max Receive Buffer Length
RCV State information about channel
Pointer to next memory write location
Pointer to current/next BD location
Down count to end of frame or Buffer
TX State information about channel
Pointer to next memory read location
Porinter to current/next BD location
Down count to end of Buffer
Current Receive CRC
Current Transmit CRC
• Best two to check are RBPTR and TBPTR. In many
“problem situations,” they are not pointing at the
buffers at all.
• T_PTR and R_PTR changing indicate data TX/RX.
• R_CNT and T_CNT are set when the BD is opened.
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WHAT THE COMMANDS
REALLY DO
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• INIT TX PARAMETERS
⋅ Copies TBASE to TBPTR and sets TSTATE to
zero.
• INIT RX PARAMETERS
⋅ Copies RBASE to RBPTR and sets RSTATE to
zero
• ENTER HUNT MODE
⋅ Issues a command to the channel to look for an
IDLE or FLAG and ignore all incoming data
• STOP TX
⋅ Tells the various transmit routines to take
requests but not send any more data.
• GRACEFUL STOP TX
⋅ Tells the various transmit routines to transmit to
the end of the current buffer/frame and then
perform a STOP TX
• RESTART TX
⋅ Reverses the operation of STOP TX
• CLOSE RX BD
⋅ Closes the current BD if data has been received
into it. Does nothing otherwise.
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HOW A FRAME GETS TRANSMITTED
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• CPM looks at the BD pointed to by TBPTR
⋅ If the INIT TX PARAMETERS command was
not executed, the TBPTR may be pointing to
garbage.
• CPM Detects Ready bit has been set.
»After this SCC goes idle, the CPM polls the
ready bit every 128 TX Clocks for Ethernet,
(64 TX Clocks for HDLC/Transparent and
every character time for UART).
⋅ This step cannot be detected by the user.
• CPM copies buffer length to T_CNT (temporary
count), and copies starting address to T_PTR
(temporary pointer)
⋅ This step is your clue that TX Clocks are
working!! Check parallel port pins and clocking
configuration.
• CPM does an SDMA cycle(s) to get the first 32-bits of
transmit data.
⋅ You can set a special function code to see this
happen on the bus. If it doesn’t happen the
SDMA arbitration priority may not be high
enough. Check SDCR.
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HOW A FRAME GETS TRANSMITTED (2)
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• CPM decrements T_CNT and increments T_PTR.
⋅ This means you are starting to fill the transmit
FIFO. The TSTATE value should no longer be
zeros.
• When TX FIFO contains at least 8 bytes, the idles or
flags should stop being transmitted, and real data
should be seen on the TXD pin. (In UART mode data
starts as soon as one character is in the FIFO).
⋅ The CTS pin can prevent data from transmitting
if the user programmed it as a sync, and never
asserted CTS.
⋅ If the Time Slot Assigner does not see a sync,
then no data will transmit.
⋅ If you still don’t see data transmit, try internal
loopback mode to eliminate the data and control
pins as a source of the problem.
• As soon as there is one 32-bit FIFO entry available,
the SCC generates a request to the RISC. The request
remains asserted until the FIFO becomes full or the
last byte of the frame is written to the FIFO.
⋅ This provides the maximum bus latency.
Minimum bus latency allowed is therefore the
time it takes to fill N-4 bytes, where N is the
number of bytes in the FIFO (either 32 for SCC1,
or 16 for the other SCCs).
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HOW A FRAME GETS TRANSMITTED (3)
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• CPM will use multiple buffers to transmit a frame if
needed.
⋅ Make sure all the buffers are “ready” before the
first ready bit is set, or an “underrun” might
occur between buffers. In this case TXE is set
but there is no BD in which to report the
underrun.
⋅ Use the TBPTR to watch the CPM sequence
through the BDs.
• After the entire frame is transmitted, the CPM will
check the next BD’s ready bit immediately. If 0, it
will go back into 128 tx clock poll mode.
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HOW A FRAME GETS RECEIVED
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• CPM receives 32-bits of data from the RX FIFO
⋅ This step cannot be detected by the user.
• CPM looks at the BD pointed to by RBPTR
⋅ If the INIT RX PARAMETERS command was
not executed, the RBPTR may be pointing to
garbage.
• CPM Checks that the Empty bit has been set.
⋅ This step cannot be detected by the user.
• CPM copies buffer length to R_CNT (temporary
count), and copies starting address to R_PTR
(temporary pointer)
⋅ This step is your clue that RX Clocks are
working!! Check parallel port pins and clocking
configuration.
⋅ Echo mode can be used to check the SCC
hardware without involving the RISC.
• CPM does an SDMA cycle(s) to write the first 32-bits
of receive data.
⋅ You can set a special function code to see this
happen on the bus. If it doesn’t happen the
SDMA arbitration priority may not be high
enough. Check SDCR.
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HOW A FRAME GETS RECEIVED (2)
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• CPM decrements R_CNT and increments R_PTR.
⋅ This means you are starting to fill the
receivebuffer. The RSTATE value should no
longer be zeros.
• As soon as there is one 32-bit entry of the receive
FIFO that is available, a request is generated to the
CPM.
⋅ This provides the maximum bus latency.
Minimum bus latency allowed is therefore the
time it takes to fill N-4 bytes, where N is the
number of bytes in the FIFO (either 32 for SCC1,
or 16 for the other SCCs).
• CPM will use multiple buffers to receive a frame if
needed.
⋅ Use the RBPTR to watch the CPM sequence
through the BDs.
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PERFORMANCE ISSUES
In Frame
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IDLE
Open
BD
Close
BD
Open
BD
In Frame
Close
BD
• Opening and closing BDs within a single frame is the
worst issue for the CPM to deal with.
⋅ Worse than between frames because often frames
have padding between them.
• The effect of a CPM performance problem can be
»SCC FIFO receive overrun
»SCC FIFO transmit underrun
⋅ FIFOs have patented emergency features that help
lower priority SCCs keep up with the system.
»Extra pads between frames
»Extra idles between UART characters
• CPM pipelines its reads so up to 9 clocks of latency
has no performance impact at all!
• Long frames are better because there is more time In
Frame to recover from the high CPM loading of
opening/closing BDs.
• Synchronize frame reception/transmission to stress the
CPM for board tests.
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SDMA Behavior
• The SCC SDMA channels do not burst. The only
bursts are from the IDMAs on the MPC860 and the
ATM protocols on the 860sar. The 860 SCC
microcode could have been re-written for bursts, but
instead it was decided to be exactly compatible with
the 68360.
• The SDMA channels do cycle stealing.
• The user will never see two back-to-back SDMA cycle
steal cycles. (I.e. SCC1 TX immediately followed by
SCC2 TX). There will always be a few clocks
inbetween.
• If the SDMA is moving a 32-bit value to a smaller
port, such as 16-bits the user will see back-to-back 16bit cycles.
• On transmit, the SDMA will either read 16 or 32-bits
at the start of a frame depending on the starting
address. (If a 16-bit read is sufficient, the SDMA will
only read 16-bits). It then throws away one of the
bytes if it does not need all of them. Then for the rest
of the transfers, the SDMA will always read 32-bits at
a time. Note: The SDMA only reads 16-bits at a time
in UART mode, and never reads 32-bits.
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