MPC8379E PowerQUICC II Pro Processor Hardware Specifications Freescale Semiconductor

Freescale Semiconductor

Technical Data

Document Number: MPC8379EEC

Rev. 8, 05/2012

MPC8379E

PowerQUICC II Pro Processor

Hardware Specifications

This document provides an overview of the MPC8379E

PowerQUICC II Pro processor features, including a block diagram showing the major functional components. This chip is a cost-effective, low-power, highly integrated host processor that addresses the requirements of several printing and imaging, consumer, and industrial applications, including main CPUs and I/O processors in printing systems, networking switches and line cards, wireless LANs (WLANs), network access servers (NAS),

VPN routers, intelligent NIC, and industrial controllers.

This chip extends the PowerQUICC family, adding higher

CPU performance, additional functionality, and faster interfaces while addressing the requirements related to time-to-market, price, power consumption, and package size.

1 Overview

This chip incorporates the e300c4s core, which includes

32 KB of L1 instruction and data caches and on-chip memory management units (MMUs). The device offers two enhanced three-speed 10, 100, 1000 Mbps Ethernet interfaces, a DDR1/DDR2 SDRAM memory controller, a flexible, a 32-bit local bus controller, a 32-bit PCI controller, an optional dedicated security engine, a USB

2.0 dual-role controller, a programmable interrupt

Contents

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6

3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10

4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 13

5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . 15

6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . 16

7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 23

9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11. Enhanced Secure Digital Host Controller (eSDHC) 43

12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

13. I

2

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

14. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

15. Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 59

16. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

17. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

18. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

19. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

20. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 68

21. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 78

22. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

23. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

24. System Design Information . . . . . . . . . . . . . . . . . . 110

25. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 112

26. Document Revision History . . . . . . . . . . . . . . . . . . 114

Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.

© 2008-2012 Freescale Semiconductor, Inc. All rights reserved.

controller, dual I

2

C controllers, a 4-channel DMA controller, an enhanced secured digital host controller, and a general-purpose I/O port. This figure shows the block diagram of the chip.

Security

DUART

Dual I

2

C

Timers

GPIO

SPI

Interrupt

Controller

MPC8379E e300 Core

32 KB

D-Cache

32 KB

I-Cache

Enhanced

Local Bus

DDR1/DDR2

SDRAM

Controller

DMA PCI

USB 2.0

Hi-Speed

Host Device eTSEC eTSEC

RGMII, RMII,

RTBI, MII

RGMII, RMII,

RTBI, MII

SATA

PHY PHY

PHY PHY

SD/MMC

Controller

Figure 1. MPC8379E Block Diagram and Features

The following features are supported in the chip:

• e300c4s core built on Power Architecture® technology with 32 KB instruction cache and 32 KB data cache, a floating point unit, and two integer units

• DDR1/DDR2 memory controller supporting a 32/64-bit interface

• Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MHz operation

• 32-bit local bus interface running up to 133-MHz

• USB 2.0 (full/high speed) support

• Power management controller for low-power consumption

• High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration

• Optional security engine provides acceleration for control and data plane security protocols

The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.

2

MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8

Freescale Semiconductor

In addition to the security engine, a new high-speed interface such as SATA, is included. This table compares the differences between MPC837xE derivatives and provides the number of ports available for each interface.

Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E

Descriptions

SGMII

PCI Express®

SATA

MPC8377E

0

2

2

MPC8378E

2

2

0

MPC8379E

0

0

4

1.1

DDR Memory Controller

The DDR1/DDR2 memory controller includes the following features:

• Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM

• Support for up to 400-MHz data rate

• Support up to 4 chip selects

• 64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with

×8/×16/×32 data ports (no direct

×4 support)

• Support for up to 32 simultaneous open pages

• Supports auto refresh

• On-the-fly power management using CKE

• 1.8-/2.5-V SSTL2 compatible I/O

1.2

USB Dual-Role Controller

The USB controller includes the following features:

• Supports USB on-the-go mode, including both device and host functionality, when using an external ULPI (UTMI + low-pin interface) PHY

• Complies with USB Specification, Rev. 2.0

• Supports operation as a stand-alone USB device

— Supports one upstream facing port

— Supports three programmable USB endpoints

• Supports operation as a stand-alone USB host controller

— Supports USB root hub with one downstream-facing port

— Enhanced host controller interface (EHCI) compatible

• Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation; low-speed operation is supported only in host mode

• Supports UTMI + low pin interface (ULPI)


Freescale Semiconductor 3

4

1.3

Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)

The eTSECs include the following features:

• Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI

• Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,

IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588™ standards

• Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating mode

• MII management interface for external PHY control and status

1.4

Integrated Programmable Interrupt Controller (IPIC)

The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.

Interrupts can also be redirected to an external interrupt controller.

1.5

Power Management Controller (PMC)

The power management controller includes the following features:

• Provides power management when the device is used in both host and agent modes

• Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states

• Support for PME generation in PCI agent mode, PME detection in PCI host mode

• Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)

• Supports MPC8349E backward-compatibility mode

1.6

Serial Peripheral Interface (SPI)

The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time clocks, A/D converters, and ISDN devices.

The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface

(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an independent baud-rate generator, and a control unit.

1.7

DMA Controller, Dual I

2

C, DUART, Enhanced Local Bus Controller

(eLBC), and Timers

The device provides an integrated four-channel DMA controller with the following features:

• Allows chaining (both extended and direct) through local memory-mapped chain descriptors

(accessible by local masters)

• Supports misaligned transfers



There are two I

2

C controllers. These synchronous, multi-master buses can be connected to additional devices for expansion and system development.

The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550 programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.

The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides a seamless interface to many types of memory devices and peripherals. The memory controller is responsible for controlling eight memory banks shared by a NAND Flash control machine (FCM), a general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash,

EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with data signals to reduce the device pin count.

The enhanced local bus controller also includes a number of data checking and protection features, such as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle is terminated within a user-specified period. The local bus can operate at up to 133 MHz.

The system timers include the following features: periodic interrupt timer, real time clock, software watchdog timer, and two general-purpose timer blocks.

1.8

Security Engine

The optional security engine is optimized to handle all the algorithms associated with IPSec,

IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto execution units (EUs). The execution units are as follows:

• Data encryption standard execution unit (DEU), supporting DES and 3DES

• Advanced encryption standard unit (AESU), supporting AES

• Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any algorithm

• One crypto-channel supporting multi-command descriptor chains

1.9

PCI Controller

The PCI controller includes the following features:

• PCI Specification Revision 2.3 compatible

• Single 32-bit data PCI interface operates at up to 66 MHz

• PCI 3.3-V compatible (not 5-V compatible)

• Support for host and agent modes

• On-chip arbitration, supporting 5 external masters on PCI

• Selectable hardware-enforced coherency



6

1.10

Serial ATA (SATA) Controllers

The serial ATA (SATA) controllers have the following features:

• Supports Serial ATA Rev 2.5 Specification

• Spread spectrum clocking on receive

• Asynchronous notification

• Hot Plug including asynchronous signal recovery

• Link power management

• Native command queuing

• Staggered spin-up and port multiplier support

• Port multiplier support

• SATA 1.5 and 3.0 Gb/s operation

• Interrupt driven

• Power management support

• Error handling and diagnostic features

— Far end/near end loopback

— Failed CRC error reporting

— Increased ALIGN insertion rates

• Scrambling and CONT override

1.11

Enhanced Secured Digital Host Controller (eSDHC)

The enhanced SD host controller (eSDHC) has the following features:

• Conforms to SD Host Controller Standard Specification, Rev 2.0 with Test Event register support.

• Compatible with the MMC System Specification, Rev 4.0

• Compatible with the SD Memory Card Specification, Rev 2.0, and supports High Capacity SD memory cards

• Compatible with the SDIO Card Specification Rev, 1.2

• Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,

MMCplus, MMC 4x, and RS-MMC cards

• SD bus clock frequency up to 50 MHz

• Supports 1-/4-bit SD and SDIO modes, 1-/4-bit MMC modes

• Supports internal DMA capabilities

2 Electrical Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the chip. The device is currently targeted to these specifications. Some of these specifications are independent of the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.



2.1

Overall DC Electrical Characteristics

This section covers the ratings, conditions, and other characteristics.

2.1.1

Absolute Maximum Ratings

This table provides the absolute maximum ratings.

Table 2. Absolute Maximum Ratings

1

Characteristic Symbol Max Value Unit Note

Core supply voltage

PLL supply voltage (e300 core, eLBC, and system)

DDR1 and DDR2 DRAM I/O voltage

V

DD

AV

DD

GV

DD

Three-speed Ethernet I/O, MII management voltage

PCI, DUART, system control and power management, I

2

C, and

JTAG I/O voltage

Local bus

SerDes

Input voltage

LV

DD

OV

[1,2]

DD

DDR DRAM signals

DDR DRAM reference

Three-speed Ethernet signals

PCI, DUART, CLKIN, system control and power management, I

2

C, and JTAG signals

LBV

DD

L[1,2]_

nV

DD

MV

IN

MV

REF

LV

IN

OV

IN

–0.3 to 1.1

–0.3 to 1.1

–0.3 to 2.75

–0.3 to 1.98

–0.3 to 3.63

–0.3 to 3.63

–0.3 to 3.63

–0.3 to 1.1

–0.3 to (GV

DD

+ 0.3)

–0.3 to (GV

DD

+ 0.3)

–0.3 to (LV

DD

+ 0.3)

–0.3 to (OV

DD

+ 0.3)

V

V

V

V

V

V

V

V

V

V

V

—

—

—

—

—

Local Bus

Storage temperature range

LB

IN

T

STG

–0.3 to (LBV

DD

+ 0.3)

–55 to 150

V

°C

—

—

Notes:

1. Functional and tested operating conditions are given in Table 3

. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device.

2. Caution: MV

IN

must not exceed GV

DD

by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

3. Caution: OV

IN

must not exceed OV

DD

by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

4. (M,O)V

IN

and MV

REF

may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2 .

5. Overshoot/undershoot by OV

IN on the PCI interface does not comply to the PCI Electrical Specification for 3.3-V operation,

as shown in Figure 2 .

6. L[1,2]_ nV

DD

includes SDAV

DD_0

, XCOREV

DD

, and XPADV

DD

power inputs.

—

6

2, 4

2, 4

—

3, 4, 5



2.1.2

Power Supply Voltage Specification

This table provides recommended operating conditions for the device. Note that the values in this table are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed.

Table 3. Recommended Operating Conditions

Characteristic Symbol

Recommended

Value

Unit Note

Core supply voltage

PLL supply voltage (e300 core, eLBC and system) up to 667 MHz

800 MHz up to 667 MHz

800 MHz

V

AV

DD

DD

1.0 ± 50 mV

1.05 ± 50 mV

1.0 ± 50 mV

1.05 ± 50 mV

V

V

V

V

1

1

1, 2

1, 2

DDR1 and DDR2 DRAM I/O voltage

Three-speed Ethernet I/O, MII management voltage LV

GV

DD

DD

[1,2]

2.5 V ± 125 mV

1.8 V ± 90 mV

3.3 V ± 165 mV

2.5 V ± 125 mV

3.3 V ± 165 mV

V

V

1

—

PCI, local bus, DUART, system control and power management, I

2

C, and

JTAG I/O voltage

Local Bus

OV

DD

V

1

LBV

DD

1.8 V ± 90 mV

2.5 V ± 125 mV

3.3 V ± 165 mV

V —

SerDes up to 667 MHz L[1,2]_ nV

DD

1.0 ± 50 mV V

1, 3

800 MHz 1.05 V ± 50 mV V

1, 3

Operating temperature range commerical T a

T j

T a

=0 (min)—

T j

=125 (max)

°C

— extended temperature T a

T j

T a

=–40 (min)—

T j

=125 (max)

°C

—

Notes:

1. GV

DD

, OV

DD

, AV direction.

DD

, and V

DD

must track each other and must vary in the same direction—either in the positive or negative

2. AV

DD

is the input to the filter discussed in

Section 24.1, “PLL Power Supply Filtering ,” and is not necessarily the voltage at

the AVDD pin.

3. L[1,2]_ nV

DD

, SDAV

DD_0

, XCOREV

DD

, and XPADV

DD

power inputs.

8



This figure shows the undershoot and overshoot voltages at the interfaces of the device.

V

IH

G/L/O/LBV

DD

+ 20%

G/L/O/LBV

DD

+ 5%

G/L/O/LBV

DD

GND

GND – 0.3 V

V

IL

GND – 0.7 V

Not to Exceed 10% of tinterface1

Note:

1. Note that t interface

refers to the clock period associated with the bus clock interface.

2. Note that with the PCI overshoot allowed (as specified above), the device does not fully comply with the maximum AC ratings and device protection guideline outlined in the PCI Rev. 2.3 Specification (Section 4.2.2.3).

Figure 2. Overshoot/Undershoot Voltage for GV

DD

/LV

DD

/OV

DD

/LBV

DD

2.1.3

chip

Output Driver Characteristics

This table provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

Table 4. Output Drive Capability

Driver Type

1

Output Impedance (

Ω)

Supply Voltage

Local bus interface utilities signals

PCI signals

DDR1 signal

45

40

25

18

LBV

DD

= 2.5 V, 3.3 V

LBV

DD

= 1.8 V

OV

DD

= 3.3 V

GV

DD

= 2.5 V

DDR2 signal eTSEC 10/100/1000 signals

DUART, system control, I

2

GPIO signals

C, JTAG, SPI, and USB

18

45

45

45

GV

DD

= 1.8 V

LV

DD

= 2.5 V, 3.3 V

OV

DD

= 3.3 V

OV

DD

= 3.3 V

Note:

1. Specialized SerDes output capabilities are described in the relevant section of the specification (such as SATA)



2.2

Power Sequencing

The device requires its power rails to be applied in a specific sequence in order to ensure proper device operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of time that all input and output pins will actively be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltages (V

DD

and AV

DD

) before the I/O voltages and assert PORESET before the power supplies fully ramp up. V

DD

and AV

DD

must reach 90% of their nominal value before GV

DD

, LV

DD

, and OV voltage supplies—GV another.

DD

, LV

DD

, and OV

DD

DD

reach 10% of their value, see the following figure. I/O

—do not have any ordering requirements with respect to one

I/O Voltage (GVDD, LVDD, and OVDD)

V

Core Voltage (VDD

,

AVDD)

0.7 V

90%

0 t

Figure 3. Power-Up Sequencing Example

Note that the SerDes power supply (L[1,2]_nV

DD

) should follow the same timing as the core supply

(V

DD

).

The device does not require the core supply voltage and I/O supply voltages to be powered down in any particular order.

3 Power Characteristics

The estimated typical power dissipation for the chip device is shown in this table.

Table 5. Power Dissipation

1

Core Frequency

(MHz)

CSB/DDR Frequency

(MHz)

Sleep Power at T j

= 65

°C (W)

2

Typical Application at T j

= 65

°C (W)

2


= 125

°C (W)

3

Max Application at T j

= 125

°C (W)

4

333

333

167

1.45

1.45

1.9

1.8

3.2

3.0

3.8

3.6

400

400

266

1.45

1.45

2.0

1.9

3.3

3.1

4.0

3.8

10



Table 5. Power Dissipation

1

(continued)

Core Frequency

(MHz)

CSB/DDR Frequency

(MHz)

Sleep Power at T j

= 65

°C (W)

2


= 65

°C (W)

2


= 125

°C (W)

3

Max Application at T j

= 125

°C (W)

4

450

300

225

1.45

1.45

2.0

1.9

3.2

3.1

3.8

3.7

500

533

333

250

355

266

1.45

1.45

1.45

1.45

2.0

1.9

2.0

2.0

3.3

3.2

3.3

3.2

3.9

3.8

4.0

3.9

600

667

800

400

300

333

266

400

1.45

1.45

1.45

1.45

1.45

2.1

2.0

2.1

2.0

2.5

3.4

3.3

3.3

3.3

3.8

4.1

4.0

4.1

3.9

4.3

Notes:

1. The values do not include I/O supply power (OV

DD

2. Typical power is based on a voltage of V

DD

, LV

DD

, GV

DD

) or AV

DD

. For I/O power values, see

= 1.0 V for core frequencies

≤ 667 MHz or V

DD

Table 6 .

= 1.05 V for core frequencies of

800 MHz, and running a Dhrystone benchmark application.

3. Typical power is based on a voltage of V

DD


800 MHz, and running a Dhrystone benchmark application.

≤ 667 MHz or V

DD

= 1.05 V for core frequencies of

4. Maximum power is based on a voltage of V

DD

= 1.0 V for core frequencies of 800 MHz, worst case process, and running an artificial smoke test.

≤ 667 MHz or V

DD




This table shows the estimated typical I/O power dissipation for the device.

Table 6. Typical I/O Power Dissipation

Interface Parameter

DDR I/O

65% utilization

2 pair of clocks

PCI I/O

Load =

30 pf

400 MHz data rate,

32-bit

400 MHz data rate,

64-bit

33 MHz,

32-bit

66 MHz,

32-bit

167 MHz,

32-bit

Local Bus

I/O

Load =

25 pf

133 MHz,

32-bit

83 MHz,

32-bit

66 MHz,

32-bit

50 MHz,

32-bit

200 MHz data rate, 32-bit








GV

DD

(1.8 V)

0.28

0.41

0.31

0.46

0.33

0.48

0.35

0.51

0.38

0.56

—

—

0.09

0.07

0.05

0.04

0.03

GV

DD

/LBV

DD

(2.5 V)

OV

DD

(3.3 V)

LV

DD

(3.3 V)

LV

DD

(2.5 V)

L[1,2]_ nV

DD

(1.0 V)

0.35

— — — —

0.49

0.4

0.56

0.43

0.6

0.45

0.64

—

—

—

—

0.17

0.14

0.09

0.07

0.06

—

—

—

—

—

—

—

—

—

0.04

0.07

0.29

0.24

0.15

0.13

0.1

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Unit

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

W

Comments

—

—

—

12



Interface Parameter

MII or RMII

Table 6. Typical I/O Power Dissipation (continued)

GV

DD

(1.8 V)

—

GV

DD

/LBV

DD

(2.5 V)

OV

DD

(3.3 V)

LV

DD

(3.3 V)

LV

DD

(2.5 V)

L[1,2]_ nV

DD

(1.0 V)

— — 0.02

— —

Unit

W

0.05

— W

Comments

Multiply by number of interfaces used.

— eTSEC I/O

Load =

25 pf

USB

(60MHz

Clock)

RGMII or

RTBI

12 Mbps

480 Mbps

—

—

—

—

—

—

—

0.01

0.2

—

—

—

SerDes

Other I/O per lane

—

—

—

—

— 0.01

Note: The values given are for typical, and not worst case, switching.

—

—

—

—

—

—

—

—

0.029

—

W

W

W

W

—

—

—

4 Clock Input Timing

This section provides the clock input DC and AC electrical characteristics for the chip. Note that the

PCI_CLK/PCI_SYNC_IN signal or CLKIN signal is used as the PCI input clock depending on whether the device is configured as a host or agent device. CLKIN is used when the device is in host mode.

4.1

DC Electrical Characteristics

This table provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.

Table 7. CLKIN DC Electrical Characteristics

Parameter Condition Symbol Min

Input high voltage

Input low voltage

CLKIN Input current

PCI_CLK Input current

—

—

0 V

≤ V

IN

≤ OV

DD

OV

0 V

DD

≤ V

IN

≤ 0.5 V or

– 0.5 V

≤ V

IN

≤ OV

DD

V

IH

V

I

I

IL

IN

IN

2.7

–0.3

Note:

1. In PCI agent mode, this specification does not comply with PCI 2.3 Specification.

—

—

Max

OV

DD

+ 0.3

0.4

± 10

± 30

Unit

V

V

μA

μA

Note

—

—

1

1



4.2

AC Electrical Characteristics

The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. This table provides the clock input

(CLKIN/PCI_CLK) AC timing specifications for the device.

Table 8. CLKIN AC Timing Specifications

Parameter Symbol Min Typical Max Unit Note

CLKIN/PCI_CLK frequency

CLKIN/PCI_CLK cycle time

CLKIN/PCI_CLK rise and fall time

CLKIN/PCI_CLK duty cycle f

CLKIN t

CLKIN t

KH

, t

KL t

KHK

/t

CLKIN

—

25

15

0.6

40

—

—

1.0

—

66.666

40

2.3

60

MHz ns ns

%

1, 6

—

2

3

CLKIN/PCI_CLK jitter — — ± 150 ps

4, 5

Notes:

1. Caution: The system, core and security block must not exceed their respective maximum or minimum operating frequencies.

2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.

3. Timing is guaranteed by design and characterization.

4. This represents the total input jitter-short term and long term-and is guaranteed by design.

5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.

6. Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.

4.3

eTSEC Gigabit Reference Clock Timing

This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.

Table 9. EC_GTX_CLK125 AC Timing Specifications

At recommended operating conditions with LV

DD

= 2.5 ± 0.125 mV/ 3.3 V ± 165 mV

Parameter/Condition Symbol Min Typical Max Unit Note

EC_GTX_CLK125 frequency

EC_GTX_CLK125 cycle time t

G125 t

G125 t

G125R

/t

G125F

—

—

125

8

—

—

MHz ns

—

—

EC_GTX_CLK rise and fall time

LV

DD

= 2.5 V

LV

DD

= 3.3 V

EC_GTX_CLK125 duty cycle

1000Base-T for RGMII, RTBI

EC_GTX_CLK125 jitter t

G125H

—

/t

G125

—

47

—

—

—

—

0.75

1.0

53

±150 ns

% ps

1

2

2

Notes:

1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LV

DD

LV

DD

= 3.3 V.

= 2.5 V and from 0.6 and 2.7 V for

2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The

EC_GTX_CLK125 duty cycle can be loosened from 47%/ 53% as long as the PHY device can tolerate the duty cycle

generated by the eTSEC GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing Specifications,”

for the duty cycle for

10Base-T and 100Base-T reference clock.

14



5 RESET Initialization

This section describes the DC and AC electrical specifications for the reset initialization timing and electrical requirements of the chip.

5.1

RESET DC Electrical Characteristics

This table provides the DC electrical characteristics for the RESET pins of the device.

Table 10. RESET Pins DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Input high voltage

Input low voltage

Input current

Output high voltage

Output low voltage

V

IH

V

V

IL

I

IN

OH

V

OL

I

OL

—

—

—

I

OH

= –8.0 mA

= 8.0 mA

2.0

–0.3

—

2.4

—

OV

DD

+ 0.3

0.8

± 30

—

0.5

V

V

μA

V

V

Output low voltage V

OL

I

OL

= 3.2 mA — 0.4

V

Notes:

• This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.

• HRESET and SRESET are open drain pin, thus V

OH

is not relevant for these pins.

5.2

RESET AC Electrical Characteristics

This table provides the reset initialization AC timing specifications of the device.

Table 11. RESET Initialization Timing Specifications

Parameter/Condition

Required assertion time of HRESET to activate reset flow

Required assertion time of PORESET with stable clock applied to CLKIN when the device is in PCI host mode

Required assertion time of PORESET with stable clock applied to PCI_CLK when the device is in PCI agent mode

HRESET assertion (output)

HRESET negation to negation (output)

Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],

CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET when the device is in PCI host mode

Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],

CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET when the device is in PCI agent mode

Input hold time for POR config signals with respect to negation of HRESET

Min

32

32

32

512

16

4

4

0

Max

—

—

—

—

—

—

—

—

Unit

t

PCI_SYNC_IN t

CLKIN

Note

1

2

t

PCI_SYNC_IN t

PCI_SYNC_IN t

PCI_SYNC_IN t

CLKIN t

PCI_SYNC_IN ns

1

1

1

2

1

—



Table 11. RESET Initialization Timing Specifications (continued)

Parameter/Condition Min Max Unit Note

Time for the device to turn off POR config signals with respect to the assertion of

HRESET

— 4 ns

3

Time for the device to start driving functional output signals multiplexed with the

POR configuration signals with respect to the negation of HRESET

1 — t

PCI_SYNC_IN

1, 3

Notes:

1. t

PCI_SYNC_IN

is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the

MPC8379E Integrated Host Processor Reference Manual for more details.

2. t

CLKIN

is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the

MPC8379E Integrated Host Processor Reference Manual for more details.

3. POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.

Table 12

provides the PLL lock times.

Table 12. PLL Lock Times

Parameter Min Max Unit Note

PLL lock times — 100

μs

—

Note:

• The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL ratio. See

Section 22, “Clocking,”

for more information.

6 DDR1 and DDR2 SDRAM

This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip.

Note that DDR1 SDRAM is GV

DD

(typ) = 2.5 V and DDR2 SDRAM is GV

DD

(typ) = 1.8 V.

6.1

DDR1 and DDR2 SDRAM DC Electrical Characteristics

This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the device when GV

DD

(typ) = 1.8 V.

Table 13. DDR2 SDRAM DC Electrical Characteristics for GV

DD

(typ) = 1.8 V

Parameter Symbol Min Max Unit Note

I/O supply voltage

I/O reference voltage

I/O termination voltage

Input high voltage

Input low voltage

Output leakage current

Output high current (V

OUT

= 1.40 V)

GV

DD

MV

REF

V

TT

V

IH

V

IL

I

OZ

I

OH

1.71

0.49

× GV

DD

MV

REF

– 0.04

MV

REF

+ 0.140

–0.3

–50

–13.4

1.89

0.51

× GV

DD

MV

REF

+ 0.04

GV

DD

+ 0.3

MV

REF

– 0.140

50

—

V

V

V

V

V

μA mA

—

4

—

1

2, 5

3

—

16



Table 13. DDR2 SDRAM DC Electrical Characteristics for GV

DD

(typ) = 1.8 V (continued)


Output low current (V

OUT

= 0.3 V) I

OL

13.4

— mA —

Notes:

1. GV

DD

is expected to be within 50 mV of the DRAM GV

DD

2. MV at all times.

REF

is expected to be equal to 0.5

× GV

DD

, and to track GV

DD

DC variations as measured at the receiver. Peak-to-peak noise on MV

REF

may not exceed ±2% of the DC value.

3. V

TT

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MV

REF

. This rail should track variations in the DC level of MV

REF

.

4. Output leakage is measured with all outputs disabled, 0 V

≤

V

OUT

≤

GV

DD

.

5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

Table 14

provides the DDR2 capacitance when GV

DD

(typ) = 1.8 V.

Table 14. DDR2 SDRAM Capacitance for GV

DD

(typ) = 1.8 V


Input/output capacitance: DQ, DQS, DQS

Delta input/output capacitance: DQ, DQS, DQS

C

IO

C

DIO

6

—

8

0.5

pF pF

1

1

Note:

1. This parameter is sampled. GV

DD

= 1.8 V ± 0.090 V, f = 1 MHz, T

A

= 25°C, V

OUT

= GV

DD

/2, V

OUT

(peak-to-peak) = 0.2 V.

This table provides the recommended operating conditions for the DDR SDRAM component(s) when

GV

DD

(typ) = 2.5 V.

Table 15. DDR SDRAM DC Electrical Characteristics for GV

DD

(typ) = 2.5 V


I/O supply voltage

I/O reference voltage

I/O termination voltage

Input high voltage

Input low voltage

Output leakage current

GV

DD

MV

REF

V

TT

V

IH

V

IL

I

OZ

I

OH

I

OL

2.375

0.49

× GV

DD

MV

REF

– 0.04

MV

REF

+ 0.18

–0.3

–50

2.625

0.51

× GV

DD

MV

REF

+ 0.04

GV

DD

+ 0.3

MV

REF

– 0.18

50

V

V

V

V

V

μA

1

2, 5

3

—

—

4

Output high current (V

OUT

= 1.9 V)

Output low current (V

OUT

= 0.38 V)

–15.2

15.2

—

— mA mA

—

—

Notes:

1. GV

2. MV

DD

is expected to be within 50 mV of the DRAM GV

DD at all times.

REF

is expected to be equal to 0.5

× GV

DD

, and to track GV

DD

DC variations as measured at the receiver. Peak-to-peak noise on MV

REF

may not exceed ±2% of the DC value.

3. V

TT

is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be equal to MV

REF

. This rail should track variations in the DC level of MV

REF

.

4. Output leakage is measured with all outputs disabled, 0 V

≤

V

OUT

≤

GV

DD

.




Table 16

provides the DDR capacitance when GV

DD

(typ) = 2.5 V.

Table 16. DDR SDRAM Capacitance for GV

DD

(typ) = 2.5 V


Input/output capacitance: DQ, DQS

Delta input/output capacitance: DQ, DQS

C

IO

C

DIO

6

—

8

0.5

pF pF

1

1

Note:

1. This parameter is sampled. GV

DD

= 2.5 V ± 0.125 V, f = 1 MHz, T

A

= 25°C, V

OUT

= GV

DD

/2, V

OUT

(peak-to-peak) = 0.2 V.

This table provides the current draw characteristics for MV

REF

.

Table 17. Current Draw Characteristics for MV

REF

Parameter

Current draw for MV

REF

Symbol

I

MVREF

Min Typ Max Unit

μA

DDR1

DDR2

—

—

250

150

600

400

Note:

1. The voltage regulator for MV

REF

must be able to supply up to the stated maximum current.

2. This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.

Note

1, 2

6.2

DDR1 and DDR2 SDRAM AC Electrical Characteristics

This section provides the AC electrical characteristics for the DDR SDRAM interface.

6.2.1

DDR1 and DDR2 SDRAM Input AC Timing Specifications

This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.

Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

Parameter

AC input low voltage

AC input high voltage

Symbol

V

IL

V

IH

Min

—

MV

REF

+ 0.25

Max

MV

REF

– 0.25

—

Unit

V

V

This table provides the input AC timing specifications for the DDR1 SDRAM when GV

DD

(typ) = 2.5 V.

Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface

Parameter

AC input low voltage

AC input high voltage

Symbol

V

IL

V

IH

Min

—

MV

REF

+ 0.31

Max

MV

REF

– 0.31

—

Unit

V

V

18



This table provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.

Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications


Controller skew for MDQS-MDQ/MECC/MDM

400 MHz data rate

333 MHz data rate

266 MHz data rate t

CISKEW

–500

–750

–750

500

750

750 ps

1, 2

3

—

—

Note:

1. t

CISKEW

represents the total amount of skew consumed by the controller between MDQS n and any corresponding bit that will be captured with MDQS n. This should be subtracted from the total timing budget.

2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t

DISKEW

. This can be determined by the following equation: t

DISKEW

= ±[T/4 – |t

CISKEW

|] where T is the MCK clock period and |t

CISKEW

| is the absolute value of t

CISKEW

.

3. This specification applies only to DDR2 interface.

6.2.2

DDR1 and DDR2 SDRAM Output AC Timing Specifications

This table shows the DDR1 and DDR2 SDRAM output AC timing specifications.

Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications

Parameter Symbol

1

Min Max Unit

MCK n cycle time, MCKn/MCKn crossing

ADDR/CMD output setup with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

ADDR/CMD output hold with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

MCS n output setup with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

MCS n output hold with respect to MCK

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate

MCK to MDQS skew t

MCK t

DDKHAS t

DDKHAX t

DDKHCS t

DDKHCX t

DDKHMH

5

1.95

2.40

3.15

4.20

1.95

2.40

3.15

4.20

1.95

2.40

3.15

4.20

1.95

2.40

3.15

4.20

–0.6

10

—

—

—

—

0.6

—

—

—

—

—

—

—

—

—

—

—

— ns ns ns ns ns ns

Note

2

3, 7

3, 7

3

3

4, 8



Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)


1

Min Max Unit Note

MDQ//MDM output setup with respect to MDQS

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate t t

DDKHDS,

DDKLDS

550

800

1100

1200

—

—

—

— ps

5, 8

MDQ//MDM output hold with respect to MDQS

400 MHz data rate

333 MHz data rate

266 MHz data rate

200 MHz data rate t t

DDKHDX,

DDKLDX

700

800

1100

1200

—

—

—

— ps

5, 8

MDQS preamble start

MDQS epilogue end t

DDKHMP t

DDKHME

–0.5

× t

MCK

–0.6

–0.6

–0.5

× t

MCK

0.6

+ 0.6

ns ns

6, 8

6, 8

Notes:

1. The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

(first two letters of functional block)(reference)(state)(signal)(state)

for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example, t

DDKHAS

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference (K) goes from the high (H) state until outputs (A) are setup (S) or output valid time. Also, t

DDKLDX

symbolizes DDR timing (DD) for the time t

MCK

memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ//MDM/MDQS.

4. Note that t

DDKHMH

follows the symbol conventions described in Note 1. For example, t

DDKHMH describes the DDR timing

(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). t

DDKHMH

can be modified through control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same adjustment value. See the MPC8379E PowerQUICC II Pro Host Processor Reference Manual for a description and understanding of the timing modifications enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK n at the pins of the microprocessor. Note that t

DDKHMP follows the

symbol conventions described in Note 1.

7. Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.


The minimum frequency for DDR2 is 250 MHz data rate (125 MHz clock), 167 MHz data rate (83 MHz clock) for DDR1. This figure shows the DDR1 and DDR2 SDRAM output timing for the MCK to MDQS skew measurement (t

DDKHMH

).

20



MCK[n]

MCK[n] t

MCK t

DDKHMHmax) = 0.6 ns

MDQS t

DDKHMH(min) = –0.6 ns

MDQS

Figure 4. DDR Timing Diagram for t

DDKHMH

This figure shows the DDR1 and DDR2 SDRAM output timing diagram.

MCK[n]

MCK[n]

ADDR/CMD t

MCK

Write A0 t

DDKHAS

,t

DDKHCS t

DDKHAX

,t

DDKHCX

NOOP t

DDKHMP t

DDKHMH

MDQS[n]

MDQ[x] t

DDKHDX

D0 t

DDKHDS t

DDKLDS

D1 t

DDKLDX

Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram

t

DDKHME



This figure provides AC test load for the DDR bus.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

GVDD/2

Figure 6. DDR AC Test Load

7 DUART

This section describes the DC and AC electrical specifications for the DUART interface of the chip.

7.1

DUART DC Electrical Characteristics

This table provides the DC electrical characteristics for the DUART interface of the device.

Table 22. DUART DC Electrical Characteristics

Parameter Symbol Min Max

High-level input voltage

Low-level input voltage OV

DD

High-level output voltage,

I

OH

= –100

μA

Low-level output voltage,

I

OL

= 100

μA

V

IH

V

V

V

IL

OH

OL

OV

2

–0.3

DD

– 0.2

—

Input current,

(0 V

≤V

IN

≤ OV

DD

)

I

IN

—

Note: The symbol V

IN

, in this case, represents the OV

IN

symbol referenced in Table 2

.

OV

DD

+ 0.3

0.8

—

0.2

±30

Unit

V

V

V

V

μA

7.2

DUART AC Electrical Specifications

this table provides the AC timing parameters for the DUART interface of the device.

Table 23. DUART AC Timing Specifications

Parameter Value Unit Note

Minimum baud rate

Maximum baud rate

256

> 1,000,000 baud baud

—

1

Oversample rate 16 —

2

Notes:

1. Actual attainable baud rate will be limited by the latency of interrupt processing.

2. The middle of a start bit is detected as the 8 th

sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each 16 th

sample.

22



8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC)

This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet controller.

8.1

Enhanced Three-Speed Ethernet Controller (eTSEC)

(10/100/1000 Mbps)—MII/RGMII/RTBI/RMII DC Electrical

Characteristics

The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit media independent interface (RGMII), reduced ten-bit interface (RTBI), reduced media independent interface (RMII) signals, management data input/output (MDIO) and management data clock (MDC).

The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated at 2.5 V. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface

(RGMII) Specification Version 1.3. The RMII interface follows the RMII Consortium RMII Specification

Version 1.2.

8.1.1

MII, RMII, RGMII, and RTBI DC Electrical Characteristics

MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 24 and

Table 25 . The RGMII and RTBI signals in Table 25

are based on a 2.5 V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.

Table 24. MII and RMII DC Electrical Characteristics

Min

3.13

Max

3.47

Unit

V

Note

1


Supply voltage 3.3 V LV

DD1

LV

DD2

V

OH

Output high voltage

(LV

DD1

/LV

DD2

= Min, I

OH

= –4.0 mA)

Output low voltage

(LV

DD1

/LV

DD2

= Min, I

OL

= 4.0 mA)

Input high voltage

V

OL

Input low voltage

V

IH

V

IL

Input high current

(V

IN

= LV

DD1

, V

IN

= LV

DD2

)

I

IH

Input low current

(V

IN

= GND)

I

IL

Notes:

1. LV

DD1

supports eTSEC 1. LV

DD2

supports eTSEC 2.

2.40

LV

DD1

/LV

DD2

+ 0.3

GND 0.50

2.0

–0.3

—

–600

LV

DD1

/LV

DD2

+ 0.3

0.90

30

—

V

V

V

V

μA

μA

—

—

—

—

1

—



Table 25. RGMII and RTBI DC Electrical Characteristics


Supply voltage 2.5 V LV

DD1

LV

DD2

V

OH

Output high voltage

(LV

DD1

/LV

DD2

= Min, IOH = –1.0 mA)

Output low voltage

(LV

DD1

/LV

DD2

= Min, I

OL

= 1.0 mA)

Input high voltage

V

OL

Input low voltage

V

IH

V

IL

I

IH

Input high current

(V

IN

= LV

DD1

, V

IN

= LV

DD2

)

Input low current

(V

IN

= GND)

I

IL

Notes:

1. LV

DD1

supports eTSEC 1. LV

DD2

supports eTSEC 2.

Min

2.37

2.00

GND

– 0.3

1.7

–0.3

—

–20

Max

2.63

LV

DD1

/LV

DD2

+ 0.3

0.40

LV

DD1

/LV

DD2

+ 0.3

0.70

–20

—

V

V

V

μA

μA

Unit

V

V

8.2

MII, RGMII, RMII, and RTBI AC Timing Specifications

The AC timing specifications for MII, RGMII, RMII, and RTBI are presented in this section.

8.2.1

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

8.2.1.1

MII Transmit AC Timing Specifications

This table provides the MII transmit AC timing specifications.

Table 26. MII Transmit AC Timing Specifications


DD

of 3.3 V ± 5%.


1

Min Typical

TX_CLK clock period 10 Mbps

TX_CLK clock period 100 Mbps

TX_CLK duty cycle

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay t

MTX t

MTX t

MTXH/ t

MTX t

MTKHDX

—

—

35

1

400

40

—

5

Max

—

—

65

15

Unit

ns ns

% ns

—

—

—

1

—

Note

1

—

24



Table 26. MII Transmit AC Timing Specifications (continued)


DD

of 3.3 V ± 5%.


1

Min Typical Max Unit

TX_CLK data clock rise (20%–80%)

TX_CLK data clock fall (80%–20%) t

MTXR t

MTXF

1.0

1.0

—

—

4.0

4.0

ns ns

Note:

1. The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t


for outputs. For example, t

MTKHDX

symbolizes MII transmit timing (MT) for the time t

MTX

clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t

MTX

represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

This figure shows the MII transmit AC timing diagram.

t

MTX

TX_CLK t

MTXH t

MTXF

TXD[3:0]

TX_EN

TX_ER t

MTXR t

MTKHDX

Figure 7. MII Transmit AC Timing Diagram

8.2.1.2

MII Receive AC Timing Specifications

This table provides the MII receive AC timing specifications.

Table 27. MII Receive AC Timing Specifications


DD

of 3.3 V ± 5%.

Parameter

Symbol

1

Min Typical

Input low voltage

Input high voltage

RX_CLK clock period 10 Mbps

RX_CLK clock period 100 Mbps

RX_CLK duty cycle

RXD[3:0], RX_DV, RX_ER setup time to RX_CLK

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK

V

IL

V

IH t

MRX t

MRX t

MRXH

/t

MRX t

MRDVKH t

MRDXKH

—

1.9

—

—

35

10.0

10.0

—

—

—

—

—

400

40

Max

65

—

—

0.7

—

—

—

Unit

% ns ns ns ns

V

V



Table 27. MII Receive AC Timing Specifications (continued)


DD

of 3.3 V ± 5%.


1


RX_CLK clock rise time (20%–80%)

RX_CLK clock fall time (80%–20%) t

MRXR t

MRXF

1.0

1.0

—

—

4.0

4.0

ns ns

Note:


(first two letters of functional block)(signal)(state)

(reference)(state)

for inputs and t



MRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

MRX

clock reference (K) going to the high (H) state or setup time. Also, t

MRDXKL

symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the t

MRX

clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t

MRX

represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

This figure provides the AC test load for eTSEC.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

LVDD/2

Figure 8. eTSEC AC Test Load

This figure shows the MII receive AC timing diagram.

t

MRX t

MRXR

RX_CLK

RXD[3:0]

RX_DV

RX_ER t

MRXH t

MRXF

Valid Data t

MRDVKH t

MRDXKL

Figure 9. MII Receive AC Timing Diagram

8.2.2

RGMII and RTBI AC Timing Specifications

This table presents the RGMII and RTBI AC timing specifications.

Table 28. RGMII and RTBI AC Timing Specifications


DD

of 2.5 V ± 5%.

Parameter

Symbol

1

Min Typical

Data to clock output skew (at transmitter)

Data to clock input skew (at receiver)

Clock period t

SKRGT t

SKRGT t

RGT

–600

1.0

7.2

0

—

8.0

Max

600

2.8

8.8

26

Unit

ps ns ns

Note

—

2

3



Table 28. RGMII and RTBI AC Timing Specifications (continued)


DD

of 2.5 V ± 5%.


1

Min Typical Max Unit Note

Duty cycle for 1000Base-T

Duty cycle for 10BASE-T and 100BASE-TX

Rise time (20%–80%)

Fall time (20%–80%) t

RGTH

/t

RGT t

RGTH

/t

RGT t

RGTR t

RGTF

45

40

—

—

50

50

—

—

55

60

0.75

0.75

%

% ns ns

4

3, 4

—

—

EC_GTX_CLK125 reference clock period t

G12

— 8.0

— ns

5

EC_GTX_CLK125 reference clock duty cycle measured at 0.5

× LV

DD1 t

G125H

/t

G125

47 — 53 % —

Notes:

1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent

RGMII and RTBI timing. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will be added to the associated clock signal.

3. For 10 and 100 Mbps, t

RGT

scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long as the minimum duty cycle is not violated and stretching occurs for no more than three t

RGT

of the lowest speed transitioned between

5. This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention.


Output

Z

0

= 50

Ω

R

L

= 50

Ω

LVDD/2




This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.

t

RGT t

RGTH

GTX_CLK

(At Transmitter) t

SKRGT_TX

TXD[8:5][3:0]

TXD[7:4][3:0]

TXD[3:0]

TXD[8:5]

TXD[7:4]

TX_CTL

TXD[4]

TXEN

TXD[9]

TXERR

TX_CLK

(At PHY) t

SKRGT_RX

RXD[8:5][3:0]

RXD[7:4][3:0]

RXD[3:0]

RXD[8:5]

RXD[7:4] t

SKRGT_TX

RX_CTL

RXD[4]

RXDV

RXD[9]

RXERR

RX_CLK

(At PHY)

Figure 11. RGMII and RTBI AC Timing and Multiplexing Diagrams

t

SKRGT_RX

8.2.3

RMII AC Timing Specifications

This section describes the RMII transmit and receive AC timing specifications.

8.2.3.1

RMII Transmit AC Timing Specifications

This table shows the RMII transmit AC timing specifications.

Table 29. RMII Transmit AC Timing Specifications


DD

of 3.3 V ± 5%.

Parameter

Symbol

1

Min Typical

REF_CLK clock period

REF_CLK duty cycle

REF_CLK peak-to-peak jitter

Rise time REF_CLK (20%–80%) t

RMT t

RMTH t

RMTJ t

RMTR

15.0

35

—

1.0

20.0

50

—

—

Max

25.0

65

250

2.0

Unit

ns

% ps ns

28



Table 29. RMII Transmit AC Timing Specifications (continued)


DD

of 3.3 V ± 5%.


1


Fall time REF_CLK (80%–20%)

REF_CLK to RMII data TXD[1:0], TX_EN delay t

RMTF t

RMTDX

1.0

2.0

—

—

2.0

10.0

ns ns

Note:


(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t



MTKHDX

symbolizes MII transmit timing (MT) for the time t

MTX

clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters representing the clock of a particular functional. For example, the subscript of t

MTX

represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

This figure shows the RMII transmit AC timing diagram.

t

RMT t

RMTR

REF_CLK t

RMTH t

RMTF

TXD[1:0]

TX_EN

TX_ER t

RMTDX

Figure 12. RMII Transmit AC Timing Diagram

8.2.3.2

RMII Receive AC Timing Specifications

This table shows the RMII receive AC timing specifications.

Table 30. RMII Receive AC Timing Specifications


DD

of 3.3 V ± 5%.

Parameter/Condition

Symbol

1

Min Typical

Input low voltage at 3.3 LV

DD

Input high voltage at 3.3 LV

DD

REF_CLK clock period

REF_CLK duty cycle

REF_CLK peak-to-peak jitter

Rise time REF_CLK (20%–80%)

Fall time REF_CLK (80%–20%)

V

IL

V

IH t

RMR t

RMRH t

RMRJ t

RMRR t

RMRF

—

2.0

15.0

35

—

1.0

1.0

—

—

—

—

—

20.0

50

Max

0.8

—

25.0

65

250

2.0

2.0

Unit

ps ns ns ns

%

V

V



Table 30. RMII Receive AC Timing Specifications (continued)


DD

of 3.3 V ± 5%.

Parameter/Condition Symbol

1


RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge t

RMRDV t

RMRDX

4.0

2.0

—

—

—

— ns ns

Note:



(reference)(state)

for inputs and t



MRDVKH symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the t

MRX


MRDXKL

symbolizes MII receive timing (GR) with respect to the time data input signals (D) went invalid (X) relative to the t

MRX

clock reference (K) going to the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t

MRX

represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).


Output

Z

0

= 50

Ω

R

L

= 50

Ω

LVDD/2


This figure shows the RMII receive AC timing diagram.

t

RMR t

RMRR

REF_CLK

RXD[1:0]

CRS_DV

RX_ER t

RMRH t

RMRF

Valid Data t

RMRDV t

RMRDX

Figure 14. RMII Receive AC Timing Diagram

8.3

Management Interface Electrical Characteristics

The electrical characteristics specified here apply to MII management interface signals MDIO

(management data input/output) and MDC (management data clock).


Output

Z

0

= 50

Ω

R

L

= 50

Ω

LVDD/2

30




8.3.1

MII Management DC Electrical Characteristics

The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in

Table 31 and Table 32 .

Table 31. MII Management DC Electrical Characteristics When Powered at 2.5 V

Parameter Conditions

Supply voltage (2.5 V)

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

—

I

OH

= –1.0 mA

I

OL

= 1.0 mA

—

—

LV

DD1

= Min

LV

DD1

= Min

LV

DD1

= Min

LV

DD1

= Min

V

IN

= LV

DD1

V

IN

= LV

DD1

Symbol

LV

DD1

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Min

2.37

2.00

GND – 0.3

1.7

–0.3

—

–15

Max

2.63

LV

DD1

+ 0.3

0.40

—

0.70

20

—

Unit

V

V

V

V

V

μA

μA

Table 32. MII Management DC Electrical Characteristics When Powered at 3.3 V

Parameter

Supply voltage (3.3 V)

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

I

OH

= –1.0 mA

I

OL

= 1.0 mA

Conditions

—

LV

DD1

= Min

LV

DD1

= Min

—

—

LV

LV

DD1

DD1

= Max

= Max

V

IN

1

= 2.1 V

V

IN

= 0.5 V

Symbol

LV

DD1

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Min

3.135

2.10

GND

2.00

—

—

–600

Max

3.465

LV

DD1

+ 0.3

0.50

—

0.80

30

—

Unit

V

V

V

V

V

μA

μA

8.3.2

MII Management AC Electrical Specifications

This table provides the MII management AC timing specifications.

Table 33. MII Management AC Timing Specifications


1

Min Typical Max

MDC frequency

MDC period

MDC clock pulse width high

MDC to MDIO valid

MDC to MDIO delay

MDIO to MDC setup time

MDIO to MDC hold time f

MDC t

MDC t

MDCH t

MDKHDV t

MDKHDX t

MDDVKH t

MDDXKH

—

80

32

2

× (t plb_clk

× 8)

10

5

0

—

—

—

2.5

—

—

—

—

400

—

—

2

× (t plb_clk

× 8)

—

—

Unit

MHz ns ns ns ns ns ns

Note

2, 4

—

—

2

—

—

4



Parameter

Table 33. MII Management AC Timing Specifications (continued)

Symbol

1

Min Typical Max Unit Note

MDC rise time (20%–80%)

MDC fall time (80%–20%) t

MDCR t

MDCF

—

—

—

—

10

10 ns ns

3

3

Notes:



(reference)(state)

for inputs and t



MDKHDX symbolizes management data timing (MD) for the time t

MDC

from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also, t

MDDVKH

symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V) relative to the t

MDC

clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This parameter is dependent on the system clock speed.

3. Guaranteed by design.

4. t plb_clk

is the platform (CSB) clock divided according to the SCCR[TSEC1CM].

This figure shows the MII management AC timing diagram.

t

MDC t

MDCR

MDC t

MDCH t

MDCF

MDIO

(Input) t

MDDVKH t

MDDXKH

MDIO

(Output) t

MDKHDX

Figure 16. MII Management Interface Timing Diagram

9 USB

This section provides the AC and DC electrical characteristics for the USB dual-role controllers.

32



9.1

USB DC Electrical Characteristics

This table provides the DC electrical characteristics for the ULPI interface at recommended

OV

DD

= 3.3 V ± 165 mV.

Table 34. USB DC Electrical Characteristics



Low-level input voltage

V

IH

V

IL

2

– 0.3

OV

DD

+ 0.3

0.8

V

V

1

1

Input current

High-level output voltage, I

OH

= –100

μA

Low-level output voltage, I

OL

= 100

μA

V

I

IN

OH

V

OL

OV

—

DD

– 0.2

—

±30

—

0.2

μA

V

V

2

—

—

Notes:

1. The minimum V

IL

and maximum V

IH

values are based on the respective minimum and maximum OV

IN

values found in

Table 3 .

2. The symbol OV

IN

represents the input voltage of the supply and is referenced in Table 3

.

9.2

USB AC Electrical Specifications

This table describes the general timing parameters of the USB interface of the device.

Table 35. USB General Timing Parameters (ULPI Mode Only)


1


USB clock cycle time

Input setup to USB clock—all inputs

Input hold to USB clock—all inputs

USB clock to output valid—all outputs t

USCK t

USIVKH t

USIXKH t

USKHOV

15

4

1

—

—

—

—

7 ns ns ns ns

2, 3, 4, 5

2, 3, 4, 5

2, 3, 4, 5

2, 3, 4, 5

Output hold from USB clock—all outputs t

USKHOX

2 — ns

2, 3, 4, 5

Notes:

1. The symbols for timing specifications follow the pattern of t

(First two letters of functional block)(signal)(state) (reference)(state)

for inputs and t

(First two letters of functional block)(reference)(state)(signal)(state)


USIXKH

symbolizes USB timing (US) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, t

USKHOX

symbolizes

USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to the USB clock, USBDR_CLK.

3. All signals are measured from OV

DD

/2 of the rising edge of the USB clock to 0.4

× OV signaling levels.

DD of the signal in question for 3.3-V

4. Input timings are measured at the pin.

5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered through the component pin is less than or equal to that of the leakage current specification.



These two figures provide the AC test load and signals for the USB, respectively.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OV

DD

/2

Figure 17. USB AC Test Load

USBDR_CLK t

USIXKH t

USIVKH

Input Signals

Output Signals t

USKHOV t

USKHOX

Figure 18. USB Interface Timing Diagram

10 Local Bus

This section describes the DC and AC electrical specifications for the local bus interface of the chip.

10.1

Local Bus DC Electrical Characteristics

This tables provide the DC electrical characteristics for the local bus interface.

Table 36. Local Bus DC Electrical Characteristics (LBV

DD

At recommended operating conditions with LBV

DD

= 3.3 V.

= 3.3 V)

Parameter

Supply voltage 3.3 V

Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

Conditions

—

I

OH

= –4.0 mA

I

OL

= 4.0 mA

—

—

V

IN

1

= LBV

DD

V

IN

1

= GND

LBV

DD

= Min

LBV

DD

= Min

—

—

Symbol

LBV

DD

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Min

3.135

2.40

—

2.0

–0.3

—

–30

Max

3.465

—

0.50

LBV

DD

+ 0.3

0.90

30

—

Unit

V

V

V

V

V

μA

μA

34




DD


DD

= 2.5 V.

= 2.5 V)

Parameter


Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

Conditions

—

I

OH

= –1.0 mA

I

OL

= 1.0 mA

—

LBV

LBV

DD

DD

= Min

= Min

LBV

DD

= Min

— LBV

DD

= Min

V

IN

1

= LBV

DD

V

IN

1

= GND

Symbol

LBV

DD

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Min

2.37

2.00

—

1.7

–0.3

—

–20

Max

2.73

—

0.40

LBV

DD

+ 0.3

0.70

20

—


DD


DD

= 1.8 V.

= 1.8 V)

Parameter


Output high voltage

Output low voltage

Input high voltage

Input low voltage

Input high current

Input low current

Conditions

—

I

OH

= –1.0 mA

I

OL

= 1.0 mA

—

LBV

LBV

DD

DD

= Min

= Min

LBV

DD

= Min

— LBV

DD

= Min

V

IN

1

= LBV

DD

V

IN

1

= GND

Symbol

LBV

DD

V

OH

V

OL

V

IH

V

IL

I

IH

I

IL

Min

1.71

LBV

DD

– 0.45

—

0.65

× LBV

DD

–0.3

—

–10

Max

1.89

—

0.45

LBV

DD

+ 0.3

0.35

× LBV

DD

10

—

Unit

V

V

V

V

V

μA

μA

Unit

V

V

V

V

V

μA

μA

10.2

Local Bus AC Electrical Specifications

This table describes the general timing parameters of the local bus interface of the device when in PLL enable mode.

Table 39. Local Bus General Timing Parameters—PLL Enable Mode


1


Local bus cycle time

Input setup to local bus clock (except LUPWAIT/LGTA)

Input hold from local bus clock

LUPWAIT/LGTA input setup to local bus clock

LALE output fall to LAD output transition (LATCH hold time)



Local bus clock to LALE rise

Local bus clock to output valid (except LALE) t

LBK t

LBIVKH t

LBIXKH t

LBIVKH1 t

LBOTOT1 t

LBOTOT2 t

LBOTOT3 t

LBKHLR t

LBKHOV

1.5

3

2.5

—

—

7.5

1.5

1.0

1.5

—

—

—

4.5

4.5

15

—

—

— ns ns ns ns ns ns ns ns ns

7

—

5

6

3

2

3, 4

3, 4

3, 4



Table 39. Local Bus General Timing Parameters—PLL Enable Mode (continued)


1


Local bus clock to output high impedance for LAD/LDP

Output hold from local bus clock for LAD/LDP t

LBKHOZ t

LBKHOX

—

1

3.8

— ns ns

3, 8

3

Notes:


(First two letters of functional block)(signal)(state)

(reference)(state)

for inputs and t



LBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t

LBK clock reference (K) goes high (H), in this case for clock one(1). Also, t

LBKHOX

symbolizes local bus timing (LB) for the t

LBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to rising edge of LSYNC_IN at LBV

3. All signals are measured from LBV

DD

DD

/2 and the 0.4

× LBV

DD

of the signal in question.

/2 of the rising/falling edge of LSYNC_IN to 0.5

× LBV

DD

of the signal in question.


5. t

LBOTOT1

should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on

LAD output pins.

6. t

LBOTOT2

should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on LAD output pins.

7. t

LBOTOT3

should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.

8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification.

36



This table describes the general timing parameters of the local bus interface of the device when in PLL bypass mode.

Table 40. Local Bus General Timing Parameters—PLL Bypass Mode


1


Local bus cycle time

Input setup to local bus clock

Input hold from local bus clock




Local bus clock to LALE rise

Local bus clock to output valid t

LBK t

LBIVKH t

LBIXKH t

LBOTOT1 t

LBOTOT2 t

LBOTOT3 t

LBKHLR t

LBKHOV

15

7.0

1.0

1.5

3.0

2.5

—

—

—

—

—

—

—

—

4.5

3.0

ns ns ns ns ns ns ns ns

2

3, 4

3, 4

5

6

7

—

3

Local bus clock to output high impedance for LAD/LDP t

LBKHOZ

— 4.0

ns

3, 8

Notes:


(First two letters of functional block)(signal)(state)

(reference)(state)

for inputs and t



LBIXKH1 symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t

LBK clock reference (K) goes high (H), in this case for clock one(1). Also, t

LBKHOX

symbolizes local bus timing (LB) for the t

LBK clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or output hold time.

2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of

LCLK0 (for all other inputs).

3. All signals are measured from LBV

DD signaling levels.

/2 of the rising/falling edge of LCLK0 to 0.4

× LBV

DD

of the signal in question for 3.3-V


5. t

LBOTOT1

should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on

LAD output pins.

6. t

LBOTOT2

should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load on LAD output pins.

7. t

LBOTOT3

should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.


This figure provides the AC test load for the local bus.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OVDD/2

Figure 19. Local Bus AC Test Load



This figures show the local bus signals.

LSYNC_IN

Input Signals:

LAD[0:31]/LDP[0:3]

Input Signal:

LGTA

Output Signals:

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

LA[27:31]/LBCTL/LBCKE/LOE

Output (Data) Signals:

LAD[0:31]/LDP[0:3] t

LBKHOV t

LBKHOV t

LBKHOV

Output (Address) Signal:

LAD[0:31] t

LBKHLR

LALE t

LBIVKH t

LBIVKH t

LBKHOX t

LBKHOZ t

LBKHOX t

LBKHOZ t

LBKHOX t

LBOTOT t

LBIXKH t

LBIXKH

Figure 20. Local Bus Signals, Non-special Signals Only (PLL Enable Mode)

38



LCLK[n]

Input Signals:

LAD[0:31]

Input Signal:

LGTA

Output Signals:

LSDA10/LSDWE/LSDRAS/

LSDCAS/LSDDQM[0:3]

LA[27:31]/LBCTL/LBCKE/LOE


LAD[0:31]/LDP[0:3] t

LBKHOV t

LBKHOV t

LBKHOV


LAD[0:31] t

LBKHLR

LALE t

LBIVKH t

LBKHOZ t

LBKHOZ t

LBIVKH t

LBIXKH t

LBOTOT

Figure 21. Local Bus Signals, Non-special Signals Only (PLL Bypass Mode)

t

LBIXKH



LSYNC_IN

T1

T3 t

LBKHOV t

LBKHOX

GPCM Mode Output Signals:

LCS[0:7]/LWE[0:3] t

LBIXKH t

LBIVKH

UPM Mode Input Signal:

LUPWAIT t

LBIXKH

Input Signals:

LAD[0:31]/LDP[0:3] t

LBIVKH

UPM Mode Output Signals:

LCS[0:7]/LBS[0:1]/LGPL[0:5] t

LBKHOV t

LBKHOX t

LBKHOZ t

LBKHOX


LAD[0:31]/LDP[0:3] t

LBKHOV t

LBKHOZ t

LBKHOX


LAD[0:31] t

LBKHOV

Figure 22. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode)

40



LCLK

T1

T3 t

LBKHOZ t

LBKHOV


LCS[0:7]/LWE[0:3] t

LBIXKH t

LBIVKH


LUPWAIT

Input Signals:

LAD[0:31]/LDP[0:3] t

LBIVKH t

LBIXKH


LCS[0:7]/LBS[0:1]/LGPL[0:5] t

LBKHOV t

LBKHOZ


LAD[0:31]/LDP[0:3] t

LBKHOV t

LBKHOZ


LAD[0:31] t

LBKHOV

Figure 23. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Bypass Mode)



LSYNC_IN

T1

T2

T3

T4 t

LBKHOZ t

LBKHOV


LCS[0:7]/LWE[0:3] t

LBIXKH t

LBIVKH


LUPWAIT t

LBIXKH

Input Signals:

LAD[0:31] t

LBIVKH t

LBKHOX


LCS[0:7]/LBS[0:1]/LGPL[0:5] t

LBKHOV t

LBKHOZ t

LBKHOX


LAD[0:31]/LDP[0:3] t

LBKHOV t

LBKHOZ t

LBKHOX


LAD[0:31] t

LBKHOV

Figure 24. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode)

42



LCLK

T1

T2

T3

T4 t

LBKHOZ t

LBKHOV


LCS[0:7]/LWE[0:3] t

LBIXKH t

LBIVKH


LUPWAIT t

LBIXKH t

LBIVKH

Input Signals:

LAD[0:31] t

LBKHOV


LCS[0:7]/LBS[0:1]/LGPL[0:5] t

LBKHOV t

LBKHOZ


LAD[0:31]/LDP[0:3] t

LBKHOV t

LBKHOZ


LAD[0:31]

Figure 25. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Bypass Mode)

11 Enhanced Secure Digital Host Controller (eSDHC)

This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC) interface of the chip.

The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the

SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full- and high-speed modes.

Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed mode, data is driven at the rising edge of the clock.



Due to the special implementation of the eSDHC, there are constraints regarding the clock and data signals propagation delay on the user board. The constraints are for minimum and maximum delays, as well as skew between the CLK and DAT/CMD signals.

In full speed mode, there is no need to add special delay on the data or clock signals. The user should make sure to meet the timing requirements as described further within this document.

If the system is designed to support both high-speed and full-speed cards, the high-speed constraints should be fulfilled. If the systems is designed to operate up to 25 MHz only, full-speed mode is recommended.

11.1

eSDHC DC Electrical Characteristics

This table provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device.

Table 41. eSDHC interface DC Electrical Characteristics

Parameter

Input high voltage

Input low voltage

Input current

Output high voltage

Output low voltage

Symbol

V

IH

V

IL

I

IN

V

OH

V

OL

Condition

—

—

—

I

OH

= –100 uA, at OV

DD

(min)

I

OL

= +100 uA, at OV

DD

(min)

Min

0.625

× OV

DD

–0.3

—

0.75

× OV

DD

—

Max

OV

DD

+ 0.3

0.25

× OV

DD

±30

—

0.125

× OV

DD

Unit

V

V

μA

V

V

11.2

eSDHC AC Timing Specifications (Full-Speed Mode)

This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device.

This table provides the eSDHC AC timing specifications for full-speed mode as defined in Figure 27 and

Figure 28

.

Table 42. eSDHC AC Timing Specifications for Full-Speed Mode

At recommended operating conditions OV

DD

= 3.3 V ± 165 mV.


1


SD_CLK clock frequency—full speed mode

SD_CLK clock cycle

SD_CLK clock frequency—identification mode

SD_CLK clock low time

SD_CLK clock high time

SD_CLK clock rise and fall times

Input setup times: SD_CMD, SD_DATx, SD_CD to

SD_CLK f

SFSCK t

SFSCK f

SIDCK t

SFSCKL t

SFSCKH t

SFSCKR

/ t

SFSCKF t

SFSIVKH

0

40

0

15

15

—

5

25

—

400

—

—

5

—

MHz ns

KHz ns ns ns ns

—

—

—

2

2

2

2

44



Table 42. eSDHC AC Timing Specifications for Full-Speed Mode (continued)


DD

= 3.3 V ± 165 mV.


1


Input hold times: SD_CMD, SD_DAT x, SD_CD to

SD_CLK t

SFSIXKH

0 — ns

2

SD_CLK delay within device t

INT_CLK_DLY

1.5

— ns

4

Output valid: SD_CLK to SD_CMD, SD_DAT

Output hold: SD_CLK to SD_CMD, SD_DAT

SD card input setup

SD card input hold x valid x valid t

SFSKHOV t

SFSKHOX t

ISU t

IH

—

0

5

5

4

—

—

— ns

— ns ns

2

—

3

3

SD card output valid

SD card output hold t

ODLY t

OH

—

0

14

— ns ns

3

3

Notes:


(first three letters of functional block)(signal)(state)

(reference)(state)

for inputs and t

(first three letters of functional block)(reference)(state)(signal)(state)


SFSIXKH symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also t

SFSKHOV

symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. Measured at capacitive load of 40 pF.

3. For reference only, according to the SD card specifications.

4. Average, for reference only.

This figure provides the eSDHC clock input timing diagram.

eSDHC

External Clock operational mode

VM VM VM t

SFSCKL t

SFSCK

VM = Midpoint Voltage (OV

DD

/2) t

SFSCKR

Figure 26. eSDHC Clock Input Timing Diagram

t

SFSCKH t

SFSCKF



11.2.1

Full-Speed Output Path (Write)

This figure provides the data and command output timing diagram.

SD CLK at the

MPC8379E pin t

SFSCK

(clock cycle)

Driving

Edge t

CLK_DELAY

SD CLK at the card pin

Output valid time: t

SFSKHOV

Output hold time: t

SFSKHOX

Output from the

MPC8379E Pins t

SFSCKL

Sampling edge

Input at the

MPC8379E pins t

DATA_DELAY t

ISU

(5 ns)

Figure 27. Full Speed Output Path

t

IH

(5 ns)

11.2.1.1

Full-Speed Write Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed skew range between the SD_CLK and

SD_DAT/CMD signals on the PCB.

No clock delay:

Eqn. 1 t

SFSKHOV

+ t

DATA_DELAY

+ t

ISU

< t

SFSCKL

With clock delay:

t

SFSKHOV

+ t

DATA_DELAY

+ t

ISU

< t

SFSCKL

+ t

CLK_DELAY t

DATA_DELAY

+ t

SFSCKL

< t

SFSCK

+ t

CLK_DELAY

–

t

ISU

–

t

SFSKHOV

This means that data can be delayed versus clock up to 11 ns in ideal case of t

SFSCKL

= 20 ns: t

DATA_DELAY

+ 20 < 40 + t

CLK_DELAY

–

5

–

4 t

DATA_DELAY

< 11 + t

CLK_DELAY

Eqn. 2

Eqn. 3

11.2.1.2

Full-Speed Write Meeting Hold (Minimum Delay)



t

CLK_DELAY

< t

SFSCKL

+ t

SFSKHOX

+ t

DATA_DELAY

–

t

IH

Eqn. 4

46



t

CLK_DELAY

+ t

IH

–

t

SFSKHOX

< t

SFSCKL

+ t

DATA_DELAY

t

This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of

SFSCLKL

= 20 ns: t

CLK_DELAY

+ 5

–

0 < 20 + t

DATA_DELAY t

CLK_DELAY

< 15 + t

DATA_DELAY

Eqn. 5

11.2.1.3

Full-Speed Write Combined Formula

The following equation is the combined formula to calculate the allowed skew range between the

SD_CLK and SD_DAT/CMD signals on the PCB.

t

CLK_DELAY

+ t

IH

–

t

SFSKHOX

< t

SFSCKL

+ t

DATA_DELAY

< t

SFSCK

+ t

CLK_DELAY

–

t

ISU

–

t

SFSKHOV

Eqn. 6

11.2.2

Full-Speed Input Path (Read)

This figure provides the data and command input timing diagram.

t

SFSCK

(clock cycle)

SD CLK at the

MPC8379E pin

Sampling edge

SD CLK at the card pin

Driving edge t

ODLY t

OH t

CLK_DELAY t

DATA_DELAY

Output from the

SD card pins

Input at the

MPC8379E pins

(MPC8379E input hold) t

SFSIXKH

Figure 28. Full Speed Input Path

t

SFSIVKH

11.2.2.1

Full-Speed Read Meeting Setup (Maximum Delay)

The following equations show how to calculate the allowed combined propagation delay range of the


t

CLK_DELAY

+ t

DATA_DELAY

+ t

ODLY

+ t

SFSIVKH

< t

SFSCK t

CLK_DELAY

+ t

DATA_DELAY

< t

SFSCK

–

t

ODLY

–

t

SFSIVKH

–

t

INT_CLK_DLY

Eqn. 7

Eqn. 8



11.2.2.2

Full-Speed Read Meeting Hold (Minimum Delay)

There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.

Eqn. 9 t

CLK_DELAY

+ t

OH

+ t

DATA_DELAY

> t

SFSIXKH

This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.

11.3

eSDHC AC Timing Specifications (High-Speed Mode)

This table provides the eSDHC AC timing specifications for high-speed mode as defined in

Figure 30 and

Figure 31

.

Table 43. eSDHC AC Timing Specifications for High-Speed Mode


DD

= 3.3 V ± 165 mV.

Parameter

Symbol

1


SD_CLK clock frequency—high speed mode

SD_CLK clock cycle

SD_CLK clock frequency—identification mode

SD_CLK clock low time

SD_CLK clock high time

SD_CLK clock rise and fall times f

SHSCK t

SHSCK f

SIDCK t

SHSCKL t

SHSCKH t

SHSCKR/ t

SHSCKF t

SHSIVKH

0

20

0

7

7

—

50

—

400

—

—

3

MHz ns

KHz ns ns ns

—

—

—

2

2

2

Input setup times: SD_CMD, SD_DATx, SD_CD to

SD_CLK

5 — ns

2

Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK

Output delay time: SD_CLK to SD_CMD, SD_DATx valid

Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid

SD_CLK delay within device t

SHSIXKH t

SHSKHOV t

SHSKHOX t

INT_CLK_DLY

0

—

0

1.5

—

4

—

— ns ns ns ns

2

2

2

4

SD Card Input Setup

SD Card Input Hold

SD Card Output Valid

SD Card Output Hold t

ISU t

IH t

ODLY t

OH

6

2

—

2.5

—

—

14

— ns ns ns ns

3

3

3

3

Notes:


(first three letters of functional block)(signal)(state)

(reference)(state)

for inputs and t

(first three letters of functional block)(reference)(state)(signal)(state)


SFSIXKH symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K) going to high (H). Also t

SFSKHOV

symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. Measured at capacitive load of 40 pF.

3. For reference only, according to the SD card specifications.

4. Average, for reference only.

48



This figure provides the eSDHC clock input timing diagram.

eSDHC

External Clock operational mode

VM VM VM t

SHSCKL t

SHSCK

VM = Midpoint Voltage (OVDD/2) t

SHSCKR

Figure 29. eSDHC Clock Input Timing Diagram

t

SHSCKH t

SHSCKF

11.3.1

High-Speed Output Path (Write)

This figure provides the data and command output timing diagram.

SD CLK at the

MPC8379E pin t

SHSCK

(clock cycle)

Driving

Edge t

CLK_DELAY

SD CLK at the card Pin

Output valid time: t

SHSKHOV

Output hold time: t

SHSKHOX

Output from the

MPC8379E pins t

SHSCKL

Sampling edge

Input at the

SD card pins t

DATA_DELAY t

ISU

(6 ns)

Figure 30. High Speed Output Path

t

IH

(2 ns)

11.3.1.1

High-Speed Write Meeting Setup (Maximum Delay)



Zero clock delay:

t

SHSKHOV

+ t

DATA_DELAY

+ t

ISU

< t

SHSCKL

Eqn. 10

With clock delay:

t

SHSKHOV

+ t

DATA_DELAY

+ t

ISU

< t

SHSCKL

+ t

CLK_DELAY t

DATA_DELAY

–

t

CLK_DELAY

< t

SHSCKL

–

t

ISU

–

t

SHSKHOV

Eqn. 11

Eqn. 12



This means that data delay should be equal or less than the clock delay in the ideal case where t

SHSCLKL

= 10 ns: t

DATA_DELAY

– t

CLK_DELAY

< 10

–

6

–

4 t

DATA_DELAY

– t

CLK_DELAY

< 0

11.3.1.2

High-Speed Write Meeting Hold (Minimum Delay)



t

CLK_DELAY

< t

SHSCKL

+ t

SHSKHOX

+ t

DATA_DELAY

–

t

IH

Eqn. 13 t

CLK_DELAY

–

t

DATA_DELAY

< t

SHSCKL

+ t

SHSKHOX

–

t

IH

This means that clock can be delayed versus data up to 8 ns (external delay line) in ideal case of t

SHSCLKL

= 10 ns: t

CLK_DELAY

– t

DATA_DELAY

< 10 + 0

–

2 t

CLK_DELAY

– t

DATA_DELAY

< 8

Eqn. 14

11.3.2

High-Speed Input Path (Read)

This figure provides the data and command input timing diagram.

t

SHSCK

(Clock Cycle)

1/2 Cycle

Wrong Edge

SD CLK at the

MPC8379E Pin

Right Edge

Sampling

Edge

SD CLK at the Card Pin

Driving

Edge t

ODLY t

OH t

CLK_DELAY t

DATA_DELAY

Output from the

SD Card Pins

Input at the

MPC8379E Pins t

SHSIVKH

(MPC8379E Input Setup)

Figure 31. High-Speed Input Path

(MPC8379E Input Hold) t

SHSIXKH

For the input path, the device eSDHC expects to sample the data 1.5 internal clock cycles after it was driven by the SD card. Since in this mode the SD card drives the data at the rising edge of the clock, a sufficient delay to the clock and the data must exist to ensure it will not be sampled at the wrong internal

50



clock falling edge. Note that the internal clock which is guaranteed to be 50% duty cycle is used to sample the data, and therefore used in the equations.

11.3.2.1

High-Speed Read Meeting Setup (Maximum Delay)



t

CLK_DELAY

+ t

DATA_DELAY

+ t

ODLY

+ t

SHSIVKH

< 1.5

× t

SHSCK t

CLK_DELAY

+ t

DATA_DELAY

< 1.5

× t

SHSCK

–

t

ODLY

–

t

SHSIVKH

This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle: t

CLK_DELAY

+ t

DATA_DELAY

< 30

–

14

–

5 t

CLK_DELAY

+ t

DATA_DELAY

< 11

Eqn. 15

Eqn. 16

11.3.2.2

High-Speed Read Meeting Hold (Minimum Delay)



0.5

× t

SHSCK

< t

CLK_DELAY

+ t

DATA_DELAY

+ t

OH

–

t

SHSIXKH

+ t

INT_CLK_DLY

0.5

× t

SHSCK

–

t

OH

+ t

SHSIXKH

–

t

INT_CLK_DLY

< t

CLK_DELAY

+ t

DATA_DELAY

This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:

10

–

2.5 + (–1.5) < t

CLK_DELAY

+ t

DATA_DELAY

6 < t

CLK_DELAY

+ t

DATA_DELAY

Eqn. 17

Eqn. 18

11.3.2.3

High-Speed Read Combined Formula

The following equation is the combined formula to calculate the propagation delay range of the SD_CLK and SD_DAT/CMD signals on the PCB.

0.5

× t

SHSCK

–

t

OH

+ t

SHSIXKH

< t

CLK_DELAY

+ t

DATA_DELAY

< 1.5

× t

SHSCK

–

t

ODLY

–

t

SHSIVKH

Eqn. 19

12 JTAG

This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the chip.



12.1

JTAG DC Electrical Characteristics

This table provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the chip.

Table 44. JTAG interface DC Electrical Characteristics

Parameter

Input high voltage

Input low voltage

Input current

Output high voltage

Output low voltage

Output low voltage

Symbol

V

IH

V

IL

I

IN

V

OH

V

OL

V

OL

Condition

—

—

—

I

OH

= –8.0 mA

I

OL

= 8.0 mA

I

OL

= 3.2 mA

Min

2.5

–0.3

—

2.4

—

—

Max

OV

DD

+ 0.3

0.8

±30

—

0.5

0.4

Unit

V

V

μA

V

V

V

12.2

JTAG AC Timing Specifications

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.

This table provides the JTAG AC timing specifications as defined in

Figure 33

through Figure 36 .

Table 45. JTAG AC Timing Specifications (Independent of CLKIN)

1


2


JTAG external clock frequency of operation

JTAG external clock cycle time

JTAG external clock pulse width measured at 1.4 V

JTAG external clock rise and fall times

TRST assert time

Input setup times:

Boundary-scan data

TMS, TDI

Input hold times:

Boundary-scan data

TMS, TDI

Valid times:

Boundary-scan data

TDO

Output hold times:

Boundary-scan data

TDO f

JTG t

JTG t

JTKHKL t

JTGR

& t

JTGF t

TRST t

JTDVKH t

JTIVKH t

JTDXKH t

JTIXKH t

JTKLDV t

JTKLOV t

JTKLDX t

JTKLOX

0

30

15

0

25

4

4

10

10

2

2

2

2

33.3

—

—

2

—

—

—

—

—

11

11

—

—

MHz ns ns ns ns ns ns ns ns

—

—

—

—

3

4

4

—

—

52



Table 45. JTAG AC Timing Specifications (Independent of CLKIN)

1

(continued)


2


JTAG external clock to output high impedance:

Boundary-scan data

TDO t

JTKLDZ t

JTKLOZ

2

2

19

9 ns

5

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of t

TCLK

to the midpoint of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50

Ω load (see

Figure 17

). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.



(reference)(state)

for inputs and t



JTDVKH symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

JTG


JTDXKH

symbolizes JTAG timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t

JTG

clock reference (K) going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

4. Non-JTAG signal input timing with respect to t

TCLK

.

5. Non-JTAG signal output timing with respect to t

TCLK

.

This figure provides the AC test load for TDO and the boundary-scan outputs of the device.

Output

Z

0

= 50

Ω

OVDD/2

R

L

= 50

Ω

Figure 32. AC Test Load for the JTAG Interface

This figure provides the JTAG clock input timing diagram.

JTAG

External Clock

VM VM VM t

JTKHKL t

JTG t

JTGR

VM = Midpoint Voltage (OVDD/2)

Figure 33. JTAG Clock Input Timing Diagram

This figure provides the TRST timing diagram.

t

JTGF

TRST VM VM t

TRST


Figure 34. TRST Timing Diagram



This figure provides the boundary-scan timing diagram.

JTAG

External Clock

VM VM t

JTDVKH

Boundary

Data Inputs

Input

Data Valid t

JTKLDV t

JTKLDX

Boundary

Data Outputs

Output Data Valid

Boundary

Data Outputs t

JTKLDZ

Output Data Valid


Figure 35. Boundary-Scan Timing Diagram

This figure provides the test access port timing diagram.

t

JTDXKH

JTAG

External Clock

VM VM t

JTIVKH t

JTIXKH

TDI, TMS

Input

Data Valid t

JTKLOV t

JTKLOX

TDO Output Data Valid

TDO t

JTKLOZ

Output Data Valid


Figure 36. Test Access Port Timing Diagram

54



13 I

2

C

This section describes the DC and AC electrical characteristics for the I

2

C interface of the chip.

13.1

I

2

C DC Electrical Characteristics

This table provides the DC electrical characteristics for the I

2

C interface of the chip.

Table 46. I

2

C DC Electrical Characteristics

At recommended operating conditions with OV

DD

of 3.3 V ± 165 mV.

Input high voltage level

Input low voltage level

Parameter

Low level output voltage

Output fall time from V

IH

(min) to V

IL

(max) with a bus capacitance from 10 to 400 pF

Symbol

V

IH

V

IL

V

OL t

I2KLKV

0.7

Min

× OV

–0.3

0

DD

20 + 0.1

× C

B

Max

OV

DD

+ 0.3

0.3

× OV

DD

0.2

× OV

DD

250

Unit

V

V

V ns

Note

Pulse width of spikes which must be suppressed by the input filter t

I2KHKL

Capacitance for each I/O pin C

I

Input current

(0 V

≤ V

IN

≤ OV

DD

)

I

IN

0

—

—

50

10

± 30 ns pF

μA

3

—

4

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. C

B

= capacitance of one bus line in pF.

3. Refer to the MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter used.

4. I/O pins will obstruct the SDA and SCL lines if OV

DD

is switched off.

1

2

—

—

13.2

I

2

C AC Electrical Specifications

This table provides the AC timing parameters for the I

2

C interface of the device.

Table 47. I

2

C AC Electrical Specifications

All values refer to V

IH

(min) and V

IL

(max) levels (see

Table 46

).

Parameter

Symbol

1

Min

SCL clock frequency

Low period of the SCL clock

High period of the SCL clock

Setup time for a repeated START condition

Hold time (repeated) START condition (after this period, the first clock pulse is generated)

Data setup time f

I2C t

I2CL t

I2CH t

I2SVKH t

I2SXKL t

I2DVKH

0

1.3

0.6

0.6

0.6

100

Max

400

—

—

—

—

—

Unit Note

kHz

μs

μs

μs

μs

—

—

—

—

— ns —



Table 47. I

2

C AC Electrical Specifications (continued)

All values refer to V

IH

(min) and V

IL

(max) levels (see Table 46 ).


1

Min

Data hold time

Setup time for STOP condition

CBUS compatible masters

I

2

Bus free time between a STOP and START condition

C bus devices t

I2DXKL t

I2PVKH t

I2KHDX

V

NL

—

0

0.6

1.3

0.1

× OV

DD

Max

—

0.9

—

—

—

Unit Note

μs

μs

μs

V

2, 3

—

—

— Noise margin at the LOW level for each connected device (including hysteresis)

Noise margin at the HIGH level for each connected device (including hysteresis)

V

NH

0.2

× OV

DD

— V —

Notes:



(reference)(state) symbolizes I

2

for inputs and t



I2DVKH

C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t

I2C


I2SXKL

symbolizes I

2

C timing (I2) for the time that the data with respect to the start condition (S) went invalid (X) relative to the t

I2C

clock reference (K) going to the low (L) state or hold time.

Also, t

I2PVKH

symbolizes I

2

C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t

I2C

clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. This chip provides a hold time of at least 300 ns for the SDA signal (referred to the V

IHmin undefined region of the falling edge of SCL.

of the SCL signal) to bridge the

3. The maximum t

I2DVKH

has only to be met if the device does not stretch the LOW period (t

I2CL

) of the SCL signal.

This figure provides the AC test load for the I

2

C.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OVDD/2

Figure 37. I

2

C AC Test Load

This figure shows the AC timing diagram for the I

2

C bus.

SDA

SCL

S t

I2CF t

I2CL t

I2SXKL t

I2DVKH t

I2SXKL t

I2KHKL t

I2CR t

I2CH t

I2SVKH t

I2DXKL Sr

Figure 38. I

2

C Bus AC Timing Diagram

t

I2PVKH

P t

I2CF

S

56



14 PCI

This section describes the DC and AC electrical specifications for the PCI bus of the chip.

14.1

PCI DC Electrical Characteristics

This table provides the DC electrical characteristics for the PCI interface of the device. The DC characteristics of the PORESET signal, which can be used as PCI RST in applications where the device is a PCI agent, deviates from the standard PCI levels.

Table 48. PCI DC Electrical Characteristics

Parameter Condition Symbol Min Max Unit


Low-level input voltage

High-level output voltage

Low-level output voltage

V

OUT

≥ V

OH

(min) or

V

OUT

≤ V

OL

(max)

I

OH

= –500

μA

I

OL

= 1500

μA

0 V

≤ V

IN

≤ OV

DD

V

V

V

V

IH

IL

OH

OL

Input current I

IN

Note:

• The symbol V

IN

, in this case, represents the OV

IN

symbol referenced in

Table 2 .

2.0

–0.5

OV

DD

+ 0.5

0.3

× OV

DD

V

V

0.9

× OV

DD

— V

— 0.1

× OV

DD

V

— ±

μA

14.2

PCI AC Electrical Specifications

This section describes the general AC timing parameters of the PCI bus of the device. Note that the

PCI_CLK/PCI_SYNC_IN or CLKIN signal is used as the PCI input clock depending on whether the chip is configured as a host or agent device. CLKIN is used when the device is in host mode.

This table shows the PCI AC timing specifications at 66 MHz.

.

Table 49. PCI AC Timing Specifications at 66 MHz

PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1

× OV

DD

, VIH = 0.7

× OV

DD

.

Parameter

Symbol

1


Clock to output valid

Output hold from clock

Clock to output high impedance

Input setup to clock t

PCKHOV t

PCKHOX t

PCKHOZ t

PCIVKH

—

1

—

3.0

6.0

—

14

— ns ns ns ns

2

2

2, 3

2, 4



Table 49. PCI AC Timing Specifications at 66 MHz (continued)


× OV

DD

, VIH = 0.7

× OV

DD

.


1


Input hold from cock

Output clock skew t

PCIXKH t

PCKOSK

0.25

—

—

0.5

ns ns

2, 4, 6

5

Notes:

1. Note that the symbols used for timing specifications herein follow the pattern of t


(reference)(state)

for inputs and t



PCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the

PCI_SYNC_IN clock, t

SYS

, reference (K) going to the high (H) state or setup time. Also, t

PCRHFV

symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.



5. PCI specifications allows 1 ns skew for 66 MHz but includes the total allowed skew, board, connectors, etc.

6. Value does not comply with the PCI 2.3 Local Bus Specifications.

This table shows the PCI AC timing specifications at 33 MHz.

Table 50. PCI AC Timing Specifications at 33 MHz


× OV

DD

, V

IH

= 0.7

× OV

DD

.

Parameter

Symbol

1


Clock to output valid

Output hold from clock t

PCKHOV t

PCKHOX

—

2

11

— ns ns

2

2

Clock to output high impedance

Input setup to clock

Input hold from clock

Output clock skew t

PCKHOZ t

PCIVKH t

PCIXKH t

PCKOSK

—

3.0

0.25

—

14

—

—

0.5

ns ns ns ns

2, 3

2, 4

2, 4, 6

5

Notes:

1. Note that the symbols used for timing specifications herein follow the pattern of t


(reference)(state)

for inputs and t



PCIVKH symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the

PCI_SYNC_IN clock, t

SYS

, reference (K) going to the high (H) state or setup time. Also, t

PCRHFV

symbolizes PCI timing (PC) with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.

2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.



5. PCI specifications allows 2 ns skew for 33 MHz but includes the total allowed skew, board, connectors, etc.

6. Value does not comply with the

PCI 2.3 Local Bus Specifications.

58



This figure provides the AC test load for PCI.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OVDD/2

Figure 39. PCI AC Test Load

This figure shows the PCI input AC timing conditions.

CLK t

PCIVKH t

PCIXKH

Input

Figure 40. PCI Input AC Timing Measurement Conditions

This figure shows the PCI output AC timing conditions.

CLK t

PCKHOV t

PCKHOX

Output Delay t

PCKHOZ

High-Impedance

Output

Figure 41. PCI Output AC Timing Measurement Condition

15 Serial ATA (SATA)

This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the

MPC8379E. Note that the external cabled applications or long backplane applications (Gen1x and Gen2x) are not supported.



15.1

Requirements for SATA REF_CLK

The reference clock is a single ended input clock required for the SATA interface operation. The AC

requirements for the SATA reference clock are listed in the Table 51

.

Table 51. SATA Reference Clock Input Requirements

Parameter

SD_REF_CLK/ SD_REF_CLK frequency range

SD_REF_CLK/ SD_REF_CLK clock frequency tolerance

Condition

—

—

Symbol

t

CLK_REF t

CLK_TOL

Min

—

Typical

100/125/150

–350 0

Max

—

+350

Unit

MHz ppm

Note

1

—

SD_REF_CLK/ SD_REF_CLK reference clock duty cycle

SD_REF_CLK/ SD_REF_CLK cycle to cycle Clock jitter (period jitter)

Measured at 1.6V

Cycle-to-cycle at ref clock input

SD_REF_CLK/ SD_REF_CLK total reference clock jitter, phase jitter

(peak-peak)

Peak-to-peak jitter at ref clock input t

CLK_DUTY t t

CLK_CJ

CLK_PJ

40

—

–50

50

—

—

60

100

+50

% ps ps

Notes:

1. Only 100/125/150 MHz have been tested, other in between values will not work correctly with the rest of the system.

2. In a frequency band from 150 kHz to 15 MHz at BER of 10

-12

.

3. Total peak to peak Deterministic Jitter "D

J

" should be less than or equal to 50 ps.

—

—

2, 3

This figure shows the SATA reference clock timing waveform.

T

H

Ref_CLK

T

L

Figure 42. SATA Reference Clock Timing Waveform

15.2

Transmitter (Tx) Output Characteristics

This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA interface.

60



15.2.1

Gen1i/1.5G Transmitter Specifications

This table provides the DC differential transmitter output DC characteristics for the SATA interface at

Gen1i or 1.5 Gbits/s transmission.

Table 52. Gen1i/1.5G Transmitter (Tx) DC Specifications

Parameter

Tx differential output voltage

Tx differential pair impedance

Note:

1. Terminated by 50

Ω load.

Symbol

V

SATA_TXDIFF

Z

SATA_TXDIFFIM

Min

400

85

Typical

500

100

Max

600

115

Units

mV p-p

Ω

Note

1

—

This table provides the differential transmitter output AC characteristics for the SATA interface at Gen1i or 1.5 Gbits/s transmission.

Table 53. Gen1i/1.5G Transmitter AC Specifications

Parameter Symbol Min Typical

Channel speed

Unit interval

Total jitter, data-data

5 UI


250 UI

Deterministic jitter, data-data

5 UI

U

U

SATA_TXTJ250UI

U t

CH_SPEED

T

UI

SATA_TXTJ5UI

SATA_TXDJ5UI

—

666.4333

—

—

—

1.5

666.667

—

—

—


250 UI

U

SATA_TXDJ250UI

— —

Note:

1. Measured at Tx output pins peak to peak phase variation, random data pattern.

Max

—

670.2333

0.355

0.47

0.175

0.22

Units

Gbps ps

UI p-p

UI p-p

UI p-p

UI p-p

Note

—

—

1

1

1

1

15.2.2

Gen2i/3G Transmitter Specifications

This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission.

Table 54. Gen 2i/3G Transmitter DC Specifications

Parameter

Tx differential output voltage

Tx differential pair impedance

Note:

1. Terminated by 50

Ω load.

Symbol

V

SATA_TXDIFF

Z

SATA_TXDIFFIM

Min

400

85

Typical

550

100

Max

700

115

Units

mV p-p

Ω

Note

1

—



This table provides the differential transmitter output AC characteristics for the SATA interface at Gen2i or 3.0 Gbits/s transmission.

Table 55. Gen 2i/3G Transmitter AC Specifications


Channel speed

Unit interval t

CH_SPEED

T

UI

U

SATA_TXTJfB/10

—

333.2

3.0

333.33

Total jitter f

C3dB

=f

BAUD

/10

Total jitter f

C3dB

= f

BAUD

/500

Total jitter f

C3dB

= f

BAUD

/1667

Deterministic jitter f

C3dB

= f

BAUD

/10

U

U

SATA_TXTJfB/1667

U

SATA_TXTJfB/500

SATA_TXDJfB/10

—

—

—

—

—

—

—

—


C3dB

= f

BAUD

/500


C3dB

= f

BAUD

/1667

U

U

SATA_TXDJfB/500

SATA_TXDJfB/1667

—

—

—

—

Note:


Max

—

335.11

0.3

0.37

0.55

0.17

0.19

0.35

Units

Gbps ps

UI p-p

UI p-p

UI p-p

UI p-p

UI p-p

UI p-p

Note

—

—

1

1

1

1

1

1

15.3

Differential Receiver (Rx) Input Characteristics

This section discusses the Gen1i/1.5G and Gen2i/3G differential receiver input AC characteristics.

15.3.1

Gen1i/1.5G Receiver Specifications

This table provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA interface.

Table 56. Gen1i/1.5G Receiver Input DC Specifications

Parameter Symbol Min

Differential input voltage

Differential Rx input impedance

V

SATA_RXDIFF

Z

SATA_RXSEIM

240

85

Note:

1. Voltage relative to common of either signal comprising a differential pair.

Typical

500

100

Max

600

115

Units

mV p-p

Ω

Note

1

—

62



This table provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA interface.

Table 57. Gen 1i/1.5G Receiver AC Specifications


Unit interval


5 UI


250 UI


5 UI

U

U

SATA_TXTJ250UI

U

T

UI

SATA_TXTJ5UI

SATA_TXDJ5UI

666.4333

—

—

—

666.667

—

—

—


250 UI

U

SATA_TXDJ250UI

— —

Note:


Max

670.2333

0.43

0.60

0.25

0.35

Units

ps

UI p-p

UI p-p

UI p-p

UI p-p

Note

—

1

1

1

1

15.3.2

Gen2i/3G Receiver (Rx) Specifications

This table provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA interface.

Table 58. Gen2i/3G Receiver Input DC Specifications


Differential input voltage

Differential RX input impedance

V

SATA_RXDIFF

Z

SATA_RXSEIM

275

85

Note:

1. Voltage relative to common of either signal comprising a differential pair.

500

100

Max

750

115

Units

mVp-p

Ω

Note

1

—

This table provides the differential receiver output AC characteristics for the SATA interface at Gen2i or

3.0 Gbits/s transmission.

Table 59. Gen 2i/3G Receiver AC Specifications

Parameter

Channel Speed

Unit Interval

Total jitter f

C3dB

= f

BAUD

/10

Total jitter f

C3dB

= f

BAUD

/500

Total jitter f

C3dB

= f

BAUD

/1667

Symbol

t

CH_SPEED

T

UI

U

SATA_TXTJfB/10

U

SATA_TXTJfB/500

U

SATA_TXTJfB/1667

Min

—

333.2

—

—

—

Typical

3.0

333.33

—

—

—

Max

—

335.11

0.46

0.60

0.65

Units

Gbps ps

UI p-p

UI p-p

UI p-p

Note

—

—

1

1

1



Table 59. Gen 2i/3G Receiver AC Specifications (continued)



C3dB

= f

BAUD

/10


C3dB

= f

BAUD

/500

U

U

SATA_TXDJfB/10

SATA_TXDJfB/500

—

—

—

—


C3dB

= f

BAUD

/1667

U

SATA_TXDJfB/1667

— —

Note:


Max

0.35

0.42

0.35

Units

UI p-p

UI p-p

UI p-p

Note

1

1

1

16 Timers

This section describes the DC and AC electrical specifications for the timers of the chip.

16.1

Timers DC Electrical Characteristics

This table provides the DC electrical characteristics for the device timers pins, including TIN, TOUT,

TGATE, and RTC_CLK.

Table 60. Timers DC Electrical Characteristics

Parameter

Output high voltage

Output low voltage

Output low voltage

Input high voltage

Input low voltage

Input current

Condition

I

OH

= –6.0 mA

I

OL

= 6.0 mA

I

OL

= 3.2 mA

—

—

0 V

≤ V

IN

≤ OV

DD

Symbol

V

OH

V

OL

V

OL

V

IH

V

IL

I

IN

Min

2.4

—

—

2.0

–0.3

Max

—

0.5

0.4

OV

DD

+ 0.3

0.8

Unit

V

V

V

V

V

μA

16.2

Timers AC Timing Specifications

This table provides the timers input and output AC timing specifications.

Table 61. Timers Input AC Timing Specifications

1

Timers inputs—minimum pulse width t

TIWID

20 ns

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.

2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any external synchronous logic. Timers inputs are required to be valid for at least t

TIWID

ns to ensure proper operation

64



This figure provides the AC test load for the timers.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OVDD/2

Figure 43. Timers AC Test Load

17 GPIO

This section describes the DC and AC electrical specifications for the GPIO of the chip.

17.1

GPIO DC Electrical Characteristics

This table provides the DC electrical characteristics for the device GPIO.

Table 62. GPIO DC Electrical Characteristics

This specification applies when operating at 3.3 V ± 165 mV supply.

Parameter

Output high voltage

Output low voltage

Output low voltage

Input high voltage

Input low voltage

Input current

Condition

I

OH

= –6.0 mA

I

OL

= 6.0 mA

I

OL

= 3.2 mA

—

—

0 V

≤ V

IN

≤ OV

DD

Symbol

V

OH

V

OL

V

OL

V

IH

V

IL

I

IN

Min

2.4

—

—

2.0

–0.3

—

Max

—

0.5

0.4

OV

DD

+ 0.3

0.8

± 30

17.2

GPIO AC Timing Specifications

This table provides the GPIO input and output AC timing specifications.

Table 63. GPIO Input AC Timing Specifications


GPIO inputs—minimum pulse width t

PIWID

20 ns

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLKIN. Timings are measured at the pin.

2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any external synchronous logic. GPIO inputs are required to be valid for at least t

PIWID ns to ensure proper operation.

Unit

V

V

V

V

V

μA



This figure provides the AC test load for the GPIO.

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OVDD/2

Figure 44. GPIO AC Test Load

18 IPIC

This section describes the DC and AC electrical specifications for the external interrupt pins of the chip.

18.1

IPIC DC Electrical Characteristics

This table provides the DC electrical characteristics for the external interrupt pins of the chip.

Table 64. IPIC DC Electrical Characteristics

Parameter Condition Symbol Min

Input high voltage

Input low voltage

—

—

V

IH

V

IL

Input current

Output low voltage

Output low voltage

—

I

OL

= 6.0 mA

I

OL

= 3.2 mA

I

IN

V

OL

V

OL

Note:

1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT.

2. IRQ_OUT and MCP_OUT are open drain pins, thus V

OH

is not relevant for those pins.

2.0

–0.3

—

—

—

Max

OV

DD

+ 0.3

0.8

±30

0.5

0.4

18.2

IPIC AC Timing Specifications

This table provides the IPIC input and output AC timing specifications.

Table 65. IPIC Input AC Timing Specifications


IPIC inputs—minimum pulse width t

PIWID

20 ns

Note:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin.

2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any external synchronous logic. IPIC inputs are required to be valid for at least t

PIWID ns to ensure proper operation when working in edge triggered mode.

Unit

V

V

μA

V

V

19 SPI

This section describes the DC and AC electrical specifications for the SPI of the chip.

66



19.1

SPI DC Electrical Characteristics

This table provides the DC electrical characteristics for the device SPI.

Table 66. SPI DC Electrical Characteristics

Parameter

Input high voltage

Input low voltage

Input current

Output high voltage

Output low voltage

Output low voltage

Condition

—

—

—

I

OH

= –8.0 mA

I

OL

= 8.0 mA

I

OL

= 3.2 mA

Symbol

V

IH

V

IL

I

IN

V

OH

V

OL

V

OL

Min

2.0

–0.3

—

2.4

—

—

Max

OV

DD

+ 0.3

0.8

± 30

—

0.5

0.4

19.2

SPI AC Timing Specifications

This table provides the SPI input and output AC timing specifications.

Table 67. SPI AC Timing Specifications


1

Min Max Unit

SPI outputs—Master mode (internal clock) delay

SPI outputs—Slave mode (external clock) delay

SPI inputs—Master mode (internal clock) input setup time

SPI inputs—Master mode (internal clock) input hold time t

NIKHOV t

NEKHOV t

NIIVKH t

NIIXKH

0.5

2

4

0

6

8

—

— ns ns ns ns

SPI inputs—Slave mode (external clock) input setup time

SPI inputs—Slave mode (external clock) input hold time t

NEIVKH t

NEIXKH

4

2

—

— ns ns

Notes:

1. The symbols used for timing specifications follow the pattern of t

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t



NIKHOV

symbolizes the internal timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. The maximum SPICLK input frequency is 66.666 MHz.

This figure provides the AC test load for the SPI.

Unit

V

V

μA

V

V

V

Output

Z

0

= 50

Ω

R

L

= 50

Ω

OVDD/2

Figure 45. SPI AC Test Load

These figures represent the AC timing from Table 67 . Note that although the specifications generally

reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.



This figure shows the SPI timing in slave mode (external clock).

SPICLK (input) tN

EIXKH t

NEIVKH

Input Signals:

SPIMOSI

(See Note) t

NEKHOV

Output Signals:

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

Figure 46. SPI AC Timing in Slave Mode (External Clock) Diagram

This figure shows the SPI timing in master mode (internal clock).

SPICLK (output) t

NIIXKH t

NIIVKH

Input Signals:

SPIMISO

(See Note) t

NIKHOV

Output Signals:

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

Figure 47. SPI AC Timing in Master Mode (Internal Clock) Diagram

20 High-Speed Serial Interfaces (HSSI)

This chip features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial interconnect applications. See

Table 1 for the interfaces supported.

This section describes the common portion of SerDes DC electrical specifications, which is the DC requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits are also shown.

20.1

Signal Terms Definition

The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals.

Figure 48

shows how the signals are defined. For illustration purpose, only one SerDes lane is used for description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B.

68



Using this waveform, the definitions are as follows. To simplify illustration, the following definitions assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling environment.

• Single-Ended Swing

The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and

SDn_RX each have a peak-to-peak swing of A

–

B volts. This is also referred as each signal wire’s single-ended swing.

•

Differential Output Voltage, V

OD

(or Differential Output Swing):

The differential output voltage (or swing) of the transmitter, V

OD

, is defined as the difference of the two complimentary output voltages: V or negative.

SDn_TX

–

V

SDn_TX

. The V

OD value can be either positive

•

Differential Input Voltage, V

ID

(or Differential Input Swing):

The differential input voltage (or swing) of the receiver, V

ID

, is defined as the difference of the two complimentary input voltages: V

SDn_RX

–

V

SDn_RX.

The V

ID value can be either positive or negative.

• Differential Peak Voltage, V

DIFFp

The peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak voltage, V

DIFFp

= |A

–

B| volts.

• Differential Peak-to-Peak, V

DIFFp-p

Since the differential output signal of the transmitter and the differential input signal of the receiver each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,

V

DIFFp-p

= 2

× V

DIFFp

= 2

× |(A – B)| volts, which is twice of differential swing in amplitude, or twice of the differential peak. For example, the output differential peak-peak voltage can also be calculated as V

TX-DIFFp-p

= 2

× |V

OD

|.

• Differential Waveform

The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for example) from the non-inverting signal (SDn_TX, for example) within a differential pair. There is only one signal trace curve in a differential waveform. The voltage represented in the differential

waveform is not referenced to ground. Refer to Figure 57 as an example for differential waveform.

• Common Mode Voltage, V cm

The common mode voltage is equal to one half of the sum of the voltages between each conductor of a balanced interchange circuit and ground. In this example, for SerDes output,

V cm_out

= (V

SDn_TX

+ V

SDn_TX

)

÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two complimentary output voltages within a differential pair. In a system, the common mode voltage may often differ from one component’s output to the other’s input. Sometimes it may be even different between the receiver input and driver output circuits within the same component. It is also referred as the DC offset in some occasion.



SD n_TX or

SD n_RX

A Volts

V cm

= (A + B)/2

SD n_TX or

SD n_RX

B Volts

Differential Swing, VID or VOD = A – B

Differential Peak Voltage, VDIFFp = |A – B|

Differential Peak-Peak Voltage, VDIFFpp = 2

× VDIFFp (not shown)

Figure 48. Differential Voltage Definitions for Transmitter or Receiver

To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing

that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD

or TD) is 500 mV p-p

, which is referred as the single-ended swing for each signal. In this example, since the differential signaling environment is fully symmetrical, the transmitter output’s differential swing

(V

OD

) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges between 500 mV and –500 mV, in other words, V

OD

is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (V

DIFFp

) is 500 mV. The peak-to-peak differential voltage (V

DIFFp-p

) is 1000 mV p-p

.

20.2

SerDes Reference Clocks

The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and

SD1_REF_CLK for both lanes of SerDes1, and SD2_REF_CLK and SD2_REF_CLK for both lanes of

SerDes2.

The following sections describe the SerDes reference clock requirements and some application information.

20.2.1

SerDes Reference Clock Receiver Characteristics

Figure 49

shows a receiver reference diagram of the SerDes reference clocks.

• SerDes Reference Clock Receiver Reference Circuit Structure

— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as

shown in Figure 49 . Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a

50

Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.

— The external reference clock driver must be able to drive this termination.

70



— The SerDes reference clock input can be either differential or single-ended. Refer to the

Differential Mode and Single-ended Mode description below for further detailed requirements.

• The maximum average current requirement that also determines the common mode voltage range

— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage is not critical as long as it is within the range allowed by the maximum average current of 8 mA (refer to the following bullet for more detail), since the input is AC-coupled on-chip.

— This current limitation sets the maximum common mode input voltage to be less than 0.4 V

(0.4 V

÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above

SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode voltage at 400 mV.

— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50

Ω to

SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it must be AC-coupled off-chip.

• The input amplitude requirement

— This requirement is described in detail in the following sections.

50

Ω

SD n_REF_CLK

Input

Amp

SD n_REF_CLK

50

Ω

Figure 49. Receiver of SerDes Reference Clocks

20.2.2

DC Level Requirement for SerDes Reference Clocks

The DC level requirement for the device SerDes reference clock inputs is different depending on the signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described below.

• Differential Mode

— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have a single-ended swing less than 800 mV and



greater than 200 mV. This requirement is the same for both external DC-coupled or

AC-coupled connection.

— For external DC-coupled connection, as described in

Section 20.2.1, “SerDes Reference

Clock Receiver Characteristics,”

the maximum average current requirements sets the requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.

Figure 50

shows the SerDes reference clock input requirement for DC-coupled connection scheme.

— For external AC-coupled connection, there is no common mode voltage requirement for the clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver and the SerDes reference clock receiver operate in different command mode voltages. The

SerDes reference clock receiver in this connection scheme has its common mode voltage set to

SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above the command mode voltage (SGND_SRDSn).

Figure 51

shows the SerDes reference clock input requirement for AC-coupled connection scheme.

• Single-ended Mode

— The reference clock can also be single-ended. The SD _REF_CLK input amplitude

(single-ended swing) must be between 400 mV and 800 mV p-p

SDn_REF_CLK either left unconnected or tied to ground.

(from V min

to V max

) with

— The SDn_REF_CLK input average voltage must be between 200 mV and 400 mV. Figure 52

shows the SerDes reference clock input requirement for single-ended signaling mode.

— To meet the input amplitude requirement, the reference clock inputs might need to be DC or

AC-coupled externally. For the best noise performance, the reference of the clock could be DC or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as the clock input (SDn_REF_CLK) in use.

200 mV < Input Amplitude or Differential Peak < 800 mV

SD n_REF_CLK

V max

< 800 mV

100 mV < V cm

< 400 mV

SD n_REF_CLK

V min

> 0 V

Figure 50. Differential Reference Clock Input DC Requirements (External DC-Coupled)

72



SD n_REF_CLK

200 mV < Input Amplitude or Differential Peak < 800 mV

150 fdafdV max

< V cm

+ 400 mV

V max

< V cm

+ 400 mV

Vcm

SD n_REF_CLK

V min

> V cm

– 400m V

Figure 51. Differential Reference Clock Input DC Requirements (External AC-Coupled)

400 mV < SD n_REF_CLK Input Amplitude < 800 mV

SD n_REF_CLK

0 V

SD n_REF_CLK

Figure 52. Single-Ended Reference Clock Input DC Requirements

20.2.3

Interfacing With Other Differential Signaling Levels

The following list provides information about interfacing with other differential signaling levels.

• With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are

HCSL (high-speed current steering logic) compatible DC-coupled.

• Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can be used but may need to be AC-coupled due to the limited common mode input range allowed

(100 mV to 400 mV) for DC-coupled connection.

• LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling.



NOTE

Figure 53

to

Figure 56 below are for conceptual reference only. Due to the

fact that clock driver chip's internal structure, output impedance, and termination requirements are different between various clock driver chip manufacturers, it is very possible that the clock circuit reference designs provided by the clock driver chip vendor are different from what is shown below. They might also vary from one vendor to the other. Therefore,

Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended to contact the selected clock driver chip vendor for the optimal reference circuits with the device SerDes reference clock receiver requirement provided in this document.

This figure shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It assumes that the DC levels of the clock driver chip is compatible with device SerDes reference clock input’s DC requirement.

HCSL CLK Driver Chip

CLK_Out

33

Ω

SD n_REF_CLK

50

Ω

Chip

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

33

Ω

SD n_REF_CLK

50

Ω

Total 50

Ω. Assume clock driver’s output impedance is about 16

Ω.

Clock driver vendor dependent source termination resistor

Figure 53. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)

This figure shows the SerDes reference clock connection reference circuits for LVDS type clock driver.

Since LVDS clock driver’s common-mode voltage is higher than the device SerDes reference clock input’s allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the LVDS

74



output driver features a 50-

Ω termination resistor. It also assumes that the LVDS transmitter establishes its own common mode level without relying on the receiver or other external component.

Chip

LVDS CLK Driver Chip

CLK_Out

10 nF

SD n_REF_CLK

50

Ω

100


SerDes Refer.

CLK Receiver

CLK_Out

10 nF

SD n_REF_CLK

50

Ω

Figure 54. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 55

shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with device SerDes reference clock input’s DC requirement, AC-coupling has to be used.

Figure 55

assumes that the LVPECL clock driver’s output impedance is 50

Ω. R1 is used to DC-bias the LVPECL outputs prior to AC-coupling. Its value could be ranged from 140

Ω to 240 Ω depending on clock driver vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50

Ω termination resistor to attenuate the LVPECL output’s differential peak level such that it meets the device SerDes reference clock’s differential input amplitude requirement (between 200 mV and 800 mV differential peak). For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25

Ω. Consult clock



driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip.

Chip

LVPECL CLK Driver Chip

CLK_Out

R2

10 nF

SD n_REF_CLK

50

Ω

SerDes Refer.

CLK Receiver

CLK_Out

R1

100


R2

10 nF

SD n_REF_CLK

R1

50

Ω

Figure 55. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.

It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC requirement.

Single-Ended CLK

Driver Chip

Clock Driver

CLK_Out

33

Ω

Total 50

Ω. Assume clock driver’s output impedance is about 16

Ω.

SD n_REF_CLK

50

Ω

100


Chip

SerDes Refer.

CLK Receiver

50

Ω

SD n_REF_CLK

50

Ω

Figure 56. Single-Ended Connection (Reference Only)

20.2.4

AC Requirements for SerDes Reference Clocks

The clock driver selected should provide a high quality reference clock with low phase noise and cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise

76



occurs in the 1–15 MHz range. The source impedance of the clock driver should be 50

Ω to match the transmission line and reduce reflections which are a source of noise to the system.

This table describes some AC parameters common to SATAprotocols

Table 68. SerDes Reference Clock Common AC Parameters

At recommended operating conditions with XV

DD_SRDS

or XV

DD_SRDS

= 1.0 V ± 5%.


Rising Edge Rate

Falling Edge Rate

Rise Edge Rate

Fall Edge Rate

1.0

1.0

4.0

4.0

V/ns

V/ns

2, 3

2, 3

Differential Input High Voltage

Differential Input Low Voltage

V

IH

V

IL

Rise-Fall Matching

200

—

—

–200 mV mV

2

2

Rising edge rate (SD n_REF_CLK) to falling edge rate

(SD n_REF_CLK) matching

— 20 %

1, 4

Notes:

1. Measurement taken from single ended waveform.

2. Measurement taken from differential waveform.

3. Measured from –200 mV to +200 mV on the differential waveform (derived from SD n_REF_CLK minus SDn_REF_CLK).

The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is centered on the differential zero crossing. See

Figure 57 .

4. Matching applies to rising edge rate for SD n_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a

200 mV window centered on the median cross point where SDn_REF_CLK rising meets SD n_REF_CLK falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The

Rise Edge Rate of SD n_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed

difference should not exceed 20% of the slowest edge rate. See Figure 58

.

Rise Edge Rate Fall Edge Rate

VIH = +200 mV

0.0 V

VIL = –200 mV

SD n_REF_CLK

Minus

SD n_REF_CLK

Figure 57. Differential Measurement Points for Rise and Fall Time

SD n_REF_CLK

SD n_REF_CLK

T

FALL

T

RISE

V

CROSS MEDIAN

V

CROSS MEDIAN

+100 mV

V

CROSS MEDIAN

V

CROSS MEDIAN

–100 mV

SD n_REF_CLK SD n_REF_CLK

Figure 58. Single-Ended Measurement Points for Rise and Fall Time Matching



20.3

SerDes Transmitter and Receiver Reference Circuits

This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.

50

Ω

SD1_TX n or

SD2_TX n

SD1_RX n or

SD2_RX n

Transmitter

50

Ω

Receiver

50

Ω

SD1_TX n or

SD2_TX n

SD1_RX n or

SD2_RX n

50

Ω

Figure 59. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in each interface protocol section below in this document based on the application usage:

•

Section 8, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC)”

•

Section 15, “Serial ATA (SATA)”

Note that an external AC coupling capacitor is required for the above three serial transmission protocols with the capacitor value defined in specification of each protocol section.

21 Package and Pin Listings

This section details package parameters, pin assignments, and dimensions.

21.1

Package Parameters for the MPC8379E TePBGA II

The package parameters are provided in the following list. The package type is 31 mm

× 31 mm,

689 plastic ball grid array (TePBGA II).

Package outline 31 mm

× 31 mm

Interconnects 689

Pitch 1.00 mm

Module height (typical)

Solder Balls

Ball diameter (typical)

2.0 mm to 2.46 mm (maximum)

3.5% Ag, 96.5% Sn

0.60 mm

78



This figure shows the mechanical dimensions and bottom surface nomenclature of the TEPBGA II package.

Figure 60. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II

Note:

1

All dimensions are in millimeters.

2

Dimensioning and tolerancing per ASME Y14. 5M-1994.

3

Maximum solder ball diameter measured parallel to Datum A.

4

Datum A, the seating plane, is determined by the spherical crowns of the solder balls.



5

Parallelism measurement should exclude any effect of mark on top surface of package.

MA8

MA9

MA10

MA11

MA12

MA13

MA14

MBA0

MBA1

MA0

MA1

MA2

MA3

MA4

MA5

MA6

MA7

21.2

Pinout Listings

This table provides the pinout listing for the TePBGA II package.

Table 69. TePBGA II Pinout Listing

Signal Package Pin Number Pin Type

CLKIN

PCI_CLK/PCI_SYNC_IN

PCI_SYNC_OUT

PCI_CLK0

PCI_CLK1

PCI_CLK2

PCI_CLK3

PCI_CLK4

RTC/PIT_CLOCK

N1

M2

M1

U5

U4

P1

N4

V3

M5

T2

T1

R1

P2

U3

U1

T5

T3

Clock Signals

K24

C10

N24

L24

M24

M25

M26

L26

AF11

DDR SDRAM Memory Interface

O

O

O

O

I

O

O

I

I

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Power Supply Note

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

—

—

—

—

—

—

—

3

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

80



Signal

MDM2

MDM3

MDM4

MDM5

MDM6

MDM7

MDM8

MDQ0

MDQ1

MCS_B0

MCS_B1

MCS_B2

MCS_B3

MDIC0

MDIC1

MDM0

MDM1

MCK0

MCK1

MCK2

MCK3

MCK4

MCK5

MCKE0

MCKE1

MBA2

MCAS_B

MCK_B0

MCK_B1

MCK_B2

MCK_B3

MCK_B4

MCK_B5

Table 69. TePBGA II Pinout Listing (continued)

Package Pin Number Note

—

—

—

11

11

—

—

—

—

—

—

9

9

—

—

—

—

3

3

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Power Supply

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

Pin Type

O

O

O

I/O

I/O

O

O

O

O

I/O

I/O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

AE6

AJ4

L6

A8

A6

E2

E1

Y6

AC6

AH8

AJ8

B6

B2

W3

P3

T4

R4

Y1

AB1

M4

R5

J1

L1

V2

W1

V1

W2

AA1

AB2

M3

W5

H1

K1



82

Signal

MDQ26

MDQ27

MDQ28

MDQ29

MDQ30

MDQ31

MDQ32

MDQ33

MDQ34

MDQ18

MDQ19

MDQ20

MDQ21

MDQ22

MDQ23

MDQ24

MDQ25

MDQ10

MDQ11

MDQ12

MDQ13

MDQ14

MDQ15

MDQ16

MDQ17

MDQ2

MDQ3

MDQ4

MDQ5

MDQ6

MDQ7

MDQ8

MDQ9


Package Pin Number

H5

F1

W6

AC1

AC3

H6

H4

D1

G3

C1

G6

F2

G5

F6

G4

F8

E4

C3

C2

D4

E6

B1

D5

B3

D6

A3

C6

D7

E8

C7

D8

A7

A5

Pin Type

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Note

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

Power Supply

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD



Signal

MDQ59

MDQ60

MDQ61

MDQ62

MDQ63

MDQS0

MDQS1

MDQS2

MDQS3

MDQ51

MDQ52

MDQ53

MDQ54

MDQ55

MDQ56

MDQ57

MDQ58

MDQ43

MDQ44

MDQ45

MDQ46

MDQ47

MDQ48

MDQ49

MDQ50

MDQ35

MDQ36

MDQ37

MDQ38

MDQ39

MDQ40

MDQ41

MDQ42


Package Pin Number Note

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

11

Power Supply

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

Pin Type

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

AH7

C8

C4

E3

G2

AJ5

AF6

AF7

AH6

AG4

AH3

AG5

AF8

AF5

AE5

AD7

AH2

AE3

AG1

AG2

AG3

AF1

AE4

AC5

AE2

AB6

AD3

AC4

AD4

AE1

V6

Y5

AA4



84

Signal

MDQS4

MDQS5

MDQS6

MDQS7

MDQS8

MECC0/MSRCID0

MECC1/MSRCID1

MECC2/MSRCID2

MECC3/MSRCID3

MECC4/MSRCID4

MECC5/MDVAL

MECC6

MECC7

MODT0

MODT1

MODT2

MODT3

MRAS_B

MVREF1

MVREF2

MWE_B

UART_SIN1/

MSRCID2/LSRCID2

UART_SOUT1/

MSRCID0/LSRCID0

UART_CTS_B[1]/

MSRCID4/LSRCID4

UART_RTS_B1

UART_SIN2/

MSRCID3/LSRCID3

UART_SOUT2/

MSRCID1/LSRCID1

UART_CTS_B[2]/

MDVAL/LDVAL



L2

N5

U6

M6

K3

J5

J2

L5

P6

AA3

K4

W4

Y2

G1

J6

J3

K2

AB5

AD1

AH1

AJ3

DUART Interface

L28

Pin Type

I/O

O

O

O

I/O

I/O

I/O

I/O

I

I

O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

L27 O

K26

N27

K27

K28

K29

I/O

O

I/O

O

I/O

Note

6

6

—

6

—

—

—

—

6

—

11

11

—

11

—

—

—

11

11

11

11

Power Supply

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

GVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

—

—

—

—

—

—

—



Signal

UART_RTS_B[2]

LA11/LAD16

LA12/LAD17

LA13/LAD18

LA14/LAD19

LA15/LAD20

LA16/LAD21

LA17/LAD22

LA18/LAD23

LA19/LAD24

LA20/LAD25

LA21/LAD26

LA22/LAD27

LA23/LAD28

LA24/LAD29

LAD8

LAD9

LAD10

LAD11

LAD12

LAD13

LAD14

LAD15

LAD0

LAD1

LAD2

LAD3

LAD4

LAD5

LAD6

LAD7



L29

A27

C25

B27

H27

E21

F20

H24

E23

B28

D28

F27

B21

A25

C28

G24

F25

H28

G25

E25

E26

A23

F24

C26

J28

F21

F23

E24

G28

H25

F26

Pin Type

O

Enhanced Local Bus Controller (eLBC) Interface



LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

Note

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Power Supply

OVDD

85

86

Signal

LCS_B4/LDP0

LCS_B5/LDP1

LA7/LCS_B6/LDP2

LA8/LCS_B7/LDP3

LFCLE/LGPL0

LFALE/LGPL1

LFRE_B/LGPL2/LOE_B

LFWP_B/LGPL3

LGPL4/LFRB_B/LGTA_B/

LUPWAIT/LPBSE

LA9/LGPL5

LSYNC_IN

LSYNC_OUT

LWE_B0/LFWE0/LBS_B0

LWE_B1/LFWE1/LBS_B1

LWE_B2/LFWE2/LBS_B2

LWE_B3/LFWE3/LBS_B3

LA25/LAD30

LA26/LAD31

LA27

LA28

LA29

LA30

LA31

LA10/LALE

LBCTL

LCLK0

LCLK1

LCLK2

LCS_B0

LCS_B1

LCS_B2

LCS_B3



D25

F19

C27

D24

A22

B22

C23

B23

E28

B26

J25

H29

D29

E20

H26

C29

D21

A26

F22

C21

J29

C24

B29

E29

F29

Pin Type

O

O

O

O

O

O

O

O

O

O

O

O

I/O

I/O

O

O

O

O

O

O

I/O

I/O

I/O

I/O

I/O

G29

A21

D23

E22

B25

E27

F28

O

O

O

O

O

O

I

Note

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

17

—

—

—

—

Power Supply

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

LBVDD

—

—

—

—

—

—

—



Signal

TSEC1_COL/GPIO2[20]

TSEC1_CRS/GPIO2[21]

TSEC1_GTX_CLK

TSEC1_RX_CLK

TSEC1_RX_DV

TSEC1_RX_ER/GPIO2[25]

TSEC1_RXD0

TSEC1_RXD1

TSEC1_RXD2

TSEC1_RXD3

TSEC1_TX_CLK

TSEC1_TX_EN

TSEC1_TX_ER/CFG_LBMUX

TSEC1_TXD0/

CFG_RESET_SOURCE[0]

TSEC1_TXD1/

CFG_RESET_SOURCE[1]

TSEC1_TXD2/

CFG_RESET_SOURCE[2]

TSEC1_TXD3/

CFG_RESET_SOURCE[3]

EC_GTX_CLK125

EC_MDC/CFG_CLKIN_DIV

EC_MDIO


Package Pin Number Pin Type eTSEC1/GPIO1/GPIO2/CFG_RESET Interface

AE22

AD21

AJ22

AG23

AH22

AD23

AF22

AE20

AJ25

AG22

AD19

AD20

AD22

AE21

I

O

I

I

I/O

I/O

I

I

I

I/O

I/O

I/O

O

I

AE23

AF23

AJ24

AH24

AJ21

AH21

eTSEC2/GPIO1 Interface

AJ27

I/O

I/O

I/O

I

I/O

I/O

I/O TSEC2_COL/GPIO1[21]/

TSEC1_TMR_TRIG1

TSEC2_CRS/GPIO1[22]/

TSEC1_TMR_TRIG2

TSEC2_GTX_CLK

TSEC2_RX_CLK/

TSEC1_TMR_CLK

TSEC2_RX_DV/GPIO1[23]

TSEC2_RX_ER/GPIO1[25]

AG29

AF28

AF25

AF26

AG25

I/O

O

I

I/O

I/O

Power Supply Note

LVDD2

LVDD2

LVDD2

LVDD2

LVDD2

LVDD2

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

LVDD1

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17



Signal

TSEC2_RXD0/GPIO1[16]




TSEC2_TX_CLK/GPIO2[24]/

TSEC1_TMR_GCLK

TSEC2_TX_EN/GPIO1[12]/

TSEC1_TMR_ALARM2

TSEC2_TX_ER/GPIO1[24]/

TSEC1_TMR_ALARM1

TSEC2_TXD0/GPIO1[20]

TSEC2_TXD1/GPIO1[19]/

TSEC1_TMR_PP1


TSEC1_TMR_PP2


TSEC1_TMR_PP3



AE28

AE29

AH26

AH25

AG28

Pin Type

I/O

I/O

I/O

I/O

I/O

AJ26

AG26

AH28

AF27

AJ28

AF29

I/O

I/O

I/O

I/O

I/O

I/O

GPIO1 Interface

P25 I/O GPIO1[0]/GTM1_TIN1/

GTM2_TIN2/DREQ0_B

GPIO1[1]/GTM1_TGATE1_B/

GTM2_TGATE2_B/DACK0_B

GPIO1[2]/GTM1_TOUT1_B/

DDONE0_B

GPIO1[3]/GTM1_TIN2/

GTM2_TIN1/DREQ1_B




GTM2_TOUT1_B/DDONE1_B

GPIO1[6]/GTM1_TIN3/

GTM2_TIN4/DREQ2_B




DDONE2_B

GPIO1[9]/GTM1_TIN4/

GTM2_TIN3/DREQ3_B

N25

N26

B9

N29

M29

A9

B10

J26

J24

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

Power Supply

LVDD2

LVDD2

LVDD2

LVDD2

LVDD2

Note

17

17

17

17

17

LVDD2

17

LVDD2

LVDD2

LVDD2

LVDD2

LVDD2

17

17

17

17

17

—

—

—

—

—

—

—

—

—

—

88



Signal




GTM2_TOUT3_B/DDONE3_B



J27

Pin Type

I/O

P24 I/O

USB/GPIO2 Interface

AJ11

AG12

I/O

I/O

USBDR_CLK/GPIO2[23]

USBDR_DIR_DPPULLUP/

GPIO2[9]

USBDR_NXT/GPIO2[8]

USBDR_PCTL0/GPIO2[11]/

SD_DAT2

USBDR_PCTL1/GPIO2[22]/

SD_DAT3

USBDR_PWRFAULT/

GPIO2[10]/SD_DAT1

USBDR_STP_SUSPEND

USBDR_D0_ENABLEN/

GPIO2[0]

USBDR_D1_SER_TXD/

GPIO2[1]

USBDR_D2_VMO_SE0/

GPIO2[2]

USBDR_D3_SPEED/GPIO2[3]

USBDR_D4_DP/GPIO2[4]

USBDR_D5_DM/GPIO2[5]

USBDR_D6_SER_RCV/

GPIO2[6]

USBDR_D7_DRVVBUS/

GPIO2[7]

AJ10

AF10

AE9

AG13

AH12

AG10

AF13

AG11

AH11

AG9

AF9

AH13

AH10

I/O

I/O

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

IIC1_SCL

IIC1_SDA

IIC2_SCL

IIC2_SDA

TCK

I

2

C Interface

C12

B12

A10

A12

JTAG Interface

B13

I/O

I/O

I/O

I/O

I

Power Supply

OVDD

Note

—

OVDD —

OVDD

OVDD

OVDD

OVDD

OVDD —

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

2

2

2

2

—

—

—

—

—

12

—

—

—

—

—

—

—

—

—



90

Signal

TDI

TDO

TMS

TRST_B

PCI_AD16

PCI_AD17

PCI_AD18

PCI_AD19

PCI_AD20

PCI_AD21

PCI_AD22

PCI_AD23

PCI_AD24

PCI_AD25

PCI_AD26

PCI_AD0

PCI_AD1

PCI_AD2

PCI_AD3

PCI_AD4

PCI_AD5

PCI_AD6

PCI_AD7

PCI_AD8

PCI_AD9

PCI_AD10

PCI_AD11

PCI_AD12

PCI_AD13

PCI_AD14

PCI_AD15



E14

C13

A13

E11

PCI Signals

Y26

V28

AA25

AA26

W29

AA24

AA27

AC26

AB25

AB24

AA28

U26

U24

T29

V24

R27

P28

U25

R28

R26

R29

T24

T25

P26

N28

P29

P27

Pin Type

I

I

I

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Power Supply

OVDD

OVDD

OVDD

OVDD

Note

4

4

4

3

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—



Signal

PCI_AD27

PCI_AD28

PCI_AD29

PCI_AD30

PCI_AD31

PCI_C_BE_B0

PCI_C_BE_B1

PCI_C_BE_B2

PCI_C_BE_B3

PCI_DEVSEL_B

PCI_FRAME_B

PCI_GNT_B0

PCI_GNT_B[1]/

CPCI_HS_LED

PCI_GNT_B[2]/

CPCI_HS_ENUM

PCI_GNT_B[3]/PCI_PME

PCI_GNT_B[4]

PCI_IDSEL

PCI_INTA_B/IRQ_OUT_B

PCI_IRDY_B

PCI_PAR

PCI_PERR_B

PCI_REQ_B0

PCI_REQ_B[1]/CPCI_HS_ES

PCI_REQ_B2

PCI_REQ_B3

PCI_REQ_B4

PCI_RESET_OUT_B

PCI_SERR_B

PCI_STOP_B

PCI_TRDY_B

M66EN



AA29

AC24

AC25

AB28

AE24

T26

T28

V29

Y29

U28

V27

AE27

AC28

Pin Type

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

AD27

AC29

AB29

AD26

W27

AD28

V26

W26

Y24

AD15

AC27

AE25

W28

AD29

U29

V25

Y25

AE26

O

O

I/O

I/O

I/O

I

I

I

I

I

I/O

I/O

I/O

I/O

I

O

O

O

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

Power Supply

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

Note

—

—

—

—

—

—

—

—

—

5

—

—

—

OVDD —

5

5

—

5

—

—

—

—

—

5

—

5

—

5

2

—

—



Signal

MCP_OUT_B

IRQ_B0/MCP_IN_B/GPIO2[12]

IRQ_B1/GPIO2[13]

IRQ_B2/GPIO2[14]

IRQ_B3/GPIO2[15]

IRQ_B4/GPIO2[16]/SD_WP

IRQ_B5/GPIO2[17]/

USBDR_PWRFAULT

IRQ_B6/GPIO2[18]

IRQ_B7/GPIO2[19]


Package Pin Number Pin Type

Programmable Interrupt Controller (PIC) Interface

AD14

F9

E9

F10

D9

C9

AE10

I/O

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

QUIESCE_B

L1_SD_IMP_CAL_RX

L1_SD_IMP_CAL_TX

L1_SD_REF_CLK

L1_SD_REF_CLK_B

L1_SD_RXA_N

L1_SD_RXA_P

L1_SD_RXE_N

L1_SD_RXE_P

L1_SD_TXA_N

L1_SD_TXA_P

L1_SD_TXE_N

L1_SD_TXE_P

L1_SDAVDD_0

AD10

AD9

PMC Interface

D13

SerDes1 Interface

AJ14

AG19

AJ17

AH17

AJ15

AH15

AJ19

AH19

AF15

AE15

AF18

AE18

AJ18

O

L1_SDAVSS_0

L1_XCOREVDD

AG17

AH14, AJ16, AF17, AH20, AJ20

I

I

I

O

O

I

O

I

I

I

I

O

SerDes PLL

Power

(1.0 or 1.05 V)

SerDes PLL

GND

SerDes Core

Power

(1.0 or 1.05 V)

Power Supply

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

—

—

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

L1_XPADVDD

—

Note

—

—

—

—

—

—

—

—

2

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

92



Signal

L1_XCOREVSS

L1_XPADVDD

L1_XPADVSS

L2_SD_IMP_CAL_RX

L2_SD_IMP_CAL_TX

L2_SD_REF_CLK

L2_SD_REF_CLK_B

L2_SD_RXA_N

L2_SD_RXA_P

L2_SD_RXE_N

L2_SD_RXE_P

L2_SD_TXA_N

L2_SD_TXA_P

L2_SD_TXE_N

L2_SD_TXE_P

L2_SDAVDD_0

L2_SDAVSS_0

L2_XCOREVDD

L2_XCOREVSS

L2_XPADVDD

L2_XPADVSS

SPICLK/SD_CLK



AG14, AG15, AG16, AH16, AG18, AG20

AE16, AF16, AD18, AE19, AF19

AF14, AE17, AF20

Pin Type

SerDes Core

GND

SerDes I/O

Power (1.0 or

1.05 V)

SerDes I/O

GND

Power Supply

—

—

—

SerDes2 Interface

A19

B19

A15

B15

C19

C15

B17

A17

D18

E18

D15

E15

A16

C17

A14, B14, D17, B18, B20

C14, C16, A18, C18, A20, C20

D14, E16, F18, D19, E19

D16, E17, D20

O

O

O

O

SerDes PLL

Power

(1.0 or 1.05 V)

SerDes PLL

GND

SerDes Core

Power

(1.0 or 1.05 V)

SerDes Core

GND

SerDes I/O

Power (1.0 or

1.05 V)

SerDes I/O

GND

I

I

I

I

I

I

I

I L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

L2_XPADVDD

—

—

—

—

—

—

SPI Interface

AH9 I/O OVDD

Note

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—



Signal

SPIMISO/SD_DAT0

SPIMOSI/SD_CMD

SPISEL_B/SD_CD

SRESET_B

HRESET_B

PORESET_B

TEST

TEST_SEL0

TEST_SEL1

Reserved

LVDD1

LVDD2

LBVDD

VDD



AD11

AJ9

AE11

System Control Interface

AD12

AE12

AE14

Test Interface

Pin Type

I/O

I/O

I

I/O

I/O

I

E10

D10

D12

Thermal Management

F15

I

I

I

I

Power Supply Signals

AC21, AG21, AH23

AG24, AH27, AH29

G20, D22, A24, G26, D27, A28

K10, L10, M10, N10, P10, R10, T10, U10,

V10, W10, Y10, K11, R11, Y11, K12, Y12,

K13, Y13, K14, Y14, K15, L15, W15, Y15,

K16, Y16, K17, Y17, K18, Y18, K19, R19,

Y19, K20, L20, M20, N20, P20, R20, T20,

U20, V20, W20, Y20

Power for eTSEC 1 I/O

(2.5 V, 3.3 V)

Power for eTSEC 2 I/O

(2.5 V, 3.3 V)

Power for eLBC

(3.3, 2.5, or

1.8 V)

Power for Core

(1.0 V or 1.5 V)

Power Supply

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

OVDD

—

—

LVDD1

LVDD2

LBVDD

VDD

Note

—

—

—

10

14

13

2

1

—

15

—

—

—

—

94



Signal

GND

(VSS)

AVDD_C

AVDD_L

AVDD_P

GVDD

OVDD

NC


Package Pin Number Pin Type

A1, AJ1, H2, N2, AA2, AD2, D3, R3, AF3, A4,

F4, J4, L4, V4, Y4, AB4, B5, E5, P5, AH5, K6,

T6, AA6, AD6, AG6, F7, J7, Y7, AJ7, B8,

AE8, AG8, G9, AC9,B11, D11, F11, L11,

M11, N11, P11, T11, U11, V11, W11, L12,

M12, N12, P12, R12, T12, U12, V12, W12,

E12, E13, L13, M13, N13, P13, R13, T13,

U13, V13, W13, AE13, AJ13, F14, L14, M14,

N14, P14, R14, T14, U14, V14, W14, M15,

N15, P15, R15, T15, U15, V15, L16, M16,

N16, P16, R16, T16, U16, V16, W16, L17,

M17, N17, P17, R17, T17, U17, V17, W17,

L18, M18, N18, P18, R18, T18, U18, V18,

W18, L19, M19, N19, P19, T19, U19, V19,

W19, AC20, G21, AF21, C22, J23, AA23,

AJ23, B24, W24, AF24, K25, R25, AD25,

D26, G27, M27, T27, Y27, AB27, AG27, A29,

AJ29

AD13

F13

—

Power for e300 core PLL (1.0 V or 1.05 V)

Power for eLBC

PLL (1.0 V or

1.05 V)

F12 Power for system PLL

(1.0 V or 1.05 V)

A2, D2, R2, U2, AC2, AF2, AJ2, F3, H3, L3,

N3, Y3, AB3, B4, P4, AF4, AH4, C5, F5, K5,

V5, AA5, AD5, N6, R6, AJ6, B7, E7, K7, AA7,

AE7, AG7, AD8

Power for DDR

SDRAM I/O

Voltage (2.5 or

1.8 V)

AC10, AF12, AJ12, K23, Y23, R24, AD24,

L25, W25, AB26, U27, M28, Y28, G10, A11,

C11

PCI, USB, and other Standard

(3.3 V)

Power Supply

—

—

—

—

GVDD

OVDD

No Connect

F16, F17, AD16, AD17

Pull Down

— —

Note

—

16

16

16

—

—

8




Signal Package Pin Number Pin Type Power Supply Note

Pull Down B16, AH18 — —

7

Notes:

1. This pin is an open drain signal. A weak pull-up resistor (1 k

Ω) should be placed on this pin to OVDD.

2. This pin is an open drain signal. A weak pull-up resistor (2–10 k

Ω) should be placed on this pin to OVDD.

3. This output is actively driven during reset rather than being released to high impedance during reset.

4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.

5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI Specification recommendation and see

AN3665, “MPC837xE Design Checklist,” for more details.

6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.

7. This pin must always be tied to GND using a 0

Ω resistor.

8. This pin must always be left not connected.

9. For DDR2 operation, it is recommended that MDIC0 be tied to GND using an 18.2

Ω resistor and MDIC1 be tied to DDR power using an 18.2

Ω resistor.

10.This pin must always be tied low. If it is left floating it may cause the device to malfunction.

11.See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.

12.This pin must not be pulled down during PORESET.

13.This pin must always be tied to GND.

14.This pin must always be tied to OVDD.

15.Open or tie to GND.

16.Voltage settings are dependent on the frequency used; see

Table 3

.

17.See AN3665, “MPC837xE Design Checklist,” for proper termination.

96



22 Clocking

This figure shows the internal distribution of clocks within this chip.

e300 core

Core PLL core_clk

System PLL csb_clk

Clock

Unit to DDR memory controller ddr_clk lbiu_clk

DDR

Clock

Div

/2

/n to local bus memory controller

LBIU

DLL csb_clk to rest of the device

6

6

CFG_CLKIN_DIV

CLKIN

PCI Clock

Divider

5

MCK[0:5]

MCK[0:5]

DDR

Memory

Device

LCLK[0:2]

LSYNC_OUT

LSYNC_IN

Local Bus

Memory

Device

PCI_CLK/

PCI_SYNC_IN

PCI_SYNC_OUT

PCI_CLK[0:4]

Figure 61. Clock Subsystem

The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (

÷2) and the multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICOEn] parameters select whether CFG_CLKIN_DIV is driven out on the PCI_CLK_OUTn signals.

PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN, with equal delay to all PCI agent devices in the system, to allow the device to function. When the device is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured as a PCI agent device the CLKIN signal should be tied to GND.



As shown in Figure 61 , the primary clock input (frequency) is multiplied up by the system phase-locked

loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the

DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).

The csb_clk frequency is derived from a complex set of factors that can be simplified into the following equation:

csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF Eqn. 20

In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.

The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low register

(RCWLR) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4,

“Reset, Clocking, and Initialization,” in the MPC8379E Reference Manual for more information on the clock subsystem.

The internal ddr_clk frequency is determined by the following equation:

ddr_clk = csb_clk × (1 + RCWLR[DDRCM]) Eqn. 21

Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider

(

÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate is the same frequency as ddr_clk.

The internal lbiu_clk frequency is determined by the following equation:

lbiu_clk = csb_clk × (1 + RCWLR[LBCM]) Eqn. 22

Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider to create the external local bus clock outputs (LCLK[0:2]). The eLBC clock divider ratio is controlled by

LCRR[CLKDIV].

Some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped register after

the device comes out of reset. Table 70

specifies which units have a configurable clock frequency.

Table 70. Configurable Clock Units

Unit Default Frequency

eTSEC1, eTSEC2 eSDHC and I

2

C1

1

Security block

USB DR csb_clk/3 csb_clk/3 csb_clk/3 csb_clk/3

PCI and DMA complex csb_clk

SATA1, 2, 3, 4 csb_clk/3

1

This only applies to I

2

C1 (I

2

C2 clock is not configurable).

Options

Off, csb_clk, csb_clk/2, csb_clk/3




Off, csb_clk


98



This table provides the operating frequencies for the TePBGA II package under recommended operating conditions (see

Table 3 ).

Table 71. Operating Frequencies for TePBGA II

Parameter

1

Minimum Operating

Frequency (MHz)

Maximum Operating

Frequency (MHz)

e300 core frequency ( core_clk)

Coherent system bus frequency ( csb_clk)

DDR2 memory bus frequency (MCK)

1

DDR1 memory bus frequency (MCK)

2

Local bus frequency (LCLK n)

1

Local bus controller frequency ( lbc_clk)

PCI input frequency (CLKIN or PCI_CLK) eTSEC frequency

Security encryption controller frequency

USB controller frequency eSDHC controller frequency

SATA controller frequency

333

133

250

167

—

—

25

133

—

—

—

—

800

400

400

333

133

400

66

400

200

200

200

200

Notes:

1. The CLKIN frequency, RCWLR[SPMF], and RCWLR[COREPLL] settings must be chosen such that the resulting csb_clk,

MCK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.

The value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core,

USB modules, SATA, and eSDHC will not exceed their respective value listed in this table.

2. The DDR data rate is 2

× the DDR memory bus frequency.

3. The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2× the csb_clk frequency (depending on RCWLR[LBCM]).

22.1

System PLL Configuration

The system PLL is controlled by the RCWLR[SPMF] parameter. The system PLL VCO frequency

depends on RCWLR[DDRCM] and RCWLR[LBCM]. Table 72

shows the multiplication factor encodings for the system PLL.

NOTE

If RCWLR[DDRCM] and RCWLR[LBCM] are both cleared, the system

PLL VCO frequency = (CSB frequency)

× (System PLL VCO Divider).

If either RCWLR[DDRCM] or RCWLR[LBCM] are set, the system PLL

VCO frequency = 2

× (CSB frequency) × (System PLL VCO Divider).

The VCO divider needs to be set properly so that the System PLL VCO frequency is in the range of 400–800 MHz.



RCWLR[SPMF]

0000

0001

0010

0011

0100

0101

0110

0111–1111

Table 72. System PLL Multiplication Factors

System PLL Multiplication Factor

Reserved

Reserved

× 2

× 3

× 4

× 5

× 6

× 7 to × 15

As described in Section 22, “Clocking,”

The LBIUCM, DDRCM, and SPMF parameters in the reset configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the

primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 74

and

Table 75 show the expected frequency values for the CSB frequency for select csb_clk to

CLKIN/PCI_SYNC_IN ratios.

The RCWLR[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 73 .

Table 73. System PLL VCO Divider

RCWLR[SVCOD]

00

01

10

11

VCO Division Factor

2

1

4

8

CFG_CLKIN_DIV

at Reset

1

High

High

High

High

High

Table 74. CSB Frequency Options for Host Mode

Input Clock Frequency (MHz)

2

SPMF csb_clk :

Input Clock Ratio

1

25 33.33

66.67

csb_clk Frequency (MHz)

0010

0011

0100

0101

0110

2 : 1

3 : 1

4 : 1

5 : 1

6 : 1 150

133

167

200

133

200

267

333

400

100



Table 74. CSB Frequency Options for Host Mode (continued)


2

CFG_CLKIN_DIV at Reset

1

SPMF csb_clk :


1

25 33.33

High

High

High

High

High

High

High

High

0111

1000

1001

1010

1011

1100

1101

1110

7 : 1

8 : 1

9 : 1

10 : 1

11 : 1

12 : 1

13 : 1

14 : 1

175

200

225

250

High 1111 15 : 1 375

Notes:

1. CFG_CLKIN_DIV select the ratio between CLKIN and PCI_SYNC_OUT.

2. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

275

300

325

350


233

267

300

333

367

400

66.67

CFG_CLKIN_DIV

at reset

1

Low

Low

Low

Low

Low

Table 75. CSB Frequency Options for Agent Mode


2

SPMF csb_clk :


1

25 33.33

66.67


0010

0011

0100

0101

0110

2 : 1

3 : 1

4 : 1

5 : 1

6 : 1 150

133

167

200

133

200

267

333

400



Table 75. CSB Frequency Options for Agent Mode (continued)


2

CFG_CLKIN_DIV at reset

1

SPMF csb_clk :


1

25 33.33

Low

Low

Low

Low

Low

Low

Low

Low

0111

1000

1001

1010

1011

1100

1101

1110

7 : 1

8 : 1

9 : 1

10 : 1

11 : 1

12 : 1

13 : 1

14 : 1

175

200

225

250

Low 1111 15 : 1 375

Notes:

1. CFG_CLKIN_DIV doubles csb_clk if set high.

2. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.

275

300

325

350


233

267

300

333

367

400

66.67

22.2

Core PLL Configuration

RCWLR[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the

e300 core clock (core_clk). Table 76 shows the encodings for RCWLR[COREPLL]. COREPLL values that are not listed in Table 76 should be considered as reserved.

NOTE

Core VCO frequency = core frequency

× VCO divider

VCO divider has to be set properly so that the core VCO frequency is in the range of 800–1600 MHz.

Table 76. e300 Core PLL Configuration

RCWLR[COREPLL] core_clk : csb_clk Ratio VCO Divider

1

0–1 nn

2–5

0000

6

0 PLL bypassed

(PLL off, csb_clk clocks core directly)

11

00

01

10

00 nnnn

0001

0001

0001

0001

0

0 n

0

1 n/a

1:1

1:1

1:1

1.5:1

PLL bypassed

(PLL off, csb_clk clocks core directly) n/a

2

4

8

2

102



Table 76. e300 Core PLL Configuration (continued)

RCWLR[COREPLL] core_clk : csb_clk Ratio VCO Divider

1

0–1 2–5 6

10

00

01

10

01

10

00

01

0001

0001

0010

0010

0010

0010

0010

0010

1

1

0

1

0

0

1

1

1.5:1

1.5:1

2:1

2:1

2:1

2.5:1

2.5:1

2.5:1

4

8

8

2

2

4

4

8

01

10

00

01

00

01

10

00

0011

0011

0011

0011

0011

0011

0100

0100

0

0

0

1

1

1

0

0

3:1

3:1

3:1

3.5:1

3.5:1

3.5:1

4:1

4:1

2

4

8

2

4

8

2

4

10 0100

0 4:1 8

Notes:

1. Core VCO frequency = Core frequency

× VCO divider. Note that VCO divider has to be set properly so that the core VCO frequency is in the range of 800–1600 MHz.

22.3

Suggested PLL Configurations

This table shows suggested PLL configurations for different input clocks (LBCM = 0).

Table 77. Example Clock Frequency Combinations eLBC

1 e300 Core

1

Ref

1

LBCM DDRCM SVCOD SPMF

Sys

VCO

1,

2

CSB

1

,3

DDR data rate

1,

4

25.0

25.0

33.3

33.3

0

0

0

0

1

1

1

1

2

2

2

2

5

6

5

4

500

600

667

533

125

150

167

133

250

300

333

267

/2 /4 /8

× 1 × 1.5 × 2 × 2.5 × 3

62.5

31.3

15.6

—

75

6

83.3

6

37.5

41.6

18.8

20.8

—

—

66.7

33.3

16.7

—

—

—

—

—

—

—

333

—

—

375

416

333

375

450

500

400



Table 77. Example Clock Frequency Combinations (continued) eLBC

1 e300 Core

1

Ref

1

LBCM DDRCM SVCOD SPMF

Sys

VCO

1,

2

CSB

1

,3

DDR data rate

1,

4

/2 /4 /8

× 1 × 1.5 × 2 × 2.5 × 3

48.0

66.7

25.0

33.3

50.0

50.0

66.7

66.7

66.7

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

0

0

0

2

2

4

2

4

2

2

2

2

3

2

8

8

4

8

4

5

6

576

533

800

533

800

800

533

667

800

144

133

200

266.7

200

400

266.7

333

400

288

266

200

267

200

400

267

333

400

5

5

72

6

36 18 — — — 360 432

66.7

33.3

16.7

—

100

6

50 25 —

— — 333 400

— 400 500 600

133

6

100

6

66.7

50

— 100

6

33.3

25

50

—

—

—

400

—

600

533

400

800

667

500

—

800

600

—

133

6

66.7

33.3

— 400 533 667 800

— 83.3

6

41.6

333 500 667 —

— 100

6

50 400 600 800 —

—

—

Notes:

1. Values in MHz.

2. System PLL VCO range: 400–800 MHz.

3. CSB frequencies less than 133 MHz will not support Gigabit Ethernet rates.

4. Minimum data rate for DDR2 is 250 MHz and for DDR1 is 167 MHz.

5. Applies to DDR2 only.

6. Applies to eLBC PLL-enabled mode only.

23 Thermal

This section describes the thermal specifications of this chip.

23.1

Thermal Characteristics

This table provides the package thermal characteristics for the 689 31

× 31mm TePBGA II package.

Table 78. Package Thermal Characteristics for TePBGA II

Parameter

Junction-to-ambient natural convection on single layer board (1s)

Junction-to-ambient natural convection on four layer board (2s2p)

Junction-to-ambient (at 200 ft/min) on single layer board (1s)

Junction-to-ambient (at 200 ft/min) on four layer board (2s2p)

Junction-to-board thermal

Junction-to-case thermal

Symbol

R

θJA

R

θJA

R

θJMA

R

θJMA

R

θJB

R

θJC

Value

21

15

16

12

8

6

Unit Note

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

1, 2

1, 2, 3

1, 3

1, 3

4

5

104



Table 78. Package Thermal Characteristics for TePBGA II (continued)

Parameter Symbol Value Unit Note

Junction-to-package natural convection on top

ψ

JT

6

°C/W

6

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.

23.2

Thermal Management Information

For the following sections, P

D

= (V

DD

× I

DD

) + P

I/O

where P

I/O

is the power dissipation of the I/O drivers.

23.2.1

Estimation of Junction Temperature with Junction-to-Ambient

Thermal Resistance

An estimation of the chip junction temperature, T

J

, can be obtained from the equation:

T

J

= T

A

+ (R

θ

JA

× P

D

) where:

T

J

= junction temperature (

°C)

T

A

= ambient temperature for the package (

°C)

R

θ

JA

= junction to ambient thermal resistance (

°C/W)

P

D

= power dissipation in the package (W)

The junction to ambient thermal resistance is an industry-standard value that provides a quick and easy estimation of thermal performance. Generally, the value obtained on a single layer board is appropriate for a tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. Test cases have demonstrated that errors of a factor of two (in the quantity T

J

–

T

A

) are possible.

23.2.2

Estimation of Junction Temperature with Junction-to-Board


NOTE

The heat sink cannot be mounted on the package.



The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal resistance. The thermal performance of any component is strongly dependent on the power dissipation of surrounding components. In addition, the ambient temperature varies widely within the application. For many natural convection and especially closed box applications, the board temperature at the perimeter

(edge) of the package is approximately the same as the local air temperature near the device. Specifying the local ambient conditions explicitly as the board temperature provides a more precise description of the local ambient conditions that determine the temperature of the device.

At a known board temperature, the junction temperature is estimated using the following equation:

T

J

= T

A

+ (R

θ

JB

× P

D

) where:

T

A

= ambient temperature for the package (

°C)

R

θ

JB

= junction to board thermal resistance (

°C/W) per JESD51-8

P

D


When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made. The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes.

23.2.3

Experimental Determination of Junction Temperature

NOTE

The heat sink cannot be mounted on the package.

To determine the junction temperature of the device in the application after prototypes are available, use the thermal characterization parameter (

Ψ

JT

) to determine the junction temperature and a measure of the temperature at the top center of the package case using the following equation:

T

J

= T

T

+ (

Ψ

JT

× P

D

) where:

T

J


°C)

T

T

= thermocouple temperature on top of package (

°C)

Ψ

JT


°C/W)

P

D


The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type

T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

23.2.4

Heat Sinks and Junction-to-Case Thermal Resistance

For the power values the device is expected to operate at, it is anticipated that a heat sink will be required.

A preliminary estimate of heat sink performance can be obtained from the following first-cut approach.

106



The thermal resistance is expressed as the sum of a junction to case thermal resistance and a case-to-ambient thermal resistance:

R

θ

JA

= R

θ

JC

+ R

θ

CA

where:

R

θ

JA

R

θ

JC


°C/W)

= junction to case thermal resistance (

°C/W)

R

θ

CA

= case to ambient thermal resistance (

°C/W)

R

θ

JC

is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, R

θ

CA

. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device.

This first-cut approach overestimates the heat sink size required, since heat flow through the board is not accounted for, which can be as much as one-third to one-half of the power generated in the package.

Accurate thermal design requires thermal modeling of the application environment using computational fluid dynamics software which can model both the conduction cooling through the package and board and the convection cooling due to the air moving through the application. Simplified thermal models of the packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in the thermal resistance table. More detailed thermal models can be made available on request.

The thermal performance of devices with heat sinks has been simulated with a few commercially available heat sinks. The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because of the wide variety of application environments, a single standard heat sink applicable to all cannot be specified.



This table shows the heat sink thermal resistance for TePBGA II package with heat sinks, simulated in a standard JEDEC environment, per JESD 51-6.

Table 79. Thermal Resistance with Heat Sink in Open Flow (TePBGA II)

Heat Sink Assuming Thermal Grease

AAVID 30

×

30

×

9.4 mm Pin Fin

AAVID 31

×

35

×

23 mm Pin Fin

AAVID 43

×

41

×

16.5mm Pin Fin

Wakefield, 53

×

53

×

25 mm Pin Fin

Air Flow

Natural Convection

0.5 m/s

1 m/s

2 m/s

4 m/s

Natural Convection

0.5 m/s

1 m/s

2 m/s

4 m/s

Natural Convection

0.5 m/s

1 m/s

2 m/s

4 m/s

Natural Convection

0.5 m/s

1 m/s

2 m/s

4 m/s


(

°/W)

7.8

7.0

6.5

9.7

7.2

6.8

11.3

9.0

7.7

6.8

6.4

6.1

7.5

11.1

8.5

7.7

13.1

10.6

9.3

8.2

Heat sink vendors include the following:

Aavid Thermalloy www.aavidthermalloy.com

Alpha Novatech www.alphanovatech.com

International Electronic Research Corporation (IERC) www.ctscorp.com

Millennium Electronics (MEI) www.mei-thermal.com

108



Tyco Electronics

Chip Coolers™ www.chipcoolers.com

Wakefield Engineering www.wakefield.com

Interface material vendors include the following:

Chomerics, Inc.

www.chomerics.com

Dow-Corning Corporation

Dow-Corning Electronic Materials www.dowcorning.com

Shin-Etsu MicroSi, Inc.

www.microsi.com

The Bergquist Company www.bergquistcompany.com

23.3

Heat Sink Attachment

The device requires the use of heat sinks. When heat sinks are attached, an interface material is required, preferably thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint lifetime of the package. The recommended maximum compressive force on the top of the package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces, and its performance should be verified under the application requirements.

23.3.1

Experimental Determination of the Junction Temperature with a

Heat Sink

When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimize the size of the clearance to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction to case thermal resistance.

T

J

= T

C

+ (R

θ

JC

× P

D

) where:

T

J


°C)

T

C

= case temperature of the package (

°C)



R

θ

JC

= junction to case thermal resistance (

°C/W)

P

D

= power dissipation (W)

24 System Design Information

This section provides electrical and thermal design recommendations for successful application of this chip.

24.1

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins. The AV

DD level should always be equivalent to V through a low frequency filter scheme.

DD

, and preferably these voltages will be derived directly from V

DD

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to

provide five independent filter circuits as illustrated in Figure 62

, one to each of the five AV

DD

pins. By providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).

Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook

of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AV

DD

pin being supplied to minimize noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV

DD pin, which is on the periphery of package, without the inductance of vias.

This figure shows the PLL power supply filter circuit.

10

Ω

VDD

2.2 µF 2.2 µF

AVDD (or L2AVDD)

GND

Low ESL Surface Mount Capacitors

Figure 62. PLL Power Supply Filter Circuit

24.2

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, the device can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads.

This noise must be prevented from reaching other components in the device system, and the device itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly under the device using a standard escape pattern. Others may surround the part.

110



These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo

OSCON).

24.3

Connection Recommendations

To ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.

Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins of the device.

24.4

Output Buffer DC Impedance

The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull single-ended driver type (open drain for I

2

C).

To measure Z

0

for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the value of each resistor is varied until the pad voltage is OV

DD

/2 (see

Figure 63

). The output impedance is the average of two components, the resistances of the pull-up and pull-down devices.

When data is held high, SW1 is closed (SW2 is open) and R

P

is trimmed until the voltage at the pad equals

OV

DD

/2. R

P

then becomes the resistance of the pull-up devices. R

P

and R

N

are designed to be close to each other in value. Then, Z

0

= (R

P

+ R

N

)/2.

OVDD

R

N

SW2

Pad

Data

SW1

R

P

OGND

Figure 63. Driver Impedance Measurement



The value of this resistance and the strength of the driver’s current source can be found by making two measurements. First, the output voltage is measured while driving logic 1 without an external differential termination resistor. The measured voltage is V

1

= R source

× I source

. Second, the output voltage is measured while driving logic 1 with an external precision differential termination resistor of value R measured voltage is V

R term

× (V

1

/V

2

2

= (1/(1/R

1

+ 1/R

2

))

× I

– 1). The drive current is then I source

= V

1

/R source term source

. Solving for the output impedance gives R

.

. The source

=

This table summarizes the signal impedance targets. The driver impedance are targeted at minimum V

DD nominal OV

DD

, 105

°C.

,

Table 80. Impedance Characteristics

Impedance

Local Bus, Ethernet,

DUART, Control,

Configuration, Power

Management

PCI Signals

(not including PCI output clocks)

R

N

R

P

Differential

42 Target

42 Target

25 Target

25 Target

NA NA

Note: Nominal supply voltages. See

Table 2

, T j

= 105

°C.

PCI Output Clocks

(including

PCI_SYNC_OUT)

42 Target

42 Target

NA

DDR DRAM Symbol

20 Target

20 Target

NA Z

Z

Z

0

0

DIFF

Unit

W

W

W

24.5

Configuration Pin Muxing

The device provides the user with power-on configuration options which can be set through the use of external pull-up or pull-down resistors of 4.7 k

Ω on certain output pins (see customer visible configuration pins). These pins are generally used as output only pins in normal operation.

While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should minimize the disruption of signal quality or speed for output pins thus configured.

24.6

Pull-Up Resistor Requirements

The device requires high resistance pull-up resistors (10 k

Ω is recommended) on open drain type pins including I

2

C pins and IPIC interrupt pins.

For more information on required pull-up resistors and the connections required for the JTAG interface, see AN3665, “MPC837xE Design Checklist.”

25 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in

Section 25.1, “Part Numbers Fully Addressed by This Document.”

112



25.1

Part Numbers Fully Addressed by This Document

Table 81

provides the Freescale part numbering nomenclature for this chip. Note that the individual part numbers correspond to a maximum processor core frequency. For available frequencies, contact your local

Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number.

Table 81. Part Numbering Nomenclature

MPC 8379

E C

ZQ AF D A

Product

Code

Part

Identifier

Encryption

Acceleratio n

MPC

Temperature

Range

1

Package

2 e300 core

Frequency

3

DDR

Data Rate

Revision

Level

4

8379 Blank = Not included

E = included

Blank = 0

°C (T a

) to 125

°C (T j

)

C = –40

°C (T a

) to 125

°C (T j

)

VR = Pb-free

689 TePBGA II

AN = 800 MHz

AL = 667 MHz

AJ = 533 MHz

AG = 400 MHz

G = 400 MHz

F = 333 MHz

D = 266 MHz

Blank = Freescale

ATMC fab

A =

GlobalFoundries fab

Note:

1

Contact local Freescale office on availability of parts with an extended temperature range.

2

See

Section 21, “Package and Pin Listings,”

for more information on the available package type.

3

Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support other maximum core frequencies.

4

No design changes occurred between initial parts and the revision “ A” parts. Only the fab source has changed in moving to revision “ A” parts. Initial revision parts and revision “A” parts are form, fit, function, and reliability equivalent.

This table lists the available core and DDR data rate frequency combinations.

Table 82. Available Parts (Core/DDR Data Rate)

MPC8377E

800 MHz/400 MHz

667 MHz/400 MHz

533 MHz/333 MHz

400 MHz/266 MHz

MPC8378E

800 MHz/400 MHz

667 MHz/400 MHz

533 MHz/333 MHz

400 MHz/266 MHz

MPC8379E

800 MHz/400 MHz

667 MHz/400 MHz

533 MHz/333 MHz

400 MHz/266 MHz



This table shows the SVR and PVR settings by device.

Table 83. SVR and PVR Settings by Product Revision

SVR

Device Package

MPC8377

MPC8377E

MPC8378

MPC8378E

MPC8379

MPC8379E

TePBGA II

Rev 1.0

0x80C7_0010

0x80C6_0010

0x80C5_0010

0x80C4_0010

0x80C3_0010

0x80C2_0010

Rev. 2.1

0x80C7_0021

0x80C6_0021

0x80C5_0021

0x80C4_0021

0x80C3_0021

0x80C2_0021

Rev. 1.0

0x8086_1010

PVR

Rev. 2.1

0x8086_1011

25.2

Part Marking

Parts are marked as in the example as shown in this figure.

MPCnnnnetppaaar core/platform MHZ

ATWLYYWW

CCCCC

*MMMMM YWWLAZ

TePBGA II

Notes

:

ATWLYYWW is the traceability code.

CCCCC is the country code.

MMMMM is the mask number.

YWWLAZ is the assembly traceability code.

Figure 64. Freescale Part Marking for TePBGA II Devices

26 Document Revision History

This table provides a revision history for this document.

Table 84. Document Revision History

Revision Date

8

7

6

Substantive Change(s)

05/2012 In Table 15 , “DDR SDRAM DC Electrical Characteristics for GV

DD

(typ) = 2.5 V,” updated Output leakage

current (I

OZ

) min and max values.

10/2011 • In Table 81 , “Part Numbering Nomenclature,” updated “Revision Level description”and added footnote 4.

07/2011 In Section 2.2, “Power Sequencing ,” updated power down sequencing information.

114



Table 84. Document Revision History (continued)

Revision Date

5


07/2011 • In

Table 2 , “Absolute Maximum Ratings

1

,” removed footnote 5 from LB

IN

to OV

IN

. Also, corrected

footnote 5.

• In

Table 3 , “Recommended Operating Conditions,” added footnote 2 to AV

DD

.

• In

Figure 2 , “Overshoot/Undershoot Voltage for GV

DD

/LV

DD

/OV

DD

/LBV

DD

,” added LBV

DD

.

• In

Table 13 , “DDR2 SDRAM DC Electrical Characteristics for GV

DD

(typ) = 1.8 V,” updated I

to –50/50.

OZ

min/max

• In

Figure 11 , “RGMII and RTBI AC Timing and Multiplexing Diagrams,” added distinction between

t

SKRGT_RX

and t

SKRGT_TX

signals.

• In

Table 33 , “MII Management AC Timing Specifications,” updated MDC frequency—removed Min and

Max values, added Typical value. Also, updated footnote 2 and removed footnote 3.

• In

Table 48 , “PCI DC Electrical Characteristics,” updated V

IH

min value to 2.0.

• In

Table 69 , “TePBGA II Pinout Listing,” added Note to LGPL4/LFRB_B/LGTA_B/LUPWAIT/LPBSE (to

be consistent with AN3665, “MPC837xE Design Checklist.”

• In

Table 71 , “Operating Frequencies for TePBGA II,” added Minimum Operating Frequency for eTSEC,

and corrected DDR2 Minimum and Maximum Operating Frequency values.

4

3

11/2010 • In

Table 25 , “RGMII and RTBI DC Electrical Characteristics,” updated V

IH

min value to 1.7.

• In

Table 40 , “Local Bus General Timing Parameters—PLL Bypass Mode,” added row for t

LBKHLR

.

• In

Section 10.2, “Local Bus AC Electrical Specifications,”

and in Section 22, “Clocking,”

updated LCCR to LCRR.

• In

Table 69 , “TePBGA II Pinout Listing,” added SD_WP to pin C9. Also clarified TEST_SEL0 and

TEST_SEL1 pins—no change in functionality.

03/2010 • Added

Section 4.3, “eTSEC Gigabit Reference Clock Timing.”

• In

Table 34 , “USB DC Electrical Characteristics ,”

and

Table 35 , “USB General Timing Parameters (ULPI

Mode Only),” added table footnotes

.

• In

Table 39 , “Local Bus General Timing Parameters—PLL Enable Mode,” and

Table 40 , “Local Bus

General Timing Parameters—PLL Bypass Mode,” corrected footnotes for t

LBOTOT1

, t

LBOTOT2

, t

LBOTOT3

.

• In

Figure 22 , “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode),” and

Figure 24 , “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode),” shifted

“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.

• In

Figure 60 , “Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II,” added

heat spreader.

• In

Section 24.6, “Pull-Up Resistor Requirements,”

removed “Ethernet Management MDIO pin” from list of open drain type pins.

• In

Table 69 , “TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and

AVDD_P pins.

• in

Table 69

, “TePBGA II Pinout Listing,” added Note 17 to eTSEC pins.

• In

Table 74 , “CSB Frequency Options for Host Mode,” and

Table 75 , “CSB Frequency Options for Agent

Mode,” updated

csb_clk frequencies available.

• In

Table 81 , “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”



Table 84. Document Revision History (continued)

Revision Date

2

1

0


10/2009 • In

Table 3 , “Recommended Operating Conditions,” added “Operating temperature range” values.

• In

Table 5 , “Power Dissipation

1

,” corrected maximal application for 800/400 MHz to 4.3 W.

• In


1

,” added a column for “Typical Application at T

j

• In


1

,” added a column for “Sleep Power at T

j

= 65

°C (W)”.

= 65

°C (W)”.

• In

Table 11 , removed overbar from CFG_CLKIN_DIV.

• In

Table 17 , “Current Draw Characteristics for MV

REF

,” updated I

MVREF

maximum value for both DDR1 and DDR2 to 600 and 400

μA, respectively. Also, updated Note 1 and added Note 2.

• In

Table 20 , “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to

“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.

• In

Table 20 , “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and Table 21 , “DDR1 and

DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.

• In

Table 29 , “RMII Transmit AC Timing Specifications,” updated t

RMTDX

I to 2.0 ns.

• In

Table 57 , Gen 1i/1.5G Transmitter AC Specifications,” and Table 59 , Gen 2i/3G Transmitter AC

Specifications,” corrected titles from “Transmitter” to “Receiver”.

• In

Table 69 , “TePBGA II Pinout Listing

,” removed pin THERM0; it is now Reserved. Also added 1.05 V to VDD pin.

• In

Table 71 , “Operating Frequencies for TePBGA II ,”

corrected “DDR2 memory bus frequency (MCK)” range to 125–200.

• In

Table 76 , “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.

• In

Table 77 , “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .

• In

Section 19.2, “SPI AC Timing Specifications,”

corrected t

NIKHOX

and t

NEKHOX

to t

NIKHOV

and t

NEKHOV

, respectively.

02/2009 • In

Table 3 , “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two

rows for SerDes. In addition, changed 666 to 667 MHz.

• In


1

,” added Notes 4 and 5. In addition, changed 666 to 667 MHz.

• In

Table 13 , “DDR2 SDRAM DC Electrical Characteristics for GV

DD

(typ) = 1.8 V,” Table 21 , “DDR1 and

DDR2 SDRAM Output AC Timing Specifications,” and

Table 69 , “TePBGA II Pinout Listing,” added

footnote to references to MVREF, MDQ, and MDQS, referencing AN3665, MPC837xE Design Checklist.

• In

Table 21 , updated t

DDKHCX

minimum value for 333 MHz to 2.40.

• In

Table 69 , “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified

footnote 10 and added footnote 15.

• In

Table 71 , “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for

core_clk.

• In

Table 77 , “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.

• Updated part numbering information in AF column in Table 81 , “Part Numbering Nomenclature.” In

addition, modified extended temperature information in notes 1 and 4.

• In

Table 82 , “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.

12/2008 Initial public release.

116



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Document Number: MPC8379EEC

Rev. 8

05/2012

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