L6385E High voltage high and low-side driver Description -

L6385E High voltage high and low-side driver Description -
L6385E
High voltage high and low-side driver
Datasheet - production data
Description
DIP-8
The L6385E is a simple and compact high voltage
gate driver, manufactured with the BCD™ “offline”
technology, and able to drive a half-bridge of
power MOSFET or IGBT devices. The high-side
(floating) section is able to work with voltage rail
up to 600 V. Both device outputs can
independently sink and source 650 mA and 400
mA respectively and can be simultaneously
driven high.
SO-8
Features
 High voltage rail up to 600 V
 dV/dt immunity ± 50 V/nsec in full temperature
range
 Driver current capability:
– 400 mA source
– 650 mA sink
 Switching times 50/30 nsec rise/fall with 1 nF
load
 CMOS/TTL Schmitt trigger inputs with
hysteresis and pull-down
 Undervoltage lockout on lower and upper
driving section
 Internal bootstrap diode
 Outputs in phase with inputs
The L6385E device provides two input pins and
two output pins and guarantees the outputs toggle
in phase with inputs. The logic inputs are
CMOS/TTL compatible to ease the interfacing
with controlling devices.
The bootstrap diode is integrated inside the
device, allowing a more compact and reliable
solution.
The L6385E features the UVLO protection on
both lower and upper driving sections (VCC and
Vboot), ensuring greater protection against voltage
drops on the supply lines.
The device is available in a DIP-8 tube and SO-8
tube, and tape and reel packaging options.
Table 1. Device summary
Applications
 Home appliances
Part number
Package
Packaging
 Induction heating
L6385E
DIP-8
Tube
L6385ED
SO-8
Tube
L6385ED013TR
SO-8
Tape and reel
 HVAC
 Motor drivers
– SR motors
– DC, AC, PMDC and PMAC motors
 Asymmetrical half-bridge topologies
 Industrial applications and drives
 Lighting applications
 Factory automation
 Power supply systems
December 2014
This is information on a product in full production.
DocID13863 Rev 3
1/15
www.st.com
Contents
L6385E
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
4.1
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3
Timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
Typical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2/15
DocID13863 Rev 3
L6385E
Block diagram
1
Block diagram
Figure 1. Block diagram
BOOTSTRAP DRIVER
VCC
3
UV
DETECTION
8
UV
DETECTION
H.V.
HVG
DRIVER
R
R
HIN
2
LOGIC
LEVEL
SHIFTER
Cboot
HVG
7
S
OUT
VCC
LIN
Vboot
1
LVG
DRIVER
6
TO LOAD
5
LVG
4
GND
D97IN514B
DocID13863 Rev 3
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Electrical data
L6385E
2
Electrical data
2.1
Absolute maximum ratings
Table 2. Absolute maximum ratings
Symbol
Value
Unit
Vout
Output voltage
-3 to Vboot -18
V
Vcc
Supply voltage
- 0.3 to +18
V
Vboot
Floating supply voltage
-1 to 618
V
Vhvg
High-side gate output voltage
-1 to Vboot
V
Vlvg
Low-side gate output voltage
-0.3 to Vcc +0.3
V
Logic input voltage
-0.3 to Vcc +0.3
V
Allowed output slew rate
50
V/ns
Total power dissipation (TJ = 85 °C)
750
mW
Tj
Junction temperature
150
°C
Ts
Storage temperature
-50 to 150
°C
Vi
dVout/dt
Ptot
2.2
Parameter
Thermal data
Table 3. Thermal data
Symbol
Rth(JA)
2.3
Parameter
Thermal resistance junction to ambient
SO-8
DIP-8
Unit
150
100
°C/W
Recommended operating conditions
Table 4. Recommended operating conditions
Symbol
Pin
Vout
6
VBS(2)
8
TJ
3
Test condition
Min.
Max.
Unit
(1)
580
V
Floating supply voltage
(1)
17
V
400
kHz
17
V
125
°C
HVG,LVG load CL = 1 nF
Supply voltage
Junction temperature
-45
1. If the condition Vboot - Vout < 18 V is guaranteed, Vout can range from -3 to 580 V.
2. VBS = Vboot - Vout.
4/15
Typ.
Output voltage
Switching frequency
fsw
Vcc
Parameter
DocID13863 Rev 3
L6385E
3
Pin connection
Pin connection
Figure 2. Pin connection (top view)
LIN
1
8
Vboot
HIN
2
7
HVG
VCC
3
6
OUT
GND
4
5
LVG
D97IN517A
Table 5. Pin description
No.
Pin
Type
Function
1
LIN
I
Low-side driver logic input
2
HIN
I
High-side driver logic input
3
VCC
P
Low voltage power supply
4
GND
P
Ground
5
LVG(1)
O
Low-side driver output
6
OUT
P
High-side driver floating reference
7
HVG(1)
O
High-side driver output
8
Vboot
P
Bootstrap supply voltage
1. The circuit guarantees 0.3 V maximum on the pin (at Isink = 10 mA). This allows to omit the “bleeder”
resistor connected between the gate and the source of the external MOSFET normally used to hold the pin
low.
DocID13863 Rev 3
5/15
15
Electrical characteristics
L6385E
4
Electrical characteristics
4.1
AC operation
Table 6. AC operation electrical characteristics (VCC = 15 V; TJ = 25 °C)
Symbol
Pin
Parameter
Test condition
Min.
Typ.
Max.
Unit
ton
1 vs. 5 High/low-side driver turn-on
2 vs. 7 propagation delay
Vout = 0 V
110
ns
toff
1 vs. 5 High/low-side driver turn-off
2 vs. 7 propagation delay
Vout = 0 V
105
ns
tr
5, 7
Rise time
CL = 1000 pF
50
ns
tf
5, 7
Fall time
CL = 1000 pF
30
ns
4.2
DC operation
Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = 25 °C)
Symbol
Pin
Parameter
Test condition
Min.
Typ.
Max.
Unit
17
V
Low supply voltage section
Vcc
Supply voltage
Vccth1
VCC UV turn-on threshold
9.1
9.6
10.1
V
Vccth2
VCC UV turn-off threshold
7.9
8.3
8.8
V
Vcchys
3
VCC UV hysteresis
1.3
V
Iqccu
Undervoltage quiescent supply
current
Vcc  9 V
150
220
A
Iqcc
Quiescent current
Vin = 15 V
250
320
A
Vcc  12.5 V
125
Bootstrap driver on resistance
Rdson
(1)

Bootstrapped supply voltage section
VBS
Bootstrap supply voltage
VBSth1
VBS UV turn-on threshold
8.5
VBS UV turn-off threshold
7.2
VBSth2
8
VBS UV hysteresis
VBShys
IQBS
V
9.5
10.5
V
8.2
9.2
V
1.3
VBS quiescent current
High voltage leakage current
ILK
17
V
HVG ON
200
A
Vhvg = Vout = Vboot = 600 V
10
A
High/low-side driver
Iso
Isi
6/15
Source short-circuit current
VIN = Vih (tp < 10 s)
300
400
mA
Sink short-circuit current
VIN = Vil (tp < 10 s)
450
650
mA
5, 7
DocID13863 Rev 3
L6385E
Electrical characteristics
Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = 25 °C) (continued)
Symbol
Pin
Parameter
Test condition
Min.
Typ.
Max.
Unit
1.5
V
Logic inputs
Vil
Low level logic threshold voltage
1, 2
Vih
Iih
Iil
High level logic threshold voltage
3.6
High level logic input current
VIN = 15 V
Low level logic input current
VIN = 0 V
1, 2
V
50
70
A
1
A
1. RDS(on) is tested in the following way:
 V CC – V CBOOT1  –  V CC – V CBOOT2 
R DSON = ------------------------------------------------------------------------------------------------------I 1  V CC ,V CBOOT1  – I 2  V CC ,V CBOOT2 
where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2.
4.3
Timing diagram
Figure 3. Input/output timing diagram
HIN
HVG
LIN
LVG
D99IN1053
DocID13863 Rev 3
7/15
15
Bootstrap driver
5
L6385E
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 4 a). In the L6385E device
a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as
shown in Figure 4 b. An internal charge pump (Figure 4 b) provides the DMOS driving
voltage. The diode connected in series to the DMOS has been added to avoid undesirable
turn-on.
CBOOT selection and charging
To choose the proper CBOOT value, the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Equation 1
Q gate
C EXT = --------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
CBOOT>>>CEXT
E.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also
the leakage losses.
E.g.: HVG steady state consumption is lower than 200 A, so if HVG TON is 5 ms, CBOOT
has to supply a maximum of 1 µC to CEXT. This charge on a 1mF capacitor means a voltage
drop of 1 V.
The internal bootstrap driver gives great advantages: the external fast recovery diode can
be avoided (it usually has a great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge ) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value:
125 ). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 2
Q gate
V drop = I ch arg e R dson  V drop = -------------------R dson
T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the
bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor.
8/15
DocID13863 Rev 3
L6385E
Bootstrap driver
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is 5 ms. In fact:
Equation 3
30nC
V drop = ---------------  125  0.8V
5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 4. Bootstrap driver
DBOOT
VS
VBOOT
VBOOT
VS
H.V.
H.V.
HVG
HVG
CBOOT
VOUT
CBOOT
VOUT
TO LOAD
TO LOAD
LVG
LVG
a
b
DocID13863 Rev 3
D99IN1056
9/15
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Typical characteristic
6
L6385E
Typical characteristic
Figure 5. Typical rise and fall times
vs. load capacitance
time
(nsec)
D99IN1054
250
Figure 6. Quiescent current vs. supply
voltage
Iq
(μA)
104
D99IN1055
200
Tr
103
150
Tf
100
102
50
0
10
0
1
2
3
4
5 C (nF)
For both high and low side buffers @25˚C Tamb
Figure 7. Turn-on time vs. temperature
8
10
12
14
16 VS(V)
@ Vcc = 15V
200
200
150
150
Toff (ns)
Ton (ns)
6
250
@ Vcc = 15V
Typ.
100
Typ.
100
50
50
0
-45
-25
0
25
50
Tj (°C)
75
100
0
125
Figure 9. VBOOT UV turn-on threshold
vs. temperature
-45
-25
0
25
50
Tj (°C)
75
100
125
Figure 10. VCC UV turn-off threshold
vs. temperature
11
13
@ Vcc = 15V
12
10
11
Typ.
Vccth2(V)
Vbth1 (V)
4
Figure 8. Turn-off time vs. temperature
250
10
2
0
9
8
7
9
Typ.
8
7
6
6
5
-45
10/15
-25
0
25
50
Tj (°C)
75
100
125
DocID13863 Rev 3
-45
-25
0
25
50
Tj (°C)
75
100 125
L6385E
Typical characteristic
Figure 11. VBOOT UV turn-off threshold
vs. temperature
Figure 12. Output source current
vs. temperature
1000
14
@ Vcc = 15V
@ Vcc = 15V
13
800
current (mA)
Vbth2 (V)
12
11
10
9
8
7
0
-45
-25
0
25
50
75
100
-45
125
Figure 13. VCC UV turn-on threshold
vs. temperature
-25
0
25
50
Tj (°C)
75
100
125
Figure 14. Output sink current
vs. temperature
13
1000
@ Vcc = 15V
12
800
current (mA)
Vccth1(V)
Typ.
400
200
Typ.
6
11
10
9
600
Typ.
600
Typ.
400
200
8
0
7
-45
-25
0
25
50
Tj (°C)
75
100
125
DocID13863 Rev 3
-45
-25
0
25
50
Tj (°C)
75
100
125
11/15
15
Package information
7
L6385E
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
Figure 15. DIP-8 package outline
Table 8. DIP-8 package mechanical data
Dimensions (mm)
Dimensions (inch)
Symbol
Min.
A
Typ.
Min.
3.32
Typ.
Max.
0.131
a1
0.51
0.020
B
1.15
1.65
0.045
0.065
b
0.356
0.55
0.014
0.022
b1
0.204
0.304
0.008
0.012
D
E
10.92
7.95
9.75
0.430
0.313
0.384
e
2.54
0.100
e3
7.62
0.300
e4
7.62
0.300
F
6.6
0.260
I
5.08
0.200
L
Z
12/15
Max.
3.18
3.81
1.52
DocID13863 Rev 3
0.125
0.150
0.060
L6385E
Package information
Figure 16. SO-8 package outline
$09
Table 9. SO-8 package mechanical data
Dimensions (mm)
Dimensions (inch)
Symbol
Min.
Typ.
A
Max.
Min.
Typ.
1.750
0.0689
A1
0.100
A2
1.250
b
0.280
0.480
0.0110
0.0189
c
0.170
0.230
0.0067
0.0091
D(1)
4.800
4.900
5.000
0.1890
0.1929
0.1969
E
5.800
6.000
6.200
0.2283
0.2362
0.2441
3.800
3.900
4.000
0.1496
0.1535
0.1575
(2)
E1
e
0.250
Max.
0.0039
0.0098
0.0492
1.270
0.0500
h
0.250
0.500
0.0098
0.0197
L
0.400
1.270
0.0157
0.0500
L1
k
ccc
1.040
0°
0.0409
8°
0.10
0°
8°
0.0039
1. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm in total (both sides).
2. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
DocID13863 Rev 3
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15
Revision history
8
L6385E
Revision history
Table 10. Document revision history
14/15
Date
Revision
Changes
02-Oct-2007
1
First release
19-Jun-2014
2
Added Section : Applications on page 1.
Updated Section : Description on page 1 (replaced by new
description).
Updated Table 1: Device summary on page 1 (moved from page 15
to page 1, renamed title of Table 1).
Updated Figure 1: Block diagram on page 3 (moved from page 1 to
page 3, added Section 1: Block diagram on page 3).
Updated Section 2.1: Absolute maximum ratings on page 4
(removed note below Table 2: Absolute maximum ratings).
Updated Table 5: Pin description on page 5 (updated “Pin” and
“Type”).
Updated Section : CBOOT selection and charging on page 8 (updated
values of “E.g.: HVG”).
Numbered Equation 1 on page 8, Equation 2 on page 8 and
Equation 3 on page 9.
Updated Section 7: Package information on page 12 [updated/added
titles, reversed order of Figure 15 and Table 8, Figure 16 and Table 9
(numbered tables), removed 3D package figures, minor
modifications].
Minor modifications throughout document.
01-Dec-2014
3
Updated Section : Description on page 1.
Updated Table 7 on page 6 (corrected typo in units of “Iso” and “Isi”
parameters).
DocID13863 Rev 3
L6385E
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2014 STMicroelectronics – All rights reserved
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