L6392 High voltage high and low-side driver Applications -

L6392 High voltage high and low-side driver Applications -
L6392
High voltage high and low-side driver
Datasheet - production data
Applications
 Motor driver for home appliances, factory
automation, industrial drives.
 HID ballasts, power supply units.
Description
The L6392 is a high voltage device manufactured
with the BCD™ “offline” technology. It is a single
chip half bridge gate driver for the N-channel
power MOSFET or IGBT.
Features
 High voltage rail up to 600 V
 dV/dt immunity ± 50 V/nsec in full temperature
range
 Driver current capability:
– 290 mA source
– 430 mA sink
 Switching times 75/35 nsec rise/fall with 1 nF
load
The high-side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for easy
interfacing microcontroller/DSP.
The IC embeds an operational amplifier suitable
for advanced current sensing in applications such
as field oriented motor control.
 3.3 V, 5 V TTL/CMOS inputs with hysteresis
 Integrated bootstrap diode
 Operational amplifier for advanced current
sensing
 Adjustable deadtime
 Interlocking function
 Compact and simplified layout
 Bill of material reduction
 Flexible, easy and fast design
September 2015
This is information on a product in full production.
DocID14494 Rev 6
1/20
www.st.com
Contents
L6392
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6
Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
8
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
SO-14 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
DocID14494 Rev 6
L6392
1
Block diagram
Block diagram
Figure 1. Block diagram
VCC
BOOTSTRAP DRIVER
4
UV
DETECTION
FLOATING STRUCTURE
from LVG
14
BOOT
13
HVG
12
OUT
UV
DETECTION
HVG
DRIVER
HIN
3
LEVEL
SHIFTER
S
R
LOGIC
5V
SHOOT
THROUGH
PREVENTION
LIN
1
VCC
SD
GND
DT
LVG
DRIVER
LVG
10
2
7
5
DEAD
TIME
VCC
OPOUT
OPAMP
6
+
8
OP+
OP-
9
DocID14494 Rev 6
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Pin connection
2
L6392
Pin connection
Figure 2. Pin connections (top view)
LIN
1
14
BOOT
SD
2
13
HVG
HIN
3
12
OUT
VCC
4
11
NC
DT
5
10
LVG
OPOUT
6
9
OP-
GND
7
8
OP+
Table 1. Pin description
Pin no.
Pin name
Type
1
LIN
I
Low-side driver logic input (active low)
I
Shutdown logic input (active low)
2
SD
(1)
Function
3
HIN
I
High-side driver logic input (active high)
4
VCC
P
Lower section supply voltage
5
DT
I
Deadtime setting
6
OPOUT
O
Opamp output
7
GND
P
Ground
8
OP+
I
Opamp non inverting input
9
OP-
I
Opamp inverting input
O
Low-side driver output
10
LVG
(1)
11
NC
Not connected
12
OUT
(1)
13
HVG
14
BOOT
P
High-side (floating) common voltage
O
High-side driver output
P
Bootstrapped supply voltage
1. The circuit provides less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This allows
to omit the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low; the gate driver assures low impedance also in SD condition.
4/20
DocID14494 Rev 6
L6392
3
Truth table
Truth table
Table 2. Truth table
Inputs
Outputs
SD
LIN
HIN
LVG
HVG
L
X(1)
X(1)
L
L
H
L
L
H
L
H
L
H
L
L
H
H
L
L
L
H
H
H
L
H
1. X: don’t care.
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Electrical data
L6392
4
Electrical data
4.1
Absolute maximum ratings
Table 3. Absolute maximum rating
Value
Symbol
Parameter
Unit
Min.
Max.
VCC
Supply voltage
- 0.3
+ 21
V
VOUT
Output voltage
VBOOT -21
VBOOT +0.3
V
VBOOT
Bootstrap voltage
- 0.3
620
V
Vhvg
High-side gate output voltage
VOUT - 0.3
VBOOT + 0.3
V
VIvg
Low-side gate output voltage
-0.3
VCC + 0.3
V
Vop+
Opamp non-inverting input
-0.3
VCC + 0.3
V
Vop-
Opamp inverting input
-0.3
VCC + 0.3
V
Logic input voltage
-0.3
15
V
50
V/ns
Vi
dVOUT/dt Allowed output slew rate
4.2
Ptot
Total power dissipation (TA = 25 °C)
800
mW
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
ESD
Human body model
-50
2
kV
Thermal data
Table 4. Thermal data
Symbol
Rth(JA)
6/20
Parameter
Thermal resistance junction to ambient
DocID14494 Rev 6
SO-14
Unit
120
°C/W
L6392
4.3
Electrical data
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Pin
VCC
4
VBO(1)
VOUT
Min.
Max.
Unit
Supply voltage
12.5
20
V
14 - 12 Floating supply voltage
12.4
20
V
580
V
800
kHz
125
°C
12
Parameter
Test condition
(2)
DC output voltage
fsw
Switching frequency
TJ
Junction temperature
-9
HVG, LVG load CL = 1 nF
-40
1. VBO = VBOOT -VOUT
2. LVG off. VCC = 12.5 V.
Logic is operational if VBOOT > 5 V.
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Electrical characteristics
L6392
5
Electrical characteristics
5.1
AC operation
Table 6. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Symbol
ton
toff
tsd
Pin
1 vs.10
3 vs. 13
2 vs. 10,
13
DT
5
High/low-side driver turnVOUT = 0 V
on propagation delay
VBOOT = Vcc
High/low side driver turnCL = 1 nF
off propagation delay
Vi = 0 to 3.3 V
Shut down to high/low
See Figure 3
side propagation delay
Deadtime setting range(1)
Matching deadtime(2)
MDT
tf
Test condition
Typ. Max. Unit
50
125
200
ns
50
125
200
ns
50
125
200
ns
30
ns
10, 13
RDT = 0; CL = 1 nF
0.1
0.18
0.25
RDT = 37 k;CL = 1 nF; CDT= 100 nF
0.48
0.6
0.72
RDT = 136 k;CL =1 nF; CDT = 100 nF 1.35
1.6
1.85
RDT = 260 k;CL = 1 nF; CDT = 100 nF
3.0
3.4
2.6
RDT = 0 ; CL = 1 nF
80
RDT = 37 k;CL= 1 nF; CDT = 100 nF
120
RDT = 136 k;CL = 1 nF; CDT = 100 nF
250
RDT = 260 k;CL = 1 nF; CDT = 100 nF
400
s
ns
Rise time
CL = 1 nF
75
120
ns
Fall time
CL = 1 nF
35
70
ns
1. See Figure 4.
2. MDT = | DTLH - DTHL | see Figure 5 on page 12.
8/20
Min.
Delay matching, HS and
LS turn-on/off
MT
tr
Parameter
DocID14494 Rev 6
L6392
Electrical characteristics
Figure 3. Timing characteristics
50%
LIN
50%
tr
tf
90%
LVG
90%
10%
10%
ton
toff
50%
HIN
50%
tr
tf
90%
HVG
90%
10%
10%
ton
toff
50%
SD
tf
90%
LVG/HVG
10%
tsd
Figure 4. Typical deadtime vs. DT resistor value
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DocID14494 Rev 6
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Electrical characteristics
5.2
L6392
DC operation
Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Symbol
Pin
Parameter
Test condition
Min.
Typ.
Max.
Unit
Vcc UV hysteresis
1200
1500
1800
mV
Vcc_thON
Vcc UV turn-ON
threshold
11.5
12
12.5
V
Vcc_thOFF
Vcc UV turn-OFF
threshold
10
10.5
11
V
Low supply voltage section
Vcc_hys
4
Iqccu
Undervoltage quiescent
supply current
VCC = 10 V; SD = 5 V; LIN = 5 V;
HIN = GND; RDT = 0 ;
OP + = GND; OP - = 5 V
120
150
A
Iqcc
Quiescent current
VCC = 15 V; SD = 5 V; LIN = 5 V;
HIN = GND; RDT = 0 ;
OP + = GND; OP - = 5 V
680
1000
A
Bootstrapped supply voltage section(1)
VBO_hys
VBO UV hysteresis
1200
1500
1800
mV
VBO_thON
VBO UV turn-ON
threshold
10.6
11.5
12.4
V
VBO_thOFF
VBO UV turn-OFF
threshold
9.1
10
10.9
V
14
IQBOU
Undervoltage VBO
quiescent current
VBO = 9 V
SD = 5 V; LIN and HIN = 5 V;
RDT = 0 ; OP + = GND; OP - = 5 V
70
110
A
IQBO
VBO quiescent current
VBO = 15 V
SD = 5 V; LIN and HIN = 5 V;
RDT = 0 ; OP + = GND; OP - = 5 V
150
210
A
ILK
High voltage leakage
current
Vhvg = VOUT = VBOOT = 600 V
10
A
RDS(on)
Bootstrap driver onresistance(2)
LVG ON
120

Driving buffers section
Iso
10, 13
Isi
High/low-side source
short-circuit current
Vi = Vih (tp < 10 ms)
200
290
mA
High/low side sink shortVi = Vil (tp < 10 ms)
circuit current
250
430
mA
Low level logic threshold
voltage
0.8
1.1
V
High level logic threshold
voltage
1.9
2.25
V
Logic inputs
Vil
1, 2, 3
Vih
10/20
DocID14494 Rev 6
L6392
Electrical characteristics
Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = +25 °C) (continued)
Symbol
Pin
Vil_S
1, 3
Parameter
Test condition
Single input voltage
LIN and HIN connected together
and floating
HIN logic “1” input bias
current
HIN = 15 V
IHINl
HIN logic “0” input bias
current
HIN = 0 V
ILINI
LIN logic “0” input bias
current
LIN = 0 V
ILINh
LIN logic “1” input bias
current
LIN = 15 V
ISDh
SD logic “1” input bias
current
SD = 15 V
SD logic “0” input bias
current
SD = 0 V
IHINh
3
1
2
ISDl
Min.
Typ.
Max.
Unit
0.8
V
260
A
1
A
20
A
1
A
100
A
1
A
Max.
Unit
6
mV
4
40
nA
100
200
nA
0
VCC-4
V
0.07
VCC-4
V
110
175
3
6
10
30
1. VBO = VBOOT - VOUT.
2. RDSon is tested in the following way:
RDSon = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC,VBOOT1) - I2 (VCC,VBOOT2)] where I1 is pin 14 current
when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2.
Table 8. Op amp characteristics(1) (VCC = 15 V, TJ = +25 °C)
Symbol
Pin
Parameter
Vio
Input offset voltage
Iio
Input offset current
Iib
6, 9
Test condition
Vic = 0 V, Vo = 7.5 V
Input bias current(2)
Output voltage swing
VOPOUT
Typ.
Vic = 0 V, Vo = 7.5 V
Input common mode voltage
range
Vicm
Min.
OPOUT = OP-; no load
Source, Vid = +1; Vo = 0 V
16
30
mA
Sink,Vid = -1; Vo = VCC
50
80
mA
Slew rate
Vi = 1  4 V; CL = 100 pF;
unity gain
2.5
3.8
V/s
GBWP
Gain bandwidth product
Vo = 7.5 V
8
12
MHz
Avd
Large signal voltage gain
RL = 2 k
70
85
dB
SVR
Supply voltage rejection ratio vs. VCC
60
75
dB
Common mode rejection
ratio
55
70
dB
Io
SR
CMRR
7
Output short-circuit current
1. The operational amplifier is disabled when VCC is in UVLO condition.
2. The direction of the input current is out of the IC.
DocID14494 Rev 6
11/20
20
Waveforms definitions
6
L6392
Waveforms definitions
Figure 5. Deadtime - timing waveforms
INTE
RLO
CKIN
G
HIN
INTE
RLO
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
CKIN
G
LIN
LVG
DTHL
DTLH
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(*) HIN and LIN can be connected togheter and driven by just one control signal
12/20
DocID14494 Rev 6
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
L6392
Typical application diagram
7
Typical application diagram
Figure 6. Application diagram
BOOTSTRAP DRIVER
VCC
4
UV
DETECTION
FLOATING STRUCTURE
from LVG
14
BOOT
UV
DETECTION
H.V.
HVG
DRIVER
HIN
3
LEVEL
SHIFTER
S
13
HVG
12
OUT
Cboot
R
LOGIC
5V
SHOOT
THROUGH
PREVENTION
LIN
1
TO LOAD
VCC
SD
GND
DT
2
LVG
DRIVER
LVG
10
SD
LATCH
7
5
DEAD
TIME
OPAMP
OPOUT
+
6
8
OP+
OP-
9
DocID14494 Rev 6
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Bootstrap driver
8
L6392
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 7 a). In the L6392 device
a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as
shown in Figure 7 b.
An internal charge pump (Figure 7 b) provides the DMOS driving voltage.
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Equation 1
Q gate
C EXT = -------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
CBOOT >>> CEXT
E.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also
the leakage and quiescent losses.
E.g.: HVG steady state consumption is lower than 200 A, so if HVG TON is 5 ms, CBOOT
has to supply 1 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 1 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value:
120 ). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 2
Q gate
V drop = I ch arg e R dson  V drop = ------------------R dson
T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on-resistance of the
bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor.
14/20
DocID14494 Rev 6
L6392
Bootstrap driver
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact:
Equation 3
30nC
V drop = ---------------  120  0.7V
5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 7. Bootstrap driver
DBOOT
VS
BOOT
BOOT
VS
H.V.
H.V.
HVG
HVG
CBOOT
VOUT
CBOOT
VOUT
TO LOAD
TO LOAD
LVG
LVG
a
b
DocID14494 Rev 6
D99IN1067
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20
Package information
9
L6392
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
SO-14 package information
Figure 8. SO-14 package outline
'
16/20
DocID14494 Rev 6
L6392
Package information
Table 9. SO-14 package mechanical data
Dimensions
Symbol
mm
Min.
Typ.
inch
Max.
Min.
Typ.
Max.
A
1.35
1.75
0.053
0.069
A1
0.10
0.30
0.004
0.012
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.01
(1)
8.55
8.75
0.337
0.344
E
3.80
4.0
0.150
0.157
D
e
1.27
0.050
H
5.8
6.20
0.228
0.244
h
0.25
0.50
0.01
0.02
L
0.40
1.27
0.016
0.050
k
0° (min.), 8° (max.)
ddd
0.10
0.004
1. “D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.
Figure 9. SO-14 footprint
".
DocID14494 Rev 6
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20
Order codes
10
L6392
Order codes
Table 10. Order codes
18/20
Order codes
Package
Packaging
L6392D
SO-14
Tube
L6392DTR
SO-14
Tape and reel
DocID14494 Rev 6
L6392
11
Revision history
Revision history
Table 11. Document revision history
Date
Revision
29-Feb-2008
1
Initial release
18-Mar-2008
2
Cover page updated
17-Sep-2008
3
Updated Table 3 on page 6, Table 3 on page 6,
17-Feb-2009
4
Updated Table 6 on page 8, Table 7 on page 10, Table 8 on page 11
Added Table 4 on page 9
11-Aug-2010
5
Updated cover page, Table 1 on page 1, Table 6 on page 8, Table 8
on page 11.
6
Removed DIP-14 package from the entire document.
Updated Table 3 on page 6 (added ESD parameter and value,
removed note below Table 3).
Updated Table 4 on page 6 (updated Rth(JA) value).
Updated Table 6 on page 8 (updated DT and MDT test conditions).
Updated Table 7 on page 10 (updated Vil and Vih parameter and
values, updated note 1. and 2. below Table 7 - minor modifications,
replaced VCBOOTx by VBOOTx ).
Updated Table 8 on page 11.
Named and numbered Equation 1 on page 14, Equation 2 on page
14 and Equation 3 on page 15.
Updated Section 9 on page 16 (added Figure 9 on page 17, minor
modifications).
Updated Table 10 on page 18 (moved from page 1 to page 18, added
and updated titles).
Minor modifications throughout document.
11-Sep-2015
Changes
DocID14494 Rev 6
19/20
20
L6392
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
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