L6398 High voltage high and low-side driver Applications Description

L6398 High voltage high and low-side driver Applications Description
L6398
High voltage high and low-side driver
Datasheet - production data
Applications
 Motor driver for home appliances, factory
automation, industrial drives and fans.
62
Description
The L6398 is a high voltage device manufactured
with the BCD™ “offline” technology. It is a singlechip half bridge gate driver for the N-channel
power MOSFET or IGBT.
Features
 High voltage rail up to 600 V
 dV/dt immunity ± 50 V/ns in full temperature
range
 Driver current capability:
– 290 mA source
– 430 mA sink
The high-side (floating) section is designed to
stand a voltage rail up to 600 V. The logic inputs
are CMOS/TTL compatible down to 3.3 V for the
easy interfacing microcontroller/DSP.
 Switching times 75/35 ns rise/fall with 1 nF load
 3.3 V, 5 V TTL/CMOS input comparators with
hysteresis
 Integrated bootstrap diode
 Fixed 320 ns deadtime
 Interlocking function
 Compact and simplified layout
 Bill of material reduction
 Flexible, easy and fast design
September 2015
This is information on a product in full production.
DocID18199 Rev 4
1/16
www.st.com
Contents
L6398
Contents
1
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5
4.1
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3
Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.1
AC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5.2
DC operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6
Waveforms definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7
Typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
8
Bootstrap driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
CBOOT selection and charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
9
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SO-8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
10
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
11
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2/16
DocID18199 Rev 4
L6398
Block diagram
1
Block diagram
Figure 1. Block diagram
#005453"1%3*7&3
7$$
67
%&5&$5*0/
7
'-0"5*/(4536$563&
GSPN-7(
)*/
)7(
%3*7&3
-0(*$
4
3
4)005
5)306()
13&7&/5*0/
)7(
065
7$$
%&"%5*.&
(/%
#005
67
%&5&$5*0/
-&7&4)*'5&3
-*/
-7(
%3*7&3
-7(
$0Y
DocID18199 Rev 4
3/16
16
Pin connection
2
L6398
Pin connection
Figure 2. Pin connection (top view)
-*/
#005
)*/
)7(
7$$
065
(/%
-7(
$0Y
Table 1. Pin description
Pin no.
Pin name
Type
1
LIN
I
Low side-driver logic input (active low)
2
HIN
I
High-side driver logic input (active high)
3
VCC
P
Lower section supply voltage
4
GND
P
Ground
5
LVG (1)
O
Low-side driver output
6
OUT
P
High-side (floating) common voltage
O
High-side driver output
P
Bootstrapped supply voltage
(1)
7
HVG
8
BOOT
Function
1. The circuit guarantees less than 1 V on the LVG and HVG pins (at Isink = 10 mA), with VCC > 3 V. This
allows omitting the “bleeder” resistor connected between the gate and the source of the external MOSFET
normally used to hold the pin low.
4/16
DocID18199 Rev 4
L6398
3
Truth table
Truth table
Table 2. Truth table
Input
Output
LIN
HIN
LVG
HVG
H
L
L
L
L
H
L
L
L
L
H
L
H
H
L
H
DocID18199 Rev 4
5/16
16
Electrical data
L6398
4
Electrical data
4.1
Absolute maximum ratings
Table 3. Absolute maximum rating
Value
Symbol
Parameter
Unit
Min.
Max.
Vcc
Supply voltage
-0.3
21
V
VOUT
Output voltage
VBOOT - 21
VBOOT + 0.3
V
VBOOT
Bootstrap voltage
-0.3
620
V
Vhvg
High-side gate output voltage
VOUT - 0.3
VBOOT + 0.3
V
Vlvg
Low-side gate output voltage
-0.3
Vcc + 0.3
V
Logic input voltage
-0.3
15
V
50
V/ns
Vi
dVOUT/dt Allowed output slew rate
4.2
Ptot
Total power dissipation (TA = 25 °C)
800
mW
TJ
Junction temperature
150
°C
Tstg
Storage temperature
150
°C
ESD
Human body model
-50
2
kV
Thermal data
Table 4. Thermal data
Symbol
Rth(JA)
4.3
Parameter
Thermal resistance junction to ambient
SO-8
Unit
150
°C/W
Recommended operating conditions
Table 5. Recommended operating conditions
Symbol
Pin
Vcc
3
VBO(1)
8-6
VOUT
6
Parameter
Min.
Max.
Unit
Supply voltage
10
20
V
Floating supply voltage
9.8
20
V
Output voltage
11(2)
580
V
800
kHz
125
°C
fsw
Switching frequency
TJ
Junction temperature
Test condition
HVG, LVG load CL = 1 nF
1. VBO = VBOOT - VOUT.
2. LVG off. VCC = 10 V
Logic is operational if VBOOT > 5 V.
6/16
DocID18199 Rev 4
-40
L6398
Electrical characteristics
5
Electrical characteristics
5.1
AC operation
Table 6. AC operation electrical characteristics (VCC = 15 V; TJ = +25 °C)
Symbol
ton
toff
Pin
1, 2
vs.
5, 7
DT
tr
tf
5, 7
Parameter
Test condition
Min. Typ. Max. Unit
High/low-side driver turn-on VOUT = 0 V
propagation delay
VBOOT = Vcc
CL = 1 nF
High/low side driver turn-off
VIN = 0 to 3.3 V
propagation delay
See Figure 3
50
125
200
ns
50
125
200
ns
225
320
415
ns
Deadtime(1)
CL = 1 nF
Rise time
CL = 1 nF
75
120
ns
Fall time
CL = 1 nF
35
70
ns
1. See Figure 4.
Figure 3. Timing
LIN
50%
50%
tr
tf
90%
LVG
10%
10%
ton
HIN
90%
toff
50%
50%
tr
tf
90%
HVG
90%
10%
10%
ton
toff
DocID18199 Rev 4
7/16
16
Electrical characteristics
5.2
L6398
DC operation
Table 7. DC operation electrical characteristics (VCC = 15 V; TJ = + 25 °C)
Symbol
Pin
Vcc_hys
Parameter
Test condition
Min.
Typ.
Max.
Unit
1.2
1.5
1.8
V
Vcc UV turn-ON threshold
9
9.5
10
V
Vcc UV turn-OFF threshold
7.6
8
8.4
V
Vcc UV hysteresis
Vcc_thON
Vcc_thOFF
3
Iqccu
Undervoltage quiescent supply
current
Vcc = 7 V
LIN = 5 V; HIN = GND;
90
150
A
Iqcc
Quiescent current
Vcc = 15 V
LIN = 5 V; HIN = GND;
380
440
A
Bootstrapped supply voltage section(1)
VBO_hys
VBO_thON
VBO_thOFF
8
VBO UV hysteresis
0.8
1
1.2
V
VBO UV turn-ON threshold
8.2
9
9.8
V
VBO UV turn-OFF threshold
7.3
8
8.7
V
IQBOU
Undervoltage VBO quiescent
current
VBO = 7 V, LIN = HIN = 5V
30
60
A
IQBO
VBO quiescent current
VBO = 15 V, LIN = HIN = 5V
190
240
A
High voltage leakage current
Vhvg = VOUT = VBOOT =
600 V
10
A
Bootstrap driver on resistance(2)
LVG ON
ILK
RDS(on)
120

Driving buffers section
Iso
5, 7
Isi
High/low-side source short-circuit
current
VIN = Vih (tp < 10 s)
200
290
mA
High/low side sink short-circuit
current
VIN = Vil (tp < 10 s)
250
430
mA
Logic inputs
Vil
Vih
Vil_S
IHINh
IHINl
ILINl
ILINh
1, 2
Low level logic threshold voltage
0.8
1.1
V
High level logic threshold voltage
1.9
2.25
V
0.8
V
260
A
1
A
20
A
1
A
LIN and HIN connected
together and floating
1, 2 Single input voltage
2
1
HIN logic “1” input bias current
HIN = 15 V
HIN logic “0” input bias current
HIN = 0 V
LIN logic “0” input bias current
LIN = 0 V
LIN logic “1” input bias current
LIN = 15 V
110
3
175
6
1. VBO = VBOOT - VOUT.
2. RDSON is tested in the following way: RDSON = [(VCC - VBOOT1) - (VCC - VBOOT2)] / [I1(VCC, VBOOT1) - I2(VCC, VBOOT2)]
where I1 is the pin 8 current when VBOOT = VBOOT1, I2 when VBOOT = VBOOT2.
8/16
DocID18199 Rev 4
L6398
Waveforms definitions
Figure 4. Deadtime and interlocking waveforms definitions
G
HIN
INTE
RLO
CKIN
CONTROL SIGNAL EDGES
OVERLAPPED:
INTERLOCKING + DEAD TIME
RLO
CKIN
G
LIN
INTE
6
Waveforms definitions
LVG
DTHL
DTLH
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
SYNCHRONOUS (*):
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
BUT INSIDE THE DEAD TIME:
DEAD TIME
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
LIN
CONTROL SIGNALS EDGES
NOT OVERLAPPED,
OUTSIDE THE DEAD TIME:
DIRECT DRIVING
HIN
LVG
DTLH
DTHL
HVG
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
gate driver outputs OFF
(HALF-BRIDGE TRI-STATE)
(*) HIN and LIN can be connected togheter and driven by just one control signal
DocID18199 Rev 4
9/16
16
Typical application diagram
7
L6398
Typical application diagram
Figure 5. Application diagram
7$$
#005453"1%3*7&3
67
%&5&$5*0/
7
'-0"5*/(4536$563&
GSPN-7(
-*/
#005
67
%&5&$5*0/
)7
)7(
%3*7&3
-0(*$
-&7&4)*'5&3
'30.$0/530--&3
4
$CPPU
)7(
065
3
4)005
5)306()
13&7&/5*0/
50-0"%
'30.$0/530--&3
)*/
(/%
7$$
%&"%5*.&
-7(
%3*7&3
-7(
$0Y
10/16
DocID18199 Rev 4
L6398
8
Bootstrap driver
Bootstrap driver
A bootstrap circuitry is needed to supply the high voltage section. This function is normally
accomplished by a high voltage fast recovery diode (Figure 6). In the L6398 device
a patented integrated structure replaces the external diode. It is realized by a high voltage
DMOS, driven synchronously with the low-side driver (LVG), with a diode in series, as
shown in Figure 7. An internal charge pump (Figure 7) provides the DMOS driving voltage.
CBOOT selection and charging
To choose the proper CBOOT value the external MOS can be seen as an equivalent
capacitor. This capacitor CEXT is related to the MOS total gate charge:
Equation 1
Q gate
C EXT = -------------V gate
The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss.
It has to be:
Equation 2
CBOOT >>> CEXT
E.g.: if Qgate is 30 nC and Vgate is 10 V, CEXT is 3 nF. With CBOOT = 100 nF the drop would be
300 mV.
If HVG has to be supplied for a long time, the CBOOT selection has to take into account also
the leakage and quiescent losses.
E.g.: HVG steady state consumption is lower than 190 A, so if HVG TON is 5 ms, CBOOT
has to supply 1 C to CEXT. This charge on a 1 F capacitor means a voltage drop of 1 V.
The internal bootstrap driver gives a great advantage: the external fast recovery diode can
be avoided (it usually has great leakage current).
This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the
LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are
fulfilled and it has to be long enough to charge the capacitor.
The bootstrap driver introduces a voltage drop due to the DMOS RDSon (typical value:
120 ). At low frequency this drop can be neglected. Anyway increasing the frequency it
must be taken in to account.
The following equation is useful to compute the drop on the bootstrap DMOS:
Equation 3
Q gate
V drop = I ch arg e R dson  V drop = ------------------R dson
T ch arg e
where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the
bootstrap DMOS and Tcharge is the charging time of the bootstrap capacitor.
DocID18199 Rev 4
11/16
16
Bootstrap driver
L6398
For example: using a power MOS with a total gate charge of 30 nC the drop on the
bootstrap DMOS is about 1 V, if the Tcharge is 5 s. In fact:
Equation 4
30nC
V drop = ---------------  120  0.7V
5s
Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop
is too high, or the circuit topology doesn’t allow a sufficient charging time, an external diode
can be used.
Figure 6. Bootstrap driver with high voltage fast recovery diode
DBOOT
VCC
BOOT
H.V.
HVG
CBOOT
OUT
TO LOAD
LVG
Figure 7. Bootstrap driver with internal charge pump
BOOT
VCC
H.V.
HVG
CBOOT
OUT
TO LOAD
LVG
12/16
DocID18199 Rev 4
L6398
9
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
SO-8 package information
Figure 8. SO-8 package outline
DocID18199 Rev 4
13/16
16
Package information
L6398
Table 8. SO-8 package mechanical data
Dimensions
Symbol
mm
Min.
Typ.
inch
Max.
Min.
Typ.
Max.
A
1.35
1.75
0.053
0.069
A1
0.10
0.25
0.004
0.010
A2
1.10
1.65
0.043
0.065
B
0.33
0.51
0.013
0.020
C
0.19
0.25
0.007
0.010
D (1)
4.80
5.00
0.189
0.197
E
3.80
4.00
0.15
0.157
e
1.27
0.050
H
5.80
6.20
0.228
0.244
h
0.25
0.50
0.010
0.020
L
0.40
1.27
0.016
0.050
k
ddd
0° (min.), 8° (max.)
0.10
0.004
1. Dimensions D do not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm (0.006 inch) in total (both sides).
Figure 9. SO-8 footprint
Footprint_0016023_G_FU
14/16
DocID18199 Rev 4
L6398
10
Order codes
Order codes
Table 9. Order codes
11
Order codes
Package
Packaging
L6398D
SO-8
Tube
L6398DTR
SO-8
Tape and reel
Revision history
Table 10. Document revision history
Date
Revision
14-Dec-2010
1
First release.
16-Feb-2011
2
Updated Table 7.
01-Apr-2011
3
Typo in coverpage
4
Removed DIP-8 package from the entire document.
Updated Table 3 on page 6 (added ESD parameter and value,
removed note below Table 3).
Updated Vil and Vih parameters and values in Table 7 on page 8 and
note 2. below Table 7 (replaced VCBOOTx by VBOOTx ).
Updated Section 9 on page 13 (added Figure 9 on page 14, minor
modifications).
Moved Table 9 on page 15 (moved from page 1 to page 15,
updated/added titles).
Minor modifications throughout document.
11-Sep-2015
Changes
DocID18199 Rev 4
15/16
16
L6398
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2015 STMicroelectronics – All rights reserved
16/16
DocID18199 Rev 4
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement