bq24620 Stand-Alone Synchronous Switched-Mode Lithium Phosphate Battery Charger With Low I q

bq24620 Stand-Alone Synchronous Switched-Mode Lithium Phosphate Battery Charger With Low I q
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bq24620
SLUS893B – MARCH 2010 – REVISED JUNE 2015
bq24620 Stand-Alone Synchronous Switched-Mode Lithium Phosphate Battery Charger
With Low Iq
1 Features
2 Applications
•
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300-kHz NMOS-NMOS Synchronous Buck
Converter
Stand-Alone Charger Designed Specifically for
Lithium Phosphate
5-V to 28-V VCC Operating Range, Supports 1 to
7 Battery Cells
High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
Integration
– Internal Loop Compensation
– Internal Soft Start
Safety
– Input Overvoltage Protection
– Battery Thermistor Sense Suspend Charge at
Hot/Cold Charge Suspend and Automatically
ICHARGE/8 at WARM/COOL
– Battery Detection
– Built-In Safety Timer
– Charge Overcurrent Protection
– Battery Short Protection
– Battery Overvoltage Protection
– Thermal Shutdown
Status Outputs
– Adapter Present
– Charger Operation Status
Charge Enable Pin
6-V Gate Drive for Synchronous Buck Converter
30-ns Driver Dead Time and 99.95% Maximum
Effective Duty Cycle
16-Pin 3.5-mm × 3.5-mm QFN Package
Energy Star Low Iq
– < 15-μA Off-State Battery Discharge Current
– < 1.5-mA Off-State Input Quiescent Current
Power Tools and Portable Equipment
Personal Digital Assistants
Handheld Terminals
Industrial and Medical Equipment
Netbooks, Mobile Internet Devices, and
Ultramobile PCs
3 Description
The bq24620 device is a highly integrated lithium
phosphate switched-mode battery charge controller.
The device offers a constant-frequency synchronous
switching PWM controller with high-accuracy charge
current
and
voltage
regulation,
charge
preconditioning, termination, and charge status
monitoring.
The bq24620 charges the battery in three phases:
preconditioning, constant current, and constant
voltage.
Device Information(1)
PART NUMBER
bq24620
PACKAGE
VQFN (16)
BODY SIZE (NOM)
3.50 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
ADAPTER
CE
VREF
HIDRV
ISET
STAT
ADAPTER
PG
VREF
PH
bq24620
1
LODRV
Battery
pack
SRP
SRN
VFB
TS
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24620
SLUS893B – MARCH 2010 – REVISED JUNE 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
4
5
5
5
5
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 12
8.3 Feature Description................................................. 13
8.4 Device Functional Modes........................................ 22
9
Application and Implementation ........................ 23
9.1 Application Information............................................ 23
9.2 Typical Application ................................................. 23
10 Power Supply Recommendations ..................... 29
11 Layout................................................................... 29
11.1 Layout Guidelines ................................................. 29
11.2 Layout Example .................................................... 30
12 Device and Documentation Support ................. 31
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
31
31
31
31
31
31
13 Mechanical, Packaging, and Orderable
Information ........................................................... 31
4 Revision History
Changes from Revision A (October 2011) to Revision B
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Original (March 2010) to Revision A
Page
•
Changed description for PH and BTST pins .......................................................................................................................... 4
•
Replaced Thermal Information table ...................................................................................................................................... 5
•
Corrected Equation 11 ......................................................................................................................................................... 24
2
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5 Device Comparison Table
Cell chemistry
bq24620
bq24630
Lithium phosphate
Lithium phosphate
1 to 7
1 to 7
1.8 to 26
1.8 to 26
5 to 28
5 to 28
32
32
Number of cells in series (minimum to
maximum, 4.2 V/cell)
Charge voltage (minimum to maximum) (V)
Input voltage range (minimum to maximum) (V)
Input overvoltage (V)
Maximum battery charging current (A)
10
10
Switching frequency (kHz)
300
300
JEITA charging temperature profile
No
No
DPM
No
IIN DPM
6 Pin Configuration and Functions
BTST
HIDRV
PH
LODRV
RVA Package
16-Pin VQFN
Top View
16
15
14
13
12 REGN
VCC 1
CE
OAR
(bq24620)
2
11 GND
QFN-16
TOP VIEW
STAT 3
10 SRP
TS 4
6
7
8
ISET
VFB
PG
5
VREF
9
SRN
Pin Functions
PIN
DESCRIPTION
NAME
NO.
BTST
16
PWM high-side driver negative supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap
Schottky diode from REGN to BTST.
CE
2
Charge enable active-HIGH logic input. HI enables charge. LO disables charge. The CE pin has an internal 1-MΩ
pulldown resistor.
GND
11
Low-current sensitive analog/digital ground. On PCB layout, connect with thermal pad underneath the IC.
HIDRV
15
PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
ISET
7
Charge current set input. The voltage of ISET pin programs the charge current regulation, precharge current and
termination current set-point.
LODRV
13
PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
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Pin Functions (continued)
PIN
NAME
DESCRIPTION
NO.
PG
5
Open-drain power good status output. The transistor turns on when a valid VCC is detected. The transistor is turned
off in the sleep mode. PG can be used to drive an LED or communicate with a host processor. The PG pin can be
used to drive ACFET and BATFET.
PH
14
PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET
drain, high-side power MOSFET source, and output inductor).
REGN
12
PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the PGND pin, close
to the IC. Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode
from REGN to BTST.
SRN
9
Charge current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to GND for common-mode
filtering.
SRP
10
Charge current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering. A 0.1-μF ceramic capacitor is placed from SRP pin to GND for common-mode filtering.
STAT
3
Open-drain charge status pin to indicate various charger operations (See Table 2)
Thermal
pad
—
Exposed pad beneath the IC. Always solder the thermal pad to the board, and have vias on the thermal-pad plane
star-connecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to
dissipate the heat.
TS
4
Temperature qualification voltage input for battery pack negative-temperature-coefficient thermistor. Program the hot
and cold temperature window with a resistor divider from VREF to TS to GND.
VCC
1
IC power positive supply. Connect through a 10-Ω resistor to the common-source (diode-OR) point: source of highside P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Or connect through a 10-Ω
resistor to the cathode of the input diode. Place a 1-μF ceramic capacitor from VCC to GND pin close to the IC.
VFB
8
Output voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery
terminals to this node to adjust the output battery regulation voltage.
VREF
6
3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to the GND pin close to the IC. This
voltage could be used for programming of voltage and current regulation and for programming the TS threshold.
7 Specifications
7.1 Absolute Maximum Ratings (1) (2) (3)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.3
33
PH
–2
36
VFB
–0.3
16
REGN, LODRV, TS
–0.3
7
BTST, HIDRV with respect to GND
–0.3
39
VREF, ISET
–0.3
3.6
SRP–SRN
VCC, SRP, SRN, CE, STAT, PG
Voltage
Maximum difference voltage
UNIT
V
–0.5
0.5
V
Junction temperature, TJ
–40
155
°C
Storage temperature, Tstg
–55
155
°C
(1)
(2)
(3)
4
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult the
packaging section of the data book for thermal limitations and considerations of packages.
Must have a series resistor between battery pack to VFB if battery pack voltage is expected to be greater than 16 V. Usually the
resistor-divider top resistor takes care of this.
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7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
VCC, SRP, SRN, CE, STAT, PG
PH
Voltage
NOM
MAX
–0.3
28
–2
30
VFB
–0.3
14
REGN, LODRV, TS
–0.3
6.5
BTST, HIDRV with respect to GND
–0.3
34
ISET
–0.3
3.3
VREF
Maximum difference
voltage
UNIT
V
3.3
SRP–SRN
–0.2
0.2
V
TJ
Junction temperature
0
125
°C
Tstg
Storage temperature
–55
155
°C
7.4 Thermal Information
bq24620
THERMAL METRIC (1)
RVA [VQFN]
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
ψJT
ψJB
RθJC(bot)
(1)
43.8
°C/W
81
°C/W
Junction-to-board thermal resistance
16
°C/W
Junction-to-top characterization parameter
0.6
°C/W
Junction-to-board characterization parameter
15.77
°C/W
Junction-to-case (bottom) thermal resistance
4
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
5 V ≤ VVCC ≤ 28 V, 0°C < TJ< 125°C, typical values are at TA= 25°C, with respect to GND unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VVCC_OP
VCC input voltage operating range
5
28
V
15
μA
QUIESCENT CURRENTS
IBAT
IAC
Total battery discharge current (sum of
currents into VCC, BTST, PH, SRP,
SRN, VFB), VFB ≤ 2.1 V
Adapter supply current (current into
VCC pin)
VVCC < VSRN, VVCC > VUVLO (SLEEP)
VVCC > VSRN, VVCC > VUVLO CE = LOW (IC quiescent
current)
1
1.5
VVCC > VSRN, VVCC >VVCCLOW , CE = HIGH, charge
done
2
5
VVCC > VSRN, VVCC >VVCCLOW , CE = HIGH,
Charging, Qg_total = 20 nC, VVCC = 20 V
mA
12
CHARGE VOLTAGE REGULATION
VFB
Feedback regulation voltage
1.8
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Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ< 125°C, typical values are at TA= 25°C, with respect to GND unless otherwise noted
PARAMETER
Charge voltage regulation accuracy
IVFB
Input leakage current into VFB pin
TEST CONDITIONS
MIN
TYP
MAX
TJ = 0°C to 85°C
–0.5%
0.5%
TJ = –40°C to 125°C
–0.7%
0.7%
VFB = 1.8 V
100
UNIT
nA
CURRENT REGULATION – FAST CHARGE
VISET
ISET voltage range
VIREG_CHG
SRP–SRN current-sense voltage range
VIREG_CHG = VSRP – VSRN
KISET
Charger current-set factor; amps of
charge current per volt on ISET pin)
RSENSE = 10 mΩ
IISET
Leakage current in to ISET Pin
2
0
100
5
VIREG_CHG = 40 mV
Charge current regulation accuracy
0
–3%
V
mV
A/V
3%
VIREG_CHG = 20 mV
–4%
4%
VIREG_CHG = 5 mV
–25%
25%
VIREG_CHG = 1.5 mV (VSRN > 3.1 V)
–40%
40%
VISET = 2 V
100
nA
200
mA
CURRENT REGULATION – PRECHARGE
Precharge current
RSENSE = 10 mΩ, VFB < VLOWV
50
125
CHARGE TERMINATION
Termination current range
RSENSE = 10 mΩ
ICHARGE/10
Termination current-set factor; amps of
termination current per volt on ISET pin
KTERM
Termination current accuracy
A
0.5
A/V
VITERM = 10 mV
–10%
10%
VITERM = 5 mV
–25%
25%
VITERM = 1.5 mV
–45%
45%
Deglitch time for termination (both
edge)
100
tQUAL
Termination qualification time
VBAT > VRECH and ICHARGE < ITERM
IQUAL
Termination qualification time
Discharge current once termination is detected
ms
250
ms
2
mA
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
VUVLO
AC undervoltage rising threshold
VUVLO_HYS
AC undervoltage hysteresis, falling
Measure on VCC
3.65
3.85
4
V
350
mV
4.1
V
VCC LOWV COMPARATOR
Falling threshold, disable charge
Measure on VCC
Rising threshold, resume charge
4.35
4.5
V
100
150
mV
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP
_FALL
VSLEEP_HYS
SLEEP falling threshold
VVCC – VSRN to enter SLEEP
40
SLEEP hysteresis
500
SLEEP rising delay
VCC falling below SRN, delay to pull up PG
SLEEP falling delay
VCC rising above SRN, delay to pull down PG
SLEEP rising shutdown deglitch
SLEEP falling powerup deglitch
mV
1
µs
30
ms
VCC falling below SRN, Delay to enter SLEEP mode
100
ms
VCC rising above SRN, Delay to come out of SLEEP
mode
30
ms
BAT LOWV COMPARATOR
VLOWV
LOWV rising threshold (precharge to
fast charge)
VLOWV_HYS
LOWV hysteresis
Measured on VFB pin
0.333
0.35
0.367
V
100
mV
LOWV rising deglitch
VFB falling below VLOWV
25
ms
LOWV falling deglitch
VFB rising above VLOWV + VLOWV_HYS
25
ms
RECHARGE COMPARATOR
VRECHG
6
Recharge threshold (with respect to
VREG)
Measured on VFB pin
Recharge rising deglitch
VFB decreasing below VRECHG
10
ms
Recharge falling deglitch
VFB increasing above VRECHG
10
ms
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110
125
140
mV
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Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ< 125°C, typical values are at TA= 25°C, with respect to GND unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BAT OVERVOLTAGE COMPARATOR
VOV_RISE
Overvoltage rising threshold
As percentage of VFB
108%
VOV_FALL
Overvoltage falling threshold
As percentage of VFB
105%
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV
AC overvoltage rising threshold on VCC
VACOV_HYS
AC overvoltage falling hysteresis
31.04
32
32.96
V
1000
mV
AC overvoltage rising deglitch
Delay to changing the STAT pins
1
ms
AC overvoltage falling deglitch
Delay to changing the STAT pins
1
ms
145
°C
15
°C
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising temperature
Temperature increasing
Thermal shutdown hysteresis
TSHUT_HYS
Thermal shutdown rising deglitch
Temperature increasing
100
μs
Thermal shutdown falling deglitch
Temperature decreasing
10
ms
THERMISTOR COMPARATOR
VLTF
Cold temperature rising threshold
VLTF_HYS
Cold temperature hysteresis
VCOOL
Cool temperature rising threshold
VCOOL_HYS
Cool temperature hysteresis
VWARM
Warm temperature rising threshold
VWARM_HYS
Warm temperature hysteresis
Charger suspended below this temperature
Charger enabled, cuts back to ICHARGE/8 below this
temperature
Charger cuts back to ICHARGE/8 above this
temperature
VHTF
Hot temperature rising threshold
Charger suspended above this temperature before
initiating charge
VTCO
Cutoff temperature rising threshold
Charger suspended above this temperature during
initiating charge
Deglitch time for temperature out-ofrange detection
VTS > VLTF, or VTS < VTCO, or VTS < VHTF
Deglitch time for temperature in-validrange detection
72.5%
73.5%
74.5%
0.2%
0.4%
0.6%
70.2%
70.7%
71.2%
0.2%
0.6%
1.0%
47.5%
48%
48.5%
1.0%
1.2%
1.4%
36.2%
37%
37.8%
33.7%
34.4%
35.1%
400
ms
VTS < VLTF – VLTF_HYS or VTS >VTCO, or VTS > VHTF
20
ms
Deglitch time for current reduction to
ICHARGE/8 due to warm or cool
temperature
VTS > VCOOL, or VTS < VWARM
25
ms
Deglitch time to charge at ICHARGE from
ICHARGE/8 when resuming from warm or
cool temperatures
VTS < VCOOL - VCOOL_HYS, or VTS > VWARM VWARM_HYS
25
ms
Charge current due to warm or cool
temperatures
VCOOL < VTS < VLTF, or VWARM < VTS < VHTF, or
VWARM < VTS < VTCO
ICHARGE/8
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
Charge overcurrent, falling threshold
VOC
Current rising, in nonsynchronous mode, measure
on V(SRP-SRN), VSRP < 2 V
45.5
Current rising, as percentage of V(IREG_CHG), in
synchronous mode, VSRP > 2.2 V
mV
160%
Charge overcurrent, threshold floor
Minimum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2 V
50
mV
Charge overcurrent, threshold ceiling
Maximum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2 V
180
mV
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET
Charge undercurrent, falling threshold
Switch from STNCH to NON-SYNCH, VSSP > 2.2 V
1
5
9
mV
BATTERY SHORTED COMPARATOR (BATSHORT)
VBATSHT
BAT short falling threshold, forced nonsyn mode
VBATSHT_HYS
BAT short rising hysteresis
VBATSHT_DEG
Deglitch on both edges
VSRP falling
2
200
mV
1
μs
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Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ< 125°C, typical values are at TA= 25°C, with respect to GND unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOW CHARGE CURRENT COMPARATOR
VLC
Average low charge current, falling
threshold
VLC_HYS
Low charge current, rising hysteresis
VLC_DEG
Deglitch on both edges
Measure on V(SRP-SRN), forced into nonsynchronous
mode
1.25
mV
1.25
mV
1
μs
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VVCC > VUVLO (0 – 35 mA Load)
IVREF_LIM
VREF current limit
VVREF = 0 V, VVCC > VUVLO
3.267
35
3.3
3.333
V
mA
REGN REGULATOR
VREGN_REG
REGN regulator voltage
VVCC > 10 V, CE = HIGH (0 – 40 mA Load)
5.7
IREGN_LIM
REGN current limit
VREGN = 0 V, VVCC > VUVLO
40
6
6.3
V
mA
SAFETY TIMER
TPRECHG
Precharge safety timer range (1)
TCHARGE
Internal fast-charge safety timer (1)
Precharge time before fault occurs
1440
1800
2160
s
4.25
5
5.75
Hr
200
mA
BATTERY DETECTION
tWAKE
Wake timer
Max time charge is enabled
IWAKE
Wake current
RSENSE = 10 mΩ
tDISCHARGE
Discharge timer
Max time discharge current is applied
IDISCHARGE
Discharge current
IFAULT
Fault current after a time-out fault
VWAKE
Wake threshold (relative to VREG)
Voltage on VFB to detect battery absent during wake
Discharge threshold
Voltage on VFB to detect battery absent during
discharge
0.35
V
VDISCH
500
50
125
ms
1
s
8
mA
2
mA
125
mV
PWM HIGH-SIDE DRIVER (HIDRV)
RDS_HI_ON
High-side driver (HSD) turnon
resistance
VBTST – VPH = 5.5 V
3.3
6
Ω
RDS_HI_OFF
High-side driver turnoff resistance
VBTST – VPH = 5.5 V
1
1.3
Ω
VBTST_REFRESH
Bootstrap refresh comparator threshold
voltage
VBTST – VPH when low-side refresh pulse is
requested
4
4.2
V
PWM LOW-SIDE DRIVER (LODRV)
RDS_LO_ON
Low-side driver (LSD) turnon resistance
RDS_LO_OFF
Low-side driver turnoff resistance
4.1
7
Ω
1
1.4
Ω
PWM DRIVERS TIMING
Driver dead time
Dead time when switching between LSD and HSD,
no load at LSD and HSD
30
ns
PWM OSCILLATOR
VRAMP_HEIGHT
PWM ramp height
As percentage of VCC
7%
PWM switching frequency (1)
255
300
345
kHz
INTERNAL SOFT START (Eight Steps to Regulation Current ICHARGE)
Soft-start steps
Soft-start step time
8
step
1.6
ms
1.5
s
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power up
Delay from when CE = 1 to when the charger is
allowed to turn on
LOGIC I/O PIN CHARACTERISTICS
VIN_LO
CE input-low threshold voltage
VIN_HI
CE input-high threshold voltage
VBIAS_CE
CE input bias current
V = 3.3 V (CE has internal 1-MΩ pulldown resistor)
VOUT_LO
STAT, PG output-low saturation voltage
Sink current = 5 mA
0.5
V
IOUT_HI
Leakage current
V = 32 V
1.2
µA
(1)
8
0.8
V
6
μA
2.1
V
Verified by design.
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7.6 Typical Characteristics
Table 1. Table Of Graphs
FIGURE
Figure 1
Charge Enable
Figure 2
Current Soft Start (CE = 1)
Figure 3
Charge Disable
Figure 4
Continuous Conduction Mode Switching Waveforms
Figure 5
Cycle-by-Cycle Synchronous to Nonsynchronous
Figure 6
Battery Insertion
Figure 7
Battery-to-Ground Short Protection
Figure 8
Efficiency vs Output Current
Figure 9
10 V/div
10 V/div
REF, REGN, and PG Power Up (CE = 1)
PH
2 A/div
IBAT
REGN
5 V/div
CE
5 V/div
2 V/div
VREF
5 V/div
/PG
2 V/div
VCC
LODRV
t − Time = 200 ms/div
Figure 2. Charge Enable
10 V/div
10 V/div
t − Time = 4 ms/div
Figure 1. REF, REGN, and PG Power Up (CE = 1)
LDRV
2 V/div
5 V/div
PH
2 A/div
5 V/div
IBAT
5 V/div
LODRV
2 A/div
PH
CE
IL
CE
t − Time = 4 ms/div
Figure 3. Current Soft Start (CE = 1)
t − Time = 4 μs/div
Figure 4. Charge Disable
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20 V/div
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LODRV
PH
2 A/div
2 A/div
5 V/div
20 V/div
HIDRV
5 V/div
5 V/div
PH
IL
LODRV
IL
t − Time = 200 ns/div
t – Time = 200 ns/div
Figure 6. Cycle-by-Cycle Synchronous to Nonsynchronous
5 V/div
10 V/div
20 V/div
Figure 5. Continuous Conduction Mode Switching
Waveform
2 A/div
2 A/div
PH
10 V/div
10 V/div
IL
VBAT
PH
LDRV
IL
VBAT
t – Time = 4 ms/div
t – Time = 200 ms/div
Figure 8. Battery-to-GND Short Protection
Figure 7. Battery Insertion
98
96
94
Efficiency - %
92
90
24 Vin, 6 cell
88
24 Vin, 5 cell
86
12 Vin, 2 cell
84
12 Vin, 1 cell
82
80
0
1
2
5
4
3
IBAT - Output Current - A
6
7
8
Figure 9. Efficiency vs Output Current
10
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8 Detailed Description
8.1 Overview
The bq24620 device is a stand-alone, integrated lithium phosphate battery charger. The device employs a
switched-mode synchronous buck PWM controller with constant switching frequency.
The bq24620 has a battery detect scheme that allows it to automatically detect the presence and absence of a
battery. When the battery is detected, charging begins in one of three phases (depending upon battery voltage):
precharge, constant current (fast-charge current regulation), and constant voltage (fast-charge voltage
regulation). The device will terminate charging when the termination current threshold has been reached and will
begin a recharge cycle when the battery voltage has dropped below the recharge threshold (VRECHG). Constant
(fastcharge) current and termination current can be configured through the ISET pin, allowing for flexibility in
battery charging profile. During charging, the integrated fault monitors of the device, such as battery overvoltage
protection, battery short detection (VBATSHT), thermal shutdown (internal TSHUT and TS pin), and input voltage
protection (VACOV and VUVLO), ensure battery safety.
The bq24620 has two status pins (STAT and PG) to indicate the charging status and input voltage (AC adapter)
status. These pins can be used to drive LEDs or communicate with a host processor. Additionally, the PG pin
can be used to drive external ACFET and BATFET.
Regulation Voltage
V RECH
Regulation Current
Fastcharge Current
Regulation Phase
Precharge
Current
Regulation
Phase
Fastcharge Voltage
Regulation Phase
Termination
Charge
Current
Charge
Voltage
V LOWV
I PRECH & I TERM
Precharge
Time
Fastcharge Safety Time
Figure 10. Typical Charging Profile
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8.2 Functional Block Diagram
bq24620
VREF
VOLTAGE
REFERENCE
VREF
3.3 V
LDO
VCC
-
SRN +100 mV
+
SLEEP
UVLO
VCC
VCC
-
V UVLO
+
SLEEP
UVLO
VCC
CE
1M
COMP
ERROR
AMPLIFIER
BTST
CE
+
+
1V
+
LEVEL
SHIFTER
-
1.8 V
PWM
-
VFB
20 mA
SRP
+
SRP-SRN
SYNCH
PH
-
IBAT_ REG
SRN
5 mV
VCC
-
20XV(SRP-SRN)
PWM
CONTROL
LOGIC
+
-
+
+
20 X
-
BTST
_
20 mA
PH
6V LDO
REFRESH
+
ENA _BIAS
4.2 V
LODRV
V(SRP -SRN )
-
160 % X IBAT _REG
+
2 mA
8 mA
5HR Safety
Timer
30 minute
Precharge
Timer
DISCHARGE
CHG _OCP
GND
FAULT
IC Tj
+
145 degC
-
STAT
TSHUT
CHARGE
STAT
PG
+
108 % X VBAT _REG
ISET
BAT _OVP
VREF
STATE
MACHINE
LOGIC
-
BAT
ISET
8
ISET
DISCHARGE
IBAT _ REG
LTF
LOWV
VFB
-
0.35V +-
BATTERY
DETECTION
LOGIC
LOWV
COOL
WARM
+
VCC
WARM
VACOV
RCHRG
HTF
+
+
-
RCHRG
-
ISET
10
TERM
TERM
TCO
+
-
+
20XV(SRP-SRN)
12
+
TS
SUSPEND
+
-
+
-
bq24620
-
-
ACOV
-
PG
+
+
COOL
VFB
+
1.25 mV
1.675 V
REGN
+
FAULT
CHARGE
HIDRV
BAT _OVP
TERMINATE CHARGE
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8.3 Feature Description
8.3.1 Battery Voltage Regulation
The bq24620 uses a high-accuracy voltage band gap and regulator for the charging voltage. The charge voltage
is programmed through a resistor-divider from the battery to ground, with the midpoint tied to the VFB pin. The
voltage at the VFB pin is regulated to 1.8 V, giving Equation 1 for the regulation voltage:
R2 ù
é
VBAT = 1.8 V ´ ê1 +
R1 úû
ë
where
•
where R2 is connected from VFB to the battery and R1 is connected from VFB to GND.
(1)
8.3.2 Battery Current Regulation
The ISET1 input sets the maximum charging current. Battery current is sensed by resistor RSR connected
between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus, for a 10-mΩ
sense resistor, the maximum charging current is 10 A. Equation 2 is for charge current:
VISET
ICHARGE =
20 ´ RSR
(2)
VISET, the input voltage range of ISET, is from 0 to 2 V. The SRP and SRN pins are used to sense voltage across
RSR with default value of 10 mΩ. However, resistors of other values can also be used. A larger sense resistor
gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher conduction loss.
8.3.3 Precharge
On power up, if the battery voltage is below the VLOWV threshold, the bq24620 applies 125 mA to the battery. (1)
The precharge feature is intended to revive deeply discharged cells. If the VLOWV threshold is not reached within
30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.
8.3.4 Charge Termination, Recharge, and Safety Timer
The bq24620 monitors the charging current during the voltage regulation phase. Termination is detected while
the voltage on the VFB pin is higher than the VRECH threshold AND the charge current is less than the ITERM
threshold, which is 1/10th of programmed charge current, as calculated in Equation 3:
VISET
ITERM =
200 ´ RSR
(3)
As a safety backup, the bq24620 also provides an internal 5-hour charge timer for fast charge.
A
•
•
•
new charge cycle is initiated when one of the following conditions occurs:
The battery voltage falls below the recharge threshold.
A power-on reset (POR) event occurs.
CE is toggled.
8.3.5 Power Up
The bq24620 uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be
supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, the bq24620
enables ACFET and disables BATFET. If all other conditions are met for charging, the bq24620 then attempts to
charge the battery (see Enable and Disable Charging). If the SRN voltage is greater than VCC, indicating that
the battery is the power source, bq24620 enters a low-quiescent-current (<15 μA) SLEEP mode to minimize
current drain from the battery.
If VCC is below the UVLO threshold, the device is disabled.
(1)
125 mA (assuming a 10-mΩ sense resistor. 1.25 mV is regulated across SRP-SRN, regardless of the value of the sense resistor.)
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Feature Description (continued)
8.3.6 Enable and Disable Charging
The following conditions must be valid before charge is enabled:
• CE is HIGH.
• The device is not in VCCLOWV mode.
• The device is not in SLEEP mode (that is, VCC > SRN) .
• The VCC voltage is lower than the ac overvoltage threshold (VCC < VACOV).
• 30-ms delay is complete after initial power up.
• The REGN LDO and VREF LDO voltages are at the correct levels.
• Thermal shutdown (TSHUT) is not valid.
• TS fault is not detected.
Any of the following conditions stops ongoing charging:
• CE is LOW.
• Adapter is removed, causing the device to enter VCCLOWV or SLEEP mode.
• Adapter voltage is less than 100 mV above battery.
• Adapter is over voltage.
• The REGN or VREF LDOs are overloaded.
• TSHUT IC temperature threshold is reached (145°C on rising edge with 15°C hysteresis).
• TS voltage goes out of range, indicating the battery temperature is too hot or too cold.
• Safety timer times out.
8.3.7 Automatic Internal Soft-Start Charger Current
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping up the charge regulation current into eight evenly divided steps up to the programmed charge
current. Each step lasts around 1.6 ms, for a typical rise time of 12.8 ms. No external components are needed
for this function.
8.3.8 Converter Operation
The synchronous buck PWM converter uses a fixed-frequency voltage mode with a feed-forward control scheme.
A type-III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 10 kHz to 15 kHz for
bq24620, where the resonant frequency, fo, is given by:
1
fo =
2 p L o Co
(4)
An internal sawtooth ramp is compared to the internal EAO error control signal to vary the duty cycle of the
converter. The ramp height is 7% of the input adapter voltage, making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop
compensation. The ramp is offset by 300 mV in order to allow zero-percent duty cycle when the EAO signal is
below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to get a 100% dutycycle PWM request. Internal gate-drive logic allows achieving 99.95% duty cycle while ensuring the N-channel
upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below 4.2 V for
more than three cycles, then the high-side N-channel power MOSFET is turned off and the low-side N-channel
power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the high-side
driver returns to 100% duty-cycle operation until the (BTST–PH) voltage is detected to fall low again due to
leakage current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region. Also see Application and Implementation for how to select the inductor, capacitor, and MOSFET.
14
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Feature Description (continued)
8.3.9 Synchronous and Nonsynchronous Operation
The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current
for a 10-mΩ sense resistor). During synchronous mode, the internal gate-drive logic ensures there is breakbefore-make complementary switching to prevent shoot-through currents. During the 30-ns dead time where both
FETs are off, the body diode of the low-side power MOSFET conducts the inductor current. Having the low-side
FET turn on keeps the power dissipation low, and allows safely charging at high currents. During synchronous
mode, the inductor current is always flowing and the converter operates in continuous conduction mode (CCM),
creating a fixed two-pole system.
The charger operates in nonsynchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor
current for a 10-mΩ sense resistor). The charger is forced into nonsynchronous mode when the battery voltage is
lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV.
During nonsynchronous operation, the body diode of the low-side MOSFET can conduct the positive inductor
current after the high-side N-channel power MOSFET turns off. When the load current decreases and the
inductor current drops to zero, the body diode is naturally turned off and the inductor current becomes
discontinuous. This mode is called discontinuous conduction mode (DCM). During DCM, the low-side N-channel
power MOSFET turns on for around 80 ns when the bootstrap capacitor voltage drops below 4.2 V; then the lowside power MOSFET turns off and stays off until the beginning of the next cycle, where the high-side power
MOSFET is turned on again. The 80-ns low-side MOSFET on-time is required to ensure the bootstrap capacitor
is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important
for battery chargers, where unlike regular DC-DC converters, there is a battery load that maintains a voltage and
can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high- and
low-side MOSFETs) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After the 80
ns, the low-side MOSFET is kept off to prevent negative inductor current from occurring.
At very low currents during nonsynchronous operation, there may be a small amount of negative inductor current
during the 80-ns recharge pulse. The charge must be low enough to be absorbed by the input capacitance.
Whenever the converter goes into zero-percent duty cycle, the high-side MOSFET does not turn on, and the lowside MOSFET does not turn on (only 80-ns recharge pulse) either, and there is almost no discharge from the
battery.
During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.
8.3.10 Cycle-by-Cycle Charge Undercurrent
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into nonsynchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current. During DCM, the low-side FET only turns on for around 80
ns when the bootstrap capacitor voltage drops below 4.2 V to provide refresh charge for the bootstrap capacitor.
This is important to prevent negative inductor current from causing a boost effect in which the input voltage
increases as power is transferred from the battery to the input capacitors, which leads to an overvoltage stress
on the VCC node and potentially causes damage to the system.
8.3.11 Input Overvoltage Protection (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage
reaches the ACOV threshold, charge is disabled and the battery is switched to the system instead of the adapter.
8.3.12 Input Undervoltage Lockout (UVLO)
The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from
either input the adapter orthe battery, if a conduction path exists from the battery to VCC through the high-side
NMOS body diode. When VCC is below the UVLO threshold, all circuits in the IC are disabled.
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Feature Description (continued)
8.3.13 Battery Overvoltage Protection
The converter does not allow the high-side FET to turn on until the BAT voltage goes below 105% of the
regulation voltage. This allows one-cycle response to an overvoltage condition, such as occurs when the load is
removed or the battery is disconnected. An 8-mA current sink from SRP/SRN to PGND is on only during charge
and allows discharging the stored output inductor energy that is transferred to the output capacitors. BATOVP
also suspends the safety timer.
8.3.14 Cycle-by-Cycle Charge Overcurrent Protection
The charger has a secondary cycle-to-cycle overcurrent protection. The charger monitors the charge current, and
prevents the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off
when the overcurrent is detected, and automatically resumes when the current falls below the overcurrent
threshold.
8.3.15 Thermal Shutdown Protection
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As an added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C. Then the charger soft-starts again if all other enable-charge
conditions are valid. Thermal shutdown also suspends the safety timer.
8.3.16 Temperature Qualification
The controller continuously monitors battery temperature by measuring the voltage between the TS pin and
GND. A negative temperature coefficient thermistor (NTC) and an external voltage divider typically develop this
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.
To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. If battery
temperature is outside of this range, the controller suspends charge and the safety timer and waits until the
battery temperature is within the VLTF to VHTF range. During the charge cycle, the battery temperature must be
within the VLTF to VTCO thresholds. If the battery temperature is outside of this range, the controller suspends
charge and the safety timer and waits until the battery temperature is within the VLTF to VHTF range. If the battery
temperature is between the VLTF and VCOOL thresholds or between the VHTF and VWARM thresholds, charge is
automatically reduced to ICHARGE/8. To avoid early termination during COOL/WARM condition, set ITERM ≤
ICHARGE/10. The controller suspends charge by turning off the PWM charge FETs. Figure 11 and Figure 12
summarize the operation.
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Feature Description (continued)
TEMPERATURE RANGE TO
INITIATE CHARGE
TEMPERATURE RANGE
DURING A CHARGE CYCLE
VREF
VREF
CHARGE SUSPENDED
CHARGE SUSPENDED
VLTF
VLTF_HYS
VLTF
CHARGE at ICHARGE/8
VCOOL
CHARGE at ICHARGE/8
VCOOL
VCOOL_HYS
CHARGE at ICHARGE
CHARGE at ICHARGE
VWARM
VWARM_HYS
VWARM
CHARGE at ICHARGE/8
CHARGE at ICHARGE/8
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
GND
GND
Figure 11. TS, Thermistor Sense Thresholds
Programmed
Charge Current
ICHARGE/8
Charge
Charge
Suspended
ICHARGEG/8
Charge
Charge
Current
Charge at ICHG
Charge
Suspended
(ICHARGE)
1/8 x Programmed
Charge Current
(ICHARGE/8)
VLTF VCOOL
VWARM VHTF/VTCO Temperature
Figure 12. Typical Charge Current vs Temperature Profile
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 17, the values of RT1 and RT2 can
be determined by using Equation 5 and Equation 6:
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Feature Description (continued)
æ 1
ö
1
VVREF ´ RTHCOOL ´ RTHWARM ´ ç
÷
VCOOL
VWARM ø
è
RT2 =
æV
ö
æ V
ö
RTHWARM ´ ç VREF - 1÷ - RTHCOOL ´ ç VREF - 1÷
V
V
è WARM
ø
è COOL
ø
(5)
VVREF
-1
VCOOL
RT1 =
1
1
+
RT2
RTHCOOL
(6)
VREF
bq24620
RT1
TS
RT2
RTH
103AT
Figure 13. TS Resistor Network
For example, a 103AT NTC thermistor is used to monitor the battery pack temperature. Select TCOOL = 0ºC,
TWARM = 60ºC. From the calculation and selecting a standard 5% resistor value, we can get RT1 = 2.2 kΩ, RT2 =
6.8 kΩ, and TCOLD is –17ºC (target –20ºC); THOT is 77ºC (target 75ºC), and TCUT-OFF is 86ºC (target 80ºC). A small
RC filter is suggested to protect the TS pin from system-level ESD.
8.3.17 Timer Fault Recovery
The bq24620 provides a recovery method to deal with timer fault conditions. The following summarizes this
method:
Condition 1: The battery voltage is above the recharge threshold and a time-out fault occurs.
Recovery Method: The timer fault clears when the battery voltage falls below the recharge threshold, and
battery detection begins. Taking CE low, or a POR condition, also clears the fault.
Condition 2: The battery voltage is below the RECHARGE threshold and a time-out fault occurs.
Recovery Method: Under this scenario, the bq24620 applies the IFAULT current to the battery. This small
current is used to detect a battery removal condition and remains on as long as the battery voltage stays below
the recharge threshold. If the battery voltage goes above the recharge threshold, the bq24620 disables the fault
current and executes the recovery method described in Condition 1. Taking CE low, or a POR condition, also
clears the fault.
8.3.18
PG Output
The open-drain PG (power good) indicates whether the VCC voltage is valid or not. The open-drain FET turns on
whenever the bq24620 has a valid VCC input (not in UVLO or ACOV or SLEEP mode). The PG pin can be used
to drive an LED or communicate with the host processor.
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Feature Description (continued)
8.3.19 CE (Charge Enable)
The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables
charge, provided all the other conditions for charge are met (see Enable and Disable Charging). A high-to-low
transition on this pin also resets all timers and fault conditions. There is an internal 1-MΩ pulldown resistor on the
CE pin, so if CE is floated, the charge does not turn on.
8.3.20 Charge Status Outputs
The open-drain STAT outputs indicate various charger operations as shown in Table 2. These status pins can be
used to drive LEDs or communicate with the host processor. OFF indicates that the open-drain transistor is
turned off.
Table 2. Stat Pin Definition For Bq24620
CHARGE STATE
STAT
Charge in progress
ON
Charge complete (PG = LOW)
OFF
Sleep mode (PG = HIGH)
OFF
Charge suspend, timer fault, ACOV, battery absent
BLINK (0.5 Hz)
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8.3.21 Battery Detection
For applications with removable battery packs, the bq24620 provides a battery-absent detection scheme to
reliably detect insertion or removal of battery packs. CE must be HIGH to enable battery detection function.
POR or RECHARGE
The battery detection routine runs on
power up, or if VFB falls below VRECH
due to removing a battery or
discharging a battery
Apply 8-mA discharge
current, start 1-s timer
VFB < VLOWV
No
1-s timer
expired
Yes
No
Yes
Battery Present,
Begin Charge
Disable 8-mA
discharge current
Enable 125-mA Charge,
Start 0.5-s timer
VFB > VRECH
No
0.5-s timer
expired
Yes
Yes
Disable 125-mA
Charge
No
Battery Present,
Begin Charge
Battery Absent
Figure 14. Battery Detection Flow Chart
Once the device has powered up, an 8-mA discharge current is applied to the SRN terminal. If the battery
voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is
turned on at low charge current (125 mA). If the battery voltage rises above the recharge threshold within 500
ms, no battery is present and the cycle restarts. If either the 500-ms or 1-second timer times out before the
respective thresholds are hit, a battery is detected and a charge cycle is initiated. See Maximum Output
Capacitance for more information.
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Battery not Detected
V REG
V RECH
Battery
Inserted
V LOWV
Battery Detected
t LOWV_ DEG
tWAKE
t RECH _ DEG
Figure 15. Battery-Detect Timing Diagram
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8.4 Device Functional Modes
Figure 16. Device Operational Flow Chart
22
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq24620 battery charger is ideal for high current charging (up to 10 A) and can charge battery packs
consisting of single cells or multiple cells in series. The bq24620EVM evaluation module is a complete charge
module for evaluating the bq24620. The application curves were taken using the bq24620EVM. Refer to the EVM
user's guide (SLUU410) for EVM information.
9.2 Typical Application
ADAPTER +
C2
2.2 µF
D2
MBRS540T3
C8
10 µF
R6
10 W
VREF
HIDRV
VCC
C7
1 µF
R7
100 kW
Q4
SiR426
PH
R8
22.1 kW
L1
BTST
ISET
REGN
VREF
D1
BAT54
C6
0.1 µF
bq24620
D3
ADAPTER +
LODRV
STAT
C10
0.1 µF
GND
R14 10 kW
D4
PG
SRP
VREF
R9
9.31 kW
TS
R10
430 kW
PACK+
C13
C12
10 µF* 10 µF*
C11
0.1 µF
R2
900 kW
Cff
22 pF
R1
100 kW
SRN
R5
100 W
VBAT
PACK-
Q5
SiR426
CE
R13 10 kW
RSR
0.010 Ω
8.2 µH*
C5
1 µF
C4
1 µF
Pack
Thermistor
Sense
C9
10 µF
N
R11
2W
N
ADAPTER -
VFB
PwrPad
0.1 μF
NOTE: VIN = 28 V, BAT = 5-cell Li-Phosphate, Icharge = 3 A, Iprecharge = 0.125 A, Iterm = 0.3 A
Figure 17. Typical System Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
DESIGN PARAMETER
AC adapter voltage (VIN)
EXAMPLE VALUE
28 V
Battery charge voltage (number of cells in series)
Battery charge current (during constant current phase)
Precharge current
18 V (5 cells)
3A
0.125 A
Termination current
0.3 A
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9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The bq24620 has a 300-kHz switching frequency to allow the use of small inductor and capacitor values.
Inductor saturation current must be higher than the charging current (ICHARGE) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE
(7)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fS) and
inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
fS ´ L
(8)
The maximum inductor ripple current happens with D = 0.5. For example, the battery-charging voltage range is
from 2.8 V to 14.4 V for a four-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives the
maximum inductor ripple current.
Usually, inductor ripple is designed in the range of 20%–40% of maximum charging current as a trade-off
between inductor size and efficiency for a practical design.
The bq24620 has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the charging-current
sensing resistor to prevent negative inductor current. The typical UCP threshold is 5 mV falling edge,
corresponding to 0.5-A falling edge for a 10-mΩ charging-current-sensing resistor.
9.2.2.2 Input Capacitor
The input capacitor must have enough ripple current rating to absorb input switching-ripple current. The worstcase RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate
at 50% duty cycle, then the worst-case capacitor RMS current ICIN occurs where the duty cycle is closest to 50%
and can be estimated by the following equation:
ICIN = ICHG ´
D ´ (1 - D)
(9)
A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input-decoupling capacitor and must be
placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The
voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V rating or higher
capacitor is preferred for 20-V input voltage. A 20-µF capacitor is suggested for typical of 3-A to 4-A charging
current.
9.2.2.3 Output Capacitor
The output capacitor also must have enough ripple current rating to absorb the output switching-ripple current.
The output capacitor RMS current ICOUT is given:
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3
(10)
The output capacitor voltage ripple can be calculated as follows:
DVo =
1
8LCfs
2
æ
V 2
ç VBAT - BAT
ç
VIN
è
ö
÷
÷
ø
(11)
At certain input and output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The bq24620 has an internal loop compensator. To get good loop stability, the resonant frequency of the output
inductor and output capacitor must be designed from 10 kHz to 15 kHz. The preferred ceramic capacitor is 25 V,
X7R, or X5R for 4-cell applications.
24
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9.2.2.4 Power MOSFET Selection
Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6 V of gate drive voltage. 30-V or higher voltage rating MOSFETs are
preferred for 20-V input voltage, and 40-V MOSFETs are preferred for 20-V to 28-V input voltage.
Figure-of-merit (FOM) is usually used for selecting the proper MOSFET, based on a tradeoff between the
conduction loss and switching loss. For the top-side MOSFET, FOM is defined as the product of the MOSFET
ON-resistance, rDS(on), and the gate-to-drain charge, QGD. For the bottom-side MOSFET, FOM is defined as the
product of the MOSFET ON-resistance, rDS(on), and the total gate charge, QG.
FOM top = RDS(on) ´ QG D
FOMbottom = RDS(on) ´ QG
(12)
The lower the FOM value, the lower the total power loss. Usually lower rDS(on) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D =
VOUT/VIN), charging current (ICHARGE), MOSFET ON-resistance rDS(on)), input voltage (VIN), switching frequency
(fS), turnon time (ton), and turnoff time (toff):
1
Ptop = D ´ ICHG2 ´ RDS(on) +
´ VIN ´ ICHG ´ (t on + t off ) ´ fS
2
(13)
The first item represents the conduction loss. Usually MOSFET rDS(on) increases by 50% with 100ºC junction
temperature rise. The second term represents the switching loss. The MOSFET turnon and turnoff times are
given by:
Q
Q
ton = SW , t off = SW
Ion
Ioff
(14)
where Qsw is the switching charge, Ion is the turnon gate-driving current, and Ioff is the turnoff gate-driving current.
If the switching charge is not given in the MOSFET data sheet, it can be estimated by gate-to-drain charge (QGD)
and gate-to-source charge (QGS):
1
QSW = QGD +
´ QGS
2
(15)
Total gate-driving current can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total
turnon gate resistance (Ron), and turnoff gate resistance Roff) of the gate driver:
VREG N - Vplt
Vplt
Ion =
, Ioff =
Ron
Roff
(16)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
Pbottom = (1 - D) ´ ICHG 2 ´ RDS(on)
(17)
If the SRP–SRN voltage decreases below 5 mV (the charger is also forced into nonsynchronous mode when the
average SRP–SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result, all the freewheeling current goes through the body diode of the bottom-side MOSFET. The maximum
charging current in nonsynchronous mode can be up to 0.9 A (0.5 A typical) for a 10-mΩ charging-currentsensing resistor, considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or
body diode capable of carrying the maximum nonsynchronous mode charging current.
MOSFET gate-driver power loss contributes to the dominant losses on controller IC when the buck converter is
switching. Choosing a MOSFET with a small Qg_total reduces the IC power loss to avoid thermal shutdown.
PICLoss_driver = VIN × Qg_total × fs
where
•
Qg_total is the total gate charge for both upper and lower MOSFETs at 6-V VREGN
(18)
The VREF load current is another component of the VCC input current (do not overload VREF), where total IC
loss can be described by following equations:
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PVREF = (VIN - VVREF ) × IVREF
PICLOSS = PICLOSS _ driver + PVREF + PQuiescent
(19)
9.2.2.5 Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a secondorder system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the
IC. The input filter must be carefully designed and tested to prevent an overvoltage event on VCC pin.
There are several methods to damping or limiting the overvoltage spike during adapter hot plug-in. An electrolytic
capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC maximum pinvoltage rating. A high-current-capability TVS Zener diode can also limit the overvoltage level to an IC-safe level.
However, these two solutions may not have low cost or small size.
A cost-effective and small-size solution is shown in Figure 18. R1 and C1 comprise a damping RC network to
damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for
reverse voltage protection for the VCC pin (it can be the input Schottky diode or the body diode of the input
ACFET). C2 is a VCC pin-decoupling capacitor, and it must be placed as close as possible to the VCC pin. R2
and C2 form a damping RC network to further protect the IC from high-dv/dt and high-voltage spikes. The C2
value must be less than the C1 value so R1 can be dominant over the ESR of C1 to get enough damping effect
for hot plug-in. R1 and R2 packages must be sized to handle the inrush-current power loss according to the
resistor manufacturer’s data sheet. The filter component values always must be verified with the real application,
and minor adjustments may be needed to fit in the real application circuit.
D1
Adapter
connector
R1
2W
C1
2.2 mF
(2010)
R2 (1206)
4.7 -30W
VCC pin
C2
0.1-1 mF
Figure 18. Input Filter
9.2.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines
The bq24620 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant
frequency, fo, is approximately 10 kHz to 15 kHz per Equation 20:
1
fo =
2 p L o Co
(20)
Table 4 provides a summary of typical LC components for various charge currents
Table 4. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current
CHARGE CURRENT
Output inductor LO
2A
4A
6A
8A
10 A
8.2 μH
8.2 μH
5.6 μH
4.7 μH
4.7 μH
Output capacitor CO
20 μF
20 μF
20 μF
40 μF
40 μF
Sense resistor
10 mΩ
10 mΩ
10 mΩ
10 mΩ
10 mΩ
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Table 5. Component List for Typical System Circuit of Figure 17
PART DESIGNATOR
QTY
DESCRIPTION
Q4, Q5
2
N-channel MOSFET, 40 V, 30 A, PowerPAK SO-8, Vishay-Siliconix, SiR426DN
D1
1
Diode, dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C
D2
1
Schottky diode, 40 V, 5 A, SMC, ON Semiconductor, MBRS540T3
RSR
2
Sense resistor, 10 mΩ, 1%, 1 W, 2010, Vishay-Dale, WSL2010R0100F
L1
1
Inductor, 6.8 μH, 5.5 A, Vishay-Dale, IHLP2525CZ
C8, C9, C12, C13
4
Capacitor, ceramic, 10 μF, 35 V, 10%, X7R
C2
1
Capacitor, ceramic, 2.2 µF, 50 V, 10%, X7R
C4, C5
2
Capacitor, ceramic, 1 μF, 16 V, 10%, X7R
C7
1
Capacitor, ceramic, 1 µF, 50 V, 10%, X7R
C1, C6, C11
4
Capacitor, ceramic, 0.1 μF, 16 V, 10%, X7R
Cff
1
Capacitor, ceramic, 22 pF, 35 V, 10%, X7R
C10
1
Capacitor, ceramic, 0.1 μF, 50 V, 10%
R1, R7
2
Resistor, chip, 100 kΩ, 1/16 W, 0.5%
R2
1
Resistor, chip, 900 kΩ, 1/16 W, 0.5%
R8
1
Resistor, chip, 22.1 kΩ, 1/16 W, 0.5%
R9
1
Resistor, chip, 9.31 kΩ, 1/16 W, 1%
R10
1
Resistor, chip, 430 kΩ, 1/16 W, 1%
R11
1
Resistor, chip, 2 Ω, 1 W, 5%
R13, R14
2
Resistor, chip, 10 kΩ, 1/16 W, 5%
R5
1
Resistor, chip, 100 Ω, 1/16 W, 0.5%
R6
1
Resistor, chip, 10 Ω, 1 W, 5%
D3, D4
2
LED diode, green, 2.1 V, 10 mΩ, Vishay-Dale, WSL2010R0100F
9.2.2.7 Maximum Output Capacitance
Care must be taken that the total output capacitance at the battery node is not so large that the discharge current
source cannot pull the voltage below the LOWV threshold during the 1-second discharge time. The maximum
output capacitance can be calculated as seen in Equation 21:
´ tDISCH
I
CMAX = DISCH
é R ù
1.425 ´ ê1+ 2 ú
ë R1 û
where
•
•
•
•
CMAX is the maximum output capacitance.
IDISCH is the discharge current.
tDISCH is the discharge time.
R2 and R1 are the voltage feedback resistors from the battery to the VFB pin.
(21)
The 1.425 factor is the difference between the RECHARGE and the LOWV thresholds at the VFB pin.
EXAMPLE
For a 3-cell Li+ charger, with R2 = 500 kΩ, R1 = 100 kΩ (giving 10.8 V for voltage regulation), IDISCH = 8 mA,
tDISCH = 1 second,
CMAX =
8mA ´ 1sec
= 930 mF
é 500k ù
1.425 ´ ê1+
ú
ë 100k û
(22)
Based on these calculations, no more than 930 μF should be allowed on the battery node for proper operation of
the battery detection circuit.
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9.2.3 Application Curves
VIN: 28 V
VBAT: 16 V
ICHG = 3 A
VIN: 28 V
Figure 19. Continuous Conduction Mode
28
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VBAT: 16 V
ICHG = 3 A
Figure 20. Battery Charging Soft Start
(by Asserting CE Low to High)
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10 Power Supply Recommendations
For proper operation of bq24620, VCC must be from 5 V to 28 V. To begin charging, VCC must be higher than
SRN by at least 500 mV (otherwise, the device will be in sleep mode). TI recommends an input voltage of at
least 1.5 V to 2 V higher than the battery voltage, taking into consideration the DC losses in the high-side FET
(Rdson), inductor (DCR), the input diode drop, and battery sense resistor (between SRP and SRN). Power limit
for the input supply must be greater than the maximum power required for battery charging.
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times must be minimized for minimum switching loss. Proper layout of the
components to minimize the high-frequency current-path loop (see Figure 21) is important to prevent electrical
and magnetic field radiation and high-frequency resonant problems. The following is a PCB layout priority list for
proper layout. Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to the switching MOSFET supply and ground connections, and
use the shortest possible copper trace connection. These parts should be placed on the same layer of the
PCB instead of on different layers, using vias to make this connection.
2. The IC must be placed close to the switching MOSFET gate terminals, keeping the gate-drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging-current-sensing resistor must be placed right next to the inductor output. Route the sense leads
connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop area),
and do not route the sense leads through a high-current path (see Figure 22 for Kelvin connection for best
current accuracy). Place the decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing-resistor output and ground.
6. The output capacitor ground connections must be tied to the same copper that connects to the input
capacitor ground before connecting to system ground.
7. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use the copper pour for analog
ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect analog ground to
GND. Connect the analog ground and power ground together using the thermal pad as the single ground
connection point, or use a 0-Ω resistor to tie analog ground to power ground (the thermal pad should tie to
analog ground in this case). A star-connection under the thermal pad is highly recommended.
8. It is critical to solder the exposed thermal pad on the back of the IC package to the PCB ground. Ensure that
there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers.
9. Place decoupling capacitors next to the IC pins to make trace connections as short as possible.
10. All via sizes and numbers must be enough for a given current path.
See the EVM design (SLUU410) for the recommended component placement with trace and via locations.
For QFN information, see SCBA017 and SLUA271.
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11.2 Layout Example
SW
L1
V BAT
R1
High
Frequency
VIN
BAT
Current
C1
Path
PGND
C2
C3
Figure 21. High-Frequency Current Path
Current Direction
R SNS
Current Sensing Direction
To SRP - SRN pin
Figure 22. Sensing Resistor PCB Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation, see the following:
• bq24600/20/40 EVM (HPA421) Multi Cell Synchronous Switch-Mode Charger, SLUU410
• Quad Flatpack No-Lead Logic Packages, SCBA017
• QFN/SON PCB Attachment, SLUA271
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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7-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24620RVAR
ACTIVE
VQFN
RVA
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAR
BQ24620RVAT
ACTIVE
VQFN
RVA
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24620RVAR
VQFN
RVA
16
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
BQ24620RVAT
VQFN
RVA
16
250
180.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24620RVAR
VQFN
RVA
16
3000
367.0
367.0
35.0
BQ24620RVAT
VQFN
RVA
16
250
210.0
185.0
35.0
Pack Materials-Page 2
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