STM32F102x4 STM32F102x6

STM32F102x4 STM32F102x6
STM32F102x4
STM32F102x6
Low-density USB access line, ARM-based 32-bit MCU with
16/32 KB Flash, USB FS, 5 timers, ADC & 5 com. interfaces
Datasheet - production data
Features
• Core: ARM 32-bit Cortex™-M3 CPU
– 48 MHz maximum frequency,
1.25 DMIPS/MHz (Dhrystone 2.1)
performance at 0 WS memory access
– Single-cycle multiplication and hardware
division
• Memories
– 16 or 32 Kbytes of Flash memory
– 4 or 6 Kbytes of SRAM
• Clock, reset and supply management
– 2.0 to 3.6 V application supply and I/Os
– POR, PDR and programmable voltage
detector (PVD)
– 4-to-16 MHz crystal oscillator
– Internal 8 MHz factory-trimmed RC
– Internal 40 kHz RC
– PLL for CPU clock
– 32 kHz oscillator for RTC with calibration
• Low power
– Sleep, Stop and Standby modes
– VBAT supply for RTC and backup registers
• Debug mode
– Serial wire debug (SWD) and JTAG
interfaces
LQFP64
10 × 10 mm
• Up to 5 timers
– Two 16-bit timers, each with up to 4
IC/OC/PWM or pulse counter
– 2 watchdog timers (Independent and
Window)
– SysTick timer: 24-bit downcounter
• Up to 5 communication interfaces
– One I2C interface (SMBus/PMBus)
– Two USARTs (ISO 7816 interface, LIN,
IrDA capability, modem control)
– One SPI (12 Mbit/s)
– One USB 2.0 full speed interface
• CRC calculation unit, 96-bit unique ID
• ECOPACK® packages
Table 1. Device summary
Reference
• DMA
– 7-channel DMA controller
– Peripherals supported: timers, ADC, SPIs,
I2Cs and USARTs
LQFP48
7 × 7 mm
Part number
STM32F102x4
STM32F102C4, STM32F102R4
STM32F102x6
STM32F102C6, STM32F102R6
• 1 × 12-bit, 1.2 µs A/D converter (up to 16
channels)
– Conversion range: 0 to 3.6 V
– Temperature sensor
• Up to 51 fast I/O ports
– 37/51 I/Os all mappable on 16 external
interrupt vectors and almost all 5 V-tolerant
August 2013
This is information on a product in full production.
DocID15057 Rev 4
1/77
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Contents
STM32F102x4, STM32F102x6
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2
Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1
2/77
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.2
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 29
5.3.3
Embedded reset and power control block characteristics . . . . . . . . . . . 30
5.3.4
Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.5
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
5.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5.3.11
Absolute maximum ratings (electrical sensitivity) . . . . . . . . . . . . . . . . . 48
5.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
DocID15057 Rev 4
STM32F102x4, STM32F102x6
6
Contents
5.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3.15
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.16
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.17
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.18
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.1
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
6.2
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.1
Evaluating the maximum junction temperature for an application . . . . . 73
7
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DocID15057 Rev 4
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3
List of tables
STM32F102x4, STM32F102x6
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F102x4 and STM32F102x6 low-density USB access line features
and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STM32F102xx USB access line family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Low-density STM32F102xx pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 30
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Maximum current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum current consumption in Run mode, code with data processing
running from RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Maximum current consumption in Sleep mode, code running from Flash or RAM. . . . . . . 34
Typical and maximum current consumptions in Stop and Standby modes . . . . . . . . . . . . 34
Typical current consumption in Run mode, code with data processing
running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 38
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
HSE 4-16 MHz oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SCL frequency (fPCLK1= 36 MHz, VDD_I2C = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
USB: Full speed electrical characteristics of the driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
DocID15057 Rev 4
STM32F102x4, STM32F102x6
Table 45.
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
List of tables
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RAIN max for fADC = 12 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ADC accuracy - limited test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data . . . . . . . . . 69
LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data . . . . . . . . . . . 71
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DocID15057 Rev 4
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List of figures
STM32F102x4, STM32F102x6
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
6/77
STM32F102T8 medium-density USB access line block diagram . . . . . . . . . . . . . . . . . . . 10
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
STM32F102xx medium-density USB access line LQFP48 pinout . . . . . . . . . . . . . . . . . . . 19
STM32F102xx medium-density USB access line LQFP64 pinout . . . . . . . . . . . . . . . . . . . 19
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals enabled. . . . . . . . . . . . . . . . . . 33
Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals disabled . . . . . . . . . . . . . . . . . 33
Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and
3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Standard I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Standard I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5 V tolerant I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5 V tolerant I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
I2C bus AC waveforms and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
SPI timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SPI timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Power supply and reference decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
LQFP64 – 10 x 10 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 68
LQFP64 recommended footprint dimensions(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . 70
LQFP48 recommended footprint dimensions(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
LQFP64 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
DocID15057 Rev 4
STM32F102x4, STM32F102x6
1
Introduction
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
STM32F102x4 and STM32F102x6 low-density USB access line microcontrollers. For more
details on the whole STMicroelectronics STM32F102xx family, please refer to Section 2.2:
Full compatibility throughout the family.
The medium-density STM32F102xx datasheet should be read in conjunction with the low-,
medium- and high-density STM32F10xxx reference manual.
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM32F10xxx Flash programming manual.
The reference and Flash programming manuals are both available from the
STMicroelectronics website www.st.com.
For information on the Cortex™-M3 core please refer to the Cortex™-M3 Technical
Reference Manual, available from the www.arm.com website at the following address:
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0337e/.
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Description
2
STM32F102x4, STM32F102x6
Description
The STM32F102xx medium-density USB access line incorporates the high-performance
ARM Cortex™-M3 32-bit RISC core operating at a 48 MHz frequency, high-speed
embedded memories (Flash memory of 16 or 32 Kbytes and SRAM of 4 or 6 Kbytes), and
an extensive range of enhanced peripherals and I/Os connected to two APB buses. All
devices offer standard communication interfaces (one I2C, one SPI, one USB and two
USARTs), one 12-bit ADC and two general-purpose 16-bit timers.
The STM32F102xx family operates in the –40 to +85 °C temperature range, from a 2.0 to
3.6 V power supply. A comprehensive set of power-saving mode allows the design of lowpower applications.
The STM32F102xx medium-density USB access line is delivered in the LQFP48 7 × 7 mm
and LQFP64 10 × 10 mm packages.
The STM32F102xx medium-density USB access line microcontrollers are suitable for a
wide range of applications.
•
Application control and user interface
•
Medical and handheld equipment
•
PC peripherals, gaming and GPS platforms
•
Industrial applications: PLC, inverters, printers, and scanners
•
Alarm systems, Video intercom, and HVAC
Figure 1 shows the general block diagram of the device family.
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STM32F102x4, STM32F102x6
2.1
Description
Device overview
Table 2. STM32F102x4 and STM32F102x6 low-density USB access line features
and peripheral counts
Peripheral
STM32F102Cx
STM32F102Rx
Flash - Kbytes
16
32
16
32
SRAM - Kbytes
4
6
4
6
General-purpose
2
2
2
2
SPI
1
1
1
1
I2C
1
1
1
1
USART
2
2
2
2
USB
1
1
1
1
Timers
Communication
interfaces
12-bit synchronized ADC
number of channels
1
10 channels
1
16 channels
37
51
GPIOs
CPU frequency
48 MHz
Operating voltage
Operating temperatures
Packages
2.0 to 3.6 V
Ambient temperature: –40 to +85 °C (see Table 8)
Junction temperature: –40 to +105 °C (see Table 8)
LQFP48
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Description
STM32F102x4, STM32F102x6
Figure 1. STM32F102T8 medium-density USB access line block diagram
TPIU
SW/JTAG
Trace/trig
SWD
Trace
Controller
ont
pbus
Ibus
Cortex M3 CPU
Fmax: 48 MHz
NVIC
Dbus
NVIC
Syst em
AHB: Fmax =48 MHz
7 channels
SUPPLY
SUPERVISION
NRST
VDDA
VSSA
POR / PDR
Rst
@VDD
PLL &
CLOCK
MANAGT
XTAL OSC
4-16 MHz
IWDG
Stand by
in terface
@VDDA
RTC
AWU
AHB2
APB 1
GPIOB
PC[15:0]
GPIOC
PD[2:0]
GPIOD
MOSI,MISO,
SCK,NSS as AF
SPI
USART1
@VDDA
Backup
reg
OSC32_IN
OSC32_OUT
TAMPER-RTC
Backup interface
APB 1: Fmax = 24 MHz
PB[ 15:0]
VBAT
@VBAT
APB2 : Fmax = 48 MHz
GPIOA
OSC_IN
OSC_OUT
RC 8 MHz
RC 40 kHz
EXTI
WAKEUP
PA[ 15:1]
16AF
PCLK1
PCLK 2
HCLK
FCLK
VDD = 2 to 3.6 V
VSS
@VDD
64 bit
Int
AHB2
APB2
RX,TX, CTS, RTS,
Smart Card as AF
Flash 32 KB
XTAL 32 kHz
PVD
51AF
VOLT. REG.
3.3 V to 1.8 V
SRAM
6 KB
GP DMA
@VDDA
POWER
Flash obl
Inte rface
JNTRST
JTDI
JTCK/SWCLK
JTMS/SWDIO
JTDO
as AF
BusM atrix
TRACECLK
TRACED[0:3]
as AS
TIM2
4 Chann els
TIM3
4 Chann els
USART2
I2C
USB 2.0 FS
RX,TX, CTS, RTS,
CK, SmartCard as AF
SCL,SDA,SMBA L
as AF
USBDP, USBDM as AF
WWDG
12bit ADC1 IF
Temp sen so r
ai15452b
1. AF = alternate function on I/O port pin.
2. TA = –40 °C to +85 °C (junction temperature up to 105 °C).
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STM32F102x4, STM32F102x6
Description
Figure 2. Clock tree
To Flash prog. if FLITFCLK
8 MHz
HSI RC
HSI
USB
Prescaler
/1, 1.5
/2
USBCLK
to USB interface
48 MHz
HCLK
to AHB bus, core,
memory and DMA
48 MHz max
PLLSRC
/8
SW
PLLMUL
HSI
..., x16
x2, x3, x4
PLL
SYSCLK
AHB
Prescaler
48 MHz
/1, 2..512
max
PLLCLK
Clock
Enable (3 bits)
APB1
Prescaler
/1, 2, 4, 8, 16
to Cortex System timer
FCLK Cortex
free running clock
24 MHz max
PCLK1
to APB1
peripherals
Peripheral Clock
HSE
Enable (13 bits)
to TIM2, TIM3
TIM2, TIM3
If (APB1 prescaler =1) x1
TIMXCLK
else
x2 Peripheral Clock
CSS
Enable (2 bits)
APB2
Prescaler
/1, 2, 4, 8, 16
PLLXTPRE
OSC_OUT
OSC_IN
4-16 MHz
48 MHz max
HSE OSC
Peripheral Clock
Enable (11 bits)
/2
ADC
Prescaler
/2, 4, 6, 8
/128
OSC32_IN
OSC32_OUT
PCLK2
to APB2
peripherals
LSE OSC
32.768 kHz
to ADC
ADCCLK
to RTC
LSE
RTCCLK
RTCSEL[1:0]
LSI RC
40 kHz
to Independent Watchdog (IWDG)
LSI
IWDGCLK
Main
Clock Output
/2
MCO
PLLCLK
HSI
Legend:
HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
LSE = low-speed external clock signal
HSE
SYSCLK
MCO
ai15455b
1. For the USB function to be available, both HSE and PLL must be enabled, with the USB clock output
(USBCLK) at 48 MHz.
2. To have an ADC conversion time of 1.2 µs, APB2 must be at 12 MHz, 24 MHz or 48 MHz.
3. The Flash memory programming interface clock (FLITFCLK) is always the HSI clock.
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2.2
STM32F102x4, STM32F102x6
Full compatibility throughout the family
The STM32F102xx is a complete family whose members are fully pin-to-pin, software and
feature compatible. In the reference manual, the STM32F102x4 and STM32F102x6 are
referred to as low-density devices and the STM32F102x8 and STM32F102xB are referred
to as medium-density devices.
Low-density devices are an extension of the STM32F102x8/B devices, they are specified in
the STM32F102x4/6 datasheet. Low-density devices feature lower Flash memory and RAM
capacities, a timer and a few communication interfaces less.
The STM32F102x4 and STM32F102x6 are a drop-in replacement for the STM32F102x8/B
medium-density devices, allowing the user to try different memory densities and providing a
greater degree of freedom during the development cycle.
Moreover the STM32F102xx family is fully compatible with all existing STM32F101xx
access line and STM32F103xx performance line devices.
Table 3. STM32F102xx USB access line family
Low-density STM32F102xx devices
Pinout
64
48
36
Medium-density STM32F102xx devices
16 KB Flash
32 KB Flash(1)
64 KB Flash
128 KB Flash
4 KB RAM
6 KB RAM
10 KB RAM
16 KB RAM
2 × USARTs, 2 × 16-bit timers
1 × SPI, 1 × I2C, 1 × ADC, 1 × USB
-
-
3 × USARTs, 3 × 16-bit timers
2 × SPIs, 2 × I2Cs, 1 × ADC, 1 × USB
2 × USARTs, 3 × 16bit timers
1× SPI, 1× I2C, 1 ×
ADC, 1 × USB
-
1. For orderable part numbers that do not show the A internal code after the temperature range code (6), the
reference datasheet for electrical characteristics is that of the STM32F102x8/B medium-density devices.
2.3
Overview
ARM® Cortex™-M3 core with embedded Flash and SRAM
The ARM Cortex™-M3 processor is the latest generation of ARM processors for embedded
systems. It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM Cortex™-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
The STM32F102xx medium-density USB access line having an embedded ARM core, is
therefore compatible with all ARM tools and software.
Embedded Flash memory
16 or 32 Kbytes of embedded Flash is available for storing programs and data.
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STM32F102x4, STM32F102x6
Description
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
Embedded SRAM
4 or 6 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states.
Nested vectored interrupt controller (NVIC)
The STM32F102xx medium-density USB access line embeds a nested vectored interrupt
controller able to handle up to 36 maskable interrupt channels (not including the 16 interrupt
lines of Cortex™-M3) and 16 priority levels.
•
Closely coupled NVIC gives low latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving higher priority interrupts
•
Support for tail-chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 19 edge detectors lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect external line with pulse
width lower than the Internal APB2 clock period. Up to 51 GPIOs are connected to the 16
external interrupt lines.
Clocks and startup
System clock selection is performed on startup, however the internal RC 8 MHz oscillator is
selected as default CPU clock on reset. An external 4-16 MHz clock can be selected, in
which case it is monitored for failure. If failure is detected, the system automatically switches
back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full
interrupt management of the PLL clock entry is available when necessary (for example on
failure of an indirectly used external crystal, resonator or oscillator).
Several prescalers allow the configuration of the AHB frequency, the High Speed APB
(APB2) and the low Speed APB (APB1) domains. The maximum frequency of the AHB and
the APB domains is 48 MHz. See Figure 2 for details on the clock tree.
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STM32F102x4, STM32F102x6
Boot modes
At startup, boot pins are used to select one of five boot options:
•
Boot from User Flash
•
Boot from System Memory
•
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
•
VDD = 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
•
VSSA, VDDA = 2.0 to 3.6 V: External analog power supplies for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used).
VDDA and VSSA must be connected to VDD and VSS, respectively.
•
VBAT = 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
For more details on how to connect power pins, refer to Figure 8: Power supply scheme.
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
Refer to Table 11: Embedded reset and power control block characteristics for the values of
VPOR/PDR and VPVD.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
•
MR is used in the nominal regulation mode (Run)
•
LPR is used in the Stop mode
•
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
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STM32F102x4, STM32F102x6
Description
Low-power modes
The STM32F102xx medium-density USB access line supports three low-power modes to
achieve the best compromise between low power consumption, short startup time and
available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
The Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
either in normal or in low power mode.
The device can be woken up from Stop mode by any of the EXTI line. The EXTI line
source can be one of the 16 external lines, the PVD output or the RTC alarm.
•
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.8 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
Standby mode, SRAM and registers content are lost except for registers in the Backup
domain and Standby circuitry.
The device exits Standby mode when an external reset (NRST pin), a IWDG reset, a
rising edge on the WKUP pin, or an RTC alarm occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped by entering Stop
or Standby mode.
DMA
The flexible 7-channel general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with support for software
trigger on each channel. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general purpose timers
TIMx and ADC.
RTC (real-time clock) and backup registers
The RTC and the backup registers are supplied through a switch that takes power either on
VDD supply when present or through the VBAT pin. The backup registers are ten 16-bit
registers used to store 20 bytes of user application data when VDD power is not present.
The real-time clock provides a set of continuously running counters which can be used with
suitable software to provide a clock calendar function, and provides an alarm interrupt and a
periodic interrupt. It is clocked by a 32.768 kHz external crystal, resonator or oscillator, the
internal low power RC oscillator or the high-speed external clock divided by 128. The
internal low power RC has a typical frequency of 40 kHz. The RTC can be calibrated using
an external 512 Hz output to compensate for any natural crystal deviation. The RTC
features a 32-bit programmable counter for long term measurement using the Compare
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STM32F102x4, STM32F102x6
register to generate an alarm. A 20-bit prescaler is used for the time base clock and is by
default configured to generate a time base of 1 second from a clock at 32.768 kHz.
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 40 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used as a watchdog to
reset the device when a problem occurs, or as a free running timer for application timeout
management. It is hardware or software configurable through the option bytes. The counter
can be frozen in debug mode.
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
SysTick timer
This timer is dedicated for OS, but could also be used as a standard down counter. It
features:
•
A 24-bit down counter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0.
•
Programmable clock source
General-purpose timers (TIMx)
There are 2 synchronizable general-purpose timers embedded in the STM32F102xx
medium-density USB access line devices. These timers are based on a 16-bit auto-reload
up/down counter, a 16-bit prescaler and feature 4 independent channels each for input
capture, output compare, PWM or one-pulse mode output. This gives up to 12 input
captures / output compares / PWMs on the LQFP48 and LQFP64 packages.
The general-purpose timers can work together via the Timer Link feature for synchronization
or event chaining. Their counter can be frozen in debug mode.
Any of the general-purpose timers can be used to generate PWM outputs. They both have
independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
I²C bus
One I²C bus interface can operate in multi-master and slave modes. It can support standard
and fast modes. It supports dual slave addressing (7-bit only) and both 7/10-bit addressing
in master mode. A hardware CRC generation/verification is embedded.
The I2C interface can be served by DMA and they support SM Bus 2.0/PM Bus.
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STM32F102x4, STM32F102x6
Description
Universal synchronous/asynchronous receiver transmitter (USART)
The available USART interfaces communicate at up to 2.25 Mbit/s. They provide hardware
management of the CTS and RTS signals, support IrDA SIR ENDEC, are ISO 7816
compliant and have LIN Master/Slave capability.
The USART interfaces can be served by the DMA controller.
Serial peripheral interface (SPI)
The SPI is able to communicate up to 12 Mbit/s in slave and master modes in full-duplex
and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies
and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification
supports basic SD Card/MMC modes.
The SPI can be served by the DMA controller.
Universal serial bus (USB)
The STM32F102xx medium-density USB access line embeds an USB device peripheral
compatible with the USB Full-speed 12 Mbs. The USB interface implements a full-speed (12
Mbit/s) function interface. It has software configurable endpoint setting and suspend/resume
support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock
source must use a HSE crystal oscillator).
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
capable.
The I/Os alternate function configuration can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/Os registers.
ADC (analog to digital converter)
The 12-bit analog to digital converter has up to 16 external channels and performs
conversions in single-shot or scan modes. In scan mode, automatic conversion is performed
on a selected group of analog inputs.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all selected channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
Temperature sensor
The temperature sensor has to generate a a voltage that varies linearly with temperature.
The conversion range is between 2 V < VDDA < 3.6 V. The temperature sensor is internally
connected to the ADC_IN16 input channel which is used to convert the sensor output
voltage into a digital value.
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP Interface is embedded. and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
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Description
STM32F102x4, STM32F102x6
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a
specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
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STM32F102x4, STM32F102x6
Pinout and pin description
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PA15
PA14
Figure 3. STM32F102xx medium-density USB access line LQFP48 pinout
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
34
3
33
4
32
5
31
6
LQFP48
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 22 23 24
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PB15
PB14
PB13
PB12
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
VSSA
VDDA
PA0-WKUP
PA1
PA2
ai14378d
VDD_3
VSS_3
PB9
PB8
BOOT0
PB7
PB6
PB5
PB4
PB3
PD2
PC12
PC11
PC10
PA15
PA14
Figure 4. STM32F102xx medium-density USB access line LQFP64 pinout
VBAT
PC13-TAMPER-RTC
PC14-OSC32_IN
PC15-OSC32_OUT
PD0-OSC_IN
PD1-OSC_OUT
NRST
PC0
PC1
PC2
PC3
VSSA
VDDA
PA0-WKUP
PA1
PA2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
8
LQFP64
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
VDD_2
VSS_2
PA13
PA12
PA11
PA10
PA9
PA8
PC9
PC8
PC7
PC6
PB15
PB14
PB13
PB12
PA3
VSS_4
VDD_4
PA4
PA5
PA6
PA7
PC4
PC5
PB0
PB1
PB2
PB10
PB11
VSS_1
VDD_1
3
Pinout and pin description
ai14387c
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STM32F102x4, STM32F102x6
Table 4. Low-density STM32F102xx pin definitions
Alternate functions(3) (4)
1
1
VBAT
2
3
(5)
2
PC13-TAMPER-RTC
3
PC14-OSC32_IN(5)
(5)
Main
function(3)
(after reset)
Default
S
VBAT
I/O
PC13(6)
TAMPER-RTC
I/O
PC14(6)
OSC32_IN
I/O
PC15(6)
OSC32_OUT
Remap
4
4
5
5
OSC_IN
I/O
FT
OSC_IN
PD0(7)
6
6
OSC_OUT
I/O
FT
OSC_OUT
PD1(7)
7
7
NRST
I/O
NRST
-
8
PC0
I/O
PC0
ADC_IN10
-
9
PC1
I/O
PC1
ADC_IN11
-
10
PC2
I/O
PC2
ADC_IN12
-
11
PC3
I/O
PC3
ADC_IN13
8
12
VSSA
S
VSSA
9
13
VDDA
S
VDDA
10
14
PA0-WKUP
I/O
PA0
WKUP/USART2_CTS/
ADC_IN0/
TIM2_CH1_ETR(8)
11
15
PA1
I/O
PA1
USART2_RTS/
ADC_IN1/TIM2_CH2(8)
12
16
PA2
I/O
PA2
USART2_TX/
ADC_IN2/TIM2_CH3(8)
13
17
PA3
I/O
PA3
USART2_RX/
ADC_IN3/TIM2_CH4(8)
-
18
VSS_4
S
VSS_4
-
19
VDD_4
S
VDD_4
14
20
PA4
I/O
PA4
SPI_NSS(8)/ADC_IN4
USART2_CK/
15
21
PA5
I/O
PA5
SPI_SCK(8)/ADC_IN5
16
22
PA6
I/O
PA6
SPI_MISO(8)/ADC_IN6/
TIM3_CH1(8)
17
23
PA7
I/O
PA7
SPI_MOSI(8)/ADC_IN7/
TIM3_CH2(8)
-
24
PC4
I/O
PC4
ADC_IN14
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PC15-OSC32_OUT
I / O level(2)
LQFP64
Pin name
Type(1)
LQFP48
Pins
DocID15057 Rev 4
STM32F102x4, STM32F102x6
Pinout and pin description
Table 4. Low-density STM32F102xx pin definitions (continued)
Alternate functions(3) (4)
I / O level(2)
Default
LQFP64
Main
function(3)
(after reset)
LQFP48
Type(1)
Pins
Pin name
-
25
PC5
I/O
PC5
ADC_IN15
18
26
PB0
I/O
PB0
ADC_IN8/TIM3_CH3(8)
19
27
PB1
I/O
PB1
ADC_IN9/TIM3_CH4(8)
20
28
PB2
I/O
FT
PB2/BOOT1
21
29
PB10
I/O
FT
PB10
(8)
TIM2_CH3
PB11
(8)
TIM2_CH4
FT
Remap
22
30
PB11
I/O
23
31
VSS_1
S
VSS_1
24
32
VDD_1
S
VDD_1
25
33
PB12
I/O
FT
PB12
26
34
PB13
I/O
FT
PB13
27
35
PB14
I/O
FT
PB14
28
36
PB15
I/O
FT
PB15
-
37
PC6
I/O
FT
PC6
TIM3_CH1
-
38
PC7
I/O
FT
PC7
TIM3_CH2
-
39
PC8
I/O
FT
PC8
TIM3_CH3
-
40
PC9
I/O
FT
PC9
TIM3_CH4
29
41
PA8
I/O
FT
PA8
USART1_CK/MCO
30
42
PA9
I/O
FT
PA9
USART1_TX(8)
31
43
PA10
I/O
FT
PA10
USART1_RX(8)
32
44
PA11
I/O
FT
PA11
USART1_CTS/USB_DM
33
45
PA12
I/O
FT
PA12
USART1_RTS/USB_DP
34
46
PA13
I/O
FT
JTMSSWDIO
35
47
VSS_2
S
VSS_2
36
48
VDD_2
S
VDD_2
37
49
PA14
I/O
FT
JTCK/SWCL
K
PA14
38
50
PA15
I/O
FT
JTDI
TIM2_CH1_ETR
/ PA15
/SPI_NSS
DocID15057 Rev 4
(8)
PA13
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76
Pinout and pin description
STM32F102x4, STM32F102x6
Table 4. Low-density STM32F102xx pin definitions (continued)
Alternate functions(3) (4)
LQFP48
LQFP64
Pin name
Type(1)
I / O level(2)
Pins
Main
function(3)
(after reset)
-
51
PC10
I/O
FT
PC10
-
52
PC11
I/O
FT
PC11
-
53
PC12
I/O
FT
PC12
-
54
PD2
I/O
FT
PD2
39
55
PB3
I/O
FT
JTDO
TIM2_CH2/ PB3/
TRACESWO/
SPI_SCK
40
56
PB4
I/O
FT
JNTRST
TIM3_CH1 / PB4
SPI_MISO
41
57
PB5
I/O
42
58
PB6
I/O
43
59
PB7
I/O
44
60
BOOT0
I
45
61
PB8
I/O
FT
PB8
I2C_SCL
46
62
PB9
I/O
FT
PB9
I2C_SDA
47
63
VSS_3
S
VSS_3
48
64
VDD_3
S
VDD_3
Default
Remap
PB5
I2C_SMBA
TIM3_CH2 /
SPI_MOSI
FT
PB6
I2C_SCL(8)
USART1_TX
FT
PB7
I2C_SDA(8)
USART1_RX
BOOT0
1. I = input, O = output, S = supply.
2. FT= 5 V tolerant.
3. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower
number of peripherals that is included. For example, if a device has only one SPI, two USARTs and two timers, they will be
called SPI1, USART1 & USART2 and TIM2 & TIM 3, respectively. Refer to Table 3 on page 12.
4. If several peripherals share the same I/O pin, to avoid conflict between these alternate functions only one peripheral should
be enabled at a time through the peripheral clock enable bit (in the corresponding RCC peripheral clock enable register).
5. PC13, PC14 and PC15 are supplied through the power switch. Since the switch only sinks a limited amount of current (3
mA), the use of GPIOs PC13 to PC15 in output mode is limited: the speed should not exceed 2 MHz with a maximum load
of 30 pF and these IOs must not be used as a current source (e.g. to drive an LED).
6. Main function after the first backup domain power-up. Later on, it depends on the contents of the Backup registers even
after reset (because these registers are not reset by the main reset). For details on how to manage these IOs, refer to the
Battery backup domain and BKP register description sections in the STM32F102xx reference manual, available from the
STMicroelectronics website: www.st.com.
7. The pins number 5 and 6 in the LQFP48 package are configured as OSC_IN/OSC_OUT after reset, however the
functionality of PD0 and PD1 can be remapped by software on these pins. For more details, refer to the Alternate function
I/O and debug configuration section in the STM32F10xxx reference manual.
The use of PD0 and PD1 in output mode is limited as they can only be used at 50 MHz in output mode.
8. This alternate function can be remapped by software to some other port pins (if available on the used package). For more
details, refer to the Alternate function I/O and debug configuration section in the STM32F10xxx reference manual,
available from the STMicroelectronics website: www.st.com.
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STM32F102x4, STM32F102x6
4
Memory mapping
Memory mapping
The memory map is shown in Figure 5.
Figure 5. Memory map
APB memory space
0xFFFF FFFF
0xE010 0000
0xFFFF FFFF
0x4002 3400
7
0xE010 0000
0xE000 0000
0x4002 3000
0x4002 2400
Cortex-M3 internal
peripherals
6
0x4002 1400
reserved
0x4002 1000
RCC
0x4002 0400
reserved
0x4001 3800
0x4001 3400
0x4001 3000
0x4001 2C00
0xA000 0000
0x4001 2800
0x4001 2400
4
0x1FFF FFFF
0x4001 1800
reserved
0x1FFF F80F
0x8000 0000
Option Bytes
0x1FFF F800
3
System memory
0x1FFF F000
Port B
0x4001 0800
Port A
0x4001 0400
EXTI
0x4001 0000
AFIO
0x4000 6000
0x4000 5800
0x2000 17FF
0x2000 0000
0x4000 5400
0x4000 4800
0x4000 4400
SRAM
0x4000 3400
0x0800 FFFF
0
Flash memory
0x0000 0000
Reserved
ADC1
reserved
0x4001 0C00
0x4000 5C00
1
reserved
Port C
0x4000 6400
Peripherals
SPI
reserved
0x4001 1000
0x4000 6C00
reserved
USART1
reserved
Port D
0x4000 7000
2
DMA
reserved
0x4001 1400
0x4000 7400
0x6000 0000
reserved
0x4002 2000
0x4001 3C00
5
reserved
CRC
Flash interface
0x4002 0000
0xC000 0000
0x4000 0000
reserved
Cortex-M3 internal
peripherals
0xE000 0000
reserved
PWR
BKP
reserved
512 byte USB SRAM
USB registers
reserved
I2C
reserved
USART2
reserved
0x4000 3000
IWDG
0x4000 2C00
WWDG
0x4000 2800
RTC
0x0800 0000
0x4000 0800
reserved
Aliased to Flash or
system memory
depending on
0x0000 0000 BOOT pins
0x4000 0400
TIM3
0x4000 0000
TIM2
ai15454b
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76
Electrical characteristics
STM32F102x4, STM32F102x6
5
Electrical characteristics
5.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
5.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
5.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.3 V (for the
2 V ≤ VDD ≤ 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
5.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 6.
5.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 7.
24/77
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STM32F102x4, STM32F102x6
Electrical characteristics
Figure 6. Pin loading conditions
Figure 7. Pin input voltage
STM32F102 pin
STM32F102 pin
C = 50 pF
VIN
ai14973
ai14972
5.1.6
Power supply scheme
Figure 8. Power supply scheme
VBAT
GP I/Os
IN
VDD
VDD
VDD
1/2/3/4
Level shifter
OUT
3 × 100 nF
+ 1 × 4.7 µF
Backup circuitry
(OSC32K,RTC,
Wake-up logic
Backup registers)
Po wer swi tch
1.8-3.6 V
IO
Logic
Kernel logic
(CPU,
Digital
& Memories)
Regulator
VSS
1/2/3/4
VDDA
VREF+
10 nF
+ 1 µF
ADC
VREF-
Analog:
RCs, PLL,
...
VSSA
ai14882c
Caution:
In Figure 8, the 4.7 µF capacitor must be connected to VDD3.
DocID15057 Rev 4
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76
Electrical characteristics
5.1.7
STM32F102x4, STM32F102x6
Current consumption measurement
Figure 9. Current consumption measurement scheme
IDD_VBAT
VBAT
IDD
VDD
VDDA
ai14126
5.2
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 5: Voltage characteristics,
Table 6: Current characteristics, and Table 7: Thermal characteristics may cause permanent
damage to the device. These are stress ratings only and functional operation of the device
at these conditions is not implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Table 5. Voltage characteristics
Symbol
VDD − VSS
VIN(2)
|ΔVDDx|
|VSSX − VSS|
VESD(HBM)
Ratings
Min
Max
–0.3
4.0
Input voltage on five volt tolerant pin
VSS − 0.3
VDD + 4.0
Input voltage on any other pin
VSS − 0.3
4.0
External main supply voltage (including
VDDA and VDD)(1)
Variations between different VDD power pins
50
Variations between all the different ground
pins
50
Electrostatic discharge voltage (human body
model)
Unit
V
mV
see Section 5.3.11: Absolute
maximum ratings (electrical
sensitivity)
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table 6: Current characteristics for the maximum
allowed injected current values.
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STM32F102x4, STM32F102x6
Electrical characteristics
Table 6. Current characteristics
Symbol
IVDD
IVSS
IIO
IINJ(PIN) (2)
ΣIINJ(PIN)
Ratings
Max.
Total current into VDD/VDDA power lines (source)(1)
150
(1)
Total current out of VSS ground lines (sink)
150
Output current sunk by any I/O and control pin
25
− 25
Output current source by any I/Os and control pin
Injected current five volt tolerant pins
(3)
mA
−5/+0
(4)
±5
Injected current on any other pin
Total injected current (sum of all I/O and control pins)
Unit
(5)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. Negative injection disturbs the analog performance of the device. See Note: on page 66.
3. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5 for maximum allowed input voltage values.
4. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 5 for maximum allowed input voltage values.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 7. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
DocID15057 Rev 4
Value
Unit
–65 to +150
°C
150
°C
27/77
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Electrical characteristics
STM32F102x4, STM32F102x6
5.3
Operating conditions
5.3.1
General operating conditions
Table 8. General operating conditions
Symbol
Parameter
fHCLK
Min
Max
Internal AHB clock frequency
0
48
fPCLK1
Internal APB1 clock frequency
0
24
fPCLK2
Internal APB2 clock frequency
0
48
VDD
Standard operating voltage
2
3.6
2
3.6
2.4
3.6
–0.3
VDD+
0.3
2 V < VDD ≤ 3.6 V
–0.3
5.5
VDD = 2 V
–0.3
5.2
0
5.5
VDDA(1)
Analog operating voltage
(ADC not used)
Analog operating voltage
(ADC used)
Conditions
Must be the same potential
as VDD(2)
Standard IO
VIN
I/O input voltage
FTIO(3)
BOOT0
PD
TA
TJ
Power dissipation at TA =
85 °C(4)
Ambient temperature
LQFP48
363
LQFP64
444
Unit
MHz
V
V
mW
Maximu
m power
dissipati
on
–40
85
°C
Low
power
dissipati
on(5)
–40
105
°C
–40
105
°C
Junction temperature range
1. When the ADC is used, refer to Table 47: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and operation.
3. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Table 6.2: Thermal
characteristics on page 73).
5. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax
(see Table 6.2: Thermal characteristics on page 73).
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STM32F102x4, STM32F102x6
5.3.2
Electrical characteristics
Operating conditions at power-up / power-down
Subject to general operating conditions for TA.
Table 9. Operating conditions at power-up / power-down
Symbol
tVDD
Parameter
Conditions
Min
Max
VDD rise time rate
0
∞
VDD fall time rate
20
∞
DocID15057 Rev 4
Unit
µs/V
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Electrical characteristics
5.3.3
STM32F102x4, STM32F102x6
Embedded reset and power control block characteristics
The parameters given in Table 11 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
.
Table 10. Embedded reset and power control block characteristics
Symbol
VPVD
VPVDhyst(2)
Parameter
Conditions
Programmable voltage
detector level selection
Min
Typ
Max
Unit
PLS[2:0]=000 (rising edge)
2.1
2.18
2.26
V
PLS[2:0]=000 (falling edge)
2
2.08
2.16
V
PLS[2:0]=001 (rising edge)
2.19
2.28
2.37
V
PLS[2:0]=001 (falling edge)
2.09
2.18
2.27
V
PLS[2:0]=010 (rising edge)
2.28
2.38
2.48
V
PLS[2:0]=010 (falling edge)
2.18
2.28
2.38
V
PLS[2:0]=011 (rising edge)
2.38
2.48
2.58
V
PLS[2:0]=011 (falling edge)
2.28
2.38
2.48
V
PLS[2:0]=100 (rising edge)
2.47
2.58
2.69
V
PLS[2:0]=100 (falling edge)
2.37
2.48
2.59
V
PLS[2:0]=101 (rising edge)
2.57
2.68
2.79
V
PLS[2:0]=101 (falling edge)
2.47
2.58
2.69
V
PLS[2:0]=110 (rising edge)
2.66
2.78
2.9
V
PLS[2:0]=110 (falling edge)
2.56
2.68
2.8
V
PLS[2:0]=111 (rising edge)
2.76
2.88
3
V
PLS[2:0]=111 (falling edge)
2.66
2.78
2.9
V
PVD hysteresis
100
VPOR/PDR
Power on/power down
reset threshold
VPDRhyst
PDR hysteresis
mV
Falling edge
1.8
(1)
1.88
1.96
V
Rising edge
1.84
1.92
2.0
V
40
tRSTTEMPO(2) Reset temporization
1.5
2.5
mV
4.5
1. The product behavior is guaranteed by design down to the minimum VPOR/PDR value.
2. Guaranteed by design, not tested in production.
5.3.4
Embedded reference voltage
The parameters given in Table 12 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
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Electrical characteristics
Table 11. Embedded internal reference voltage
Symbol
VREFINT
Parameter
Internal reference voltage
TS_vrefint(1)
ADC sampling time when reading
the internal reference voltage
VRERINT(2)
Internal reference voltage spread
over the temperature range
TCoeff(2)
Conditions
Min
Typ
–40 °C < TA < +85 °C
1.16
1.20
1.24
V
5.1
17.1(2)
µs
10
mV
100
ppm/
°C
VDD = 3 V ±10 mV
Temperature coefficient
Max
Unit
1. Shortest sampling time can be determined in the application by multiple iterations.
2. Guaranteed by design, not tested in production.
5.3.5
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 9: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code.
Maximum current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in input mode with a static value at VDD or VSS (no load)
•
All peripherals are disabled except if it is explicitly mentioned
•
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz)
•
Prefetch in on (reminder: this bit must be set before clock setting and bus prescaling)
•
When the peripherals are enabled fPCLK1 = fHCLK/2, fPCLK2 = fHCLK
The parameters given in Table 13 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
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STM32F102x4, STM32F102x6
Table 12. Maximum current consumption in Run mode, code with data processing
running from Flash
Max(1)
Symbol
Parameter
Conditions
External clock (2), all
peripherals enabled
IDD
Supply current
in Run mode
External clock (2), all
peripherals Disabled
fHCLK
Unit
TA = 85 °C
48 MHz
32
36 MHz
26
24 MHz
18
16 MHz
13
8 MHz
7
48 MHz
23
36 MHz
19
24 MHz
13
16 MHz
10
8 MHz
6
mA
1. Based on characterization results, not tested in production.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 13. Maximum current consumption in Run mode, code with data processing
running from RAM
Max
Symbol
Parameter
Conditions
External clock (2), all
peripherals enabled
IDD
Supply current in
Run mode
External clock(2) all
peripherals disabled
fHCLK
48 MHz
27
36 MHz
20
24 MHz
14
16 MHz
10
8 MHz
6
48 MHz
19
36 MHz
15
24 MHz
10
16 MHz
7
8 MHz
5
1. Based on characterization, tested in production at VDD max, fHCLK max.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
32/77
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TA = 85 °C(1)
Unit
mA
STM32F102x4, STM32F102x6
Electrical characteristics
Figure 10. Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals enabled
30
Consumption (mA)
25
20
48 MHz
36MHz
15
16 MHz
8 MHz
10
5
0
–40 °C
25 °C
0 °C
70 °C
85 °C
Temperature (°C)
Figure 11. Typical current consumption in Run mode versus temperature (at 3.6 V) code with data processing running from RAM, peripherals disabled
20
18
Consumption (mA)
16
14
48 MHz
12
36 MHz
10
16 MHz
8
8 MHz
6
4
2
0
–40 °C
25 °C
0 °C
70 °C
85 °C
Temperature (°C)
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Electrical characteristics
STM32F102x4, STM32F102x6
Table 14. Maximum current consumption in Sleep mode, code running from Flash or RAM
Max(1)
Symbol
Parameter
Conditions
External clock(2) all
peripherals enabled
Supply current in
Sleep mode
IDD
External clock(2), all
peripherals disabled
fHCLK
Unit
TA = 85 °C
48 MHz
17
36 MHz
14
24 MHz
10
16 MHz
7
8 MHz
4
48 MHz
6
36 MHz
5
24 MHz
4.5
16 MHz
4
8 MHz
3
mA
1. Based on characterization, tested in production at VDD max and fHCLK max with peripherals enabled.
2. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 15. Typical and maximum current consumptions in Stop and Standby modes
Typ(1)
Symbol
Parameter
Conditions
Regulator in Run mode,
Low-speed and high-speed internal
RC oscillators and high-speed
oscillator OFF (no independent
Supply current watchdog)
in Stop mode Regulator in Low Power mode,
IDD
Low-speed and high-speed internal
RC oscillators and high-speed
oscillator OFF (no independent
watchdog)
Low-speed internal RC oscillator and
independent watchdog ON
Supply current Low-speed internal RC oscillator ON,
independent watchdog OFF
in Standby
mode(2)
Low-speed internal RC oscillator and
independent watchdog OFF, lowspeed oscillator and RTC OFF
Backup
IDD_VBAT domain supply Low-speed oscillator and RTC ON
current
1. Typical values are measured at TA = 25 °C.
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VDD/
VBAT =
2.4 V
Max
VDD/VBAT VDD/VBAT TA =
= 3.3 V
= 2.0 V
85 °C
21.3
21.7
-
160
11.3
11.7
-
145
2.75
3.4
-
-
2.55
3.2
-
-
1.55
1.9
-
3.2
1.1
1.4
0.9
1.9(3)
Unit
µA
STM32F102x4, STM32F102x6
Electrical characteristics
2. To have the Standby consumption with RTC ON, add IDD_VBAT (Low-speed oscillator and RTC ON) to IDD Standby (when
VDD is present the Backup Domain is powered by VDD supply).
3. Based on characterization, not rested in production.
Figure 12. Typical current consumption on VBAT with RTC on versus temperature at different
VBAT values
Consumption ( µA )
2.5
2
2V
1.5
2.4 V
1
3V
0.5
3.6 V
0
–40 °C
25 °C
70 °C
85 °C
105 °C
Temperature (°C)
ai17351
Figure 13. Typical current consumption in Stop mode with regulator in Run mode versus
temperature at VDD = 3.3 V and 3.6 V
45
40
Consumption (µA)
35
30
25
3.3 V
3.6 V
20
15
10
5
0
–45 °C
25 °C
85 °C
Temperature (°C)
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Electrical characteristics
STM32F102x4, STM32F102x6
Figure 14. Typical current consumption in Stop mode with regulator in Low-power mode versus
temperature at VDD = 3.3 V and 3.6 V
30
Consumption (µA)
25
20
3.3 V
3.6 V
15
10
5
0
–45 °C
25 °C
85 °C
Temperature (°C)
Figure 15. Typical current consumption in Standby mode versus temperature at VDD = 3.3 V and
3.6 V
3.5
3
Consumption (µA)
2.5
2
3.3 V
3.6 V
1.5
1
0.5
0
–45 °C
25 °C
85 °C
Temperature (°C)
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STM32F102x4, STM32F102x6
Electrical characteristics
Typical current consumption
The MCU is placed under the following conditions:
•
All I/O pins are in input mode with a static value at VDD or VSS (no load)
•
All peripherals are disabled except if it is explicitly mentioned
•
The Flash access time is adjusted to fHCLK frequency (0 wait state from 0 to 24 MHz, 1
wait state from 24 to 48 MHz)
•
Prefetch is on (reminder: this bit must be set before clock setting and bus prescaling)
•
When the peripherals are enabled fPCLK1 = fHCLK/4, fPCLK2 = fHCLK/2, fADCCLK =
fPCLK2/4
The parameters given in Table 17 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
Table 16. Typical current consumption in Run mode, code with data processing
running from Flash
Symbol
Parameter
Conditions
External
clock(3)
IDD
Supply
current in
Run mode
Running on
high speed
internal RC
(HSI), AHB
prescaler
used to
reduce the
frequency
Typ(1)
Typ(1)
All peripherals
enabled(2)
All peripherals
disabled
48 MHz
21.9
17.4
36 MHz
17.2
13.8
24 MHz
11.2
8.9
16 MHz
8.1
6.6
8 MHz
5
4.2
4 MHz
3
2.6
2 MHz
2
1.8
1 MHz
1.5
1.4
500 kHz
1.2
1.2
125 kHz
1.05
1
48 MHz
21.2
16.7
36 MHz
16.5
13.1
24 MHz
10.5
8.2
16 MHz
7.4
5.9
8 MHz
4.3
3.6
4 MHz
2.4
2
2 MHz
1.5
1.3
1 MHz
1
0.9
500 kHz
0.7
0.65
125 kHz
0.5
0.45
fHCLK
Unit
mA
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
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76
Electrical characteristics
STM32F102x4, STM32F102x6
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
Table 17. Typical current consumption in Sleep mode, code running from Flash or
RAM
Typ(1)
Symbol
Parameter
Conditions
External clock(3)
IDD
Supply
current in
Sleep mode
Running on High
Speed Internal
RC (HSI), AHB
prescaler used to
reduce the
frequency
fHCLK
Typ(1)
All peripherals All peripherals
enabled(2)
disabled
48 MHz
8.7
3.8
36 MHz
6.7
3.1
24 MHz
4.8
2.3
16 MHz
3.4
1.8
8 MHz
2
1.2
4 MHz
1.5
1.1
2 MHz
1.25
1
1 MHz
1.1
0.98
500 kHz
1.05
0.96
125 kHz
1
0.95
48 MHz
8.1
3.2
36 MHz
6.1
2.5
24 MHz
4.2
1.7
16 MHz
2.8
1.2
8 MHz
1.4
0.55
4 MHz
0.9
0.5
2 MHz
0.7
0.45
1 MHz
0.55
0.42
500 kHz
0.48
0.4
125 kHz
0.4
0.38
1. Typical values are measures at TA = 25 °C, VDD = 3.3 V.
2. Add an additional power consumption of 0.8 mA per ADC for the analog part. In applications, this
consumption occurs only while the ADC is on (ADON bit is set in the ADC_CR2 register).
3. External clock is 8 MHz and PLL is on when fHCLK > 8 MHz.
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Unit
mA
STM32F102x4, STM32F102x6
Electrical characteristics
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in Table 19. The MCU is placed
under the following conditions:
•
all I/O pins are in input mode with a static value at VDD or VSS (no load)
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
•
–
with all peripherals clocked off
–
with only one peripheral clocked on
ambient operating temperature and VDD supply voltage conditions summarized in
Table 5.
Table 18. Peripheral current consumption
Peripheral
APB1
APB2
Typical consumption at 25 °C(1)
TIM2
0.6
TIM3
0.6
USART2
0.21
USB
0.65
I2C
0.18
GPIO A
0.21
GPIO B
0.21
GPIO C
0.21
GPIO D
0.21
(2)
1.
ADC
1.4
SPI
0.24
USART
0.35
Unit
mA
fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, default prescaler value for each peripheral.
2. Specific conditions for ADC: fHCLK = 48 MHz, fAPB1 = fHCLK/2, fAPB2 = fHCLK, fADCCLK = fAPB2/4, ADON bit
in the ADC_CR2 register is set to 1.
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Electrical characteristics
5.3.6
STM32F102x4, STM32F102x6
External clock source characteristics
High-speed external user clock generated from an external source
The characteristics given in Table 20 result from tests performed using an high-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 8.
Table 19. High-speed external user clock characteristics
Symbol
Parameter
Conditions
(1)
Min
Typ
Max
Unit
1
8
25
MHz
fHSE_ext
User external clock source frequency
VHSEH
OSC_IN input pin high level voltage
0.7VDD
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time(1)
tr(HSE)
tf(HSE)
OSC_IN rise or fall time(1)
Cin(HSE)
DuCy(HSE)
IL
V
5
ns
20
OSC_IN input capacitance(1)
5
Duty cycle
pF
45
VSS ≤ VIN ≤ VDD
OSC_IN Input leakage current
55
%
±1
µA
1. Guaranteed by design, not tested in production.
Low-speed external user clock generated from an external source
The characteristics given in Table 21 result from tests performed using an low-speed
external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 8.
Table 20. Low-speed external user clock characteristics
Symbol
Parameter
Conditions
Min
frequency(1)
Typ
Max
Unit
32.768
1000
kHz
fLSE_ext
User external clock source
VLSEH
OSC32_IN input pin high level voltage
0.7VDD
VDD
VLSEL
OSC32_IN input pin low level voltage
VSS
0.3VDD
tw(LSE)
tw(LSE)
OSC32_IN high or low time(1)
450
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time(1)
Cin(LSE)
DuCy(LSE)
IL
ns
50
OSC32_IN input capacitance(1)
5
Duty cycle
OSC32_IN Input leakage current
30
VSS ≤ VIN ≤ VDD
1. Guaranteed by design, not tested in production.
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V
DocID15057 Rev 4
pF
70
%
±1
µA
STM32F102x4, STM32F102x6
Electrical characteristics
Figure 16. High-speed external clock source AC timing diagram
VHSEH
90%
VHSEL
10%
tr(HSE)
tf(HSE)
tW(HSE)
tW(HSE)
t
THSE
External
clock source
fHSE_ext
OSC _IN
IL
STM32F102xx
ai14975b
Figure 17. Low-speed external clock source AC timing diagram
VLSEH
90%
VLSEL
10%
tr(LSE)
tf(LSE)
tW(LSE)
OSC32_IN
IL
tW(LSE)
t
TLSE
External
clock source
fLSE_ext
STM32F102xx
ai14976b
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76
Electrical characteristics
STM32F102x4, STM32F102x6
High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 4 to 16 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 22. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 21. HSE 4-16 MHz oscillator characteristics(1)(2)
Symbol
fOSC_IN
Parameter
Conditions
Oscillator frequency
Min
Typ
Max
Unit
4
8
16
MHz
RF
Feedback resistor
200
kΩ
C
Recommended load capacitance
versus equivalent serial
RS = 30 Ω
resistance of the crystal (RS)(3)
30
pF
i2
HSE driving current
VDD = 3.3 V
VIN = VSS with 30 pF load
gm
Oscillator transconductance
Startup
Startup time
VDD is stabilized
tSU(HSE)
(4)
1
25
mA
mA/V
2
ms
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Based on characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a
humid environment, due to the induced leakage and the bias condition change. However, it is
recommended to take this point into account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz
oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly
with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 18). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
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STM32F102x4, STM32F102x6
Electrical characteristics
Figure 18. Typical application with an 8 MHz crystal
Resonator with
integrated capacitors
CL1
fHSE
OSC_IN
8 MH z
resonator
CL2
REXT(1)
RF
Bias
controlled
gain
STM32F102xx
OSC_OU T
ai14977b
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 23. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 22. LSE oscillator characteristics (fLSE = 32.768 kHz)
Symbol
Parameter
Conditions
Min
Typ
Max
RF
Feedback resistor
C(1)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)
RS = 30 kΩ
15
pF
I2
LSE driving current
VDD = 3.3 V
VIN = VSS
1.4
µA
gm
Oscillator transconductance
tSU(LSE)(2)
Startup time
5
Unit
5
VDD is stabilized
MΩ
µA/V
TA = 50 °C
1.5
TA = 25 °C
2.5
TA = 10 °C
4.0
TA = 0 °C
6.0
TA = −10 °C
10.0
TA = −20 °C
17.0
TA = −30 °C
32.0
TA = −40 °C
60.0
s
1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
2. tSU(LSE) is the startup time measured from the moment it is enabled by software to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and can vary significantly with the crystal manufacturer, PCB layout
and humidity.
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Electrical characteristics
STM32F102x4, STM32F102x6
Note:
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator. CL1 and CL2,
are usually the same size. The crystal manufacturer typically specifies a load capacitance
which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray
where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it
is between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤ 7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF, and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Figure 19. Typical application with a 32.768 kHz crystal
Resonator with
integrated capacitors
CL1
fLSE
OSC32_IN
32.768 KH z
resonator
RF
Bias
controlled
gain
OSC32_OU T
CL2
STM32F102xx
ai14978b
5.3.7
Internal clock source characteristics
The parameters given in Table 24 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
High-speed internal (HSI) RC oscillator
Table 23. HSI oscillator characteristics(1)
Symbol
fHSI
Parameter
Conditions
Min
Frequency
Typ
8
DuCy(HSI) Duty cycle
45
TA = –40 to 105 °C
Accuracy of the HSI
oscillator
TA = –10 to 85 °C
Factory(4)(5)
calibrated
TA = 0 to 70 °C
TA = 25 °C
tsu(HSI)(4)
HSI oscillator
startup time
IDD(HSI)(4)
HSI oscillator power
consumption
44/77
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MHz
%
1(3)
%
–2
2.5
%
–1.5
2.2
%
–1.3
2
%
–1.1
1.8
%
1
2
µs
100
µA
80
1. VDD = 3.3 V, TA = –40 to 105 °C unless otherwise specified.
Unit
55
User-trimmed with the RCC_CR
register(2)
ACCHSI
Max
STM32F102x4, STM32F102x6
Electrical characteristics
2. Refer to application note AN2868 “STM32F10xxx internal RC oscillator (HSI) calibration” available from the
ST website www.st.com.
3. Guaranteed by design, not tested in production.
4. Based on characterization, not tested in production.
5. The actual frequency of HSI oscillator may be impacted by a reflow, but does not drift out of the specified
range.
low-speed internal (LSI) RC oscillator
Table 24. LSI oscillator characteristics (1)
Symbol
fLSI
Parameter
Frequency
tsu(LSI)(3)
LSI oscillator startup time
IDD(LSI)(3)
LSI oscillator power consumption
Min(2)
Typ
Max
Unit
30
40
60
kHz
85
µs
1.2
µA
0.65
1. VDD = 3 V, TA = −40 to 85 °C unless otherwise specified.
2. Based on characterization, not tested in production.
3. Guaranteed by design, not tested in production.
Wakeup time from low-power mode
The wakeup times given in Table 26 is measured on a wakeup phase with a 8-MHz HSI RC
oscillator. The clock source used to wake up the device depends from the current operating
mode:
•
Stop or Standby mode: the clock source is the RC oscillator
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode.
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 8.
Table 25. Low-power mode wakeup timings
Symbol
tWUSLEEP(1)
tWUSTOP(1)
tWUSTDBY(1)
Parameter
Typ
Unit
Wakeup from Sleep mode
1.8
µs
Wakeup from Stop mode (regulator in run mode)
3.6
Wakeup from Stop mode (regulator in low-power
mode)
5.4
Wakeup from Standby mode
50
µs
µs
1. The wakeup times are measured from the wakeup event to the point at which the user application code
reads the first instruction.
5.3.8
PLL characteristics
The parameters given in Table 27 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 8.
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76
Electrical characteristics
STM32F102x4, STM32F102x6
Table 26. PLL characteristics
Value
Symbol
Parameter
Unit
Min(1)
Typ
Max(1)
PLL input clock(2)
1
8.0
25
MHz
PLL input clock duty cycle
40
60
%
fPLL_OUT
PLL multiplier output clock
16
48
MHz
tLOCK
PLL lock time
200
µs
Jitter
Cycle-to-cycle jitter
300
ps
fPLL_IN
1. Based on characterization, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
5.3.9
Memory characteristics
Flash memory
The characteristics are given at TA = –40 to 85 °C unless otherwise specified.
Table 27. Flash memory characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
52.5
70
µs
tprog
16-bit programming time
TA = –40 to +85 °C
40
tERASE
Page (1 KB) erase time
TA = –40 to +85 °C
20
40
ms
Mass erase time
TA = –40 to +85 °C
20
40
ms
Read mode
fHCLK = 48 MHz with 2
wait states, VDD = 3.3 V
20
mA
Write / Erase modes
fHCLK = 48 MHz, VDD =
3.3 V
5
mA
Power-down mode / Halt,
VDD = 3.0 to 3.6 V
50
µA
3.6
V
tME
IDD
Vprog
Supply current
Programming voltage
2
1. Guaranteed by design, not tested in production.
Table 28. Flash memory endurance and data retention
Value
Symbol
Parameter
NEND
Endurance
tRET
Data retention
Conditions
TA = 85 °C, 1000 cycles
1. Based on characterization not tested in production.
46/77
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Min(1)
Unit
Typ
Max
10
kcycles
30
Years
STM32F102x4, STM32F102x6
5.3.10
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (Electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 31. They are based on the EMS levels and classes
defined in application note AN1709.
Table 29. EMS characteristics
Symbol
Parameter
Conditions
Level/Class
VFESD
Voltage limits to be applied on any I/O pin to
induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK= 48 MHz
conforms to IEC 61000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS pins
to induce a functional disturbance
VDD = 3.3 V, TA = +25 °C,
fHCLK = 48 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre
qualification tests in relation with the EMC level requested for his application.
Software recommendations: the software flowchart must include the management of
runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical Data corruption (control registers, etc.)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second. To complete these trials, ESD stress can be applied directly on the device, over the
range of specification values. When unexpected behavior is detected, the software can be
hardened to prevent unrecoverable errors occurring (see application note AN1015).
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Electrical characteristics
STM32F102x4, STM32F102x6
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device is monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 30. EMI characteristics
Symbol Parameter
SEMI
5.3.11
Peak level
Conditions
VDD = 3.3 V, TA = 25 °C,
Monitored
frequency band
Max vs. [fHSE/fHCLK]
Unit
8/48 MHz
0.1 MHz to 30 MHz
7
30 MHz to 130 MHz
8
130 MHz to 1GHz
13
SAE EMI Level
3.5
dBµV
-
Absolute maximum ratings (electrical sensitivity)
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 31. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Maximum
value(1)
VESD(HBM)
Electrostatic discharge voltage TA = +25 °C, conforming
(human body model)
to JESD22-A114
2
2000
VESD(CDM)
Electrostatic discharge voltage TA = +25 °C, conforming
(charge device model)
to ANSI/ESD STM5.3.1
II
500
Unit
V
1. Based on characterization results, not tested in production.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78 IC latch-up standard.
Table 32. Electrical sensitivities
Symbol
LU
48/77
Parameter
Static latch-up class
Conditions
TA = +105 °C conforming to JESD78A
DocID15057 Rev 4
Class
II level A
STM32F102x4, STM32F102x6
5.3.12
Electrical characteristics
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product
operation. However, in order to give an indication of the robustness of the microcontroller in
cases when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibilty to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (>5
LSB TUE), out of spec current injection on adjacent pins or other functional failure (for
example reset, oscillator frequency deviation).
The test results are given in Table 35.
Table 33. I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
5.3.13
Description
Negative
injection
Positive
injection
Injected current on OSC_IN32,
OSC_OUT32, PA4, PA5, PC13
-0
+0
Injected current on all FT pins
-5
+0
Injected current on any other pin
-5
+5
Unit
mA
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 36 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.
General input/output characteristics
Unless otherwise specified, the parameters given in Table 34 are derived from tests
performed under the conditions summarized in Table 8. All I/Os are CMOS and TTL
compliant.
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STM32F102x4, STM32F102x6
Table 34. I/O static characteristics
Symbol
Parameter
Conditions
Standard IO
input low level
voltage
VIL
Low level input voltage IO FT(3) input
low level voltage
All I/Os except
BOOT0
Standard IO
input high level
voltage
VIH
Vhys
Ilkg
Min
Typ
Max
-
-
0.28*(VDD-2 V)+0.8 V(1)
-
-
0.32*(VDD-2V)+0.75 V(1)
-
-
0.35VDD(2)
V
0.41*(VDD-2 V)+1.3 V
(1)
-
-
IO FT(3) input
high level
voltage
0.42*(VDD-2 V)+1 V(1)
-
-
All I/Os except
BOOT0
0.65VDD(2)
-
-
Standard IO Schmitt
trigger voltage
hysteresis(4)
200
-
-
IO FT Schmitt trigger
voltage hysteresis(4)
5% VDD(5)
-
-
VSS ≤ VIN ≤ VDD
Standard I/Os
-
-
±1
VIN = 5 V
I/O FT
-
-
3
30
40
50
High level input
voltage
Input leakage current
(6)
mV
RPU
Weak pull-up
equivalent resistor(7)
VIN = VSS
RPD
Weak pull-down
equivalent resistor(7)
VIN = VDD
CIO
I/O pin capacitance
µA
kΩ
30
40
50
-
5
-
1. Data based on design simulation.
2. Tested in production.
3. FT = Five-volt tolerant. In order to sustain a voltage higher than VDD+0.3 the internal pull-up/pull-down resistors must be
disabled.
4. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization, not tested in production.
5. With a minimum of 100 mV.
6. Leakage could be higher than max. if negative current is injected on adjacent pins.
7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimum (~10% order).
50/77
Unit
DocID15057 Rev 4
pF
STM32F102x4, STM32F102x6
Electrical characteristics
All I/Os are CMOS and TTL compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters. The
coverage of these requirements is shown in Figure 20 and Figure 21 for standard I/Os, and
in Figure 22 and Figure 23 for 5 V tolerant I/Os.
Figure 20. Standard I/O input characteristics - CMOS port
Area not
determined
VIH/VIL (V)
=0.65V DD
ment V IH
CMOS
7IHmin
7ILmax
Tested
ction
in produ
quire
dard re
1.3
(V -2)+
V IH=0.41 DD simulations
sign
de
on
Based
0.8
(V -2)+
VIL=0.28 DD
mulations
design si
Based on
5V
ment V IL=0.3 DD
dard require
stan
1.3
CMOS stan
0.8
0.7
tion
oduc
Tested in pr
2
2.7
3
3.3
VDD (V)
3.6
ai17277c
Figure 21. Standard I/O input characteristics - TTL port
VIH/VIL (V)
7IHmin
Area not
determined
TTL requirements VIH =2V
2.0
1.3
V -2)+
V IH=0.41( DD simulations
sign
de
on
1.96 Based
1.3
1.25 V IL=0.28(V DD
ations
design simul
-2)+0.8
7ILmax
Based on
0.8
TTL requirements
2
VIL=0.8V
2.16
3.6
VDD (V)
ai17278b
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STM32F102x4, STM32F102x6
Figure 22. 5 V tolerant I/O input characteristics - CMOS port
Area not
determined
VIH/VIL (V)
=0.65V DD
nts V IH
quireme
dard re
OS stan
CM
Tested
ction
in produ
1.3
1.295
0.975
1
0.7
0.75
1.55
1.16
-2)+1
V IH=0.42(V DD simulations
gn
si
de
on
d
1.67 Base
-2)+0.75
1 V IL=0.32(V DD
ions
sign simulat
Based on de
1.42
1.07
5V DD
ent V IL =0.3
dard requirm
CMOS stan
oduction
Tested in pr
2
2.7
3
3.3
VDD (V)
3.6
VDD
ai17279c
Figure 23. 5 V tolerant I/O input characteristics - TTL port
VIH/VIL (V)
Area not
determined
TTL requirement VIH=2V
1
(V DD-2)+
ions
V IH=0.42* si
gn simulat
de
on
1.67 Based
75
0.
)+
-2
1 V IL=0.32*(V DD simulations
design
Based on
2.0
7IHmin
7ILmax
0.8
0.75
TTL requirements VIL=0.8V
2
2.16
3.6
VDD (V)
ai17280b
Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can
sink or source up to ±3 mA. When using the GPIOs PC13 to PC15 in output mode, the
speed should not exceed 2 MHz with a maximum load of 30 pF.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
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•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 6).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS (see Table 6).
DocID15057 Rev 4
STM32F102x4, STM32F102x6
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 37 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 8. All I/Os are CMOS and TTL compliant.
Table 35. Output voltage characteristics
Symbol
VOL(1)
VOH
(3)
VOL(1)
VOH
(3)
VOL(1)
VOH
(3)
VOL(1)
VOH
(3)
Parameter
Output Low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output High level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Output low level voltage for an I/O pin
when 8 pins are sunk at the same time
Output high level voltage for an I/O pin
when 8 pins are sourced at the same time
Conditions
CMOS port(2),
IIO = +8 mA,
2.7 V < VDD < 3.6 V
TTL port(2)
IIO = +8 mA
2.7 V < VDD < 3.6 V
IIO = +20 mA(4)
2.7 V < VDD < 3.6 V
IIO = +6 mA(4)
2 V < VDD < 2.7 V
Min
Max
Unit
0.4
V
VDD–0.4
0.4
V
2.4
1.3
V
VDD–1.3
0.4
V
VDD–0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 6
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 6 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Based on characterization data, not tested in production.
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STM32F102x4, STM32F102x6
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 24 and
Table 38, respectively.
Unless otherwise specified, the parameters given in Table 38 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 8.
Table 36. I/O AC characteristics(1)
MODEx
[1:0] bit
value(1)
Symbol
Parameter
fmax(IO)out Maximum frequency(2)
10
tf(IO)out
Output high to low level fall
time
tr(IO)out
Output low to high level rise
time
fmax(IO)out Maximum frequency(2)
01
tf(IO)out
Output high to low level fall
time
tr(IO)out
Output low to high level rise
time
Fmax(IO)out Maximum
11
tf(IO)out
tr(IO)out
Frequency(2)
Output high to low level fall
time
Conditions
CL = 50 pF, VDD = 2 V to 3.6 V
tEXTIpw
2
MHz
CL = 50 pF, VDD = 2 V to 3.6 V
ns
(3)
125
CL= 50 pF, VDD = 2 V to 3.6 V
10
MHz
25(3)
CL= 50 pF, VDD = 2 V to 3.6 V
ns
25(3)
CL= 30 pF, VDD = 2.7 V to 3.6 V
50
MHz
CL = 50 pF, VDD = 2.7 V to 3.6 V
30
MHz
CL = 50 pF, VDD = 2 V to 2.7 V
20
MHz
CL = 30 pF, VDD = 2.7 V to 3.6 V
5(3)
CL = 50 pF, VDD = 2.7 V to 3.6 V
8(3)
CL = 50 pF, VDD = 2 V to 2.7 V
12(3)
CL = 30 pF, VDD = 2.7 V to 3.6
V
5(3)
Output low to high level rise
CL = 50 pF, VDD = 2.7 V to 3.6 V
time
Pulse width of external
signals detected by the
EXTI controller
Unit
125(3)
CL = 50 pF, VDD = 2 V to 2.7 V
-
Max
ns
8(3)
12(3)
10
ns
1. The I/O speed is configured using the MODEx[1:0] bits. Refer to the STM32F10xxx reference manual for a
description of GPIO Port configuration register.
2. The maximum frequency is defined in Figure 24.
3. Guaranteed by design, not tested in production.
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STM32F102x4, STM32F102x6
Electrical characteristics
Figure 24. I/O AC characteristics definition
90%
10%
50%
50%
90%
10%
EXTERNAL
OUTPUT
ON 50pF
tr(IO)out
tf(IO)out
T
Maximum frequency is achieved if (tr + tf) ≤ 2/3)T and if the duty cycle is (45-55%)
when loaded by 50pF
ai14131c
5.3.14
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 36).
Unless otherwise specified, the parameters given in Table 39 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 8.
Table 37. NRST pin characteristics
Symbol
VIL(NRST)(1)
VIH(NRST)
(1)
Vhys(NRST)
(1)
Conditions
Min
Typ
Max
NRST Input low level voltage
–0.5
0.8
NRST Input high level voltage
2
VDD+0.5
NRST Schmitt trigger voltage
hysteresis
Weak pull-up equivalent resistor(2)
RPU
VF(NRST)
Parameter
200
VIN = VSS
30
NRST Input filtered pulse
VNF(NRST)(1) NRST Input not filtered pulse
40
Unit
V
mV
50
kΩ
100
ns
300
ns
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution
to the series resistance must be minimum (~10% order).
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Electrical characteristics
STM32F102x4, STM32F102x6
Figure 25. Recommended NRST pin protection
VDD
External
reset circuit(1)
NRST(2)
RPU
Internal Reset
Filter
0.1 μF
STM32Fxxx
ai14132c
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 39. Otherwise the reset will not be taken into account by the device.
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5.3.15
Electrical characteristics
TIM timer characteristics
The parameters given in Table 40 are guaranteed by design.
Refer to Section 5.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 38. TIMx(1) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Conditions
Timer resolution time
Timer external clock
frequency on CH1 to CH4
fTIMxCLK = 48 MHz
fTIMxCLK = 48 MHz
Min
tMAX_COUNT Maximum possible count
Unit
1
tTIMxCLK
20.84
ns
0
fTIMxCLK/2
MHz
0
24
MHz
16
bit
65536
tTIMxCLK
1365
µs
65536 × 65536
tTIMxCLK
89.48
s
Timer resolution
16-bit counter clock period
when internal clock is
selected
Max
1
fTIMxCLK = 48 MHz 0.0208
fTIMxCLK = 48 MHz
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
5.3.16
Communications interfaces
I2C interface characteristics
The STM32F102xx medium-density USB access line I2C interface meets the requirements
of the standard I2C communication protocol with the following restrictions: the I/O pins SDA
and SCL are mapped to are not “true” open-drain. When configured as open-drain, the
PMOS connected between the I/O pin and VDD is disabled, but is still present.
The I2C characteristics are described in Table 41. Refer also to Section 5.3.13: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
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STM32F102x4, STM32F102x6
Table 39. I2C characteristics
Standard mode I2C(1) Fast mode I2C(1)(2)
Symbol
Parameter
Unit
Min
Max
Min
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
Max
µs
100
(3)
0
900(3)
20+0.1Cb
300
th(SDA)
SDA data hold time
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
th(STA)
Start condition hold time
4.0
0.6
tsu(STA)
Repeated Start condition setup
time
4.7
0.6
tsu(STO)
Stop condition setup time
4.0
0.6
µs
tw(STO:STA)
Stop to Start condition time (bus
free)
4.7
1.3
µs
Cb
Capacitive load for each bus line
0
400
ns
300
µs
400
pF
1. Values guaranteed by design, not tested in production.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I2C frequencies. It must be at least 4 MHz to
achieve fast mode I2C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I2C
fast mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of the SCL
signal.
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STM32F102x4, STM32F102x6
Electrical characteristics
Figure 26. I2C bus AC waveforms and measurement circuit(1)
VDD_I2C
VDD_I2C
Rp
Rp
STM32F10x
Rs
SDA
I²C bus
Rs
SCL
Start repeated
Start
Start
tsu(STA)
SDA
tf(SDA)
tr(SDA)
th(STA)
tsu(SDA)
tw(SCLL)
th(SDA)
tsu(STO:STA)
Stop
SCL
tw(SCLH)
tr(SCL)
tf(SCL)
tsu(STO)
ai14133e
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 40. SCL frequency (fPCLK1= 36 MHz, VDD_I2C = 3.3 V)(1)(2)
fSCL
I2C_CCR value
(kHz)
RP = 4.7 kΩ
400
0x801E
300
0x8028
200
0x803C
100
0x00B4
50
0x0168
20
0x0384
2
1. RP = External pull-up resistance, fSCL = I C speed,
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed ±2%. These variations depend on the accuracy of the external
components used to design the application.
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Electrical characteristics
STM32F102x4, STM32F102x6
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions
summarized in Table 8.
Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO).
Table 41. SPI characteristics
Symbol
fSCK
1/tc(SCK)
Parameter
Conditions
SPI clock frequency
Min
18
Slave mode
18
8
ns
70
%
SPI clock rise and fall
time
Capacitive load: C = 30 pF
DuCy(SCK)
SPI slave input clock
duty cycle
Slave mode
30
tsu(NSS)(1)
NSS setup time
Slave mode
4tPCLK
th(NSS)(1)
NSS hold time
Slave mode
2tPCLK
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
Master mode
5
Slave mode
5
Master mode
5
Slave mode
4
tw(SCKH)
tw(SCKL)(1)
tsu(MI) (1)
tsu(SI)(1)
th(MI)
Data input setup time
(1)
th(SI)(1)
ta(SO)(1)(2)
Data input hold time
Data output access time Slave mode, fPCLK = 20 MHz
tdis(SO)(1)(3) Data output disable time Slave mode
ns
0
3tPCLK
2
10
Data output valid time
Slave mode (after enable edge)
25
tv(MO)(1)
Data output valid time
Master mode (after enable
edge)
5
th(SO)(1)
th(MO)(1)
Data output hold time
Slave mode (after enable edge)
15
Master mode (after enable
edge)
2
MHz
60
(1)
tv(SO)
Unit
Master mode
tr(SCK)
tf(SCK)
(1)
Max
1. Based on characterization, not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
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STM32F102x4, STM32F102x6
Electrical characteristics
Figure 27. SPI timing diagram - slave mode and CPHA=0
NSS input
tc(SCK)
th(NSS)
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
M SB IN
LSB IN
B I T1 IN
th(SI)
ai14134c
Figure 28. SPI timing diagram - slave mode and CPHA=1(1)
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCLH)
tw(SCLL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCL)
tf(SCL)
tdis(SO)
LSB OUT
th(SI)
M SB IN
B I T1 IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics
STM32F102x4, STM32F102x6
Figure 29. SPI timing diagram - master mode(1)
High
NSS input
SCK Output
CPHA= 0
CPOL=0
SCK Output
tc(SCK)
CPHA=1
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
MS BIN
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
B I T1 OUT
M SB OUT
tv(MO)
LSB OUT
th(MO)
ai14136V2
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
USB characteristics
The USB interface is USB-IF certified (Full Speed).
Table 42. USB startup time
Symbol
tSTARTUP
62/77
Parameter
USB transceiver startup time
DocID15057 Rev 4
Max
Unit
1
µs
STM32F102x4, STM32F102x6
Electrical characteristics
Table 43. USB DC electrical characteristics
Symbol
Parameter
VDD
Input
levels
VDI
(4)
VCM(4)
Min.(1)
Conditions
USB operating voltage(2)
3.0(3)
Differential input sensitivity
VOL
VOH
V
V
0.2
Includes VDI range
0.8
2.5
1.3
2.0
Differential common mode range
RL of 1.5 kΩ to 3.6
V(5)
Static output level low
RL of 15 kΩ to
Static output level high
3.6
I(USB_DP, USB_DM)
VSE(4) Single ended receiver threshold
Output
levels
Max.(1) Unit
VSS(5)
0.3
2.8
V
3.6
1. All the voltages are measured from the local ground potential.
2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled
up with a 1.5 kΩ resistor to a 3.0-to-3.6 V voltage range.
3. The STM32F102xx USB functionality is ensured down to 2.7 V but not the full USB electrical
characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range.
4. Guaranteed by design, not tested in production.
5. RL is the load connected on the USB drivers
Figure 30. USB timings: definition of data signal rise and fall time
Crossover
points
Differen tial
Data L ines
VCRS
VS S
tr
tf
ai14137
Table 44. USB: Full speed electrical characteristics of the driver(1)
Symbol
tr
tf
trfm
VCRS
Parameter
Rise time(2)
Fall
time(2)
Conditions
Min
Max
Unit
CL = 50 pF
4
20
ns
CL = 50 pF
4
20
ns
tr/tf
90
110
%
1.3
2.0
V
Rise/ fall time matching
Output signal crossover voltage
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
5.3.17
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 47 are derived from tests
performed under ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 8.
Note:
It is recommended to perform a calibration after each power-up.
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Electrical characteristics
STM32F102x4, STM32F102x6
Table 45. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
2.4
3.6
V
fADC
ADC clock frequency
0.6
12
MHz
fS(1)
Sampling rate
0.05
0.85
Msps
823
kHz
17
1/fADC
VREF+
V
50
κΩ
fTRIG(1)
VAIN
External trigger frequency
fADC = 12 MHz
0 (VSSA or
VREF- tied to
ground)
Conversion voltage range(2)
See Equation 1
and Table 48
for details
RAIN(1)
External input impedance
RADC(1)
Sampling switch resistance
1
κΩ
CADC(1)
Internal sample and hold
capacitor
8
pF
tCAL(1)
Calibration time
fADC = 12 MHz
tlat(1)
Injection trigger conversion
latency
fADC = 12 MHz
tlatr(1)
Regular trigger conversion
latency
fADC = 12 MHz
tS(1)
Sampling time
Power-up time
tCONV(1)
Total conversion time
(including sampling time)
µs
83
1/fADC
0.214
µs
3(3)
1/fADC
0.143
µs
2
fADC = 12 MHz
tSTAB(1)
5.9
1/fADC
0.125
19.95
µs
1.5
239.5
1/fADC
1
µs
21
µs
0
fADC = 12 MHz
(3)
0
1.2
14 to 252 (tS for sampling +12.5
for successive approximation)
1/fADC
1. Guaranteed by design, not tested in production.
2. VREF+ is internally connected to VDDA and VREF- is internally connected to VSSA,
3. For external triggers, a delay of 1/fPCLK2 must be added to the latency specified in Table 47.
Equation 1: RAIN max formula:
TS
- – R ADC
R AIN < -----------------------------------------------------------N+2
f ADC × C ADC × ln ( 2
)
The formula above (Equation 1) is used to determine the maximum external impedance allowed for an
error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
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Electrical characteristics
Table 46. RAIN max for fADC = 12 MHz(1)
Ts (cycles)
tS (µs)
RAIN max (kΩ)
1.5
0.13
0.4
7.5
0.63
5.9
13.5
1.13
11.4
28.5
2.38
25.2
41.5
3.46
37.2
55.5
4.63
50
71.5
5.96
NA
239.5
19.96
NA
1. Data guaranteed by design, not tested in production.
Table 47. ADC accuracy - limited test conditions(1)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
Test conditions
Typ
Max(2)
fPCLK2 = 48 MHz,
fADC = 12 MHz, RAIN < 10 kΩ,
VDDA = 3 V to 3.6 V
TA = 25 °C
Measurements made after
ADC calibration
±1.3
±2
±1
±1.5
±0.5
±1.5
±0.7
±1
±0.8
±1.5
Typ
Max(4)
±2
±5
±1.5
±2.5
±1.5
±3
±1
±2
±1.5
±3
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. Based on characterization, not tested in production.
Table 48. ADC accuracy(1) (2) (3)
Symbol
Parameter
Test conditions
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
fPCLK2 = 48 MHz,
fADC = 12 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
Measurements made after
ADC calibration
Unit
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance could be achieved in restricted VDD, frequency and temperature ranges.
3. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should
be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially
inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 5.3.13 does not
affect the ADC accuracy.
4. Based on characterization, not tested in production.
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Electrical characteristics
STM32F102x4, STM32F102x6
Figure 31. ADC accuracy characteristics
[1LSBIDEAL =
VDDA
4096
EG
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
4095
4094
4093
(2)
ET
7
(1)
6
5
4
ET=Total u nadjusted er ror: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset e rror: deviation between the first actual
transition and the first ideal one.
EG=Gain er ror: deviation between the last ideal
transition and the last actual one.
ED=Differential linearity error: maximum deviation
between actual steps and the ideal one.
EL=Integral linearity error: maximum deviation
between any actual transition and the end point
correlation line.
(3)
EO
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
4093 4094 4095 4096
VDDA
ai15497
Figure 32. Typical connection diagram using the ADC
VDD
RAIN(1)
VAIN
VT
0.6 V
AINx
Cparasitic
VT
0.6 V
IL±1 µA
STM32F102
Sample and hold ADC
converter
RADC(1)
12-bit
converter
CADC(1)
ai14974b
1. Refer to Table 47 for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
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Electrical characteristics
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 33. The 10 nF capacitors
should be ceramic (good quality). They should be placed as close as possible to the chip.
Figure 33. Power supply and reference decoupling
STM32F102xx
VDDA
1 µF // 10 nF
VSSA
ai14980b
5.3.18
Temperature sensor characteristics
Table 49. TS characteristics
Symbol
TL(1)
Parameter
Min
Typ
Max
Unit
VSENSE linearity with temperature
±1.5
°C
Avg_Slope(1)
Average slope
4.35
mV/°C
V25(1)
Voltage at 25°C
1.42
V
tSTART
(2)
TS_temp(3)(2)
Startup time
4
ADC sampling time when reading the
temperature
10
µs
17.1
µs
1. Guaranteed by characterization, not tested in production.
2. Data guaranteed by design, not tested in production.
3. Shortest sampling time can be determined in the application by multiple iterations.
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Package characteristics
STM32F102x4, STM32F102x6
6
Package characteristics
6.1
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
Figure 34. LQFP64 – 10 x 10 mm, 48-pin low-profile quad flat package outline
A2
c
A1
A
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
A1
ccc C
K
L
D
L1
D1
D3
33
48
32
49
64
PIN 1
IDENTIFICATION
E
E1
E3
b
17
16
1
e
5W_ME_V2
1. Drawing is not to scale.
2. Dimensions are in millimeters.
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Package characteristics
Table 50. LQFP64 – 10 x 10 mm, 64-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
A
Min
Typ
1.600
A1
0.050
A2
1.350
b
0.170
c
0.090
D
11.800
D1
9.800
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
12.000
12.200
0.4646
0.4724
0.4803
10.000
10.200
0.3858
0.3937
0.4016
D3
0.0059
0.0079
7.50
0.2953
E
11.800
12.000
12.200
0.4646
0.4724
0.4803
E1
9.800
10.000
10.200
0.3858
0.3937
0.4016
E3
7.500
0.2953
e
0.500
0.0197
L
0.450
0.600
0.750
0.0177
0.0236
L1
1.00
0.0394
ccc
0.080
0.0031
K
0°
3.5°
7°
0°
3.5°
0.0295
7°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 35. LQFP64 recommended footprint dimensions(1)(2)
48
33
0.3
49
12.7
32
0.5
10.3
10.3
64
17
1.2
1
16
7.8
12.7
ai14909
1. Drawing is not to scale.
2. Dimensions are in millimeters.
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Package characteristics
STM32F102x4, STM32F102x6
Figure 36. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package outline
c
A1
A
A2
SEATING
PLANE
C
0.25 mm
GAUGE PLANE
ccc C
K
A1
D
L
D1
L1
D3
36
25
37
24
48
PIN 1
IDENTIFICATION
E
13
1
12
e
1. Drawing is not to scale.
2. Dimensions are in millimeters.
70/77
E1
E3
b
DocID15057 Rev 4
5B_ME_V2
STM32F102x4, STM32F102x6
Package characteristics
Table 51. LQFP48 – 7 x 7 mm, 48-pin low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
A
Min
Typ
1.600
A1
0.050
A2
1.350
b
0.170
c
0.090
D
8.800
D1
6.800
D3
Max
0.0630
0.150
0.0020
0.0059
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
9.000
9.200
0.3465
0.3543
0.3622
7.000
7.200
0.2677
0.2756
0.2835
0.0079
5.500
0.2165
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
5.500
0.2165
e
0.500
0.0197
L
0.450
0.600
0.750
0.0177
0.0236
L1
1.000
0.0394
ccc
0.080
0.0031
k
0°
3.5°
7°
0°
3.5°
0.0295
7°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 37. LQFP48 recommended footprint dimensions(1)(2)
0.50
1.20
9.70
0.30
25
36
37
24
0.20
7.30
5.80
7.30
48
13
12
1
1.20
5.80
9.70
ai14911b
1. Drawing is not to scale.
2. Dimensions are in millimeters.
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Package characteristics
6.2
STM32F102x4, STM32F102x6
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 8: General operating conditions on page 30.
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
•
TA max is the maximum ambient temperature in °C,
•
ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 52. Package thermal characteristics
Symbol
ΘJA
6.3
Parameter
Value
Thermal resistance junction-ambient
LQFP48 - 7 × 7 mm / 0.5 mm pitch
55
Thermal resistance junction-ambient
LQFP64 - 10 × 10 mm / 0.5 mm pitch
45
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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Evaluating the maximum junction temperature for an application
When ordering the microcontroller, the temperature range is specified in the ordering
information scheme shown in Table 55: Ordering information scheme.
Each temperature range suffix corresponds to a specific guaranteed ambient temperature at
maximum dissipation and, to a specific maximum junction temperature. Here, only
temperature range 6 is available (–40 to 85 °C).
The following example shows how to calculate the temperature range needed for a given
application, making it possible to check whether the required temperature range is
compatible with the STM32F102xx junction temperature range.
Example: High-performance application
Assuming the following application conditions:
Maximum ambient temperature TAmax = 82 °C (measured according to JESD51-2),
IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output
mode at low level with IOL = 20 mA, VOL= 1.3 V
PINTmax = 50 mA × 3.5 V= 175 mW
PIOmax = 20 × 8 mA × 0.4 V + 8 × 20 mA × 1.3 V = 272 mW
This gives: PINTmax = 175 mW and PIOmax = 272 mW
PDmax = 175 + 272 = 447 mW
Thus: PDmax = 447 mW
Using the values obtained in Table 54 TJmax is calculated as follows:
–
For LQFP64, 45 °C/W
TJmax = 82 °C + (45 °C/W × 447 mW) = 82 °C + 20.1 °C = 102.1 °C
This is within the junction temperature range of the STM32F102xx (–40 < TJ < 105 °C).
Figure 38. LQFP64 PD max vs. TA
700
600
PD (mW)
6.3.1
Package characteristics
500
400
Suffix 6
300
200
100
0
65
75
85
95
105
115
TA (°C)
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Ordering information scheme
7
STM32F102x4, STM32F102x6
Ordering information scheme
Table 53. Ordering information scheme
Example:
STM32 F 102 C 6
T
6
A xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
102 = USB access line, USB 2.0 full-speed interface
Pin count
C = 48 pins
R = 64 pins
Flash memory size
4 = 16 Kbytes of Flash memory
6 = 32 Kbytes of Flash memory
Package
T = LQFP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
Internal code
“A” or blank(1)
Options
xxx = programmed parts
TR = tape and real
1. For STM32F102x6 devices with a blank Internal code, please refer to the STM32F103x8/B datasheet
available from the ST website: www.st.com.
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8
Revision history
Revision history
Table 54. Document revision history
Date
Revision
23-Sep-2008
1
Initial release.
2
I/O information clarified on page 1. Figure 1: STM32F102T8 mediumdensity USB access line block diagram and Figure 5: Memory map
modified.
In Table 4: low-density STM32F102xx pin definitions: PB4, PB13, PB14,
PB15, PB3/TRACESWO moved from Default column to Remap column,
Note 4. added.
PD value added for LQFP64 package in Table 8: General operating
conditions.
Note modified in Table 13: Maximum current consumption in Run mode,
code with data processing running from Flash and Table 15: Maximum
current consumption in Sleep mode, code running from Flash or RAM.
Figure 13, Figure 14 and Figure 15 show typical curves.
Figure 31: ADC accuracy characteristics modified.
Figure 33: Power supply and reference decoupling modified. Small text
changes.
Table 20: High-speed external user clock characteristics and Table 21:
Low-speed external user clock characteristics modified.
ACCHSI max values modified in Table 24: HSI oscillator characteristics.
09-Apr-2009
Changes
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Revision history
STM32F102x4, STM32F102x6
Table 54. Document revision history (continued)
Date
24-Sep-2009
02-Aug-2013
76/77
Revision
Changes
3
Note 5. updated and Note 4. added in Table 4: low-density
STM32F102xx pin definitions. Typical IDD_VBAT value added in Table 16:
Typical and maximum current consumptions in Stop and Standby modes.
Figure 12: Typical current consumption on VBAT with RTC on versus
temperature at different VBAT values added.
fHSE_ext min modified in Table 20: High-speed external user clock
characteristics.
CL1 and CL2 replaced by C in Table 22: HSE 4-16 MHz oscillator
characteristics and Table 23: LSE oscillator characteristics (fLSE = 32.768
kHz), notes modified and moved below the tables. Table 24: HSI
oscillator characteristics modified. Conditions removed from Table 26:
Low-power mode wakeup timings.
Note 1. modified below Figure 18: Typical application with an 8 MHz
crystal.
Figure 25: Recommended NRST pin protection modified.
IEC 1000 standard updated to IEC 61000 and SAE J1752/3 updated to
IEC 61967-2 in Section 5.3.10: EMC characteristics on page 46.
Jitter added to Table 27: PLL characteristics.
CADC and RAIN parameters modified in Table 47: ADC characteristics.
RAIN max values modified in Table 48: RAIN max for fADC = 12 MHz.
4
Figure 2: Clock tree: added FLITFCLK and Note 3., and modified Note 1..
Removed sentence in “Unless otherwise specified the parameters ...” in
I2C interface characteristics section.
Added VIN in Table 8: General operating conditions
Added note 5. in Table 23: HSI oscillator characteristics
Added DuCy(HSI) in Table 24: HSI oscillator characteristics
Table 23: LSE oscillator characteristics (fLSE = 32.768 kHz): removed
note 2 related to oscillator selection, updated Note 2., and tSU(LSE)
specified for various ambient temperature values.
Modified charge device model in Table 33: ESD absolute maximum
ratings
Updated ‘VIL’ and ‘VIH’ in Table 34: I/O static characteristics
Added notes to Figure 20: Standard I/O input characteristics - CMOS
port, Figure 21: Standard I/O input characteristics - TTL port, Figure 22:
5 V tolerant I/O input characteristics - CMOS port and Figure 23: 5 V
tolerant I/O input characteristics - TTL port
Table 37: Output voltage characteristics: updated VOL and VOH
conditions for TTL and CMOS outputs and added Note 2.
Updated Figure 24: I/O AC characteristics definition
Updated Figure 25: Recommended NRST pin protection
Updated note 2. and 3. in Table 39: I2C characteristics
Updated Figure 26: I2C bus AC waveforms and measurement circuit(1)
Updated title of Table 40: SCL frequency (fPCLK1= 36 MHz, VDD_I2C =
3.3 V)
In Table 43: SPI characteristics, removed note 1 related to SPI1
remapped characteristics.
Updated Table 47: ADC characteristics
Updated Section 6.1: Package mechanical data
DocID15057 Rev 4
STM32F102x4, STM32F102x6
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