STM32L052x6 STM32L052x8

STM32L052x6 STM32L052x8

STM32L052x6 STM32L052x8

Ultra-low-power 32-bit MCU ARM

®

-based Cortex

®

-M0+, up to 64 KB

Flash memory, 8 KB SRAM, 2 KB EEPROM, USB, ADC, DAC

Datasheet

-

production data

Features

Ultra-low-power platform

– 1.65 V to 3.6 V power supply

-

40 to 125 °C temperature range

– 0.27 µA Standby mode (2 wakeup pins)

– 0.4 µA Stop mode (16 wakeup lines)

– 0.8 µA Stop mode + RTC + 8 KB RAM retention

– 88 µA/MHz Run mode

– 3.5 µs wakeup time (from RAM)

– 5 µs wakeup time (from Flash memory)

Core: ARM

®

32-bit Cortex

®

-M0+ with MPU

– From 32 kHz up to 32 MHz max.

– 0.95 DMIPS/MHz

Reset and supply management

– Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds

– Ultra-low-power POR/PDR

– Programmable voltage detector (PVD)

Clock sources

– 1 to 25 MHz crystal oscillator

– 32 kHz oscillator for RTC with calibration

– High speed internal 16 MHz factory-trimmed RC

(+/- 1%)

– Internal low-power 37 kHz RC

– Internal multispeed low-power 65 kHz to

4.2 MHz RC

– Internal self calibration of 48 MHz RC for USB

– PLL for CPU clock

Pre-programmed bootloader

– USART, SPI supported

Development support

– Serial wire debug supported

Up to 51 fast I/Os (45 I/Os 5V tolerant)

Memories

– Up to 64 KB Flash memory with ECC

– 8KB RAM

– 2 KB of data EEPROM with ECC

– 20-byte backup register

– Sector protection against R/W operation

)%*$

UFQFPN32

5x5 mm

LQFP32 7x7 mm

LQFP48 7x7 mm

LQFP64 10x10 mm

WLCSP36

TFBGA64

5x5mm

Rich Analog peripherals

– 12-bit ADC 1.14 Msps up to 16 channels (down to 1.65 V)

– 12-bit 1 channel DAC with output buffers (down to 1.8 V)

– 2x ultra-low-power comparators (window mode and wake up capability, down to 1.8 V)

Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors

7-channel DMA controller, supporting ADC, SPI,

I2C, USART, DAC, Timers

8x peripheral communication interfaces

1x USB 2.0 crystal-less, battery charging detection and LPM

2x USART (ISO 7816, IrDA), 1x UART (low power)

2x SPI 16 Mbits/s

2x I2C (SMBus/PMBus)

9x timers: 1x 16-bit with up to 4 channels, 2x 16-bit with up to 2 channels, 1x 16-bit ultra-low-power timer, 1x SysTick, 1x RTC, 1x 16-bit basic for DAC, and 2x watchdogs (independent/window)

CRC calculation unit, 96-bit unique ID

True RNG and firewall protection

All packages are ECOPACK

®

2

Table 1. Device summary

Reference Part number

STM32L052x6

STM32L052x8

STM32L052C6

STM32L052K6

STM32L052R6

STM32L052T6

STM32L052C8

STM32L052K8

STM32L052R8

STM32L052T8

July 2015

This is information on a product in full production.

DocID025936 Rev 5 1/134

www.st.com

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Contents

Contents

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STM32L052x6 STM32L052x8

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.1

Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

2.2

Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

3.5

3.6

3.7

3.8

3.9

3.10

3.11

3.12

3.13

3.14

3.15

3.16

3.17

Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.1

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

3.2

3.3

3.4

Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

ARM® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3.4.1

3.4.2

3.4.3

Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 26

General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 26

Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.12.1

Internal voltage reference (V

REFINT

) . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 30

System configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.17.1

3.17.2

3.17.3

3.17.4

General-purpose timers (TIM2, TIM21 and TIM22) . . . . . . . . . . . . . . . . 32

Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

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3.18

3.19

3.20

3.21

3.17.5

3.17.6

Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.18.1

3.18.2

3.18.3

3.18.4

3.18.5

I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Universal synchronous/asynchronous receiver transmitter (USART) . . 34

Low-power universal asynchronous receiver transmitter (LPUART) . . . 35

Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 35

Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Clock recovery system (CRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 36

Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1

6.2

6.3

Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.1.7

Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.3.1

6.3.2

6.3.3

6.3.4

6.3.5

6.3.6

6.3.7

6.3.8

6.3.9

6.3.10

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Embedded reset and power control block characteristics . . . . . . . . . . . 57

Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

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STM32L052x6 STM32L052x8

6.3.11

6.3.12

6.3.13

6.3.14

6.3.15

6.3.16

6.3.17

6.3.18

6.3.19

6.3.20

Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

7.1

LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

7.2

7.3

7.4

7.5

7.6

7.7

UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113

LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

7.7.1

Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

4/134 DocID025936 Rev 5

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List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Ultra-low-power STM32L052x6/x8 device features and peripheral counts. . . . . . . . . . . . . 11

Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 17

CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 17

Functionalities depending on the working mode

(from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

STM32L0xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Capacitive sensing GPIOs available on STM32L052x6/8 devices . . . . . . . . . . . . . . . . . . . 31

Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

STM32L052x6/8 I

2

C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

STM32L052x6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Alternate function port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Alternate function port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Alternate function port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Alternate function port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Alternate function port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 57

Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Current consumption in Run mode, code with data processing running from Flash. . . . . . 61

Current consumption in Run mode vs code type, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Current consumption in Run mode, code with data processing running from RAM . . . . . . 63

Current consumption in Run mode vs code type, code with data processing running from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 67

Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 68

Average current consumption during Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Peripheral current consumption in Run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 70

Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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List of tables STM32L052x6 STM32L052x8

Table 62.

Table 63.

Table 64.

Table 65.

Table 66.

Table 67.

Table 68.

Table 69.

Table 70.

Table 71.

Table 72.

Table 73.

Table 74.

Table 75.

Table 76.

Table 77.

Table 78.

Table 79.

Table 80.

Table 81.

Table 46.

Table 47.

Table 48.

Table 49.

Table 50.

Table 51.

Table 52.

Table 53.

Table 54.

Table 55.

Table 56.

Table 57.

Table 58.

Table 59.

Table 60.

Table 61.

Table 82.

Table 83.

Table 84.

Table 85.

Table 86.

Table 87.

Table 88.

Table 89.

Table 90.

16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 81

EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

R

AIN

max for f

ADC

= 14 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 111

UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 117

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

WLCSP36 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 125

Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

STM32L052x6/8 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

6/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

List of figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

Figure 37.

Figure 38.

Figure 39.

Figure 40.

Figure 41.

Figure 42.

STM32L052x6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

STM32L052x6/8 WLCSP36 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

STM32L052x6/8 LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

STM32L052x6/8 UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

STM32L052x6/8 LQFP48 pinout - 7 x 7 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

STM32L052x6/8 LQFP64 pinout - 10 x 10 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

STM32L052x6/8 TFBGA64 ballout - 5x 5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from

Flash memory, Range 2, HSE, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from

Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Low-power run mode, code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled, all clocks off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 77

VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Power supply and reference decoupling (V

REF+

Power supply and reference decoupling (V

REF+ not connected to V

DDA connected to V

DDA

). . . . . . . . . . . . . . 95

). . . . . . . . . . . . . . . . . 95

12-bit buffered/non-buffered DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

I

SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

SPI timing diagram - slave mode and CPHA = 1

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

SPI timing diagram - master mode

2

I

2

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

S slave timing diagram (Philips protocol)

(1)

S master timing diagram (Philips protocol)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

(1)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 109

LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 110

LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 111

LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

DocID025936 Rev 5 7/134

8

List of figures STM32L052x6 STM32L052x8

Figure 43.

Figure 44.

Figure 45.

Figure 46.

Figure 47.

Figure 48.

Figure 49.

Figure 50.

Figure 51.

Figure 52.

Figure 53.

Figure 54.

Figure 55.

Figure 56.

UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 116

LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 118

LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 119

LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 120

LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball

,grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

TFBGA64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

8/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

1 Introduction

The ultra-low-power STM32L052x6/8 are offered in 6 different package types: from 32 pins to 64 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family.

These features make the ultra-low-power STM32L052x6/8 microcontrollers suitable for a wide range of applications:

Gas/water meters and industrial sensors

Healthcare and fitness equipment

Remote control and user interface

PC peripherals, gaming, GPS equipment

Alarm system, wired and wireless sensors, video intercom

This STM32L052x6/8 datasheet should be read in conjunction with the STM32L0x2xx reference manual (RM0376)

.

For information on the ARM

®

Cortex

®

-M0+ core please refer to the Cortex

Reference Manual, available from the www.arm.com website.

®

-M0+ Technical

Figure 1

shows the general block diagram of the device family.

DocID025936 Rev 5 9/134

36

Description

2 Description

STM32L052x6 STM32L052x8

The ultra-low-power STM32L052x6/8 microcontrollers incorporate the connectivity power of the universal serial bus (USB 2.0 crystal-less) with the high-performance ARM

®

Cortex

®

-

M0+ 32-bit RISC core operating at a 32 MHz frequency, a memory protection unit (MPU), high-speed embedded memories (64 Kbytes of Flash program memory, 2 Kbytes of data

EEPROM and 8 Kbytes of RAM) plus an extensive range of enhanced I/Os and peripherals.

The STM32L052x6/8 devices provide high power efficiency for a wide range of performance. It is achieved with a large choice of internal and external clock sources, an internal voltage adaptation and several low-power modes.

The STM32L052x6/8 devices offer several analog features, one 12-bit ADC with hardware oversampling, one DAC, two ultra-low-power comparators, several timers, one low-power timer (LPTIM), three general-purpose 16-bit timers and one basic timer, one RTC and one

SysTick which can be used as timebases. They also feature two watchdogs, one watchdog with independent clock and window capability and one window watchdog based on bus clock.

Moreover, the STM32L052x6/8 devices embed standard and advanced communication interfaces: up to two I2Cs, two SPIs, one I2S, two USARTs, a low-power UART (LPUART), and a crystal-less USB. The devices offer up to 24 capacitive sensing channels to simply add touch sensing functionality to any application.

The STM32L052x6/8 also include a real-time clock and a set of backup registers that remain powered in Standby mode.

The ultra-low-power STM32L052x6/8 devices operate from a 1.8 to 3.6 V power supply

(down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without

BOR option. They are available in the -40 to +125 °C temperature range. A comprehensive set of power-saving modes allows the design of low-power applications.

10/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 2. Ultra-low-power STM32L052x6/x8 device features and peripheral counts

Peripheral

STM32L

052T6

STM32

L052K6

STM32

L052C6

STM32

L052R6

STM32L

052T8

STM32

L052K8

STM32

L052C8

STM32

L052R8

Flash (Kbytes)

Data EEPROM (Kbytes)

RAM (Kbytes)

Generalpurpose

Timers

Basic

LPTIMER

RTC/SYSTICK/IWDG/

WWDG

SPI/(I2S)

I

2

C

Communic ation interfaces

USART

LPUART

USB/

(VDD_USB)

GPIOs

Clocks:

HSE/LSE/HSI/MSI/LSI

12-bit synchronized

ADC

Number of channels

12-bit DAC

Number of channels

Comparators

Capacitive sensing channels

Max. CPU frequency

Operating voltage

1/(0)

2

1

29

0/1/1/1/1

1

10

1/(0)

14

1/(0)

27

1

0

1

(1)

10

32

2

8

3

1

1

1/1/1/1

2

1

1

2/(1)

37

1

10

17

2

1

1/(1)

1/(1)

51

1

16

24

(2)

1/(1)

2

1

29

1

10

1/(0)

1/(0)

27

1

0

1

(1)

10

64

2

8

3

1

1

1/1/1/1

2

1

1

37

1

10

2/(1)

32 MHz

1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option

1.65 V to 3.6 V without BOR option

2

1

1/(1)

51

(2)

0/1/1/1/1 1/1/1/1/1 1/1/1/1/1 0/1/1/1/1 0/1/1/1/1 1/1/1/1/1 1/1/1/1/1

(2)

(2)

2

14 17

16

24

1

(2)

(2)

DocID025936 Rev 5 11/134

36

Description STM32L052x6 STM32L052x8

Table 2. Ultra-low-power STM32L052x6/x8 device features and peripheral counts (continued)

Peripheral

STM32L

052T6

STM32

L052K6

STM32

L052C6

STM32

L052R6

STM32L

052T8

STM32

L052K8

STM32

L052C8

STM32

L052R8

Operating temperatures

Packages

WLCSP

36

LQFP32,

UFQFPN

32

Ambient temperature: –40 to +125 °C

Junction temperature: –40 to +130 °C

LQFP48

LQFP64

TFBGA

64

WLCSP

36

LQFP32,

UFQFPN

32

1. LQFP32 has two GPIOs, less than UFQFPN32 (27).

2. TFBGA64 has one GPIO, one ADC input and one capacitive sensing channel less than LQFP64.

LQFP48

LQFP64

TFBGA

64

12/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Figure 1. STM32L052x6/8 block diagram

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DocID025936 Rev 5 13/134

36

Description

2.2

STM32L052x6 STM32L052x8

Ultra-low-power device continuum

The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary core up to ARM

®

Cortex

®

-M4, including ARM

®

Cortex

®

-M3 and ARM

®

Cortex

®

-M0+. The

STM32Lx series are the best choice to answer your needs in terms of ultra-low-power features. The STM32 ultra-low-power series are the best solution for applications such as gaz/water meter, keyboard/mouse or fitness and healthcare application. Several built-in features like LCD drivers, dual-bank memory, low-power run mode, operational amplifiers,

128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all

STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to respond to the latest market feature and efficiency requirements.

14/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

The ultra-low-power STM32L052x6/8 support dynamic voltage scaling to optimize its power consumption in Run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system’s maximum operating frequency and the external voltage supply.

There are three power consumption ranges:

Range 1 (V

DD

range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz

Range 2 (full V

DD

range), with a maximum CPU frequency of 16 MHz

Range 3 (full V

DD

range), with a maximum CPU frequency limited to 4.2 MHz

Seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:

Sleep mode

In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at

16 MHz is about 1 mA with all peripherals off.

Low-power run mode

This mode is achieved with the multispeed internal (MSI) RC oscillator set to the lowspeed clock (max 131 kHz), execution from SRAM or Flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. In Lowpower run mode, the clock frequency and the number of enabled peripherals are both limited.

Low-power sleep mode

This mode is achieved by entering Sleep mode with the internal voltage regulator in low-power mode to minimize the regulator’s operating current. In Low-power sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz.

When wakeup is triggered by an event or an interrupt, the system reverts to the Run mode with the regulator on.

Stop mode with RTC

The Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the V

CORE domain are stopped, the

PLL, MSI RC, HSE crystal and HSI RC oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low-power mode.

Some peripherals featuring wakeup capability can enable the HSI RC during Stop mode to detect their wakeup condition.

The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or resume the code. The EXTI line source can be any

GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event

DocID025936 Rev 5 15/134

36

Functional overview

Note:

STM32L052x6 STM32L052x8

(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup events, the USB/USART/I2C/LPUART/LPTIMER wakeup events.

Stop mode without RTC

The Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and

LSE crystal oscillators are disabled.

Some peripherals featuring wakeup capability can enable the HSI RC during Stop mode to detect their wakeup condition.

The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB/USART/I2C/LPUART/LPTIMER wakeup events.

Standby mode with RTC

The Standby mode is used to achieve the lowest power consumption and real time clock. The internal voltage regulator is switched off so that the entire V

CORE

domain is powered off. The PLL, MSI RC, HSE crystal and HSI RC oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,

RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).

The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),

RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.

Standby mode without RTC

The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire V

CORE

domain is powered off. The

PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off.

After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).

The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising edge on one of the three WKUP pin occurs.

The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by entering Stop or Standby mode.

16/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 3. Functionalities depending on the operating power supply range

Functionalities depending on the operating power supply range

Operating power supply range DAC and ADC operation

Dynamic voltage scaling range

I/O operation USB

V

DD

= 1.65 to 1.71 V

ADC only, conversion time up to 570 ksps

Range 2 or range 3

V

DD

= 1.71 to 1.8 V

(1)

ADC only, conversion time up to 1.14 Msps

Range 1, range 2 or range 3

Degraded speed performance

Degraded speed performance

Not functional

Functional

(2)

V

DD

= 1.8 to 2.0 V

(1)

Conversion time up to 1.14 Msps

Range1, range 2 or range 3

Degraded speed performance

Functional

(2)

V

V

DD

DD

= 2.0 to 2.4 V

= 2.4 to 3.6 V

Conversion time up to

1.14 Msps

Range 1, range 2 or range 3

Conversion time up to

1.14 Msps

Range 1, range 2 or range 3

Full speed operation

Full speed operation

Functional

Functional

1. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5

μ s delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2

MHz to 16 MHz, wait 5 μ s, then switch from 16 MHz to 32 MHz.

2. To be USB compliant from the I/O voltage standpoint, the minimum V

DD_USB is 3.0 V.

(2)

(2)

Table 4. CPU frequency range depending on dynamic voltage scaling

CPU frequency range Dynamic voltage scaling range

16 MHz to 32 MHz (1ws)

32 kHz to 16 MHz (0ws)

8 MHz to 16 MHz (1ws)

32 kHz to 8 MHz (0ws)

32 kHz to 4.2 MHz (0ws)

Range 1

Range 2

Range 3

DocID025936 Rev 5 17/134

36

Functional overview STM32L052x6 STM32L052x8

IPs

CPU

Flash memory

RAM

Backup registers

EEPROM

Brown-out reset

(BOR)

DMA

Programmable

Voltage Detector

(PVD)

Power-on/down reset (POR/PDR)

High Speed

Internal (HSI)

High Speed

External (HSE)

Low Speed Internal

(LSI)

Low Speed

External (LSE)

Multi-Speed

Internal (MSI)

Inter-Connect

Controller

RTC

RTC Tamper

Auto WakeUp

(AWU)

USB

USART

LPUART

SPI

I2C

ADC

DAC

Y

O

O

O

O

O

O

O

O

O

O

Table 5. Functionalities depending on the working mode

(from Run/active down to standby)

(1)

Stop

Run/Active Sleep

Lowpower run

Lowpower sleep

Wakeup capability

Y

Y

Y

O

O

Y

Y

--

O

O

Y

Y

Y

O

O

Y

Y

--

O

O

Y

Y

--

--

--

O

O

O

O

O

O

O

O

O

--

O O

--

--

Y

--

--

--

Standby

Wakeup capability

O

O

Y

O

O

O

O

O

O

Y

O

O

O

O

O

Y

O

O

O

O

O

O

O

O

O

O

O

Y

--

O

O

O

Y

Y

O

O

O

O

O

O

--

O

--

O

O

Y

--

O

O

O

Y

O

Y

(2)

--

O

O

--

Y

O

O

O

--

O

(3)

O

(3)

--

O

(4)

--

O

Y

O

O

O

O

O

O

--

O

--

O

O

Y

O

O

O

O

O

O

O

-

Y

--

--

O

O

--

--

O

O

O

--

--

--

--

--

--

--

Y

O

O

18/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

IPs

Table 5. Functionalities depending on the working mode

(from Run/active down to standby) (continued)

(1)

Stop

Run/Active Sleep

Lowpower run

Lowpower sleep

Wakeup capability

Standby

Wakeup capability

Temperature sensor

Comparators

16-bit timers

LPTIMER

IWDG

WWDG

Touch sensing controller (TSC)

SysTick Timer

GPIOs

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

--

O

O

O

O

O

O

--

O

O

--

O

O

--

--

O

O

O

--

--

--

O

--

--

O

O

O

O

O

O

O

O

O O O

--

2 pins

Wakeup time to

Run mode

0 µs 0.36 µs 3 µs 32 µs 3.5 µs 50 µs

Consumption

V

DD

=1.8 to 3.6 V

(Typ)

Down to

140 µA/MHz

(from Flash memory)

Down to

37 µA/MHz

(from Flash memory)

Down to

8 µA

Down to

4.5 µA

0.4 µA (No

RTC) V

DD

=1.8 V

0.8 µA (with

RTC) V

DD

=1.8 V

0.4 µA (No

RTC) V

DD

=3.0 V

1 µA (with RTC)

V

DD

=3.0 V

0.28 µA (No

RTC) V

DD

=1.8 V

0.65 µA (with

RTC) V

DD

=1.8 V

0.29 µA (No

RTC) V

DD

=3.0 V

0.85 µA (with

RTC) V

DD

=3.0 V

1. Legend:

“Y” = Yes (enable).

“O” = Optional can be enabled/disabled by software)

“-” = Not available

2. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need it anymore.

3. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start.To generate a wakeup on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep running the HSI clock.

4. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up the HSI during reception.

Several peripherals are directly interconnected. This allows autonomous communication between peripherals, thus saving CPU resources and power consumption. In addition, these hardware connections allow fast and predictable latency.

Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power run, Low-power sleep and Stop modes.

DocID025936 Rev 5 19/134

36

Functional overview STM32L052x6 STM32L052x8

Interconnect source

COMPx

RTC

All clock source

GPIO

Table 6. STM32L0xx peripherals interconnect matrix

Interconnect destination

Interconnect action Run Sleep

Low- power run

Low- power sleep

Stop

TIM2,TIM21,

TIM22

LPTIM

TIMx TIMx

TIM21

LPTIM

TIMx

USB CRS/HSI48

TIMx

LPTIM

ADC,DAC

Timer input channel, trigger from analog signals comparison

Timer input channel, trigger from analog signals comparison

Timer triggered by other timer

Timer triggered by Auto wake-up

Timer triggered by RTC event

Clock source used as input channel for RC measurement and trimming the clock recovery system trims the HSI48 based on USB SOF

Timer input channel and trigger

Timer input channel and trigger

Conversion trigger

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

Y

-

Y

Y

Y

Y

Y

Y

Y

Y

Y

-

Y

Y

Y -

-

Y

Y

-

-

-

-

-

Y

3.3 ARM

®

Cortex

®

-M0+ core with MPU

The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a broad range of embedded applications. It offers significant benefits to developers, including: a simple architecture that is easy to learn and program ultra-low power, energy-efficient operation excellent code density deterministic, high-performance interrupt handling upward compatibility with Cortex-M processor family platform security robustness, with integrated Memory Protection Unit (MPU).

The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor core, with a 2-stage pipeline von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware including a single-cycle multiplier.

20/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

The Cortex-M0+ processor provides the exceptional performance expected of a modern 32bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.

Owing to its embedded ARM core, the STM32L052x6/8 are compatible with all ARM tools and software.

Nested vectored interrupt controller (NVIC)

The ultra-low-power STM32L052x6/8 embed a nested vectored interrupt controller able to handle up to 32 maskable interrupt channels and 4 priority levels.

The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt

Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC: includes a Non-Maskable Interrupt (NMI) provides zero jitter interrupt option provides four interrupt priority levels

The tight integration of the processor core and NVIC provides fast execution of Interrupt

Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to abandon and restart loadmultiple and store-multiple operations. Interrupt handlers do not require any assembler wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also significantly reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to enter rapidly stop or standby mode.

This hardware block provides flexible interrupt management features with minimal interrupt latency.

3.4

3.4.1

3.4.2

Reset and supply management

Power supply schemes

V

DD

= 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through V

DD

pins.

V

SSA

, V

DDA

= 1.65 to 3.6 V: external analog power supplies for ADC, DAC, reset blocks, RCs and PLL (minimum voltage to be applied to V

DDA used). V

DDA

and V

SSA

must be connected to V

DD

and V

SS

is 1.8 V when the DAC is

, respectively.

V

DD_USB

= 1.65 to 3.6V: external power supply for USB transceiver, USB_DM (PA11) and USB_DP (PA12). To guarantee a correct voltage level for USB communication

V

DD_USB

must be above 3.0V. If USB is not used this pin must be tied to V

DD

.

Power supply supervisor

The deviceshave an integrated ZEROPOWER power-on reset (POR)/power-down reset

(PDR) that can be coupled with a brownout reset (BOR) circuitry.

Two versions are available:

The version with BOR activated at power-on operates between 1.8 V and 3.6 V.

The other version without BOR operates between 1.65 V and 3.6 V.

DocID025936 Rev 5 21/134

36

Functional overview

Note:

STM32L052x6 STM32L052x8

After the V

DD

threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or not at power-on), the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes

1.65 V (whatever the version, BOR active or not, at power-on).

When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the power ramp-up should guarantee that 1.65 V is reached on V

DD the POR area.

at least 1 ms after it exits

Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (V

REFINT

V

DD reset circuit.

) in Stop mode. The device remains in reset mode when

is below a specified threshold, V

POR/PDR

or V

BOR

, without the need for any external

The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive at power-up.

The devices feature an embedded programmable voltage detector (PVD) that monitors the

V

DD/VDDA

power supply and compares it to the V

PVD

threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when V

V

DD/VDDA

is higher than the V

PVD

DD/VDDA

drops below the V

PVD

threshold and/or when

threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.

The regulator has three operation modes: main (MR), low power (LPR) and power down.

MR is used in Run mode (nominal regulation)

LPR is used in the Low-power run, Low-power sleep and Stop modes

Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,

LSI, LSE crystal 32 KHz oscillator, RCC_CSR).

22/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

Clock prescaler

To get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.

Safe clock switching

Clock sources can be changed safely on the fly in Run mode through a configuration register.

Clock management

To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.

System clock source

Three different clock sources can be used to drive the master clock SYSCLK:

– 1-25 MHz high-speed external crystal (HSE), that can supply a PLL

16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL

Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).

When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a ±0.5% accuracy.

Auxiliary clock source

Two ultra-low-power clock sources that can be used to drive the real-time clock:

32.768 kHz low-speed external crystal (LSE)

37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.

The LSI clock can be measured using the high-speed internal RC oscillator for greater precision.

RTC clock source

The LSI, LSE or HSE sources can be chosen to clock the RTC, whatever the system clock.

USB clock source

A 48 MHz clock trimmed through the USB SOF supplies the USB interface.

Startup clock

After reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI).

The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.

Clock security system (CSS)

This feature can be enabled by software. If an HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled.

Another clock security system can be enabled, in case of failure of the LSE it provides an interrupt or wakeup event which is generated if enabled.

DocID025936 Rev 5 23/134

36

Functional overview STM32L052x6 STM32L052x8

Clock-out capability (MCO: microcontroller clock output)

It outputs one of the internal clocks for external use by the application.

Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and

APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See

Figure 2

for details on the clock tree.

24/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

#9

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DocID025936 Rev 5 25/134

36

Functional overview STM32L052x6 STM32L052x8

3.7

26/134

The real time clock (RTC) and the 5 backup registers are supplied in all modes including standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user application data. They are not reset by a system reset, or when the device wakes up from

Standby mode.

The RTC is an independent BCD timer/counter. Its main features are the following:

Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format

Automatically correction for 28, 29 (leap year), 30, and 31 day of the month

Two programmable alarms with wake up from Stop and Standby mode capability

Periodic wakeup from Stop and Standby with programmable resolution and period

On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock.

Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision.

Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy

2 anti-tamper detection pins with programmable filter. The MCU can be woken up from

Stop and Standby modes on tamper event detection.

Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.

The RTC clock sources can be:

A 32.768 kHz external crystal

A resonator or oscillator

The internal low-power RC oscillator (typical frequency of 37 kHz)

The high-speed external clock

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated alternate function registers. All GPIOs are high current capable.

Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated

IO bus with a toggling speed of up to 32 MHz.

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 28 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event

(rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected to the 16 configurable interrupt/event lines. The 12 other lines are connected to PVD, RTC,

USB, USARTs, LPUART, LPTIMER or comparator events.

DocID025936 Rev 5

STM32L052x6 STM32L052x8

3.8 Memories

The STM32L052x6/8 deviceshave the following features:

8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses).

The non-volatile memory is divided into three arrays:

– 32 or 64 Kbytes of embedded Flash program memory

2 Kbytes of data EEPROM

Information block containing 32 user and factory options bytes plus 4 Kbytes of system memory

The user options bytes are used to write-protect or read-out protect the memory (with

4 Kbyte granularity) and/or readout-protect the whole memory with the following options:

Level 0

Level 1

: no protection

: memory readout protected.

The Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected

Level 2

: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in

RAM selection disabled (debugline fuse)

The firewall protects parts of code/data from access by the rest of the code that is executed outside of the protected area. The granularity of the protected code segment or the nonvolatile data segment is 256 bytes (Flash memory or EEPROM) against 64 bytes for the volatile data segment (RAM).

The whole non-volatile memory embeds the error correction code (ECC) feature.

At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options:

Boot from Flash memory

Boot from System memory

Boot from embedded RAM

The boot loader is located in System memory. It is used to reprogram the Flash memory by using USART1(PA9, PA10), SPI1(PA4, PA5, PA6, PA7) or SPI2(PB12, PB13, PB14, PB15) and USART2(PA2, PA3). See STM32™ microcontroller system memory boot mode

AN2606 for details.

The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.

Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.

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36

Functional overview STM32L052x6 STM32L052x8

The DMA can be used with the main peripherals: SPI, I

2

C, USART, LPUART, general-purpose timers, DAC, and ADC.

3.11 Analog-to-digital converter (ADC)

A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital converter is embedded into STM32L052x6/8 device. It has up to 16 external channels and 3 internal channels (temperature sensor, voltage reference). It performs conversions in singleshot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs.

The ADC frequency is independent from the CPU frequency, allowing maximum sampling rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all frequencies (~25 µA at 10 kSPS, ~200 µA at 1MSPS). An auto-shutdown function guarantees that the ADC is powered off except during the active conversion phase.

The ADC can be served by the DMA controller. It can operate from a supply voltage down to

1.65 V.

The ADC features a hardware oversampler up to 256 samples, this improves the resolution to 16 bits (see AN2668).

An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all scanned channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.

The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start triggers, to allow the application to synchronize A/D conversions and timers.

The temperature sensor (T

SENSE temperature.

) generates a voltage V

SENSE that varies linearly with

The temperature sensor is internally connected to the ADC_IN18 input channel which is used to convert the sensor output voltage into a digital value.

The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.

To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.

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STM32L052x6 STM32L052x8

3.12.1

Table 7. Temperature sensor calibration values

Calibration value name Description Memory address

TSENSE_CAL1

TSENSE_CAL2

TS ADC raw data acquired at temperature of 30 °C,

V

DDA

= 3 V

TS ADC raw data acquired at temperature of 130 °C

V

DDA

= 3 V

0x1FF8 007A - 0x1FF8 007B

0x1FF8 007E - 0x1FF8 007F

Internal voltage reference (V

REFINT

)

The internal voltage reference (V

REFINT

ADC and Comparators. V

REFINT enables accurate monitoring of the V

DD

) provides a stable (bandgap) voltage output for the

is internally connected to the ADC_IN17 input channel. It

value (when no external voltage, V

REF+ for ADC). The precise voltage of V

REFINT

, is available

is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.

Table 8. Internal voltage reference measured values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at temperature of 30 °C

V

DDA

= 3 V

0x1FF8 0078 - 0x1FF8 0079

One 12-bit buffered DAC can be used to convert digital signal into analog voltage signal output. An optional amplifier can be used to reduce the output signal impedance.

This digital Interface supports the following features:

One data holding register

Left or right data alignment in 12-bit mode

Synchronized update capability

Noise-wave generation

Triangular-wave generation

DMA capability (including the underrun interrupt)

External triggers for conversion

Input reference voltage V

REF+

Four DAC trigger inputs are used in the STM32L052x6/8. The DAC channel is triggered through the timer update outputs that are also connected to different DMA channels.

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36

Functional overview

3.14

STM32L052x6 STM32L052x8

Ultra-low-power comparators and reference voltage

The STM32L052x6/8 embed two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O).

One comparator with ultra low consumption

One comparator with rail-to-rail inputs, fast or slow mode.

The threshold can be one of the following:

DAC output

External I/O pins

Internal reference voltage (V

REFINT

) submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail comparator.

Both comparators can wake up the devices from Stop mode, and be combined into a window comparator.

The internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 µA typical).

3.16

The system configuration controller provides the capability to remap some alternate functions on different I/O ports.

The highly flexible routing interface allows the application firmware to control the routing of different I/Os to the TIM2, TIM21, TIM22 and LPTIM timer input captures. It also controls the routing of internal analog signals to the USB internal oscillator, ADC, COMP1 and COMP2 and the internal reference voltage V

REFINT

.

Touch sensing controller (TSC)

The STM32L052x6/8 provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.

Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (such as glass, plastic). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage, this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.

The touch sensing controller is fully supported by the STMTouch touch sensing firmware library, which is free to use and allows touch sensing functionality to be implemented reliably in the end application.

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STM32L052x6 STM32L052x8

Table 9. Capacitive sensing GPIOs available on STM32L052x6/8 devices

Group

Capacitive sensing signal name

Pin name

Group

Capacitive sensing signal name

Pin name

1

2

3

4

TSC_G1_IO1

TSC_G1_IO2

TSC_G1_IO3

TSC_G1_IO4

TSC_G2_IO1

TSC_G2_IO2

TSC_G2_IO3

TSC_G2_IO4

TSC_G3_IO1

TSC_G3_IO2

TSC_G3_IO3

TSC_G3_IO4

TSC_G4_IO1

TSC_G4_IO2

TSC_G4_IO3

TSC_G4_IO4

PA7

PC5

PB0

PB1

PB2

PA9

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA10

PA11

PA12

5

6

7

8

TSC_G5_IO1

TSC_G5_IO2

TSC_G5_IO3

TSC_G5_IO4

TSC_G6_IO1

TSC_G6_IO2

TSC_G6_IO3

TSC_G6_IO4

TSC_G7_IO1

TSC_G7_IO2

TSC_G7_IO3

TSC_G7_IO4

TSC_G8_IO1

TSC_G8_IO2

TSC_G8_IO3

TSC_G8_IO4

PB14

PC0

PC1

PC2

PC3

PC6

PB3

PB4

PB6

PB7

PB11

PB12

PB13

PC7

PC8

PC9

3.17 Timers and watchdogs

The ultra-low-power STM32L052x6/8 devices include three general-purpose timers, one low- power timer (LPTIM), one basic timer, two watchdog timers and the SysTick timer.

Table 10

compares the features of the general-purpose and basic timers.

Timer

TIM2

TIM21,

TIM22

TIM6

Counter resolution

16-bit

16-bit

16-bit

Table 10. Timer feature comparison

Counter type Prescaler factor

DMA request generation

Capture/compare channels

Complementary outputs

Up, down, up/down

Up, down, up/down

Up

Any integer between

1 and 65536

Any integer between

1 and 65536

Any integer between

1 and 65536

Yes

No

Yes

4

2

0

No

No

No

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36

Functional overview STM32L052x6 STM32L052x8

There are three synchronizable general-purpose timers embedded in the STM32L052x6/8

devices (see

Table 10

for differences).

TIM2

TIM2 is based on 16-bit auto-reload up/down counter. It includes a 16-bit prescaler. It features four independent channels each for input capture/output compare, PWM or onepulse mode output.

The TIM2 general-purpose timers can work together or with the TIM21 and TIM22 generalpurpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs.

TIM2 has independent DMA request generation.

This timer is capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors.

TIM21 and TIM22

TIM21 and TIM22 are based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. They have two independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together and be synchronized with the TIM2, fullfeatured general-purpose timers.

They can also be used as simple time bases and be clocked by the LSE clock source

(32.768 kHz) to provide time bases independent from the main CPU clock.

3.17.3

The low-power timer has an independent clock and is running also in Stop mode if it is clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.

This low-power timer supports the following features:

16-bit up counter with 16-bit autoreload register

16-bit compare register

Configurable output: pulse, PWM

Continuous / one shot mode

Selectable software / hardware input trigger

Selectable clock source

Internal clock source: LSE, LSI, HSI or APB clock

External clock source over LPTIM input (working even with no internal clock source running, used by the Pulse Counter Application)

Programmable digital glitch filter

Encoder mode

Basic timer (TIM6)

This timer can be used as a generic 16-bit timebase. It is mainly used for DAC trigger generation.

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STM32L052x6 STM32L052x8

This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit downcounter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches ‘0’.

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode.

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.

3.18.1 I

2

C bus

Up to two I

2

C interfaces (I2C1, I2C2) can operate in multimaster or slave modes. All I

2

C interfaces can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to

400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.

All I

2

C interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses

(2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.

Pulse width of suppressed spikes

Benefits

Drawbacks

Table 11. Comparison of I2C analog and digital filters

Analog filter Digital filter

≥ 50 ns

Available in Stop mode

Variations depending on temperature, voltage, process

Programmable length from 1 to 15

I2C peripheral clocks

1. Extra filtering capability vs. standard requirements.

2. Stable length

Wakeup from Stop on address match is not available when digital filter is enabled.

In addition, I2C1 provides hardware support for SMBus 2.0 and PMBus 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and

ALERT protocol management. I2C1 also has a clock domain independent from the CPU clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.

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Functional overview STM32L052x6 STM32L052x8

All I2C interfaces can be served by the DMA controller.

Refer to

Table 12

for the differences between I2C interfaces.

Table 12. STM32L052x6/8 I

2

C implementation

I2C features

(1)

I2C1

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

1. X = supported.

2. See for the list of I/Os that feature Fast Mode Plus capability

X

X

X

X

X

X

X

X

I2C2

X

X

X

X

X

(2)

-

-

-

34/134

The two USART interfaces (USART1, USART2) are able to communicate at speeds of up to

4 Mbit/s.

They provide hardware management of the CTS, RTS and RS485 driver enable (DE) signals, multiprocessor communication mode, master synchronous communication and single-wire half-duplex communication mode. They also support SmartCard communication

(ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has a clock domain independent from the CPU clock, allowing to wake up the MCU from Stop mode.

All USART interfaces can be served by the DMA controller.

Table 13

for the supported modes and features of USART interfaces.

Table 13. USART implementation

USART modes/features

(1)

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain and wakeup from Stop mode

Receiver timeout interrupt

USART1 and USART2

X

X

X

X

X

X

X

X

X

X

DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 13. USART implementation (continued)

USART modes/features

(1)

USART1 and USART2

Modbus communication

Auto baud rate detection (4 modes)

Driver Enable

1. X = supported.

X

X

X

3.18.4

The devices embed one Low-power UART. The LPUART supports asynchronous serial communication with minimum power consumption. It supports half duplex single wire communication and modem operations (CTS/RTS). It allows multiprocessor communication.

The LPUART has a clock domain independent from the CPU clock, and can wake up the system from Stop mode. The Wakeup events from Stop mode are programmable and can be:

Start bit detection

Or any received data frame

Or a specific programmed data frame

Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600 baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while having an extremely low energy consumption. Higher speed clock can be used to reach higher baudrates.

LPUART interface can be served by the DMA controller.

Serial peripheral interface (SPI)/Inter-integrated sound (I2S)

Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes.

One standard I2S interfaces (multiplexed with SPI2) is available. It can operate in master or slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When the

I2S interfaces is configured in master mode, the master clock can be output to the external

DAC/CODEC at 256 times the sampling frequency.

The SPIs can be served by the DMA controller.

Refer to

Table 14

for the differences between SPI1 and SPI2.

Hardware CRC calculation

I2S mode

TI mode

1. X = supported.

Table 14. SPI/I2S implementation

SPI features

(1)

SPI1

X

-

X

SPI2

X

X

X

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36

Functional overview STM32L052x6 STM32L052x8

The STM32L052x6/8 embed a full-speed USB device peripheral compliant with the USB specification version 2.0. The internal USB PHY supports USB FS signaling, embedded DP pull-up and also battery charging detection according to Battery Charging Specification

Revision 1.2. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has software-configurable endpoint setting with packet memory up to 1 KB and suspend/resume support. It requires a precise

48 MHz clock which can be generated from the internal main PLL (the clock source must use a HSE crystal oscillator) or by the internal 48 MHz oscillator in automatic trimming mode. The synchronization for this oscillator can be taken from the USB data stream itself

(SOF signalization) which allows crystal-less operation.

The STM32L052x6/8 embed a special block which allows automatic trimming of the internal

48 MHz oscillator to guarantee its optimal accuracy over the whole device operational range. This automatic trimming is based on the external synchronization signal, which could be either derived from USB SOF signalization, from LSE oscillator, from an external signal on CRS_SYNC pin or generated by user software. For faster lock-in during startup it is also possible to combine automatic trimming with manual trimming action.

3.21

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.

Serial wire debug port (SW-DP)

An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected to the MCU.

36/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Figure 3. STM32L052x6/8 WLCSP36 ballout

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DocID025936 Rev 5 37/134

50

Pin descriptions STM32L052x6 STM32L052x8

Figure 5. STM32L052x6/8 UFQFPN32 pinout

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2. I/O pin supplied by VDD_USB.

DocID025936 Rev 5

STM32L052x6 STM32L052x8

Figure 7. STM32L052x6/8 LQFP64 pinout - 10 x 10 mm

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DocID025936 Rev 5 39/134

50

Pin descriptions STM32L052x6 STM32L052x8

Figure 8. STM32L052x6/8 TFBGA64 ballout - 5x 5 mm

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Table 15. Legend/abbreviations used in the pinout table

Name Abbreviation Definition

Pin name

Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name

Pin type

I/O structure

Notes

I/O

FT

FTf

Input / output pin

5 V tolerant I/O

5 V tolerant I/O, FM+ capable

TC

B

Standard 3.3V I/O

Dedicated BOOT0 pin

RST Bidirectional reset pin with embedded weak pull-up resistor

Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset.

40/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 15. Legend/abbreviations used in the pinout table (continued)

Name Abbreviation Definition

Pin functions

Alternate functions

Additional functions

Functions selected through GPIOx_AFR registers

Functions directly selected/enabled through peripheral registers

Pin Number

Table 16. STM32L052x6/8 pin definitions

Pin name

(function after reset)

Alternate functions

Additional functions

-

-

-

-

4

-

2

3

-

-

-

-

-

-

-

-

2

3

-

4

A6

B6

-

-

-

-

C6

-

-

-

1

2

3

4

5

6

7

-

-

-

6

7

1

2

3

4

5

8

9

10

B2

A2

VDD

PC13

S

I/O

-

FT -

-

-

-

RTC_TAMP1/

RTC_TS/RTC

_OUT/WKUP2

A1

B1

C1

D1

E1

PC14-

OSC32_IN

(PC14)

PC15-

OSC32_OUT

(PC15)

PH0-OSC_IN

(PH0)

PH1-OSC_OUT

(PH1)

NRST

I/O

I/O

I/O

I/O

I/O

FT

TC

TC

TC

RST

E3

E2

F2

PC0

PC1

PC2

I/O

I/O

I/O

FT

FT

FT

-

-

-

-

-

-

USB_CRS_SYNC

-

-

-

-

-

LPTIM1_IN1,

EVENTOUT,

TSC_G7_IO1

LPTIM1_OUT,

EVENTOUT,

TSC_G7_IO2

LPTIM1_IN2,

SPI2_MISO/I2S2_MC

K, TSC_G7_IO3

OSC32_IN

OSC32_OUT

OSC_IN

OSC_OUT

-

ADC_IN10

ADC_IN11

ADC_IN12

DocID025936 Rev 5 41/134

50

Pin descriptions STM32L052x6 STM32L052x8

Pin Number

Table 16. STM32L052x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

-

-

-

5

11 -

-

-

5

-

E6

D5

8

-

9

12

-

13

F1

G1

H1

6

7

8

9

-

-

10

11

42/134

6

7

8

D4 10 14 G2

F6 11 15 H2

E5 12 16 F3

9 F5 13 17 G3

-

-

10

11

-

-

E4

F4

-

18

19

14 20

15 21

C2

D2

H3

F4

PC3

VSSA

VREF+

VDDA

PA3

VSS

VDD

PA0

PA1

PA2

PA4

PA5

S

S

S

S

S

I/O

I/O

I/O

I/O

I/O

I/O

I/O

-

-

-

-

-

FT

TC

FT

FT

FT

TC

TC

-

-

-

-

-

-

-

-

-

-

-

(2)

LPTIM1_ETR,

SPI2_MOSI/I2S2_SD,

TSC_G7_IO4

-

ADC_IN13

-

-

-

TIM2_CH1,

TSC_G1_IO1,

USART2_CTS,

TIM2_ETR,

COMP1_OUT

EVENTOUT,

TIM2_CH2,

TSC_G1_IO2,

USART2_RTS_DE,

TIM21_ETR

TIM21_CH1,

TIM2_CH3,

TSC_G1_IO3,

USART2_TX,

COMP2_OUT

TIM21_CH2,

TIM2_CH4,

TSC_G1_IO4,

USART2_RX

-

-

-

-

COMP1_INM6

, ADC_IN0,

RTC_TAMP2/

WKUP1

COMP1_INP,

ADC_IN1

COMP2_INM6

, ADC_IN2

COMP2_INP,

ADC_IN3

SPI1_NSS,

TSC_G2_IO1,

USART2_CK,

TIM22_ETR

SPI1_SCK,

TIM2_ETR,

TSC_G2_IO2,

TIM2_CH1

-

-

COMP1_INM4

,

COMP2_INM4

, ADC_IN4,

DAC_OUT

COMP1_INM5

,

COMP2_INM5

, ADC_IN5

DocID025936 Rev 5

STM32L052x6 STM32L052x8

Pin Number

Table 16. STM32L052x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

12

13

14 14

15 15

-

-

E2 21 29 G7 PB10

16

17

-

-

12

13

16

-

-

-

-

17

E3

F3

-

-

F2

16

-

-

20

22 G4

17 23

24

25

28

H4

H5

H6

D3 18 26 F5

C3 19 27 G5

G6

D2 22 30 H7

-

F1

23

24

31

32

D6

E5

PA6

PA7

PC4

PC5

PB0

PB1

PB2

PB11

VSS

VDD

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

I/O FT

S

S

-

-

-

-

-

-

-

-

-

-

-

-

-

SPI1_MISO,

TSC_G2_IO3,

LPUART1_CTS,

TIM22_CH1,

EVENTOUT,

COMP1_OUT

SPI1_MOSI,

TSC_G2_IO4,

TIM22_CH2,

EVENTOUT,

COMP2_OUT

EVENTOUT,

LPUART1_TX

LPUART1_RX,

TSC_G3_IO1

EVENTOUT,

TSC_G3_IO2

TSC_G3_IO3,

LPUART1_RTS_DE

LPTIM1_OUT,

TSC_G3_IO4

TIM2_CH3,

TSC_SYNC,

LPUART1_TX,

SPI2_SCK,

I2C2_SCL

EVENTOUT,

TIM2_CH4,

TSC_G6_IO1,

LPUART1_RX,

I2C2_SDA

-

-

ADC_IN6

ADC_IN7

ADC_IN14

ADC_IN15

ADC_IN8,

VREF_OUT

ADC_IN9,

VREF_OUT

-

-

-

-

-

DocID025936 Rev 5 43/134

50

Pin descriptions STM32L052x6 STM32L052x8

Pin Number

Table 16. STM32L052x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

-

-

26 34 G8 PB13

-

-

-

-

-

-

-

-

-

-

18

-

-

18

19 19

20 20

-

-

-

-

-

-

-

E1

25 33 H8

27 35 F8

-

-

28 36 F7

37 F6

-

38 E7

39 E8

40 D8

29 41 D7

D1 30 42 C7

C1 31 43 C6

PB12

PB14

PB15

PC6

PC7

PC8

PC9

PA8

PA9

PA10

I/O

I/O FTf

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

FT

FTf

FT

FT

FT

FT

FT

FT

FT

FT

-

-

-

-

-

-

-

-

-

-

-

SPI2_NSS/I2S2_WS,

LPUART1_RTS_DE,

TSC_G6_IO2,

I2C2_SMBA,

EVENTOUT

SPI2_SCK/I2S2_CK,

TSC_G6_IO3,

LPUART1_CTS,

I2C2_SCL,

TIM21_CH1

SPI2_MISO/I

2S2_MCK,

RTC_OUT,

TSC_G6_IO4,

LPUART1_RTS_DE,

I2C2_SDA,

TIM21_CH2

SPI2_MOSI/I2S2_SD,

RTC_REFIN

TIM22_CH1,

TSC_G8_IO1

TIM22_CH2,

TSC_G8_IO2

TIM22_ETR,

TSC_G8_IO3

TIM21_ETR,

USB_OE,

TSC_G8_IO4

MCO,

USB_CRS_SYNC,

EVENTOUT,

USART1_CK

MCO, TSC_G4_IO1,

USART1_TX

TSC_G4_IO2,

USART1_RX

-

-

-

-

-

-

-

-

-

-

-

44/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Pin Number

Table 16. STM32L052x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

21

22

25

-

-

-

-

26

27

21

22

25

-

-

-

-

26

27

C2

B1

A2

-

-

-

-

B3

A3

32 44

33 45

38 50

-

-

-

-

51

52

53

54

39 55

40 56

C8

B8

A6

B7

B6

C5

B5

A5

A4

PA11

PA12

PC10

PC11

PC12

PD2

(3)

(3)

23

-

-

24

23

-

-

24

A1

-

-

B2

34

35

36

37

46

47

48

49

A8

D5

E6

A7

PA13

VSS

VDD_USB

PA14

PA15

PB3

PB4

I/O FT

I/O

I/O

I/O

I/O

I/O

I/O

I/O

S

S

I/O

I/O

I/O

FT

FT

-

-

FT

FT

FT

FT

FT

FT

FT

FT

-

-

-

-

-

-

-

-

-

-

-

-

-

SPI1_MISO,

EVENTOUT,

TSC_G4_IO3,

USART1_CTS,

COMP1_OUT

SPI1_MOSI,

EVENTOUT,

TSC_G4_IO4,

USART1_RTS_DE,

COMP2_OUT

SWDIO, USB_OE

-

-

SWCLK, USART2_TX

SPI1_NSS,

TIM2_ETR,

EVENTOUT,

USART2_RX,

TIM2_CH1

LPUART1_TX

LPUART1_RX

-

LPUART1_RTS_DE

SPI1_SCK,

TIM2_CH2,

TSC_G5I_O1,

EVENTOUT

SPI1_MISO,

EVENTOUT,

TSC_G5_IO2,

TIM22_CH1

USB_DM

USB_DP

-

-

-

-

-

-

-

-

-

COMP2_INN

COMP2_INP

DocID025936 Rev 5 45/134

50

Pin descriptions STM32L052x6 STM32L052x8

Pin Number

Table 16. STM32L052x6/8 pin definitions (continued)

Pin name

(function after reset)

Alternate functions

Additional functions

28

29

30

31

-

-

32

1

28

29

30

31

32

-

-

1

C4

B4

A4

C5

B5

-

D6

A5

41

42

43

44

45

46

47

48

57

58

59

60

61

62

63

64

C4

D3

C3

B4

B3

A3

D4

E4

PB5

PB6

PB7

BOOT0

PB8

PB9

VSS

VDD

I/O

I/O

I/O

B

I/O

I/O

S

S

FT

FTf

FTf

-

FTf

FTf

-

-

-

-

-

-

-

-

-

-

SPI1_MOSI,

LPTIM1_IN1,

I2C1_SMBA,

TIM22_CH2

USART1_TX,

I2C1_SCL,

LPTIM1_ETR,

TSC_G5_IO3

USART1_RX,

I2C1_SDA,

LPTIM1_IN2,

TSC_G5_IO4

-

TSC_SYNC,

I2C1_SCL

EVENTOUT,

I2C1_SDA,

SPI2_NSS/I2S2_WS

-

-

COMP2_INP

COMP2_INP

COMP2_INP,

PVD_IN

-

-

-

-

-

1. PB9/12/13/14/15, PH0/1 and PC13 GPIOs should be configured as output and driven Low, even if they are not available on this package.

2. PA4 offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling capacitor I/O.

3. These pins are powered by VDD_USB. For all characteristics that refer to V

DD

, V

DD_USB

must be used instead.

46/134 DocID025936 Rev 5

PA1

Port A

PA6

PA7

PA8

PA9

PA2

PA3

PA4

PA5

PA10

PA11

AF0

Port

PA0

SPI1/TIM21/SYS_A

F/EVENTOUT/

-

PA12

PA13

PA14

PA15

EVENTOUT

TIM21_CH1

TIM21_CH2

SPI1_NSS

SPI1_SCK

SPI1_MISO

SPI1_MOSI

MCO

MCO

-

SPI1_MISO

SPI1_MOSI

SWDIO

SWCLK

SPI1_NSS

AF1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Table 17. Alternate function port A

AF2 AF3 AF4

USB/TIM2/

EVENTOUT/

TSC/

EVENTOUT

USART1/2/3

TIM2_CH1

TIM2_CH2

TIM2_CH3

TIM2_CH4

-

TIM2_ETR

TSC_G1_IO1 USART2_CTS

TSC_G1_IO2

USART2_RTS_

DE

TSC_G1_IO3

TSC_G1_IO4

TSC_G2_IO1

TSC_G2_IO2

USART2_TX

USART2_RX

USART2_CK

-

-

USB_CRS_SYNC

-

TSC_G2_IO3 LPUART1_CTS

TSC_G2_IO4

EVENTOUT

TSC_G4_IO1

USART1_CK

USART1_TX

-

EVENTOUT

EVENTOUT

TSC_G4_IO2 USART1_RX

TSC_G4_IO3 USART1_CTS

TSC_G4_IO4

USART1_RTS_

DE

USB_OE

-

TIM2_ETR

-

-

EVENTOUT

-

USART2_TX

USART2_RX

AF5

TIM2/21/22

TIM2_ETR

TIM21_ETR

-

-

TIM22_ETR

TIM2_CH1

TIM22_CH1

TIM22_CH2

-

-

-

-

-

-

-

TIM2_CH1

AF6 AF7

EVENTOUT COMP1/2

-

COMP1_OUT

-

EVENTOUT

EVENTOUT

-

-

-

-

-

-

-

COMP2_OUT

-

-

-

COMP1_OUT

COMP2_OUT

-

-

-

COMP1_OUT

-

-

-

COMP2_OUT

-

-

-

Port B

Port

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

PB8

PB9

PB10

PB11

PB12

AF0

SPI1/SPI2/I2S2/

USART1/

EVENTOUT/

EVENTOUT

-

-

SPI1_SCK

SPI1_MISO

SPI1_MOSI

USART1_TX

USART1_RX

-

PB13

PB14

PB15

-

-

EVENTOUT

SPI2_NSS/I2S2_WS

SPI2_SCK/I2S2_CK

SPI2_MISO/I2S2_MCK

SPI2_MOSI/I2S2_SD

-

-

-

-

I2C1_SCL

I2C1_SDA

-

-

-

-

-

-

-

-

AF1

Table 18. Alternate function port B

AF2 AF3

I2C1

-

LPUART1/LPTIM

/TIM2/SYS_AF/

EVENTOUT

-

I2C1/TSC

TSC_G3_IO2

TSC_G3_IO3

LPTIM1_OUT

TIM2_CH2

EVENTOUT

LPTIM1_IN1

LPTIM1_ETR

LPTIM1_IN2

-

EVENTOUT

TIM2_CH3

TIM2_CH4

LPUART1_RTS_

DE

-

RTC_OUT

RTC_REFIN

TSC_G3_IO4

TSC_G5I_O1

TSC_G5_IO2

I2C1_SMBA

TSC_G5_IO3

TSC_G5_IO4

TSC_SYNC

-

TSC_SYNC

TSC_G6_IO1

TSC_G6_IO2

TSC_G6_IO3

TSC_G6_IO4

-

AF4 AF5

I2C1/TIM22/

EVENTOUT/

LPUART1

SPI2/I2S2/I2C2

-

LPUART1_RTS_

DE

-

EVENTOUT

TIM22_CH1

TIM22_CH2

-

-

I2C1_SCL

I2C1_SDA

LPUART1_TX

LPUART1_RX

-

-

-

-

-

-

-

-

-

SPI2_NSS/I2S2_

WS

SPI2_SCK

AF6

I2C2/TIM21/

EVENTOUT

-

-

-

I2C2_SCL

I2C2_SDA

-

-

-

-

-

-

-

I2C2_SMBA EVENTOUT -

LPUART1_CTS

LPUART1_RTS_

DE

-

I2C2_SCL

I2C2_SDA

-

TIM21_CH1

TIM21_CH2

-

Port

Port C

PC8

PC9

PC10

PC11

PC12

PC13

PC14

PC15

PC4

PC5

PC6

PC7

PC0

PC1

PC2

PC3

AF0

LPUART1/LPTIM/

TIM21/12/

EVENTOUT/

LPTIM1_IN1

LPTIM1_OUT

LPTIM1_IN2

LPTIM1_ETR

EVENTOUT

-

TIM22_CH1

TIM22_CH2

TIM22_ETR

TIM21_ETR

LPUART1_TX

LPUART1_RX

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Table 19. Alternate function port C

AF1

-

AF2

SPI2/I2S2/USB/

LPUART1/

EVENTOUT

EVENTOUT

EVENTOUT

SPI2_MISO/I2S2_MCK

SPI2_MOSI/I2S2_SD

LPUART1_TX

LPUART1_RX

-

-

-

USB_OE

-

-

-

-

-

-

AF3

TSC

TSC_G7_IO1

TSC_G7_IO2

TSC_G7_IO3

TSC_G7_IO4

-

TSC_G3_IO1

TSC_G8_IO1

TSC_G8_IO2

TSC_G8_IO3

TSC_G8_IO4

-

-

-

-

-

-

Port D

Port H

Port

PH0

PH1

Port

PD2

Table 20. Alternate function port D

AF0

LPUART1

LPUART1_RTS_DE

Table 21. Alternate function port H

AF0

USB

USB_CRS_SYNC

-

STM32L052x6 STM32L052x8

Figure 9. Memory map

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DocID025936 Rev 5 51/134

51

Electrical characteristics STM32L052x6 STM32L052x8

6.1.1

Unless otherwise specified, all voltages are referenced to V

SS

.

Minimum and maximum values

Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on

100% of the devices with an ambient temperature at T

A the selected temperature range).

= 25 °C and T

A

= T

A max (given by

Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3 σ ).

Unless otherwise specified, typical data are based on T

A

= 25 °C, V

DD

1.65 V tested.

V

DD

= 3.6 V (for the

3.6 V voltage range). They are given only as design guidelines and are not

Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean±2 σ )

.

Unless otherwise specified, all typical curves are given only as design guidelines and are not tested.

6.1.5

The loading conditions used for pin parameter measurement are shown in

Figure 10

.

Pin input voltage

The input voltage measurement on a pin of the device is described in

Figure 11

.

Figure 10. Pin loading conditions Figure 11. Pin input voltage

0&8SLQ

0&8SLQ

& S)

9

,1

DLF

DLF

52/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

6.1.6 Power supply scheme

Figure 12. Power supply scheme

*3,2V

Q)

—)

1îQ)

î—)

9

''

9

''

9

66

9

''$

9

5()

9

''$

9

5()

Q)

—)

9

5()

9

66$

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9

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9

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Figure 13. Current consumption measurement scheme

,''

9''$

1îQ)

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1[9''

1[966

DocID025936 Rev 5

06Y9

53/134

109

Electrical characteristics

6.2

STM32L052x6 STM32L052x8

Absolute maximum ratings

Stresses above the absolute maximum ratings listed in

Table 22: Voltage characteristics

,

Table 23: Current characteristics

, and

Table 24: Thermal characteristics

may cause

permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

Symbol

Table 22. Voltage characteristics

Ratings Min Max Unit

|V

V

V

|

DD

V

Δ V

DDA

–V

IN

(2)

SS

DD

-V

|

DDx

ESD(HBM)

|

|

Δ

V

SS

|

V

REF+

–V

DDA

External main supply voltage

(including V

DDA

, V

DD_USB

, V

DD

)

(1)

Input voltage on FT and FTf pins

Input voltage on TC pins

Input voltage on BOOT0

Input voltage on any other pin

Variations between different V

DDx power pins

Variations between any V

DDx and V pins

(3)

DDA

power

Variations between all different ground pins

Allowed voltage difference for V

REF+

> V

DDA

Electrostatic discharge voltage

(human body model)

V

V

–0.3

SS

SS

V

V

SS

-

-

-

-

0.3

0.3

SS

0.3

see

4.0

V

DD

+4.0

4.0

V

DD

+ 4.0

4.0

50

300

50

0.4

Section 6.3.11

1. All main power (V

DD

,V

DD_USB

, V ) and ground (V

SS

, V

SSA

) pins must always be connected to the

2. V

IN maximum must always be respected. Refer to

Table 23

for maximum allowed injected current values.

3. It is recommended to power V between V from V

DD

DD

and V

DDA

DDA

DD

and V

DDA from the same source. A maximum difference of 300 mV

DD_USB is independent

V mV

V

54/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

I

I

Symbol

Σ I

Σ I

VDD

(2)

VSS

(2)

VDD(PIN)

VSS(PIN)

I

IO

Table 23. Current characteristics

Ratings

Total current into sum of all V

DD

power lines (source)

(1)

Total current out of sum of all V

SS

ground lines (sink)

(1)

Maximum current into each V

DD

power pin (source)

(1)

Maximum current out of each V

SS

ground pin (sink)

(1)

Output current sunk by any I/O and control pin except FTf pins

Output current sunk by FTf pins

Output current sourced by any I/O and control pin

Max.

105

105

100

100

16

22

-16

Unit

mA

Total output current sunk by sum of all IOs and control pins

(2)

90

Σ I

IO(PIN)

Total output current sourced by sum of all IOs and control pins

(2)

-90

I

INJ(PIN)

Σ I

INJ(PIN)

Injected current on FT, FFf, RST and B pins

Injected current on TC pin

Total injected current (sum of all I/O and control pins)

(5)

-5/+0

(3)

± 5

(4)

± 25

1. All main power (V , V

DDA

) and ground (V supply, in the permitted range.

SS

, V

SSA

) pins must always be connected to the external power

2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count

LQFP packages.

3. Positive current injection is not possible on these I/Os. A negative injection is induced by V must never be exceeded. Refer to

Table 22

for maximum allowed input voltage values.

IN

<V

SS

. I

INJ(PIN)

4. A positive injection is induced by V

IN

< V

SS

. I must never be exceeded. Refer to

Table 22: Voltage characteristics

for the maximum allowed input voltage values.

IN

> V

DD

while a negative injection is induced by V

INJ(PIN)

5. When several inputs are submitted to a current injection, the maximum

Σ

I positive and negative injected currents (instantaneous values).

INJ(PIN)

is the absolute sum of the

Symbol

T

STG

T

J

Table 24. Thermal characteristics

Ratings

Storage temperature range

Maximum junction temperature

Value

–65 to +150

150

Unit

°C

°C

DocID025936 Rev 5 55/134

109

Electrical characteristics STM32L052x6 STM32L052x8

6.3.1 General operating conditions

Symbol

f

HCLK f

PCLK1 f

PCLK2

V

DD

V

DDA

V

DDA

V

DD_USB

V

IN

P

D

Table 25. General operating conditions

Parameter Conditions

Internal AHB clock frequency

Internal APB1 clock frequency

Internal APB2 clock frequency

Standard operating voltage

-

-

-

BOR detector disabled

BOR detector enabled, at power on

BOR detector disabled, after power on

Analog operating voltage (DAC not used)

Analog operating voltage

(all features)

Standard operating voltage, USB domain

(2)

Input voltage on FT, FTf and RST pins

(3)

Must be the same voltage as V

DD

(1)

Must be the same voltage as V

DD

(1)

USB peripheral used

USB peripheral not used

2.0 V

DD

3.6 V

1.65 V ≤

DD

2.0 V

Input voltage on BOOT0 pin

Input voltage on TC pin -

TFBGA64 package

LQFP64 package

Power dissipation at T or T

A

=105 °C (rage 7)

= 85 °C (range 6)

LQFP48 package

WLCSP36 package

LQFP32 package

Power dissipation at T

3)

(4)

A

= 125 °C (range

UFQFPN32

TFBGA64 package

LQFP64 package

LQFP48 package

WLCSP36 package

LQFP32 package

UFQFPN32

1.65

1.65

1.8

-

-

-

-

-

-

-

-

-

-

3.0

1.65

-0.3

-0.3

0

-0.3

-

-

Min

0

0

0

1.65

1.8

3.6

3.6

3.6

363

318

351

526

81

111

91

79

88

132

3.6

3.6

5.5

5.2

5.5

V

DD

+0.3

327

444

Max

32

32

32

3.6

3.6

Unit

MHz

V

V

V

V

V mW

56/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Symbol

Table 25. General operating conditions (continued)

Parameter Conditions Min Max Unit

T

A

Temperature range

Maximum power dissipation (range 6)

Maximum power dissipation (range 7)

–40 85

–40 105

Maximum power dissipation (range 3)

–40 125

°C

T

J

Junction temperature range (range 6)

Junction temperature range (range 7)

Junction temperature range (range 3)

-40 °C

A

85 °

-40 °C ≤

A

≤ 105 °C

-40 °C

A

125 °C

–40

–40

–40

105

125

130

1. It is recommended to power V

V

DDA

and V from the same source. A maximum difference of 300 mV between V

can be tolerated during power-up and normal operation.

DD

and

2. V

DD_USB

must respect the following conditions:

- When V

DD

is powered on (V

DD

< V

DD_min

), V

DD_USB

should be always lower than V

DD.

- When V

DD

is powered down (V

DD

< V

DD_min

), V

DD_USB

should be always lower than V

DD.

- In operating mode, V

DD_USB

could be lower or higher V

DD.

- If the USB is not used, V

DD_USB

must range from V

DD_min

to V

DD_max to be able to use PA11 and PA12 as standard I/Os.

3. To sustain a voltage higher than V

DD

+0.3V, the internal pull-up/pull-down resistors must be disabled.

4. If T is lower, higher P

on page 55

).

D

values are allowed as long as T

J

does not exceed T

J

max (see

Table 24: Thermal characteristics

6.3.2 Embedded reset and power control block characteristics

The parameters given in the following table are derived from the tests performed under the

ambient temperature condition summarized in

Table 25

.

Symbol

Table 26. Embedded reset and power control block characteristics

Parameter Conditions Min Typ

t

VDD

(1)

V

DD

rise time rate

V

DD

fall time rate

T

RSTTEMPO

(1)

Reset temporization

BOR detector enabled

BOR detector disabled

BOR detector enabled

BOR detector disabled

V

DD

rising, BOR enabled

V

DD

rising, BOR disabled

(2)

0

-

0.4

0

0

20

-

2

0.7

-

-

-

Max

1000

1000

3.3

1.6

Unit

µs/V ms

DocID025936 Rev 5 57/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Table 26. Embedded reset and power control block characteristics (continued)

Symbol Parameter Conditions Min Typ Max Unit

V

POR/PDR

V

V

V

V

V

V

V

V

V

V

V

V

BOR0

BOR1

BOR2

BOR3

BOR4

V

PVD0

PVD1

PVD2

PVD3

PVD4

PVD5

PVD6 hyst

Power on/power down reset threshold

Brown-out reset threshold 0

Brown-out reset threshold 1

Brown-out reset threshold 2

Brown-out reset threshold 3

Brown-out reset threshold 4

Programmable voltage detector threshold 0

PVD threshold 1

PVD threshold 2

PVD threshold 3

PVD threshold 4

PVD threshold 5

PVD threshold 6

Hysteresis voltage

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

Falling edge

Rising edge

BOR0 threshold

All BOR and PVD thresholds excepting BOR0

100 -

-

V

V mV

1. Guaranteed by characterization results, not tested in production.

2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.

2.6

2.7

2.85

2.95

1.88

1.99

2.09

2.18

2.28

2.38

1.97

2.07

2.35

2.44

1.65

1.65

1.74

1.8

2.48

2.58

2.69

2.79

2.88

2.99

3.09

3.20

2.39

2.47

2.57

2.68

2.77

2.87

2.97

3.08

-

2.45

2.54

2.68

2.78

1.8

1.88

1.98

2.08

2.20

2.28

1.87

1.96

2.22

2.31

1

1.3

1.67

1.69

2.44

2.54

2.64

2.74

2.83

2.94

3.05

3.15

40

2.55

2.66

2.8

2.9

1.85

1.94

2.04

2.14

2.24

2.34

1.93

2.03

2.30

2.41

1.5

1.5

1.7

1.76

The parameters given in

Table 28

are based on characterization results, unless otherwise

specified.

58/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 27. Embedded internal reference voltage calibration values

Calibration value name Description Memory address

VREFINT_CAL

Raw data acquired at temperature of 30 °C

V

DDA

= 3 V

0x1FF8 0078 - 0x1FF8 0079

V

V

A

Symbol

REFINT out

(2)

T

VREFINT

VREF_MEAS

VREF_MEAS

Table 28. Embedded internal reference voltage

(1)

Parameter Conditions Min

Internal reference voltage

Internal reference startup time

V

DDA

V

and V

REF+

REFINT

voltage during

factory measure

– 40 °C < T

J

< +125 °C 1.202

-

2.99

Accuracy of factory-measured

V

REF

value

(3)

Temperature coefficient

Long-term stability

Including uncertainties due to ADC and

V

DDA

/V

REF+

values

–40 °C < T

J

< +125 °C

1000 hours, T= 25 °C

-

-

-

Typ

1.224

2

3

-

Max

1.242

3

3.01

±5

Unit

V ms

V mV

T

Coeff

(4)

A

Coeff

(4)

V

DDCoeff

(4)

25

-

-

100

1000

2000 ppm/°C ppm ppm/V

T

T

S_vrefint

(4)(5)

ADC_BUF

(4)

Voltage coefficient

ADC sampling time when reading the internal reference voltage

Startup time of reference voltage buffer for ADC

3.0 V < V

DDA

-

-

< 3.6 V -

5

-

10

-

-

10

µs

µs

I

BUF_ADC

(4)

I

VREF_OUT

(4)

C

VREF_OUT

(4)

Consumption of reference voltage buffer for ADC

VREF_OUT output current

VREF_OUT output load

(6)

-

-

-

-

-

-

13.5

-

-

25

1

50

µA

µA pF

I

LPBUF

(4)

Consumption of reference voltage buffer for VREF_OUT and COMP

730 1200 nA

V

REFINT_DIV1

(4)

V

REFINT_DIV2

(4)

V

REFINT_DIV3

(4)

1/4 reference voltage

1/2 reference voltage

3/4 reference voltage -

-

24

49

74

25

50

75

26

51

76

V

%

REFINT

1. Refer to

Table 40: Peripheral current consumption in Stop and Standby mode

for the value of the internal reference current

consumption (I

REFINT

).

2. Guaranteed by test in production.

3. The internal V

REF

value is individually measured in production and stored in dedicated EEPROM bytes.

4. Guaranteed by design, not tested in production.

5. Shortest sampling time can be determined in the application by multiple iterations.

6. To guarantee less than 1% VREF_OUT deviation.

DocID025936 Rev 5 59/134

109

Electrical characteristics

6.3.4

STM32L052x6 STM32L052x8

Supply current characteristics

The current consumption is a function of several parameters and factors such as the operating voltage, temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code.

The current consumption is measured as described in

Figure 13: Current consumption measurement scheme

.

All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified otherwise.

The current consumption values are derived from the tests performed under ambient temperature and V

DD

supply voltage conditions summarized in

Table 25: General operating conditions

unless otherwise specified.

The MCU is placed under the following conditions:

All I/O pins are configured in analog input mode

All peripherals are disabled except when explicitly mentioned

The Flash memory access time and prefetch is adjusted depending on fHCLK frequency and voltage range to provide the best CPU performance unless otherwise specified.

When the peripherals are enabled f

APB1

= f

APB2

HSE = 16 MHz (if HSE bypass mode is used)

= f

APB

When PLL is on, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or

The HSE user clock applied to OSCI_IN input follows the characteristic specified in

Table 42: High-speed external user clock characteristics

For maximum current consumption V

DD

= V

DDA

= 3.6 V is applied to all supply pins

For typical current consumption V

DD specified otherwise

= V

DDA

= 3.0 V is applied to all supply pins if not

The parameters given in

Table 50

,

Table 25

and

Table 26

are derived from tests performed under ambient temperature and V

DD

supply voltage conditions summarized in

Table 25

.

60/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 29. Current consumption in Run mode, code with data processing running from Flash

Symbol Parameter Conditions f

HCLK

Typ Max

(1)

Unit

I

DD

(Run from

Flash)

Supply current in

Run mode, code executed from Flash

Range 3, V

CORE

=1.2 V

VOS[1:0]=11 f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above

16 MHz (PLL on)

(2)

Range 2, V

CORE

VOS[1:0]=10,

=1.5 V,

MSI clock

Range 1, V

CORE

VOS[1:0]=01

=1.8 V,

Range 3, V

CORE

VOS[1:0]=11

=1.2 V,

1 MHz

2 MHz

4 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

65 kHz

524 kHz

4.2 MHz

165

290

555

0.665

1.3

2.6

1.55

3.1

6.3

36.5

99.5

620

µA mA

µA

1.4

2.8

1.7

3.4

230

360

630

0.74

6.8

110

190

700

HSI clock

Range 2, V

CORE

VOS[1:0]=10,

=1.5 V,

Range 1, V

CORE

VOS[1:0]=01

=1.8 V,

16 MHz

32 MHz

2.6

6.25

2.9

7 mA

1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Symbol

I

DD

(Run from

Flash)

Table 30. Current consumption in Run mode vs code type, code with data processing running from Flash

Parameter Conditions f

HCLK

Supply current in

Run mode, code executed from Flash f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above

16 MHz (PLL on)

(1)

Range 3,

V

CORE

=1.2 V,

VOS[1:0]=11

Range 1,

V

CORE

=1.8 V,

VOS[1:0]=01

Dhrystone

CoreMark

Fibonacci while(1) while(1), prefetch off

Dhrystone

CoreMark

Fibonacci while(1) while(1), prefetch off

4 MHz

32 MHz

1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Typ

555

585

440

355

353

Unit

µA

6.3

6.3

6.55

5.4

mA

5.2

DocID025936 Rev 5 61/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Figure 14. I

DD

vs V

DD

, at T

A

= 25/55/85/105 °C, Run mode, code running from

Flash memory, Range 2, HSE, 1WS

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s;sͿ

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06Y9

Figure 15. I

DD

vs V

DD

, at T

A

= 25/55/85/105 °C, Run mode, code running from

Flash memory, Range 2, HSI16, 1WS

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'KU\VWRQH:6ƒ&

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06Y9

62/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 31. Current consumption in Run mode, code with data processing running from RAM

Symbol Parameter Conditions f

HCLK

Typ Max

(1)

Unit

I

DD

(Run from

RAM)

Supply current in

Run mode, code executed from

RAM, Flash switched off

Range 3,

V

CORE

=1.2 V,

VOS[1:0]=11 f

HSE

= f

HCLK

up to 16

MHz included, f

HSE

= f

HCLK

/2 above

16 MHz (PLL on)

(2)

Range 2,

V

CORE

=1.5 ,V,

VOS[1:0]=10

MSI clock

Range 1,

V

CORE

=1.8 V,

VOS[1:0]=01

Range 3,

V

CORE

=1.2 V,

VOS[1:0]=11

1 MHz

2 MHz

4 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

65 kHz

524 kHz

4.2 MHz

1

2

1.25

2.45

135

240

450

0.52

5.1

34.5

83

485

µA mA

µA

1.2

2.3

1.4

2.8

170

270

480

0.6

5.4

75

120

540

HSI16 clock source

(16 MHz)

Range 2,

V

CORE

=1.5 V,

VOS[1:0]=10

Range 1,

V

CORE

=1.8 V,

VOS[1:0]=01

16 MHz

32 MHz

2.1

5.1

2.3

5.6

mA

1.

2.

Guaranteed by characterization results at 125 °C

, not tested in production, unless otherwise specified.

Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Symbol

Table 32. Current consumption in Run mode vs code type, code with data processing running from RAM

(1)

Parameter Conditions f

HCLK

I

DD

(Run from

RAM)

Supply current in

Run mode, code executed from

RAM, Flash switched off f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above

16 MHz (PLL on)

(2)

Range 3,

V

CORE

=1.2 V,

VOS[1:0]=11

Range 1,

V

CORE

=1.8 V,

VOS[1:0]=01

Dhrystone

CoreMark

Fibonacci while(1)

Dhrystone

CoreMark

Fibonacci while(1)

4 MHz

32 MHz

1.

2.

Guaranteed by characterization results, not tested in production, unless otherwise specified.

Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Typ

450

575

370

340

5.1

6.25

4.4

4.7

Unit

µA mA

DocID025936 Rev 5 63/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Symbol

I

DD

(Sleep)

Parameter

Supply current in Sleep mode, Flash off

Table 33. Current consumption in Sleep mode

Conditions f

HCLK

f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above

16 MHz (PLL on)

(2)

Range 2,

V

CORE

=1.5 V,

VOS[1:0]=10

MSI clock

Range 3,

V

CORE

=1.2 V,

VOS[1:0]=11

Range 1,

V

CORE

=1.8 V,

VOS[1:0]=01

Range 3,

V

CORE

=1.2 V,

VOS[1:0]=11

1 MHz

2 MHz

4 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

65 kHz

524 kHz

4.2 MHz

HSI16 clock source

(16 MHz)

Range 2,

V

CORE

=1.5 V,

VOS[1:0]=10

Range 1,

V

CORE

=1.8 V,

VOS[1:0]=01

16 MHz

32 MHz

Supply current in Sleep mode, Flash on f

HSE

= f

HCLK

up to

16 MHz included, f

HSE

= f

HCLK

/2 above

16 MHz (PLL on)

(2)

Range 2,

CORE

=1.5 V,

VOS[1:0]=10

MSI clock

Range 3,

V

CORE

=1.2 V,

VOS[1:0]=11

Range 1,

V

CORE

=1.8 V,

VOS[1:0]=01

Range 3,

V

CORE

=1.2 V,

VOS[1:0]=11

1 MHz

2 MHz

4 MHz

4 MHz

8 MHz

16 MHz

8 MHz

16 MHz

32 MHz

65 kHz

524 kHz

4.2 MHz

HSI16 clock source

(16 MHz)

Range 2,

V

CORE

=1.5 V,

VOS[1:0]=10

Range 1,

V

CORE

=1.8 V,

VOS[1:0]=01

16 MHz

32 MHz

Typ

665

1750

680

1750

1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.

305

590

370

715

43.5

72

130

160

1650

18

31.5

140

380

730

1650

29.5

44.5

150

57.5

84

150

170

315

605

Max

(1)

370

710

430

860

90

120

180

210

1900

65

75

210

Unit

830

2100

µA

2100

460

950

2400

110

130

270

130

170

280

310

420

770

950

64/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).

Symbol Parameter

Table 34. Current consumption in Low-power run mode

Conditions Typ

I

DD

(LP Run)

Supply current in

Low-power run mode

All peripherals off, code executed from

RAM, Flash switched off,

V

DD

from 1.65 to 3.6 V

All peripherals off, code executed from

Flash, V

DD from 1.65 V to

3.6 V

MSI clock = 65 kHz, f

HCLK

= 32 kHz

MSI clock= 65 kHz, f

HCLK

= 65 kHz

T

A

=

40 to 25°C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

T

A

=-40 °C to 25 °C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

T

A

=

40 to 25°C

MSI clock= 131 kHz, f

HCLK f

HCLK f

HCLK

= 131 kHz

MSI clock= 65 kHz,

= 32 kHz

MSI clock = 65 kHz,

= 65 kHz

MSI clock =

131 kHz, f

HCLK

= 131 kHz

T

A

= 55 °C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

T

A

=

40 to 25°C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

T

A

=

40 to 25°C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

T

A

=

40 to 25°C

T

A

= 55 °C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

8.5

11.5

15.5

27.5

10

15.5

19.5

31.5

20

23

25.5

29.5

40

22

26

31

44

27.5

31.5

36.5

49

39

41

44

49.5

60

1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.

Max

(1)

80

100

46

80

75

95

33

73

86

100

120

64

140

28

68

130

25

50

55

130

15

50

54

10

48

53

Unit

µA

DocID025936 Rev 5 65/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Figure 16. I

DD

vs V

DD

, at T

A

= 25/55/ 85/105/125 °C, Low-power run mode, code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS

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(

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(

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:6ƒ&

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:6ƒ&

:6ƒ&

Table 35. Current consumption in Low-power sleep mode

Parameter Conditions Typ

06Y9

Symbol Max

(1)

Unit

MSI clock = 65 kHz, f

HCLK

= 32 kHz,

Flash off

T

A

=

40 to 25°C 4.7

(2)

-

I

DD

(LP Sleep)

Supply current in

Low-power sleep mode

All peripherals off, V

DD

from

1.65 to 3.6 V

MSI clock = 65 kHz, f

HCLK f

HCLK

= 32 kHz,

Flash on

MSI clock =65 kHz,

= 65 kHz,

Flash on

MSI clock = 131 kHz, f

HCLK

= 131 kHz,

Flash on

T

A

=

40 to 25°C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

T

A

=

40 to 25°C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

T

A

=

40 to 25°C

T

A

= 55 °C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

17

19.5

23

32.5

17

20

23.5

32.5

19.5

20.5

22.5

26

35

23

63

69

90

23

63

69

90

36

64

66

72

95

1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.

2. As the CPU is in Sleep mode, the difference between the current consumption with Flash on and off (nearly 12 µA) is the same whatever the clock frequency.

µA

66/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Symbol

Table 36. Typical and maximum current consumptions in Stop mode

Parameter Conditions Typ Max

(1)

Unit

I

DD

(Stop) Supply current in Stop mode

T

A

=

40 to 25°C

T

A

= 55°C

T

A

= 85°C

T

A

= 105°C

T

A

= 125°C

0.41

0.63

1.7

4

11

1

2.1

4.5

9.6

24

(2)

1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified.

2.

Guaranteed by test in production.

µA

Figure 17. I

DD

vs V

DD

, at T

A

= 25/55/ 85/105/125 °C, Stop mode with RTC enabled and running on LSE Low drive

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Figure 18. I

DD

vs V

DD

, at T

A

= 25/55/85/105/125 °C, Stop mode with RTC disabled, all clocks off

06Y9

,''P$

(

(

(

(

(

(

(

9''9

ƒ&

ƒ&

ƒ&

ƒ&

ƒ&

06Y9

DocID025936 Rev 5 67/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Symbol

Table 37. Typical and maximum current consumptions in Standby mode

Parameter Conditions Typ

I

DD

(Standby)

Supply current in Standby mode

Independent watchdog and LSI enabled

Independent watchdog and LSI off

T

A

=

40 to 25°C

T

A

= 55 °C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

T

A

=

40 to 25°C

T

A

= 55 °C

T

A

= 85 °C

T

A

= 105 °C

T

A

= 125 °C

1.3

0.29

0.32

0.5

0.94

2.6

1. Guaranteed by characterization results at 125 °C, not tested in production, unless otherwise specified

-

-

-

-

Max

(1)

8.5

0.6

0.9

2.3

1.7

2.9

3.3

4.1

3

7

Unit

µA

Symbol

Table 38. Average current consumption during Wakeup parameter System frequency

Current consumption during wakeup

I

DD

(Wakeup from

Stop)

Supply current during Wakeup from

Stop mode

I

DD

(Reset) Reset pin pulled down

HSI 1

HSI/4 0,7

MSI clock = 4,2 MHz

MSI clock = 1,05 MHz

0,7

0,4

MSI clock = 65 KHz

-

0,1

0,21

0,23 I

DD

(Power-up) BOR on

I

DD

(Wakeup from

StandBy)

With Fast wakeup set

With Fast wakeup disabled

MSI clock = 2,1 MHz

MSI clock = 2,1 MHz

0,5

0,12

Unit

mA

68/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following tables. The

MCU is placed under the following conditions: all I/O pins are in input mode with a static value at V the given value is calculated by measuring the current consumption

– with all peripherals clocked off

DD

or V all peripherals are disabled unless otherwise mentioned

SS

(no load)

– with only one peripheral clocked on

Table 39. Peripheral current consumption in Run or Sleep mode

(1)

Typical consumption, V

DD

= 3.0 V, T

A

= 25 °C

Peripheral

Range 1,

V

CORE

=1.8 V

VOS[1:0] = 01

Range 2,

V

CORE

=1.5 V

VOS[1:0] = 10

Range 3,

V

CORE

=1.2 V

VOS[1:0] = 11

Low-power sleep and run

APB1

WWDG

SPI2

LPUART1

I2C1

I2C2

USB

DAC1

USART2

LPTIM1

TIM2

TIM6

CRS

ADC1

(2)

SPI1

APB2

USART1

TIM21

TIM22

FIREWALL

DBGMCU

SYSCFG

Cortex-

M0+ core

I/O port

GPIOA

GPIOB

GPIOC

1.5

2.5

3.5

3.5

8.5

5.5

4

14.5

7.5

7

1.5

4

14.5

10

10.5

3.5

2.5

3

9

8

11

4

8.5

1

2

3

2.5

6.5

5

3

11.5

6

6

1

3.5

12

8.5

8.5

3

2

9.5

3.5

4.5

2

4.5

6.5

1

2

2.5

2

5.5

3.5

3

9.5

5

5

1

3

9.5

6.5

7

2.5

2

2

3.5

5.5

7.5

3

4

0.5

1.5

2.5

2.5

7

4

2.5

12

5.5

6

0.5

2.5

11

8

9

2

2

2

4

6

9

2.5

4.5

Unit

µA/MHz

(f

HCLK

)

µA/MHz

(f

HCLK

)

µA/MHz

(f

HCLK

)

DocID025936 Rev 5 69/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Table 39. Peripheral current consumption in Run or Sleep mode

(1)

(continued)

Typical consumption, V

DD

= 3.0 V, T

A

= 25 °C

Peripheral

Range 1,

V

CORE

=1.8 V

VOS[1:0] = 01

Range 2,

V

CORE

=1.5 V

VOS[1:0] = 10

Range 3,

V

CORE

=1.2 V

VOS[1:0] = 11

Low-power sleep and run

Unit

Cortex-

M0+ core

I/O port

GPIOD

GPIOH

CRC

FLASH

1

1.5

1.5

0

(3)

0.5

1

1

0

(3)

0.5

1

1

0

(3)

0.5

0.5

1

0

(3)

µA/MHz

(f

HCLK

)

AHB

All enabled

DMA1

RNG

TSC

10

5.5

3

279

8

1

2.5

221.5

6.5

0.5

2

219.5

8.5

0.5

3

215

µA/MHz

(f

HCLK

)

PWR 2.5

2 2 1

µA/MHz

(f

HCLK

)

1. Data based on differential I enabled, in the following conditions: f

(range 3), f

HCLK

DD

measurement between all peripherals off an one peripheral with clock

HCLK

= 32 MHz (range 1), f

= 64kHz (Low-power run/sleep), f

APB1

HCLK

= 16 MHz (range 2), f

= f

HCLK

, f

APB2

= f

HCLK

HCLK

= 4 MHz

, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.

2. HSI oscillator is off for this measure.

3. Current consumption is negligible and close to 0 µA.

Table 40. Peripheral current consumption in Stop and Standby mode

(1)

Typical consumption, T

A

= 25 °C

Symbol Peripheral

V

DD

=1.8 V V

DD

=3.0 V

I

DD(PVD / BOR)

I

REFINT

-

-

-

LSE Low drive

(2)

0.7

-

0,1

1.2

1.4

0,1

Unit

LPTIM1, Input 100 Hz 0,01 0,01

µA

LPTIM1, Input 1 MHz 6

LPUART1 0,2

RTC

1. LPTIM and LPUART peripherals cannot operate in Standby mode.

0,3

6

0,2

0,48

70/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

2. LSE Low drive consumption is the difference between an external clock on OSC32_IN and a quartz between OSC32_IN and OSC32_OUT.-

6.3.5 Wakeup time from low-power mode

The wakeup times given in the following table are measured with the MSI or HSI16 RC oscillator. The clock source used to wake up the device depends on the current operating mode:

Sleep mode: the clock source is the clock that was set before entering Sleep mode

Stop mode: the clock source is either the MSI oscillator in the range configured before entering Stop mode, the HSI16 or HSI16/4.

Standby mode: the clock source is the MSI oscillator running at 2.1 MHz

All timings are derived from tests performed under ambient temperature and V

DD voltage conditions summarized in

Table 25

.

supply

Symbol

t

WUSLEEP

Table 41. Low-power mode wakeup timings

Parameter Conditions

Wakeup from Sleep mode t

WUSLEEP_

LP

Wakeup from Low-power sleep mode, f

HCLK

= 262 kHz f

HCLK

= 32 MHz f

HCLK

= 262 kHz

Flash memory enabled f

HCLK

= 262 kHz

Flash memory switched OFF

Typ

7

7

9

Max

8

8

10

Unit

Number of clock cycles

DocID025936 Rev 5 71/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Symbol

Table 41. Low-power mode wakeup timings (continued)

Parameter Conditions

t

WUSTOP t

WUSTDBY

Wakeup from Stop mode, regulator in Run mode f

HCLK

= f

MSI

= 4.2 MHz f

HCLK

= f

HSI

= 16 MHz f

HCLK

= f

HSI

/4 = 4 MHz f

HCLK

= f

MSI

= 4.2 MHz

Voltage range 1

Wakeup from Stop mode, regulator in lowpower mode

Wakeup from Stop mode, regulator in lowpower mode, code running from RAM f

HCLK

= f

MSI

= 4.2 MHz

Voltage range 2 f

HCLK

= f

MSI

= 4.2 MHz

Voltage range 3 f

HCLK

= f

MSI

= 2.1 MHz f

HCLK

= f

MSI

= 1.05 MHz f

HCLK

= f

MSI

= 524 kHz f

HCLK

= f

MSI

= 262 kHz f

HCLK

= f

MSI

= 131 kHz f

HCLK

= MSI = 65 kHz f

HCLK

= f

HSI

= 16 MHz f

HCLK

= f

HSI

/4 = 4 MHz f

HCLK

= f

HSI

= 16 MHz f

HCLK

= f

HSI

/4 = 4 MHz f

HCLK

= f

MSI

= 4.2 MHz

Wakeup from Standby mode

FWU bit = 1

Wakeup from Standby mode

FWU bit = 0 f f

HCLK

HCLK

= MSI = 2.1 MHz

= MSI = 2.1 MHz

Typ

5.0

4.9

8.0

5.0

5.0

5.0

65

2.2

7.3

13

28

51

100

190

4.9

8.0

4.9

7.9

4.7

Unit

µs ms

8

13

23

38

65

120

260

7

11

7

10

8

130

3

Max

8

7

11

8

8

72/134

High-speed external user clock generated from an external source

In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The

external clock signal has to respect the I/O characteristics in

Section 6.3.12

. However, the

recommended clock input waveform is shown in

Figure 19

.

Symbol

f

HSE_ext

Table 42. High-speed external user clock characteristics

(1)

Parameter Conditions Min Typ Max

User external clock source frequency

CSS is on or

PLL is used

CSS is off, PLL not used

1

0

8

8

32

32

Unit

MHz

MHz

DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 42. High-speed external user clock characteristics

(1)

(continued)

Symbol Parameter Conditions Min Typ Max

V

HSEH

V

HSEL t w(HSE) t w(HSE) t r(HSE) t f(HSE)

C in(HSE)

DuCy

(HSE)

I

L

OSC_IN input pin high level voltage

OSC_IN input pin low level voltage

OSC_IN high or low time

OSC_IN rise or fall time

OSC_IN input capacitance

Duty cycle

OSC_IN Input leakage current

1. Guaranteed by design, not tested in production.

-

V

SS

V

IN

V

DD

0.7V

DD

V

SS

12

-

-

45

-

-

-

2.6

-

-

-

V

DD

0.3V

DD

-

20

-

55

±1

Unit

V ns pF

%

µA

Figure 19. High-speed external clock source AC timing diagram

9

+6(+

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DocID025936 Rev 5 73/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Low-speed external user clock generated from an external source

The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in

Table 25

.

Symbol

Table 43. Low-speed external user clock characteristics

(1)

Parameter

f

LSE_ext

V

LSEH

User external clock source frequency

OSC32_IN input pin high level voltage

V

LSEL

OSC32_IN input pin low level voltage t w(LSE) t w(LSE) t r(LSE) t f(LSE)

C

IN(LSE)

DuCy

(LSE)

I

L

OSC32_IN high or low time

OSC32_IN rise or fall time

OSC32_IN input capacitance

Duty cycle

OSC32_IN Input leakage current

1. Guaranteed by design, not tested in production

Conditions

-

-

-

V

SS

V

IN

V

DD

Min

1

0.7V

DD

V

SS

465

-

-

45

-

Typ

32.768

-

-

-

-

0.6

-

-

Max

1000

V

DD

0.3V

DD

-

10

-

55

±1

Unit

kHz

V ns pF

%

µA

Figure 20. Low-speed external clock source AC timing diagram

9

/6(+

9

/6(/

W

U/6(

7

/6(

W

I/6(

W

:/6(

W

:/6(

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High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 1 to 25 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in

Table 44

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization

74/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol

Table 44. HSE oscillator characteristics

(1)

Parameter

t f

OSC_IN

R

F

G m

Oscillator frequency

Feedback resistor

Maximum critical crystal transconductance

Startup time

Conditions

-

-

Startup

V

DD

is stabilized

Min Typ Max Unit

1

-

-

-

200

-

2

25

-

700

-

MHz k Ω

µA

/V ms

1. Guaranteed by design, not tested in production.

2. Guaranteed by characterization results, not tested in production. t

SU(HSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.

For C

L1

and C

L2

, it is recommended to use high-quality external ceramic capacitors in the

5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see

Figure 21

). C

L1

and C

L2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of C

L1

and C

L2

. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing

C

L1

and C

L2

. Refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website

www.st.com

.

Figure 21. HSE oscillator circuit diagram

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P

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2

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Low-speed external clock generated from a crystal/ceramic resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on

characterization results obtained with typical external components specified in

Table 45

. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization

DocID025936 Rev 5 75/134

109

Electrical characteristics STM32L052x6 STM32L052x8

time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy).

Symbol Parameter

Table 45. LSE oscillator characteristics

(1)

Conditions

(2)

Min

(2)

Typ Max Unit

f

LSE

LSE oscillator frequency 32.768

kHz

LSEDRV[1:0]=00 lower driving capability

LSEDRV[1:0]= 01 medium low driving capability

-

-

-

-

0.5

0.75

G m

Maximum critical crystal transconductance

1.7

µA/V

LSEDRV[1:0] = 10 medium high driving capability

LSEDRV[1:0]=11 higher driving capability

2.7

t

SU(LSE)

(3)

Startup time V

DD

is stabilized 2 -

1. Guaranteed by design, not tested in production.

2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for

ST microcontrollers”.

3. Guaranteed by characterization results, not tested in production. t

SU(LSE)

is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. To increase speed, address a lower-drive quartz with a high- driver mode.

s

Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator design guide for ST microcontrollers” available from the ST website www.st.com

.

Figure 22. Typical application with a 32.768 kHz crystal

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FDSDFLWRUV

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26&B287

&

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Note:

069

An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one.

76/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

6.3.7 Internal clock source characteristics

The parameters given in

Table 46

are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 25

.

High-speed internal 16 MHz (HSI16) RC oscillator

Symbol

Table 46. 16 MHz HSI16 oscillator characteristics

Parameter Conditions Min Typ Max Unit

f

HSI16

TRIM

(1)(2)

ACC

Frequency

HSI16 usertrimmed resolution

Accuracy of the factory-calibrated

HSI16 oscillator

V

DD

= 3.0 V

Trimming code is not a multiple of 16

Trimming code is a multiple of 16

V

DDA

= 3.0 V, T

A

= 25 °C

V

DDA

= 3.0 V, T

A

= 0 to 55 °C

V

DDA

= 3.0 V, T

A

= -10 to 70 °C

V

DDA

= 3.0 V, T

A

= -10 to 85 °C

V

DDA

= 3.0 V, T

A

= -10 to 105 °C

V

DDA

T

A

= 1.65 V to 3.6 V

=

40 to 125 °C

-1

-

-

-

(3)

-5.45

-1.5

-2

-2.5

-4

16

± 0.4

-

-

-

-

-

-

-

±

1

-

0.7

1.5

(3)

1.5

2

2

2

3.25

% t

SU(HSI16)

(2)

HSI16 oscillator startup time

I

DD(HSI16)

(2)

HSI16 oscillator power consumption

-

-

-

3.7

100

6

140

1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).

2. Guaranteed by characterization results, not tested in production.

3. Guaranteed by test in production.

µs

µA

%

%

%

%

MHz

%

%

%

Figure 23. HSI16 minimum and maximum value versus temperature

DocID025936 Rev 5

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77/134

109

Electrical characteristics STM32L052x6 STM32L052x8

High-speed internal 48 MHz (HSI48) RC oscillator

Symbol

Table 47. HSI48 oscillator characteristics

(1)

Parameter Conditions

f

HSI48

TRIM t su(HSI48)

Frequency

HSI48 user-trimming step

DuCy

(HSI48)

Duty cycle

ACC

HSI48

Accuracy of the HSI48 oscillator (factory calibrated before CRS calibration)

HSI48 oscillator startup time

I

DDA(HSI48)

HSI48 oscillator power consumption

T

A

= 25 °C

1. V

DDA

= 3.3 V, T

A

= –40 to 125 °C unless otherwise specified.

2. Guaranteed by design, not tested in production.

3. Guaranteed by characterization results, not tested in production.

Min

-

0.09

(2)

45

(2)

-4

(3)

-

-

Typ

48

0.14

-

-

-

330

Low-speed internal (LSI) RC oscillator

Symbol

Table 48. LSI oscillator characteristics

Parameter Min Typ

f

LSI

(1)

LSI frequency 26 38

D

LSI

(2) t su(LSI)

(3)

I

DD(LSI)

(3)

LSI oscillator frequency drift

0°C

T

A

LSI oscillator startup time

LSI oscillator power consumption

-10

-

-

-

-

400

1.

Guaranteed by test in production.

2. This is a deviation for an individual part, once the initial frequency has been measured.

3. Guaranteed by design, not tested in production.

Max

56

4

200

510

Multi-speed internal (MSI) RC oscillator

Symbol

f

MSI

Table 49. MSI oscillator characteristics

Parameter Condition

Frequency after factory calibration, done at

V

DD

= 3.3 V and T

A

= 25 °C

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

Max

-

0.2

(2)

55

(2)

4

(3)

6

(2)

380

(2)

Unit

MHz

%

%

%

µs

µA

Unit

kHz

%

µs nA

Typ

65.5

131

262

524

1.05

2.1

4.2

Max Unit

-

-

-

-

-

-

kHz

MHz

78/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Symbol

ACC

MSI

Table 49. MSI oscillator characteristics (continued)

Parameter Condition Typ

-

±

0.5

Frequency error after factory calibration

MSI oscillator frequency drift

0 °C

T

A

85 °C

-

±

3

D

TEMP(MSI)

(1)

MSI oscillator frequency drift

V

DD

= 3.3 V,

40 °C T

A

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

8.9

7.1

6.4

6.2

5.2

4.8

4.7

D

VOLT(MSI)

(1)

MSI oscillator frequency drift

1.65 V ≤ V

DD

≤ 3.6 V, T

A

= 25 °C

-

I

DD(MSI)

(2) t

SU(MSI)

MSI oscillator power consumption

MSI oscillator startup time

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6,

Voltage range 1 and 2

MSI range 6,

Voltage range 3

15

10

6

5

15

30

20

0.75

1

1.5

2.5

4.5

8

3.5

5

Max Unit

%

-

+7.0

+5.0

+4.0

+3.0

+3.0

+2.0

+2.0

%

2.5

%/V

-

-

-

-

-

-

-

-

-

-

-

-

-

µA

µs

-

-

DocID025936 Rev 5 79/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Symbol

Table 49. MSI oscillator characteristics (continued)

Parameter Condition

t

STAB(MSI)

(2) f

OVER(MSI)

MSI oscillator stabilization time

MSI oscillator frequency overshoot

MSI range 0

MSI range 1

MSI range 2

MSI range 3

MSI range 4

MSI range 5

MSI range 6,

Voltage range 1 and 2

MSI range 3,

Voltage range 3

Any range to range 5

Any range to range 6

1. This is a deviation for an individual part, once the initial frequency has been measured.

2. Guaranteed by characterization results, not tested in production.

Typ

-

-

-

-

-

-

-

-

-

-

Max Unit

40

20

10

4

2.5

2

µs

2

3

4

6

MHz

The parameters given in

Table 50

are derived from tests performed under ambient

temperature and V

DD

supply voltage conditions summarized in

Table 25

.

Table 50. PLL characteristics

Value

Symbol Parameter Unit

Min Typ Max

(1)

f

PLL_IN

PLL input clock

(2)

PLL input clock duty cycle

2

45

-

-

24

55

MHz

% f

PLL_OUT

PLL output clock 2 32 MHz t

LOCK

PLL input = 16 MHz

PLL VCO = 96 MHz

115 160 µs

I

I

Jitter

DDA

DD

(PLL)

(PLL)

Cycle-to-cycle jitter

Current consumption on V

DDA

Current consumption on V

DD

-

-

220

120

±

600

450

150 ps

µA

1. Guaranteed by characterization results, not tested in production.

2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by f

PLL_OUT

.

80/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

RAM memory

Table 51. RAM and hardware registers

Symbol

VRM

Parameter

Data retention mode

(1)

Conditions

STOP mode (or RESET)

Min

1.65

Typ Max Unit

-

1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode).

V

Flash memory and data EEPROM

Symbol

Table 52. Flash memory and data EEPROM characteristics

Parameter Conditions

t

V

I

DD prog

DD

Operating voltage

Read / Write / Erase

-

Programming time for word or half-page

Erasing

Programming

Average current during the whole programming / erase operation

Maximum current (peak) during the whole programming / erase operation

T

A

=

25 °C, V

DD

= 3.6 V

1. Guaranteed by design, not tested in production.

Min

1.65

-

-

-

-

Typ

-

3.28

3.28

500

1.5

Max

(1)

3.6

3.94

3.94

700

2.5

Unit

V ms

µA mA

Symbol

Table 53. Flash memory and data EEPROM endurance and retention

Value

Parameter Conditions

Min

(1)

N

CYC

(2)

Cycling (erase / write)

Program memory

Cycling (erase / write)

EEPROM data memory

Cycling (erase / write)

Program memory

Cycling (erase / write)

EEPROM data memory

T

A

=

-40°C to 105 °C

T

A

=

-40°C to 125 °C

10

100

0.2

2

Unit

kcycles

DocID025936 Rev 5 81/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Table 53. Flash memory and data EEPROM endurance and retention (continued)

Value

Symbol Parameter Conditions Unit

Min

(1)

t

RET

(2)

Data retention (program memory) after

10 kcycles at T

A

= 85 °C

Data retention (EEPROM data memory) after 100 kcycles at T

A

= 85 °C

Data retention (program memory) after

10 kcycles at T

A

= 105 °C

Data retention (EEPROM data memory) after 100 kcycles at T

A

= 105 °C

Data retention (program memory) after

200 cycles at T

A

= 125 °C

Data retention (EEPROM data memory) after 2 kcycles at T

A

= 125 °C

T

RET

= +85 °C

T

RET

= +105 °C

T

RET

= +125 °C

1. Guaranteed by characterization results, not tested in production.

2. Characterization is done according to JEDEC JESD22-A117.

30

30

10 years

82/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Susceptibility tests are performed on a sample basis during device characterization.

Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs:

Electrostatic discharge (ESD)

(positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.

FTB

: A Burst of Fast Transient voltage (positive and negative) is applied to V

V

SS compliant with the IEC 61000-4-4 standard.

DD

and

through a 100 pF capacitor, until a functional disturbance occurs. This test is

A device reset allows normal operations to be resumed.

The test results are given in

Table 54

. They are based on the EMS levels and classes defined in application note AN1709.

Table 54. EMS characteristics

Symbol

V

V

FESD

EFTB

Parameter Conditions

Level/

Class

Voltage limits to be applied on any I/O pin to induce a functional disturbance

Fast transient voltage burst limits to be applied through 100 pF on V

DD

and V pins to induce a functional disturbance

SS

V

DD

=

3.3 V, LQFP64, T

A

=

+25 °C, f

HCLK

= 32 MHz conforms to IEC 61000-4-2

V

DD

= 3.3 V, LQFP64, T

A

= +25 °C, f

HCLK

=

32 MHz conforms to IEC 61000-4-4

3B

4A

Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular.

Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application.

Software recommendations

The software flowchart must include the management of runaway conditions such as:

Corrupted program counter

Unexpected reset

Critical data corruption (control registers...)

Prequalification trials

Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second.

DocID025936 Rev 5 83/134

109

Electrical characteristics STM32L052x6 STM32L052x8

To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).

Electromagnetic Interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with

IEC 61967-2 standard which specifies the test board and the pin loading.

Symbol Parameter

S

EMI

Table 55. EMI characteristics

Max vs. frequency range

Conditions

Monitored frequency band

4 MHz voltage range 3

16 MHz voltage range 2

32 MHz voltage range 1

Unit

Peak level

V

DD

=

3.3 V,

T

A

= 25 °C,

LQFP100 package compliant with IEC

61967-2

0.1 to 30 MHz

30 to 130 MHz

130 MHz to 1GHz

SAE EMI Level

3

18

15

2.5

-6

4

5

2

-5

-7

-7

1 dBµV

-

Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity.

Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test conforms to the ANSI/JEDEC standard.

Symbol

Table 56. ESD absolute maximum ratings

Ratings Conditions Class

Maximum value

(1)

Unit

V

ESD(HBM)

Electrostatic discharge voltage (human body model)

V

ESD(CDM)

Electrostatic discharge voltage (charge device model)

T

A

=

+25 °C, conforming to

ANSI/JEDEC JS-001

T

A

=

+25 °C, conforming to

ANSI/ESD STM5.3.1.

1. Guaranteed by characterization results, not tested in production.

2

C4

2000

500

V

84/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Static latch-up

Two complementary static tests are required on six parts to assess the latch-up performance:

A supply overvoltage is applied to each power supply pin

A current injection is applied to each input, output and configurable I/O pin

These tests are compliant with EIA/JESD 78A IC latch-up standard.

Symbol

LU

Parameter

Table 57. Electrical sensitivities

Conditions

Static latch-up class T

A

=

+125 °C conforming to JESD78A

Class

II level A

As a general rule, current injection to the I/O pins, due to external voltage below V

SS

(for standard pins) should be avoided during normal product operation.

or above V

DD

However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization.

Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures.

The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator frequency deviation).

The test results are given in the

Table 58

.

Symbol

Table 58. I/O current injection susceptibility

Functional susceptibility

Description

Negative injection

Positive injection

Unit

Injected current on BOOT0

Injected current on PA0, PA4, PA5, PA11,

PA12, PC15, PH0 and PH1

Injected current on any other FT, FTf pins

Injected current on any other pins

-0

-5

NA

0

I

INJ

-5

(1)

-5

(1)

NA

+5

1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.

mA

DocID025936 Rev 5 85/134

109

Electrical characteristics STM32L052x6 STM32L052x8

General input/output characteristics

Unless otherwise specified, the parameters given in

Table 59

are derived from tests

performed under the conditions summarized in

Table 25

. All I/Os are CMOS and TTL compliant.

Table 59. I/O static characteristics

Parameter Conditions Min Typ Max Unit Symbol

V

V

V

IL

IH hys

Input low level voltage

Input high level voltage

TC, FT, FTf, RST

I/Os

BOOT0 pin

All I/Os

I/O Schmitt trigger voltage hysteresis

(2)

Standard I/Os

BOOT0 pin

V

SS

V

IN

V

DD

All I/Os except for

PA11, PA12, BOOT0 and FTf I/Os

V

SS

V

IN

V

DD

,

PA11 and PA12 I/Os

-

-

0.7 V

DD

-

-

-

-

-

-

-

10% V

DD

(3)

0.01

-

-

0.3V

0.14V

-

-

-

DD

DD

(1)

±50

-50/+250

V

SS

V

IN

V

FTf I/Os

DD

±100

I lkg

Input leakage current

(4)

V

DD

V

IN

5 V

All I/Os except for

PA11, PA12, BOOT0 and FTf I/Os

V

DD

V

IN

5 V

FTf I/Os

-

-

-

200

500

V

DD

V

IN

5 V

PA11, PA12 and

BOOT0

10

R

PU

R

PD

C

IO

Weak pull-up equivalent resistor

Weak pull-down equivalent resistor

I/O pin capacitance

(5)

(5)

V

IN

=

V

IN

=

-

V

SS

V

DD

30

30

-

45

45

5

60

60

-

1.

G uaranteed by characterization, not tested in production

2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not tested in production.

3. With a minimum of 200 mV. Guaranteed by characterization results, not tested in production.

4. The max. value may be exceeded if negative current is injected on adjacent pins.

5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

MOS/NMOS contribution to the series resistance is minimum (~10% order).

V nA nA

µA k Ω k

Ω pF

86/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

9

,/

9

,+

9

9

,+PLQ

9

,/PD[

Figure 24. V

IH

/V

IL

versus VDD (CMOS I/Os)

&026VWDQGDUGUHTXLUHPHQWV9

,+PLQ

9

''

9

,+PLQ

9

''

DOOSLQV

9

,+PLQ

%2273&3+

9

,/PD[

9

''

,QSXWUDQJHQRW

JXDUDQWHHG

&026VWDQGDUGUHTXLUHPHQWV9

,/PD[

9

''

9

''

9

9

,/

9

,+

9

9

,+PLQ

9

,/PD[

06Y9

Figure 25. V

IH

/V

IL

versus VDD (TTL I/Os)

,QSXWUDQJHQRW

JXDUDQWHHG

77/VWDQGDUGUHTXLUHPHQWV9

,+PLQ

9

9

,+PLQ

9

''

DOOSLQV

9

,+PLQ

%2273&3+

9

,/PD[

9

''

77/VWDQGDUGUHTXLUHPHQWV9

,/PD[

9

9

''

9

06Y9

Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±15 mA with the non-standard V

OL

/V

OH specifications given in

Table 60

.

In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in

Section 6.2

:

The sum of the currents sourced by all the I/Os on V

I consumption of the MCU sourced on V

DD,

VDD( Σ )

(see

Table 23

).

DD, plus the maximum Run cannot exceed the absolute maximum rating

The sum of the currents sunk by all the I/Os on V

SS

I consumption of the MCU sunk on V

SS

VSS( Σ )

(see

Table 23

).

plus the maximum Run

cannot exceed the absolute maximum rating

DocID025936 Rev 5 87/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Output voltage levels

Unless otherwise specified, the parameters given in

Table 60

are derived from tests performed under ambient temperature and V

DD

supply voltage conditions summarized in

Table 25

. All I/Os are CMOS and TTL compliant.

Symbol

Table 60. Output voltage characteristics

Parameter Conditions Min Max Unit

V

V

OL

(1)

OH

(3)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

CMOS port

(2)

,

I

IO

= +8 mA

2.7 V

V

DD

3.6 V

V

DD

-

-0.4

0.4

-

V

V

V

V

V

V

V

OL

(1)

OH

(3)(4)

OL

(1)(4)

OH

(3)(4)

OL

(1)(4)

OH

(3)(4)

OLFM+

(1)(4)

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an I/O pin

Output high level voltage for an I/O pin

Output low level voltage for an FTf

I/O pin in Fm+ mode

TTL port

(2)

,

I

IO

=+ 8 mA

2.7 V

V

DD

3.6 V

TTL port

(2)

,

I

IO

= -6 mA

2.7 V

V

DD

3.6 V

I

IO

= +15 mA

2.7 V ≤ V

DD

≤ 3.6 V

I

IO

= -15 mA

2.7 V

V

DD

3.6 V

I

IO

= +4 mA

1.65 V

V

DD

< 3.6 V

I

IO

= -4 mA

1.65 V ≤ V

DD

≤ 3.6 V

I

IO

= 20 mA

2.7 V

V

DD

3.6 V

I

IO

= 10 mA

1.65 V

V

DD

3.6 V

V

V

-

2.4

DD

DD

-

-

-

-

-1.3

-0.45

0.4

-

1.3

-

0.45

-

0.4

0.4

1. The I

IO

current sunk by the device must always respect the absolute maximum rating specified in

Table 23

. must not exceed Σ I

IO(PIN)

.

2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.

3. The I

IO

current sourced by the device must always respect the absolute maximum rating specified in

. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be respected and must not exceed Σ I

IO(PIN)

.

4. Guaranteed by characterization results, not tested in production.

V

88/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Input/output AC characteristics

The definition and values of input/output AC characteristics are given in

Figure 26

and

Table 61

, respectively.

Unless otherwise specified, the parameters given in

Table 61

are derived from tests performed under ambient temperature and V

DD

Table 25

.

supply voltage conditions summarized in

Table 61. I/O AC characteristics

(1)

OSPEEDRx

[1:0] bit value

(1)

Symbol Parameter Conditions Min Max

(2)

Unit

00

01

10

11

Fm+ configuration

(4)

f f

F

F max(IO)out t t f(IO)out r(IO)out max(IO)out t t f(IO)out r(IO)out max(IO)out t t f(IO)out r(IO)out max(IO)out t f max(IO)out t f(IO)out t r(IO)out f max(IO)out t t f(IO)out r(IO)out t f(IO)out t r(IO)out

EXTIpw

Maximum frequency

(3)

Output rise and fall time

Maximum frequency

Maximum frequency

Maximum frequency

(3)

Output rise and fall time

(3)

Output rise and fall time

(3)

Output rise and fall time

Maximum frequency

(3)

Output fall time

Output rise time

Maximum frequency

(3)

Output fall time

Output rise time

Pulse width of external signals detected by the

EXTI controller

C

L

C

L

= 50 pF, V

= 50 pF, V

DD

= 2.7 V to 3.6 V

DD

= 1.65 V to 2.7 V

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 1.65 V to 2.7 V

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 1.65 V to 2.7 V

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 1.65 V to 2.7 V

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 1.65 V to 2.7 V

C

L

= 50 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 1.65 V to 2.7 V

C

L

= 30 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 1.65 V to 2.7 V

C

L

= 30 pF, V

DD

= 2.7 V to 3.6 V

C

L

= 50 pF, V

DD

= 1.65 V to 2.7 V

C

C

L

L

= 50 pF, V

= 50 pF, V

DD

DD

= 2.5 V to 3.6 V

= 1.65 V to 3.6 V

-

17

1

10

30

350

35

10

6

15

60

2

0.6

30

65

10

2

13

28

400

100

125

320

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

8 -

1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO

Port configuration register.

2. Guaranteed by design. Not tested in production.

3. The maximum frequency is defined in

Figure 26

.

kHz ns

MHz ns

MHz ns

MHz ns

MHz ns

KHz ns ns

DocID025936 Rev 5 89/134

109

Electrical characteristics STM32L052x6 STM32L052x8

4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the line reference manual for a detailed description of Fm+ I/O configuration.

Figure 26. I/O AC characteristics definition

90/134

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DLG

The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, R

PU

, except when it is internally driven low (see

Table 62

).

Unless otherwise specified, the parameters given in

Table 62

are derived from tests performed under ambient temperature and V

DD

Table 25

.

supply voltage conditions summarized in

Table 62. NRST pin characteristics

V

V

V

Symbol

IL(NRST)

(1)

IH(NRST)

(1)

OL(NRST)

(1) voltage

Parameter

NRST input low level voltage

NRST input high level voltage

NRST output low level

Conditions

-

-

I

OL

= 2 mA

2.7 V < V

DD

< 3.6 V

I

OL

= 1.5 mA

1.65 V < V

DD

< 2.7 V

Min

V

SS

1.4

-

-

Typ

-

-

-

-

Max Unit

0.8

V

DD

0.4

V

V hys(NRST)

(1)

NRST Schmitt trigger voltage hysteresis

10%V

DD

(2)

mV

R

PU

Weak pull-up equivalent resistor

(3)

V

IN

= V

SS

30 45 60 k

Ω

V

F(NRST)

(1)

V

NF(NRST)

(1)

NRST input filtered pulse

NRST input not filtered pulse -

-

350 -

50

-

1. Guaranteed by design, not tested in production.

2. 200 mV minimum value

3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%.

ns ns

DocID025936 Rev 5

STM32L052x6 STM32L052x8

Figure 27. Recommended NRST pin protection

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1567

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1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the V

Table 62

. Otherwise the reset will not be taken into account by the device.

max level specified in

DLF

Note:

Unless otherwise specified, the parameters given in

Table 63

are preliminary values derived

from tests performed under ambient temperature, f

PCLK frequency and V

conditions summarized in

Table 25: General operating conditions

.

DDA

supply voltage

It is recommended to perform a calibration after each power-up.

Symbol

V

DDA f

ADC f

S

(2) f

TRIG

(2)

V

AIN

Parameter

Analog supply voltage for

ADC on

Table 63. ADC characteristics

Conditions Min

1.65

Current consumption of the

ADC on V

DDA and V

REF+

I

DDA (ADC)

Current consumption of the

ADC on V

DD

(1)

ADC clock frequency

Sampling rate

External trigger frequency

Conversion voltage range

1.14 Msps

10 ksps

1.14 Msps

10 ksps

Voltage scaling Range 1

Voltage scaling Range 2

Voltage scaling Range 3 f

ADC

= 16 MHz

0.14

0.14

0.14

0.05

-

-

-

-

-

-

0

R

AIN

(2)

External input impedance

See

Equation 1

and

Table 64

for details

-

R

ADC

(2)

-

C

ADC

(2)

Sampling switch resistance

Internal sample and hold capacitor

-

Typ

-

-

-

-

-

200

40

70

1

-

-

-

-

-

-

Max

3.6

16

8

4

1.14

-

-

-

-

941

17

V

DDA

50

1

8

Unit

V

µA

MHz

MHz kHz

1/f

ADC

V k

Ω k

Ω pF

DocID025936 Rev 5 91/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Symbol Parameter

Table 63. ADC characteristics (continued)

Conditions Min Typ Max Unit

W t

CAL

(2)

LATENCY t latr

(2)

Calibration time

ADC_DR register write latency

Trigger conversion latency f

ADC

= 16 MHz 5.2

83

µs

1/f

ADC

ADC clock = HSI16

1.5 ADC f cycles + 2

PCLK

cycles

f

1.5 ADC cycles + 3

PCLK

cycles

-

ADC clock = PCLK/2

ADC clock = PCLK/4 -

4.5

8.5 -

f

PCLK cycle f

PCLK cycle f

ADC

= f

PCLK

/2 = 16 MHz 0.266

µs f

ADC

= f

PCLK

1/f

PCLK f f

ADC

ADC

= f f

ADC

= f

PCLK

/4

= f

PCLK

/4 = 8 MHz

HSI16

= 16 MHz 0.252

0.516

16.5

0.260

1/f

µs

PCLK

µs

Jitter

ADC

ADC jitter on trigger conversion f

ADC

= f

HSI16

1 1/f

HSI16 t t

S

(2)

UP_LDO

(2) t

STAB

(2)

Sampling time

Internal LDO power-up time

ADC power-up time f

ADC

= 16 MHz 0.093

1.5

-

-

-

-

-

-

15

239.5

10

1 t

ConV

(2)

Total conversion time

(including sampling time) f

ADC

= 16 MHz 1 15.75

14 to 252 (t

S

for sampling +12.5 for successive approximation)

1. A current consumption proportional to the APB clock frequency has to be added (see

Table 39: Peripheral current consumption in Run or Sleep mode

).

2. Guaranteed by design, not tested in production.

µs

1/f

ADC

µs conversion cycle

µs

1/f

ADC

Equation 1: R

AIN

R

AIN

< f

ADC

×

C

max formula

T

ADC

× ln

(

2

)

R

ADC

The formula above (

Equation 1

) is used to determine the maximum external impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).

92/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

T s

(cycles)

1.5

7.5

13.5

28.5

41.5

55.5

71.5

239.5

1. Guaranteed by design, not tested in production.

Table 64. R

AIN

max for f

ADC

= 14 MHz t

S

(µs)

2.96

3.96

5.11

17.1

0.11

0.54

0.96

2.04

R

AIN

max (k

Ω

)

(1)

0.4

5.9

11.4

25.2

37.2

50

NA

NA

Symbol Parameter

Table 65. ADC accuracy

(1)(2)(3)

Conditions Min

THD

ET

EO

EG

EL

ED

ET

EO

EG

Total unadjusted error

Offset error

Gain error

EL

ED

Integral linearity error

Differential linearity error

ENOB

Effective number of bits

Effective number of bits (16-bit mode oversampling with ratio =256)

(4)

SINAD Signal-to-noise distortion

SNR

Signal-to-noise ratio

Signal-to-noise ratio (16-bit mode oversampling with ratio =256)

(4)

Total harmonic distortion

Total unadjusted error

Offset error

Gain error

Integral linearity error

Differential linearity error

ENOB Effective number of bits

SINAD Signal-to-noise distortion

SNR Signal-to-noise ratio

THD Total harmonic distortion

1.65 V < V

DDA range 1/2/3

= V

REF+

< 3.6 V,

-

-

10.2

-

-

-

11.3

63

63

70

1.65 V < V

REF+ range 1/2/3

< V

DDA

< 3.6 V,

-

-

-

-

-

-

10.0

62

61

-

1. ADC DC accuracy values are measured after internal calibration.

12.1

69

69

Typ

1.5

1

11

2

1

1

76

1

1.5

1

-85

2

1

11.0

69

69

-85

Max

4

2.5

2

2.5

1.5

-

2

3

2

-73

5

2.5

-

-

-

-65

-

-

-

Unit

LSB bits dB

LSB bits dB

DocID025936 Rev 5 93/134

109

Electrical characteristics STM32L052x6 STM32L052x8

2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject negative current.

Any positive injection current within the limits specified for I accuracy.

INJ(PIN)

and Σ I

INJ(PIN)

in

Section 6.3.12

does not affect the ADC

3. Better performance may be achieved in restricted V

DDA

, frequency and temperature ranges.

4. This number is obtained by the test board without additional noise, resulting in non-optimized value for oversampling mode.

Figure 28. ADC accuracy characteristics

9

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1. Refer to

Table 63: ADC characteristics

for the values of R

AIN

, R

ADC

and C

ADC

.

2. C parasitic this, f

represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

ADC

should be reduced.

parasitic

value will downgrade conversion accuracy. To remedy

94/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

General PCB design guidelines

Power supply decoupling should be performed as shown in

Figure 30

or

Figure 31

, depending on whether V

REF+

is connected to V

DDA

or not. The 10 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip.

Figure 30. Power supply and reference decoupling (V

REF+ not connected to

V

DDA

)

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Figure 31. Power supply and reference decoupling (V

REF+ connected to

V

DDA

)

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069

DocID025936 Rev 5 95/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Data guaranteed by design, not tested in production, unless otherwise specified.

Symbol

V

DDA

V

REF+

V

REF-

I

DDVREF+

(1)

I

DDA

(2)

R

L

(2)

C

L

(2)

R

O

Parameter

Table 66. DAC characteristics

Conditions Min

Analog supply voltage

Reference supply voltage

V

REF+

must always be below

V

DDA

Lower reference voltage

Current consumption on

V

REF+

V

REF+

supply

= 3.3 V

Current consumption on

V

DDA

V

DDA

supply

= 3.3 V

Resistive load

No load, middle code (0x800)

No load, worst code (0x000)

No load, middle code (0x800)

No load, worst code (0xF1C)

DAC output buffer on

Capacitive load

Output impedance DAC output buffer off

1.8

1.8

-

-

5

-

6

-

-

Typ

-

-

130

V

SSA

220

210

320

-

-

8

Max

3.6

3.6

220

350

320

520

-

50

10

DAC output buffer ON 0.2 V

DDA

– 0.2

V

DAC_OUT

Voltage on DAC_OUT output

DAC output buffer OFF 0.5

-

V

REF+

1LSB

Unit

V

V

V

µA

V mV

µA k Ω pF k

Ω

DNL

(2)

INL

(2)

Offset

(2)

Offset1

(2)

Differential non linearity

(3)

Integral non linearity

(4)

Offset error at code

0x800

0x001

(5)

Offset error at code

(6)

C

L

≤ 50 pF, R

L

≥ 5 k Ω

DAC output buffer on

No R

LOAD

, C

L

50 pF

DAC output buffer off

C

L

50 pF, R

L

5 k

Ω

DAC output buffer on

No R

LOAD

, C

L

50 pF

DAC output buffer off

C

L

50 pF, R

L

5 k

Ω

DAC output buffer on

No R

LOAD

, C

L

50 pF

DAC output buffer off

No R

LOAD

, C

L

50 pF

DAC output buffer off

-

-

-

-

-

-

1.5

1.5

2

2

±10

±5

±1.5

3

4

±25

3

4

±8

±5

LSB

96/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Symbol Parameter

Table 66. DAC characteristics (continued)

Conditions

t t dOffset/dT

(2)

Gain

(2) dGain/dT

TUE

(2)

SETTLING

(2)

Update rate

WAKEUP

PSRR+

Offset error temperature coefficient (code 0x800)

V

DDA

=

3.3V

V

REF+

= 3.0 V

T

A

= 0 to 50

°

C

DAC output buffer off

V

DDA

=

3.3V

V

REF+

= 3.0 V

T

A

= 0 to 50

°

C

DAC output buffer on

Gain error

(7)

C

L

50 pF, R

L

5 k

Ω

DAC output buffer on

No R

LOAD

, C

L

50 pF

DAC output buffer off

Gain error temperature coefficient

Total unadjusted error

V

DDA

=

3.3V

V

REF+

= 3.0 V

T

A

= 0 to 50

°

C

DAC output buffer off

V

DDA

=

3.3V

V

REF+

=

3.0 V

T

A

= 0 to 50

°

C

DAC output buffer on

C

L

50 pF, R

L

5 k

Ω

DAC output buffer on

No R

LOAD

, C

L

50 pF

DAC output buffer off

Settling time (full scale: for a 12-bit code transition between the lowest and the highest input codes till

DAC_OUT reaches final value ±1LSB

C

L

50 pF, R

L

5 k

Ω

Max frequency for a correct DAC_OUT change (95% of final value) with 1 LSB variation in the input code

V

DDA

supply rejection ratio (static DC measurement)

C

Wakeup time from off state (setting the ENx bit in the DAC Control register)

(8)

C

L

≤ 50 pF, R

L

≥ 5 k Ω

C

L

L

50 pF, R

50 pF, R

L

L

5 k

5 k

Ω

Ω

1. Guaranteed by characterization results, not tested in production.

Min

-20

0

-

-

-10

-40

-

-

-

-

-

-

Typ

-10

20

+0 / -0.2%

-2

-8

12

8

7

-

9

Max

0

50

+0.1 / -0.2% +0.2 / -0.5%

+0 / -0.4%

0

0

30

12

12

1

15

-60 -35

Unit

µV/°C

%

µV/°C

LSB

µs

Msps

µs dB

DocID025936 Rev 5 97/134

109

Electrical characteristics STM32L052x6 STM32L052x8

2. Connected between DAC_OUT and V

SSA

.

3. Difference between two consecutive codes - 1 LSB.

4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.

5. Difference between the value measured at Code (0x800) and the ideal value = V

REF+

/2.

6. Difference between the value measured at Code (0x001) and the ideal value.

7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is off, and from code giving 0.2 V and (V

DDA

– 0.2) V when buffer is on.

8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).

Figure 32. 12-bit buffered/non-buffered DAC

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Temperature sensor characteristics

Table 67. Temperature sensor calibration values

Calibration value name Description Memory address

TS_CAL1

TS_CAL2

TS ADC raw data acquired at temperature of 30 °C,

V

DDA

= 3 V

TS ADC raw data acquired at temperature of 130 °C

V

DDA

= 3 V

0x1FF8 007A - 0x1FF8 007B

0x1FF8 007E - 0x1FF8 007F

T

V

T

Symbol

L

(1)

Avg_Slope

130

I

DDA

(TEMP)

(3) t

START

(3)

(1)

S_temp

(4)(3)

Table 68. Temperature sensor characteristics

Parameter

V

SENSE

linearity with temperature

Average slope

Voltage at 130°C ±5°C

(2)

Current consumption

Startup time

ADC sampling time when reading the temperature

Min

-

1.48

640

-

-

10

Typ

±

1.61

670

3.4

-

-

1

Max

±

2

1.75

700

6

10

-

1. Guaranteed by characterization results, not tested in production.

2. Measured at V

DD

= 3 V ±10 mV. V130 ADC conversion result is stored in the TS_CAL2 byte.

Unit

°C mV/°C mV

µA

µs

98/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

3. Guaranteed by design, not tested in production.

4. Shortest sampling time can be determined in the application by multiple iterations.

6.3.18 Comparators

Symbol

Table 69. Comparator 1 characteristics

Parameter Conditions Min

(1)

Typ Max

(1)

Unit

V

R

R

DDA

400K

V

10K

IN

Analog supply voltage

R

400K

value

R

10K

value

Comparator 1 input voltage range

Comparator startup time

Propagation delay

(2)

-

-

-

-

1.65

-

-

0.6

400

10

V

3.6

-

-

DDA k

V

Ω

V t

START td

-

-

-

-

7

3

10

10

µs

Voffset Comparator offset ± 3 ± 10 mV d

Voffset

/dt

Comparator offset variation in worst voltage stress conditions

Current consumption

(3)

V

DDA

V

IN+

V

T

IN-

A

=

3.6 V

= 0 V

=

V

REFINT

= 25

°

C

-

0 1.5

10 mV/1000 h

I

COMP1

160 260

1.

Guaranteed by characterization, not tested in production.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

3. Comparator consumption only. Internal reference voltage not included.

nA

Symbol

Table 70. Comparator 2 characteristics

Parameter Conditions

t t

V t

DDA

V

IN

START d slow

V d fast offset dThreshold/ dt

Analog supply voltage

Comparator 2 input voltage range -

-

Fast mode

Comparator startup time

Propagation delay

(2)

in slow mode

Propagation delay

(2)

in fast mode

Slow mode

1.65 V

V

DDA

2.7 V ≤

DDA

≤ 3.6 V

1.65 V

V

DDA

2.7 V ≤

DDA

≤ 3.6 V

Comparator offset error

Threshold voltage temperature coefficient

V

T

DDA

A

V- =V

3/4 V

REFINT

1/2 V

1/4 V

=

3.3V

= 0 to 50

°

C

REFINT

REFINT

REFINT

.

,

,

,

Min Typ Max

(1)

1.65

0

-

-

-

-

-

-

-

-

0.8

1.2

±

4

20

1.8

2.5

-

-

15

15

3.6

V

DDA

20

25

3.5

6

2

4

±

20

30

Unit

V

V

µs mV ppm

/°C

DocID025936 Rev 5 99/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Symbol

Table 70. Comparator 2 characteristics (continued)

Parameter Conditions Min Typ Max

(1)

I

COMP2

Current consumption

(3)

Fast mode

Slow mode

-

-

3.5

0.5

5

2

1. Guaranteed by characterization results, not tested in production.

2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.

3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included.

Unit

µA

TIM timer characteristics

The parameters given in the

Table 71

are guaranteed by design.

Refer to

Section 6.3.13: I/O port characteristics

for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Symbol

Table 71. TIMx

(1)

characteristics

Parameter Conditions Min Max

t t res(TIM) f

EXT

Res

TIM

COUNTER

1

Timer resolution time

f

TIMxCLK

= 32 MHz 31.25

0

Timer external clock frequency on CH1 to CH4

Timer resolution

16-bit counter clock period when internal clock is selected (timer’s prescaler disabled) f

TIMxCLK

= 32 MHz

-

-

0

1

f

TIMxCLK

= 32 MHz 0.0312

-

f

TIMxCLK

/2

16

16

65536

2048 t

MAX_COUNT

65536 × 65536

Maximum possible count

f

TIMxCLK

= 32 MHz -

1. TIMx is used as a general term to refer to the TIM2, TIM6, TIM21, and TIM22 timers.

134.2

µs t

TIMxCLK s

Unit

t

TIMxCLK ns

MHz

MHz bit t

TIMxCLK

100/134

I

2

C interface characteristics

The I

2

C interface meets the timings requirements of the I

2

C-bus specification and user manual rev. 03 for:

Standard-mode (Sm) : with a bit rate up to 100 kbit/s

Fast-mode (Fm) : with a bit rate up to 400 kbit/s

Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s.

The I

2

C timing requirements are guaranteed by design when the I

2

C peripheral is properly configured (refer to the reference manual for details). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain.

DocID025936 Rev 5

STM32L052x6 STM32L052x8

Note:

When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement (refer to

Section 6.3.13: I/O port characteristics

for the I2C I/Os characteristics).

All I

2

C SDA and SCL I/Os embed an analog filter (see

Table 72

for the analog filter

characteristics).

The analog spike filter is compliant with I

2

C timings requirements only for the following voltage ranges:

Fast mode Plus: 2.7 V

V

Fast mode:

DD

3.6 V and voltage scaling Range 1

2 V

V

DD

3.6 V and voltage scaling Range 1 or Range 2.

V

DD

< 2 V, voltage scaling Range 1 or Range 2, C load

< 200 pF.

In other ranges, the analog filter should be disabled. The digital filter can be used instead.

In Standard mode, no spike filter is required.

Symbol

Table 72. I2C analog filter characteristics

(1)

Parameter

t

AF

Maximum pulse width of spikes that are suppressed by the analog filter

Range 1

Range 2

Range 3

1. Guaranteed by design, not tested in production.

2. Spikes with widths below t

AF(min) are filtered.

3. Spikes with widths above t

AF(max)

are not filtered

Conditions Min

50

(2)

Max

260

(3)

-

-

Unit

ns

SPI characteristics

Unless otherwise specified, the parameters given in the following tables are derived from tests performed under ambient temperature, f

conditions summarized in

Table 25

.

PCLKx frequency and V

DD

supply voltage

Refer to

Section 6.3.12: I/O current injection characteristics

for more details on the

input/output alternate function characteristics (NSS, SCK, MOSI, MISO).

DocID025936 Rev 5 101/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Symbol

Table 73. SPI characteristics in voltage Range 1

(1)

Parameter Conditions Min Typ Max Unit

Master mode

Slave mode receiver

-

16

16

1/t f

SCK c(SCK)

SPI clock frequency

Slave mode Transmitter

1.71<V

DD

<3.6V

Slave mode Transmitter

2.7<V

DD

<3.6V

-

-

-

12

16

(2)

(2)

MHz

Duty

(SCK)

Duty cycle of SPI clock frequency

Slave mode 30 50 70 % t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO t dis(SO)

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output disable time

Slave mode, SPI presc = 2

Slave mode, SPI presc = 2

Master mode

Master mode

Slave mode

Master mode

Slave mode

Slave mode

Slave mode

4*Tpclk

2*Tpclk

Tpclk-2

8.5

8.5

6

1

15

10

Tpclk

-

-

-

-

-

-

-

-

-

-

Tpclk+2

-

-

-

-

36

30 ns t v(SO)

Data output valid time

Slave mode 1.71<V

DD

<3.6V -

Slave mode 2.7<V

DD

<3.6V

-

Master mode -

29

22

41

28 t v(MO) t h(SO) t h(MO)

Data output hold time

Slave mode

Master mode

9

3

10

-

-

17

-

-

1. Guaranteed by characterization results, not tested in production.

2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of t with a master having t su(MI)

= 0 while Duty

(SCK)

= 50%.

v(SO)

and t su(MI)

which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates

102/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Duty

(SCK) t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO t dis(SO)

Symbol

f

SCK

1/t c(SCK)

Table 74. SPI characteristics in voltage Range 2

(1)

Parameter Conditions Min

SPI clock frequency

Master mode

Slave mode Transmitter

1.65<V

DD

<3.6V

Slave mode Transmitter

2.7<V

DD

<3.6V

-

Duty cycle of SPI clock frequency

NSS setup time

NSS hold time

Slave mode

Slave mode, SPI presc = 2

Slave mode, SPI presc = 2

30

4*Tpclk

2*Tpclk

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output disable time

Master mode

Master mode

Slave mode

Master mode

Slave mode

Slave mode

Slave mode

Typ

-

-

-

50

Tpclk-2 Tpclk

12

11

6.5

2

18

12

-

-

-

-

-

-

Max

8

8

8

(2)

70

-

-

52

42

-

-

-

-

Tpclk+2

Unit

MHz ns t v(SO)

Data output valid time

Slave mode

Master mode

-

-

40

16

55

26 t v(MO) t h(SO)

Data output hold time

Slave mode

Master mode

12

4 -

-

-

-

1. Guaranteed by characterization results, not tested in production.

2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of t with a master having t su(MI)

= 0 while Duty

(SCK)

= 50%.

v(SO)

and t su(MI)

which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates

%

DocID025936 Rev 5 103/134

109

Electrical characteristics STM32L052x6 STM32L052x8

Symbol

Table 75. SPI characteristics in voltage Range 3

(1)

Parameter Conditions Min Typ Max Unit

f

1/t

SCK c(SCK)

SPI clock frequency

Master mode

Slave mode

-

2

2

(2)

MHz

Duty

(SCK) t su(NSS) t h(NSS) t w(SCKH) t w(SCKL) t su(MI) t su(SI) t h(MI) t h(SI) t a(SO t dis(SO)

Duty cycle of SPI clock frequency

NSS setup time

NSS hold time

SCK high and low time

Data input setup time

Data input hold time

Data output access time

Data output disable time

Slave mode

Slave mode, SPI presc = 2

Slave mode, SPI presc = 2

Master mode

Master mode

Slave mode

Master mode

Slave mode

Slave mode

Slave mode

30

4*Tpclk

2*Tpclk

Tpclk-2

28.5

22

7

5

30

40

50

Tpclk

-

-

-

-

-

-

-

-

70

-

-

-

-

-

-

Tpclk+2

70

80

% ns

Slave mode 53 86 t v(SO)

Data output valid time

Master mode 30 54 t v(MO) t h(SO)

Data output hold time

Slave mode

Master mode

18

8 -

-

-

-

1. Guaranteed by characterization results, not tested in production.

2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of t with a master having t su(MI)

= 0 while Duty

(SCK)

= 50%.

v(SO)

and t su(MI)

which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates

Figure 33. SPI timing diagram - slave mode and CPHA = 0

166LQSXW

W

68166

&3+$

&32/

&3+$

&32/

W

Z6&.+

W

Z6&./

W

D62

0,62

287387

W

VX6,

026,

,1387

W

W

962

06%287

F6&.

06%,1

W

K6,

W

K62

%,7287

%,7,1

W

K166

W

U6&.

W

I6&.

/6%287

W

GLV62

/6%,1

DLF

104/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Figure 34. SPI timing diagram - slave mode and CPHA = 1

(1)

166LQSXW

W68166

&3+$

&32/

&3+$

&32/

WZ6&.+

WZ6&./

0,62

287 3 87

WD62

WVX6,

026,

, 1387

WF6&.

WY62

06 % 2 87

WK6,

0 6% ,1 % , 7 ,1

WK62

%, 7 287

WK166

WU6&.

WI6&.

WGLV62

/6% 287

/6% ,1

1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

Figure 35. SPI timing diagram - master mode

(1)

+LJK

166LQSXW

WF6&.

&3+$

&32/

&3+$

&32/

&3+$

&32/

&3+$

&32/

0,62

,13 87

026,

287387

WVX0,

WZ6&.+

WZ6&./

06%,1

WK0,

06%287

WY02

%,7,1

% , 7287

WK02

1. Measurement points are done at CMOS levels: 0.3V

DD

and 0.7V

DD.

WU6&.

WI6&.

/6%,1

/6%287

DL

DLF

DocID025936 Rev 5 105/134

109

Electrical characteristics STM32L052x6 STM32L052x8

I2S characteristics

Table 76. I2S characteristics

(1)

Symbol Parameter Conditions

f

MCK f

CK

I2S Main clock output

I2S clock frequency

-

Master data: 32 bits

Slave data: 32 bits

D

CK

I2S clock frequency duty cycle

Slave receiver t v(WS) t h(WS) t su(WS) t h(WS) t su(SD_MR) t su(SD_SR) t h(SD_MR) t h(SD_SR) t v(SD_ST) t v(SD_MT) t h(SD_ST) t h(SD_MT)

WS valid time

WS hold time

WS setup time

WS hold time

Data input setup time

Data input hold time

Data output valid time

Data output hold time

Master mode

Master mode

Slave mode

Slave mode

Master receiver

Slave receiver

Master receiver

Slave receiver

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

Slave transmitter (after enable edge)

Master transmitter (after enable edge)

1. Guaranteed by characterization results, not tested in production.

2. 256xFs maximum value is equal to the maximum clock frequency.

256 x 8K

-

-

30

16

11

0

-

-

8

3

6

2

-

11

18

256xFs

(2)

64xFs

64xFs

70

-

-

-

77

26

-

-

-

-

15

-

-

MHz

MHz

% ns

Note: Refer to the I2S section of the product reference manual for more details about the sampling frequency (Fs), f

MCK

, f

CK

and D

CK

values. These values reflect only the digital peripheral behavior, source clock precision might slightly change them. DCK depends mainly on the

ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of

(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.

106/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Figure 36. I

2

S slave timing diagram (Philips protocol)

(1)

WF&.

&32/

&32/

WZ&.+ WZ&./

WK:6

:6LQSXW

6'WUDQVPLW

WVX:6

/6%WUDQVPLW

WVX6'B65

/6%UHFHLYH

06%WUDQVPLW

06%UHFHLYH

WY6'B67

%LWQWUDQVPLW

WK6'B65

%LWQUHFHLYH

WK6'B67

/6%WUDQVPLW

/6%UHFHLYH

6'UHFHLYH

DLE

1. Measurement points are done at CMOS levels: 0.3 × V

DD and 0.7 × V

DD

.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

Figure 37. I

2

S master timing diagram (Philips protocol)

(1)

TF#+ TR#+

TC#+

#0/,

TW#+(

#0/,

TV73

TW#+,

TH73

73OUTPUT

3$TRANSMIT

,3"TRANSMIT

TSU3$?-2

,3"RECEIVE

-3"TRANSMIT

-3"RECEIVE

TV3$?-4

"ITNTRANSMIT

TH3$?-2

"ITNRECEIVE

TH3$?-4

,3"TRANSMIT

,3"RECEIVE

3$RECEIVE

AIB

1. Guaranteed by characterization results, not tested in production.

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte.

DocID025936 Rev 5 107/134

109

Electrical characteristics STM32L052x6 STM32L052x8

USB characteristics

The USB interface is USB-IF certified (full speed).

Symbol

Table 77. USB startup time

Parameter

t

STARTUP

(1)

USB transceiver startup time

1. Guaranteed by design, not tested in production.

Max

1

Unit

µs

Symbol

Table 78. USB DC electrical characteristics

Parameter Conditions Min.

(1)

Input levels

V

DD

V

DI

(2)

V

CM

(2)

V

SE

(2)

USB operating voltage

Differential input sensitivity I(USB_DP, USB_DM)

Differential common mode range Includes V

Single ended receiver threshold

Output levels

-

DI range

-

V

OL

(3)

V

OH

(3)

Static output level low

Static output level high

R

L

R

L

of 1.5

k

Ω

to 3.6 V

of 15 k Ω to V

SS

1. All the voltages are measured from the local ground potential.

2. Guaranteed by characterization results, not tested in production.

3. Guaranteed by test in production.

4. R

L

is the load connected on the USB drivers.

(4)

(4)

3.0

0.2

0.8

1.3

-

2.8

Max.

(1)

Unit

3.6

-

2.5

2.0

0.3

3.6

V

V

V

108/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Figure 38. USB timings: definition of data signal rise and fall time

&URVVRYHU

SRLQWV

'LIIHUHQWLDO

GDWDOLQHV

9

&56

9

66

WI

WU

DL

Table 79. USB: full speed electrical characteristics

Driver characteristics

(1)

Symbol Parameter Conditions Min Max

t r t f t rfm

V

CRS

Rise time

Fall Time

(2)

(2)

Rise/ fall time matching

Output signal crossover voltage

C

C

L

L

= 50 pF

= 50 pF t r

/t f

4

4

90

1.3

20

20

110

2.0

1. Guaranteed by design, not tested in production.

2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB

Specification - Chapter 7 (version 2.0).

Unit

ns ns

%

V

DocID025936 Rev 5 109/134

109

Package information STM32L052x6 STM32L052x8

7.1

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK

®

packages, depending on their level of environmental compliance. ECOPACK

® specifications, grade definitions and product status

are available at www.st.com

.

ECOPACK

®

is an ST trademark.

LQFP32 package information

Figure 39. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline

3%!4).'

0,!.%

#

CCC #

$

$

$

,

,

MM

'!5'%0,!.%

+

110/134

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

DocID025936 Rev 5

E

[email protected]&@7

STM32L052x6 STM32L052x8

Table 80. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

e

L

L1

D3

E

E1

E3 k ccc b c

D

D1

A

A1

A2

-

0.050

1.350

0.300

0.090

8.800

6.800

-

8.800

6.800

-

-

0.450

-

-

-

-

1.400

0.370

-

9.000

7.000

5.600

9.000

7.000

5.600

0.800

0.600

1.000

3.5°

-

1.600

0.150

1.450

0.450

0.200

9.200

7.200

-

9.200

7.200

-

-

0.750

-

0.100

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

0.3465

0.2677

-

-

0.0177

-

-

-

0.0020

0.0531

0.0118

0.0035

0.3465

0.2677

0.2205

0.3543

0.2756

0.2205

0.0315

0.0236

0.0394

3.5°

-

-

-

0.0551

0.0146

-

0.3543

0.2756

-

0.3622

0.2835

-

-

0.0295

-

0.0039

0.0630

0.0059

0.0571

0.0177

0.0079

0.3622

0.2835

Figure 40. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint

1. Dimensions are expressed in millimeters.

DocID025936 Rev 5

6?&0?6

111/134

129

Package information STM32L052x6 STM32L052x8

Device marking for LQFP32

The following figure gives an example of topside marking versus pin 1 position identifier location.

Figure 41. LQFP32 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

670/

.7

'DWHFRGH

< ::

5HYLVLRQFRGH

3LQLQGHQWLILHU

5

06Y9

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

112/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

7.2 UFQFPN32 package information

Figure 42. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline

'

E

'

H

$

$

$

GGG

&

&

6($7,1*

3/$1(

H

(

E

( (

/

/

3,1,GHQWLILHU

1. Drawing is not to scale.

'

!"?-%?6

DocID025936 Rev 5 113/134

129

Package information STM32L052x6 STM32L052x8

Table 81. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

E

E1

E2 e

L ddd b

D

D1

D2

A

A1

A3

0.500

0.000

-

0.180

4.900

3.400

3.400

4.900

3.400

3.400

-

0.300

-

0.550

0.020

0.152

0.230

5.000

3.500

3.500

5.000

3.500

3.500

0.500

0.400

-

0.600

0.050

-

0.280

5.100

3.600

3.600

5.100

3.600

3.600

-

0.500

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

0.0197

0.0000

-

0.0071

0.1929

0.1339

0.1339

0.1929

0.1339

0.1339

-

0.0118

-

0.0217

0.0008

0.0060

0.0091

0.1969

0.1378

0.1378

0.1969

0.1378

0.1378

0.0197

0.0157

-

0.2008

0.1417

0.1417

-

0.0197

0.0031

0.0236

0.0020

-

0.0110

0.2008

0.1417

0.1417

Figure 43. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat recommended footprint

114/134

1. Dimensions are expressed in millimeters.

DocID025936 Rev 5

$%B)3B9

STM32L052x6 STM32L052x8

Device marking for UFQFPN32

The following figure gives an example of topside marking versus pin 1 position identifier location.

Figure 44. UFQFPN32 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

/.

'DWHFRGH <HDUZHHN

< ::

5HYLVLRQFRGH

5

3LQ

06Y9

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

DocID025936 Rev 5 115/134

129

Package information

7.3

STM32L052x6 STM32L052x8

LQFP48 package information

Figure 45. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline

3%!4).'

0,!.%

#

CCC #

$

$

$

MM

'!5'%0,!.%

+

,

,

B

0).

)$%.4)&)#!4)/.

1. Drawing is not to scale.

E

"?-%?6

116/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 82. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

e

L

L1

D3

E

E1

E3 k ccc b c

D

D1

A

A1

A2

-

0.050

1.350

0.170

0.090

8.800

6.800

-

8.800

6.800

-

-

0.450

-

-

-

-

1.400

0.220

-

9.000

7.000

5.500

9.000

7.000

5.500

0.500

0.600

1.000

3.5°

-

1.600

0.150

1.450

0.270

0.200

9.200

7.200

-

9.200

7.200

-

-

0.750

-

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

0.3465

0.2677

-

-

0.0177

-

-

-

0.0020

0.0531

0.0067

0.0035

0.3465

0.2677

0.2165

0.3543

0.2756

0.2165

0.0197

0.0236

0.0394

3.5°

-

-

-

0.0551

0.0087

-

0.3543

0.2756

-

0.3622

0.2835

-

-

0.0295

-

0.0031

0.0630

0.0059

0.0571

0.0106

0.0079

0.3622

0.2835

DocID025936 Rev 5 117/134

129

Package information STM32L052x6 STM32L052x8

Figure 46. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint

AID

1. Dimensions are expressed in millimeters.

Device marking for LQFP48

The following figure gives an example of topside marking versus pin 1 position identifier location.

Figure 47. LQFP48 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

670/

&7

118/134

'DWHFRGH

< ::

5HYLVLRQFRGH

3LQ

LQGHQWLILHU

5

06Y9

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

DocID025936 Rev 5

STM32L052x6 STM32L052x8

7.4 LQFP64 package information

Figure 48. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline

6($7,1*3/$1(

&

PP

*$8*(3/$1(

FFF &

.

'

'

'

/

/

E

3,1

,'(17,),&$7,21

H

:B0(B9

D

D1 b c

A

A1

A2

D3

E

E1

1. Drawing is not to scale.

Table 83. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data millimeters inches

(1)

Symbol

Min Typ

-

0.050

1.350

-

-

1.400

0.170

0.090

0.220

-

- 12.000

10.000

-

-

-

7.500

12.000

10.000

Max

1.600

0.150

1.450

0.270

0.200

-

-

-

-

-

Min

-

0.0020

0.0531

0.0067

0.0035

-

-

-

-

-

Typ

-

-

0.0551

0.0087

-

0.4724

0.3937

0.2953

0.4724

0.3937

Max

0.0630

0.0059

0.0571

0.0106

0.0079

-

-

-

-

-

DocID025936 Rev 5 119/134

129

Package information STM32L052x6 STM32L052x8

Table 83. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package mechanical data (continued) millimeters inches

(1)

Symbol

Min Typ Max Min

L

L1 ccc

E3 e

K

-

-

0.450

-

-

7.500

0.500

3.5°

0.600

1.000

-

-

-

0.750

-

0.080

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

-

0.0177

-

-

Typ

0.2953

0.0197

3.5°

0.0236

0.0394

-

Max

-

-

0.0295

-

0.0031

Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint

120/134

1. Dimensions are expressed in millimeters.

DocID025936 Rev 5

AIC

STM32L052x6 STM32L052x8

Device marking for LQFP64

The following figure gives an example of topside marking versus pin 1 position identifier location.

Figure 50. LQFP64 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

5HYLVLRQFRGH

5

670/

57

'DWHFRGH

< ::

3LQ

LQGHQWLILHU

06Y9

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

DocID025936 Rev 5 121/134

129

Package information STM32L052x6 STM32L052x8

Figure 51. WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale package outline

H

H

)

$EDOOORFDWLRQ

EEE =

$

*

'HWDLO$

H

H

)

%XPSVLGH

$

$

$

6LGHYLHZ

122/134

%XPS

$

RULHQWDWLRQ

UHIHUHQFH

HHH =

$

:DIHUEDFNVLGH

[

DDD

‘EEDOOV

FFF

GGG

= ; <

=

E

=

6HDWLQJSODQH

'HWDLO$

URWDWHGƒ

$<B0(B9

1. Drawing is not to scale.

Table 84. WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A

A1

A2

A3

(2) b

(3)

D e1 e2

E e

F

0.525

-

-

-

0.220

2.561

2.833

-

-

-

-

0.555

0.175

0.380

0.025

0.250

2.596

2.868

0.400

2.000

2.000

0.298

0.585

-

-

-

0.280

2.631

2.903

-

-

-

-

0.0207

-

-

-

0.0087

0.1008

0.1115

-

-

-

-

0.0219

0.0069

0.0150

0.0010

0.0098

0.1022

0.1129

0.0157

0.0787

0.0787

0.0117

0.0230

-

-

-

0.0110

0.1036

0.1143

-

-

-

-

DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 84. WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale mechanical data (continued) millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

G aaa bbb ccc ddd eee

-

-

-

-

-

-

0.434

-

-

-

-

-

-

0.100

0.100

0.100

0.050

0.050

-

-

-

-

-

-

1. Values in inches are converted from mm and rounded to 4 decimal digits.

2. Back side coating.

3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.

0.0171

-

-

-

-

-

-

0.0039

0.0039

0.0039

0.0020

0.0020

Figure 52. WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale recommended footprint

'SDG

'VP

Pitch

Dpad

Table 85. WLCSP36 recommended PCB design rules

Dimension Recommended values

Dsm

PCB pad design

0.4 mm

260 µm max. (circular)

220 µm recommended

300 µm min. (for 260 µm diameter pad)

Non-solder mask defined via underbump allowed

069

DocID025936 Rev 5 123/134

129

Package information

7.6

STM32L052x6 STM32L052x8

TFBGA64 package information

Figure 53. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball grid array package outline

$ (

(

H )

+

'

)

H

'

%

‘

‘

‘EEDOOV

HHH

III

0

0

& % $

&

$

124/134

7239,(:

$EDOO

LQGH[DUHD

$EDOO

LGHQWLILHU

%277209,(:

& 6HDWLQJSODQH

GGG &

$

$

6,'(9,(:

$ $

5B0(B9

1. Drawing is not to scale.

Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

A4 b

D

D1

A

A1

A2

E

E1

-

0.150

-

-

0.250

4.850

-

4.850

-

-

-

0.200

-

0.300

5.000

3.500

5.000

3.500

1.200

-

-

0.600

0.350

5.150

-

5.150

-

-

0.0059

-

-

0.0098

0.1909

-

0.1909

-

-

-

0.0079

-

0.0118

0.1969

0.1378

0.1969

0.1378

0.0472

-

-

0.0236

0.0138

0.2028

-

0.2028

-

DocID025936 Rev 5

STM32L052x6 STM32L052x8

Table 86. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball grid array package mechanical data (continued) millimeters inches

(1)

Symbol

Min Typ Max Min Typ Max

e

F ddd eee fff -

-

-

-

0.500

0.750

-

-

-

-

-

0.080

0.150

0.050

1. Values in inches are converted from mm and rounded to 4 decimal digits.

-

-

-

-

-

0.0197

0.0295

-

-

-

-

-

0.0031

0.0059

0.0020

Figure 54. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball

,grid array recommended footprint

Note:

'SDG

'VP

069

Pitch

Dpad

Dsm

Table 87. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA)

Dimension Recommended values

Solder paste

0.5

0.27 mm

0.35 mm typ. (depends on the soldermask registration tolerance)

0.27 mm aperture diameter.

Non solder mask defined (NSMD) pads are recommended.

4 to 6 mils solder paste screen printing process.

DocID025936 Rev 5 125/134

129

Package information STM32L052x6 STM32L052x8

Device marking for TFBGA64

The following figure gives an example of topside marking versus ball A 1 position identifier location.

Figure 55. TFBGA64 marking example (package top view)

3URGXFWLGHQWLILFDWLRQ

/5+

%DOO$

'DWHFRGH <HDUZHHN

< ::

5

5HYLVLRQ

FRGH

06Y9

1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity.

126/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

The maximum chip-junction temperature, T

J using the following equation:

max, in degrees Celsius, may be calculated

T

J

max = T

A

max + (P

D

max ×

Θ

JA

)

Where:

T

A

max is the maximum ambient temperature in

°

C,

Θ

JA

is the package junction-to-ambient thermal resistance, in

°

C/W,

P

D

max is the sum of P

INT

max and P

I/O max (P

D

max = P

INT

max + P

I/O max),

P

INT

max is the product of I

DD and internal power.

V

DD

, expressed in Watts. This is the maximum chip

P

I/O

max represents the maximum power dissipation on output pins where:

P

I/O

max =

Σ

(V

OL

× I

OL

) +

Σ

((V

DD

– V

OH

) × I

OH

), taking into account the actual V

OL application.

/ I

OL

and V

OH

/ I

OH of the I/Os at low and high level in the

Symbol

Θ

JA

Table 88. Thermal characteristics

Parameter

Thermal resistance junction-ambient

TFBGA64 - 5 x 5 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP64 - 10 x 10 mm / 0.5 mm pitch

Thermal resistance junction-ambient

WLCSP36 - 0.4 mm pitch

Thermal resistance junction-ambient

LQFP48 - 7 x 7 mm / 0.5 mm pitch

Thermal resistance junction-ambient

LQFP32 - 7 x 7 mm / 0.8 mm pitch

Thermal resistance junction-ambient

UFQFPN32 - 5 x 5 mm / 0.5 mm pitch

Value

61

45

63

55

57

38

Unit

°C/W

DocID025936 Rev 5 127/134

129

Package information

3'P:

ϮϱϬϬ

ϮϬϬϬ ϭϱϬϬ ϭϬϬϬ ϱϬϬ

Ϭ ϰϬϬϬ ϯϱϬϬ ϯϬϬϬ ϭϮϱ ϭϬϬ

STM32L052x6 STM32L052x8

Figure 56. Thermal resistance

ϳϱ ϱϬ

7HPSHUDWXUHƒ&

Ϯϱ Ϭ hY&EϯϮ

>Y&Wϲϰ

>Y&Wϰϴ

>Y&WϯϮ d&'ϲϰ t>^Wϯϲ

06Y9

JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural

Convection (Still Air). Available from www.jedec.org.

128/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Example:

Table 89. STM32L052x6/8 ordering information scheme

Device family

STM32 = ARM-based 32-bit microcontroller

STM32 L 052 R 8 T 6 D TR

Product type

L = Low power

Device subfamily

052 = USB

Pin count

K = 32 pins

T = 36 pins

C = 48/49 pins

R = 64 pins

Flash memory size

6 = 32 Kbytes

8 = 64 Kbytes

Package

T = LQFP

H = TFBGA

U = UFQFPN

Y = WLCSP pins

Temperature range

6 = Industrial temperature range, –40 to 85 °C

7 = Industrial temperature range, –40 to 105 °C

3 = Industrial temperature range, –40 to 125 °C

Options

No character = V

DD

range: 1.8 to 3.6 V and BOR enabled

D = V

DD

range: 1.65 to 3.6 V and BOR disabled

Packing

TR = tape and reel

No character = tray or tube

For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office.

DocID025936 Rev 5 129/134

129

Revision history STM32L052x6 STM32L052x8

130/134

Date

27-Feb-2014

29-Apr-2014

Revision

Table 90. Document revision history

Changes

1

2

Initial release.

Added WLCSP36 package.

Updated

Table 2: Ultra-low-power STM32L052x6/x8 device features and peripheral counts

Updated

Figure 8: STM32L052x6/8 TFBGA64 ballout - 5x 5 mm

.

Updated

Table 5: Functionalities depending on the working mode (from

Run/active down to standby)

. Added

Section 3.2: Interconnect matrix

.

Replaced TTa I/O structure by TC, updated PA0/4/5, PC5/14, BOOT0 and NRST I/O structure, and added note

3.

in

Table 16:

STM32L052x6/8 pin definitions

.

Updated

Table 25: General operating conditions

,

Table 22: Voltage characteristics

and

Table 23: Current characteristics

.

Modified conditions in

Table 28: Embedded internal reference voltage

.

Updated

Table 29: Current consumption in Run mode, code with data processing running from Flash

,

Table 31: Current consumption in Run mode, code with data processing running from RAM

,

Table 33: Current consumption in Sleep mode

,

Table 34: Current consumption in Lowpower run mode

,

Table 35: Current consumption in Low-power sleep mode

, and

Table 36: Typical and maximum current consumptions in

Stop modeTable 37: Typical and maximum current consumptions in

Standby mode

. Added

Figure 14: IDD vs VDD, at TA= 25/55/85/105 °C,

Run mode, code running from Flash memory, Range 2, HSE, 1WS

,

Figure 15: IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from Flash memory, Range 2, HSI16, 1WS

,

Figure 16: IDD vs

VDD, at TA= 25/55/ 85/105/125 °C, Low-power run mode, code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS

,

Figure 17: IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled and running on LSE Low drive

and

Figure 18: IDD vs VDD, at TA=

25/55/85/105/125 °C, Stop mode with RTC disabled, all clocks off

.

Updated

Table 44: HSE oscillator characteristics

and

Table 45: LSE oscillator characteristics

. Added

Figure 23: HSI16 minimum and maximum value versus temperature

.

Updated

Table 56: ESD absolute maximum ratings

,

Table 58: I/O current injection susceptibility

and

Table 59: I/O static characteristics

,

and added

Figure 24: VIH/VIL versus VDD (CMOS I/Os)

and

Figure 25:

VIH/VIL versus VDD (TTL I/Os)

. Updated

Table 60: Output voltage characteristics

,

Table 61: I/O AC characteristics

, and

Figure 26: I/O AC characteristics definition

.

Updated

Table 63: ADC characteristics

,

Table 65: ADC accuracy

, and

Figure 29: Typical connection diagram using the ADC

. Updated

Table 68: Temperature sensor characteristics

.

Updated

Table 73: SPI characteristics in voltage Range 1

and

Table 76:

I2S characteristics

.

Added

Figure 56: Thermal resistance

.

DocID025936 Rev 5

STM32L052x6 STM32L052x8

Date

25-Jun-2014

Table 90. Document revision history (continued)

Revision Changes

3

Cover page: changed LQFP32 size, updated core speed, added minimum supply voltage for ADC, DAC and comparators.

ADC now guaranteed down to 1.65 V.

Updated list of applications in

Section 1: Introduction

. Changed number

of I2S interfaces to one in

Section 2: Description

.

Updated

Table 2: Ultra-low-power STM32L052x6/x8 device features and peripheral counts

.

Updated RTC/TIM21 in

Table 6: STM32L0xx peripherals interconnect matrix

.

Updated

Table 3: Functionalities depending on the operating power supply range

.

Splitted LQFP32/UFQFPN32 pinout schematics into two distinct figures:

Figure 4

and

Figure 5

. Added note related to WLCSP36

package in

Table 16: STM32L052x6/8 pin definitions

.

Updated

Section 3.4.1: Power supply schemes

.

Updated V

DDA

in

Table 25: General operating conditions

.

Splitted Table

Current consumption in Run mode, code with data processing running from Flash

into

Table 29

and

Table 30

and content

updated. Splitted Table

Current consumption in Run mode, code with data processing running from RAM

into

Table 31

and

Table 32

and

content updated. Updated

Table 33: Current consumption in Sleep mode

,

Table 34: Current consumption in Low-power run mode

,

Table 35: Current consumption in Low-power sleep mode

,

Table 36:

Typical and maximum current consumptions in Stop mode

,

Table 37:

Typical and maximum current consumptions in Standby mode

, and

added

Table 38: Average current consumption during Wakeup

.

Updated

Table 39: Peripheral current consumption in Run or Sleep mode

and added

Table 40: Peripheral current consumption in Stop and

Standby mode

.

Updated

Table 47: HSI48 oscillator characteristics

. Removed note 1

below

Figure 21: HSE oscillator circuit diagram

.

Updated t

LOCK

in

Table 50: PLL characteristics

.

Updated

Table 52: Flash memory and data EEPROM characteristics

and

Table 53: Flash memory and data EEPROM endurance and retention

.

Updated

Table 61: I/O AC characteristics

.

Updated

Table 63: ADC characteristics

.

Updated

Figure 56: Thermal resistance

and added note 1.

DocID025936 Rev 5 131/134

133

Revision history STM32L052x6 STM32L052x8

Date

05-Sep-2104

Table 90. Document revision history (continued)

Revision Changes

4

Extended operating temperature range to 125 °C.

Updated minimum ADC operating voltage to 1.65 V.

Changed number of I2S interface from 1 to 0 in

Table 2: Ultra-lowpower STM32L052x6/x8 device features and peripheral counts

.

Replaced USART3 by LPUART1 in

Table 16: STM32L052x6/8 pin definitions

and LPUART by LPUART1 in

Table 17: Alternate function port A

,

Table 18: Alternate function port B

,

Table 19: Alternate function port C

,

Table 20: Alternate function port D

and

Table 21: Alternate function port H

. Updated PA6 in

Table 17: Alternate function port A

.

Updated temperature range in

Section 2: Description

,

Table 2: Ultralow-power STM32L052x6/x8 device features and peripheral counts

.

Updated P

D

, T

A and

T

J to add range 3 in

Table 25: General operating conditions

. Added range 3 in

Table 53: Flash memory and data

EEPROM endurance and retention

,

Table 89: STM32L052x6/8 ordering information scheme

. Update note 1 in

Table 29: Current consumption in Run mode, code with data processing running from

Flash

,

Table 31: Current consumption in Run mode, code with data processing running from RAM

,

Table 33: Current consumption in Sleep mode

,

Table 34: Current consumption in Low-power run mode

,

Table 35: Current consumption in Low-power sleep mode

,

Table 36:

Typical and maximum current consumptions in Stop mode

,

Table 37:

Typical and maximum current consumptions in Standby mode

and

Table 58: Low-power mode wakeup timings

. Updated

Figure 56:

Thermal resistance

and removed note 1. Updated

Figure 16: IDD vs

VDD, at TA= 25/55/ 85/105/125 °C, Low-power run mode, code running from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS

,

Figure 17: IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled and running on LSE Low drive

,

Figure 18: IDD vs VDD, at TA=

25/55/85/105/125 °C, Stop mode with RTC disabled, all clocks off

.

Updated

Table 37: Typical and maximum current consumptions in

Standby mode

.

Updated SYSCFG in

Table 39: Peripheral current consumption in Run or Sleep mode

.

Updated

Table 40: Peripheral current consumption in Stop and Standby mode

and

Table 58: Low-power mode wakeup timings

.

Updated ACC

HSI16 temperature conditions in

Table 46: 16 MHz HSI16 oscillator characteristics

. Changed ambient temperature range in note

1 below

Table 47: HSI48 oscillator characteristics

.

Updated V

F(NRST) and V

NF(NRST) in

Table 62: NRST pin characteristics

.

Updated

Table 63: ADC characteristics

and

Table 65: ADC accuracy

.

Added range 3 in

Table 89: STM32L052x6/8 ordering information scheme

.

132/134 DocID025936 Rev 5

STM32L052x6 STM32L052x8

Date

23-Jul-2015

Table 90. Document revision history (continued)

Revision Changes

5

Updated all pinout/ballout schematics except for LQFP32 to highlight pin/ball supplied through VDD_USB.

Updated

Table 16: STM32L052x6/8 pin definitions

PC5 as FT pin.

Updated

Figure 6: STM32L052x6/8 LQFP48 pinout - 7 x 7 mm

,

Figure 7: STM32L052x6/8 LQFP64 pinout - 10 x 10 mm

and

Figure 8:

STM32L052x6/8 TFBGA64 ballout - 5x 5 mm

.

Updated

Figure 41

,

Figure 44

,

Figure 47

,

Figure 50

and

Figure 55

device marking example.

Updated current consumption in Run mode in

Section : Features

.

ADC no more available in Low-power run and Low-power Sleep modes in

Table 5: Functionalities depending on the working mode (from

Run/active down to standby)

.

Updated ES disclaimer.

Added CSP outline.

Updated

Table 22: Voltage characteristics

adding VDDA-VDDX variations and adding note 3.

Renamed BOOT1 into nBOOT1.

Added t

UP_LDO

in

Table 63: ADC characteristics

.

Updated LQFP32 pinout (PC14).

Updated MSI oscillator temperature frequency drift in Table MSI oscillator characteristics.

Added note related to Standby mode in table Peripheral current consumption in Stop /standby.

Updated

Section 1: Introduction

packages from 32 pins to 64 pins.

I

2

C interface characteristics: updated introduction and characteristics table.

Changed USARTx_RTS into USARTx_RTS_DE and LPUARTx_RTS into LPUARTx_RTS_DE.

Updated T

Coeff in

Table 28: Embedded internal reference voltage

.

Updated

Figure 16: IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Lowpower run mode, code running from RAM, Range 3, MSI (Range 0) at

64 KHz, 0 WS

,

Figure 17: IDD vs VDD, at TA= 25/55/ 85/105/125 °C,

Stop mode with RTC enabled and running on LSE Low drive

and

Figure 18: IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with

RTC disabled, all clocks off

.

Updated

Table 14: SPI/I2S implementation

removing Rx/Tx FIFO and

NSS pulse mode rows.

Updated I lkg

in

Table 59: I/O static characteristics

.

Updated VDD_USB in

Table 25: General operating conditions

.

Updated

Table 2: Ultra-low-power STM32L052x6/x8 device features and peripheral counts

2 comparators for all devices.

Updated

Table 16: STM32L052x6/8 pin definitions

VDD and VDD_USB connected to respectively E5 and E6.

Updated

Table 54: EMS characteristics

LQFP64 conditions and level/class 3B.

Updated

Table 58: I/O current injection susceptibility

.

Updated

Figure 3: STM32L052x6/8 WLCSP36 ballout

,

Figure 5:

STM32L052x6/8 UFQFPN32 pinout

removing grey PA11, PA12 pins and removing note 2.

DocID025936 Rev 5 133/134

133

STM32L052x6 STM32L052x8

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on

ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2015 STMicroelectronics – All rights reserved

134/134 DocID025936 Rev 5

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