S29AL032D

S29AL032D
S29AL032D
32 Megabit CMOS 3.0 Volt-only Flash Memory
4 M x 8-Bit Uniform Sector
4 M x 8-Bit/2 M x 16-Bit Boot Sector
S29AL032D Cover Sheet
Data Sheet
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.
Publication Number S29AL032D_00
Revision A
Amendment 9
Issue Date January 19, 2007
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Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue. Spansion
Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion Inc.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion Inc. reserves the right to change or discontinue work on this proposed
product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a commitment
to production has taken place. This designation covers several aspects of the product life cycle, including
product qualification, initial production, and the subsequent phases in the manufacturing process that occur
before full production is achieved. Changes to the technical specifications presented in a Preliminary
document should be expected while keeping these aspects of production under consideration. Spansion
places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification has been
completed, and that initial production has begun. Due to the phases of the manufacturing process that
require maintaining efficiency and quality, this document may be revised by subsequent versions or
modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their designations
wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or VIO range. Changes may also include those needed to clarify a
description or to correct a typographical error or incorrect specification. Spansion Inc. applies the following
conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production volume such
that subsequent versions of this document are not expected to change. However, typographical or
specification corrections, or modifications to the valid combinations offered may occur.”
Questions regarding these document designations may be directed to your local sales office.
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S29AL032D
S29AL032D_00_A9 January 19, 2007
S29AL032D
32 Megabit CMOS 3.0 Volt-only Flash Memory
4 M x 8-Bit Uniform Sector
4 M x 8-Bit/2 M x 16-Bit Boot Sector
Data Sheet
Distinctive Characteristics
Architectural Advantages
Performance Characteristics
„ Single power supply operation
„ High performance
– Full voltage range: 2.7 to 3.6 volt read and write operations for
battery-powered applications
„ Manufactured on 200-nm process technology
– Fully compatible with 0.23 µm Am29LV320D, 0.32 µm Am29LV033C,
and 0.33 µm MBM29LV320E devices
„ Flexible sector architecture
– Boot sector models: Eight 8-Kbyte sectors; sixty-three 64-Kbyte
sectors; top or bottom boot block configurations available
– Uniform sector models: Sixty-four 64-Kbyte sectors
„ Sector Protection features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
„ Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
„ Secured Silicon Sector
– 128-word sector for permanent, secure identification through an 8word random Electronic Serial Number
– May be programmed and locked at the factory or by the customer
– Accessible through a command sequence
„ Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
Package Options
–
–
–
–
200 nA Automatic Sleep mode current
200 nA standby mode current
9 mA read current
20 mA program/erase current
„ Cycling endurance: 1,000,000 cycles per sector typical
„ Data retention: 20 years typical
Software Features
„ CFI (Common Flash Interface) compliant
– Provides device-specific information to the system, allowing host
software to easily reconfigure for different Flash devices
„ Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data to,
a sector that is not being erased, then resumes the erase operation
„ Data# Polling and toggle bits
– Provides a software method of detecting program or erase operation
completion
– Unlock Bypass Program Command
Reduces overall programming time when issuing multiple program
command sequences
Hardware Features
„ Ready/Busy# pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
„ Hardware reset pin (RESET#)
„ 48-ball FBGA
– Hardware method to reset the device to reading array data
„ 48-pin TSOP
„ WP#/ACC input pin
„ 40-pin TSOP
Publication Number S29AL032D_00
– Access times as fast as 70 ns
„ Ultra low power consumption (typical values at 5 MHz)
– Write protect (WP#) function allows protection of two outermost
boot sectors (boot sector models only), regardless of sector protect
status
– Acceleration (ACC) function provides accelerated program times
Revision A
Amendment 9
Issue Date January 19, 2007
D at a
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General Description
The S29AL032D is a 32-megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits
each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0-DQ15; byte mode data appears on
DQ0-DQ7. The device is designed to be programmed in-system with the standard 3.0 volt VCC supply, and
can also be programmed in standard EPROM programmers.
The device is available with access times as fast as 70 ns. The devices are offered in 40-pin TSOP, 48-pin
TSOP and 48-ball FBGA packages. Standard control pins- chip enable (CE#), write enable (WE#), and output
enable (OE#)-control normal read and write operations, and avoid bus contention issues.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally
generated and regulated voltages are provided for the pro-gram and erase operations.
S29AL032D Features
The Secured Silicon Sector is an extra sector capable of being permanently locked by Spansion or
customers. The Secured Silicon Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a factory
locked part. Note that the S29AL032D has a Secured Silicon Sector size of 128 words (256 bytes).
Factory locked parts provide several options. The Secured Silicon Sector may store a secure, random 16
byte ESN (Electronic Serial Number), customer code (programmed through the Spansion programming
service), or both.
The S29AL032D is entirely command set compatible with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using standard microprocessor write timings. Register
contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations. Reading
data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by executing the program command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write
cycles to program data instead of four.
Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the device automatically times the erase pulse widths
and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin,
or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been
completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations
during power transitions. The hardware sector protection feature disables both program and erase
operations in any combination of the sectors of memory. This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# pin terminates any operation in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the
device enters the automatic sleep mode. The system can also place the device into the standby mode.
Power consumption is greatly reduced in both these modes.
The Spansion Flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot-electron
injection.
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S29AL032D
S29AL032D_00_A9 January 19, 2007
Data
She et
Table of Contents
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
S29AL032D Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
FBGA Package for Model 00 Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
FBGA Package for Models 03, 04 Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
Special Handling Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1
S29AL032D Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.2
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
7.
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
Word/Byte Configuration (Models 03, 04 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.2
Requirements for Reading Array Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3
Writing Commands/Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.4
Program and Erase Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5
Accelerated Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.6
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.7
Automatic Sleep Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.8
RESET#: Hardware Reset Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.9
Output Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.10 Sector Addresss Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.11 Autoselect Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.12 Sector Protection/Unprotection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.13 Write Protect (WP#) — Models 03, 04 Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.14 Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.
Secured Silicon Sector Flash Memory Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1
Factory Locked: Secured Silicon Sector Programmed and Protected at the Factory . . . . . . 27
8.2
Customer Lockable: Secured Silicon Sector NOT Programmed
or Protected at the Factory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
9.
Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.1
Low VCC Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.2
Write Pulse “Glitch” Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
Logical Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.4
Power-Up Write Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10.
Common Flash Memory Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11.
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.1 Reading Array Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.2 Reset Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.3 Autoselect Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.4 Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence . . . . . . . . .
11.5 Word/Byte Program Command Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.6 Unlock Bypass Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.7 Chip Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11.8 Sector Erase Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
January 19, 2007 S29AL032D_00_A9
S29AL032D
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11.9 Erase Suspend/Erase Resume Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
11.10 Command Definitions Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
12.
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.1 DQ7: Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.2 RY/BY#: Ready/Busy#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.3 DQ6: Toggle Bit I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.4 DQ2: Toggle Bit II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.5 Reading Toggle Bits DQ6/DQ2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.6 DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12.7 DQ3: Sector Erase Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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13.
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
15.
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
15.1 Zero Power Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
16.
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
16.1 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
17.
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.1 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.2 Hardware Reset (RESET#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.3 Word/Byte Configuration (BYTE#) (Models 03, 04 Only). . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.4 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.5 Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17.6 Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18.
Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
19.
TSOP and BGA Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
20.
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.1 TS040—40-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.2 TS 048—48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20.3 VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm . . . . . . . . . . . . . . . . . .
21.
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
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List of Tables
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Table 7.6
Table 7.7
Table 7.8
Table 7.9
Table 7.10
Table 7.11
Table 7.12
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 11.1
Table 11.2
Table 11.3
4
S29AL032D Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Automatic Sleep Mode Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Model 00 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Model 00 Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Model 03 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Model 03 Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Model 04 Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Model 04 Secured Silicon Sector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
S29AL032D Autoselect Codes (High Voltage Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Sector Block Addresses for Protection/Unprotection — Model 00 . . . . . . . . . . . . . . . . . . . . .22
Sector Block Addresses for Protection/Unprotection — Model 03 . . . . . . . . . . . . . . . . . . . . .23
Sector Block Addresses for Protection/Unprotection — Model 04 . . . . . . . . . . . . . . . . . . . . .24
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
System Interface String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
S29AL032D Command Definitions — Model 00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
S29AL032D Command Definitions, x8 Mode — Models 03, 04 . . . . . . . . . . . . . . . . . . . . . . .38
S29AL032D Command Definitions, x16 Mode — Models 03, 04 . . . . . . . . . . . . . . . . . . . . . .39
S29AL032D
S29AL032D_00_A9 January 19, 2007
Data
Table 12.1
Table 13.1
Table 14.1
Table 15.1
Table 16.1
Table 17.1
Table 17.2
Table 17.3
She et
Write Operation Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
DC Characteristics, CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Temporary Sector Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Alternate CE# Controlled Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
List of Figures
Figure 3.1
Figure 3.2
Figure 3.3
Figure 3.4
Figure 5.1
Figure 7.1
Figure 7.2
Figure 8.1
Figure 11.1
Figure 11.2
Figure 12.1
Figure 12.2
Figure 13.1
Figure 13.2
Figure 15.1
Figure 15.2
Figure 16.1
Figure 16.2
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Figure 17.6
Figure 17.7
Figure 17.8
Figure 17.9
Figure 17.10
Figure 17.11
Figure 17.12
Figure 17.13
Figure 17.14
January 19, 2007 S29AL032D_00_A9
40-pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
48-pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Model 00 48-ball FBGA (Top View, Balls Facing Down) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Models 03, 04 48-ball FBGA (Top View, Balls Facing Down) . . . . . . . . . . . . . . . . . . . . . . . . . .9
Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
In-System Sector Protect/Unprotect Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Temporary Sector Unprotect Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Secured Silicon Sector Protect Verify . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Data# Polling Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Toggle Bit Algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) . . . . . . . . . . . . . . . . 47
Typical ICC1 vs. Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Input Waveforms and Measurement Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Read Operations Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
RESET# Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
BYTE# Timings for Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
BYTE# Timings for Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Program Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Chip/Sector Erase Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Back to Back Read/Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Data# Polling Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Toggle Bit Timings (During Embedded Algorithms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
DQ2 vs. DQ6 for Erase and Erase Suspend Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Temporary Sector Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Accelerated Program Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Sector Protect/Unprotect Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Alternate CE# Controlled Write Operation Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
S29AL032D
5
D at a
1.
S hee t
Product Selector Guide
Family Part Number
S29AL032D
Voltage Range: VCC = 2.7–3.6 V
Speed Option
Max access time, ns (tACC)
70
90
70
90
Max CE# access time, ns (tCE)
70
90
Max OE# access time, ns (tOE)
30
35
Note
See AC Characteristics on page 49 for full specifications.
2. Block Diagram
DQ0–DQ15 (A-1), (DQ0-DQ7 Model 00)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A20 (A0-A21 Model 00)
6
S29AL032D
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
S29AL032D_00_A9 January 19, 2007
Data
3.
She et
Connection Diagrams
Figure 3.1 40-pin Standard TSOP
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
VSS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCC
VCC
A21
DQ3
DQ2
DQ1
DQ0
OE#
VSS
CE#
A0
Figure 3.2 48-pin Standard TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
January 19, 2007 S29AL032D_00_A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
S29AL032D
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
7
D at a
3.1
S hee t
FBGA Package for Model 00 Only
Figure 3.3 Model 00 48-ball FBGA (Top View, Balls Facing Down)
A6
B6
C6
D6
E6
F6
G6
H6
A14
A13
A15
A16
A17
NC
A20
VSS
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A11
A12
A19
A10
DQ6
DQ7
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
NC
DQ5
NC
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
ACC
NC
NC
DQ2
DQ3
VCC
A21
A2
B2
C2
D2
E2
F2
G2
H2
A7
A18
A6
A5
DQ0
NC
NC
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
OE#
VSS
A3
8
A4
A2
A1
S29AL032D
A0
CE#
S29AL032D_00_A9 January 19, 2007
Data
3.2
She et
FBGA Package for Models 03, 04 Only
Figure 3.4 Models 03, 04 48-ball FBGA (Top View, Balls Facing Down)
A6
B6
C6
D6
E6
A13
A12
A14
A15
A16
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G6
G4
H4
DQ4
BYTE# DQ15/A-1
H6
VSS
WE#
RESET#
NC
A19
DQ5
DQ12
VCC
A3
B3
C3
D3
E3
F3
G3
H3
A18
A20
DQ2
DQ10
DQ11
DQ3
RY/BY# WP#/ACC
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
OE#
VSS
A3
3.3
F6
A4
A2
A1
A0
CE#
Special Handling Instructions
Special handling is required for Flash Memory products in FBGA packages.
Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.
January 19, 2007 S29AL032D_00_A9
S29AL032D
9
D at a
S hee t
4. Pin Configuration
Pin
Description
A0–A21
22 address inputs
A0-A20
21 address inputs
DQ0–DQ7
8 data inputs/outputs
DQ0-DQ14
15 data inputs/outputs
DQ15/A-1
DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode)
BYTE#
Selects 8-bit or 16-bit mode
CE#
Chip enable
OE#
Output enable
WE#
Write enable
RESET#
Hardware reset pin
WP#/ACC
Hardware Write Protect input/Programming Acceleration input.
ACC
Hardware Write Protect input
RY/BY#
Ready/Busy output
3.0 volt-only single power supply
VCC
(see Product Selector Guide on page 6 for speed options and voltage supply tolerances)
VSS
Device ground
NC
Pin not connected internally
5. Logic Symbols
Figure 5.1 Logic Symbols
Model 00
Models 03, 04
21
22
A0–A21
8
A0–A20
DQ0–DQ15
(A-1)
DQ0–DQ7
CE#
CE#
OE#
OE#
WE#
WE#
RESET#
RESET#
ACC
16 or 8
WP#/ACC
RY/BY#
RY/BY#
BYTE#
10
S29AL032D
S29AL032D_00_A9 January 19, 2007
Data
6.
She et
Ordering Information
6.1
S29AL032D Standard Products
Spansion standard products are available in several packages and operating ranges. The order number
(Valid Combination) is formed by a combination of the elements below.
S29AL032D
70
T
A
I
00
0
PACKING TYPE
0
= Tray
2
= 7” Tape and Reel
3
= 13” Tape and Reel
MODEL NUMBER
00 = x8, VCC = 2.7 V to 3.6 V, Uniform sector device
03 = x8/x16, VCC = 2.7 V to 3.6 V, Top boot sector device, top two address
sectors protected when WP#/ACC = VIL
04 = x8/x16, VCC = 2.7 V to 3.6 V, Bottom boot sector device, bottom two
address sectors protected when WP#/ACC = VIL
TEMPERATURE RANGE
I
= Industrial (–40°C to +85°C)
N
= Extended (-40°C to +125°C)
PACKAGE MATERIAL SET
A
= Standard
F
= Pb-Free
PACKAGE TYPE
T
= Thin Small Outline Package (TSOP) Standard Pinout
B
= Fine-pitch Ball-Grid Array Package
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
S29AL032D
3.0 Volt-only, 32 Megabit Standard Flash Memory, manufactured using 200 nm process technology
S29AL032D Valid Combinations
Device Number
Speed
Option
Package Type, Material,
and Temperature
Range
TAI, TFI
70
BAI, BFI
S29AL032D
TAI, TFI, TAN, TFN
90
BAI, BFI, BAN, BFN
Model
Number
00
03, 04
00, 03, 04
00
03, 04
00, 03, 04
Packing Type
0, 3 (Note 1)
0, 2, 3 (Note 1)
0, 3 (Note 1)
0, 2, 3 (Note 1)
Package Description
TS040 (Note 2)
TS048 (Note 2)
VBN048 (Note 3)
TS040 (Note 2)
TS048 (Note 2)
VBN048 (Note 3)
TSOP
Fine-Pitch
BGA
TSOP
Fine-Pitch
BGA
Notes
1. Type 0 is standard. Specify other options as required.
2. TSOP package marking omits packing type designator from ordering part number.
3. BGA package marking omits leading S29 and packing type designator from ordering part number.
January 19, 2007 S29AL032D_00_A9
S29AL032D
11
D at a
6.2
S hee t
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.
7. Device Bus Operations
This section describes the requirements and use of the device bus operations, which are initiated through the
internal command register. The command register itself does not occupy any addressable memory location.
The register is composed of latches that store the commands, along with the address and data information
needed to execute the command. The contents of the register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the device. Table 7.1 lists the device bus operations, the
inputs and control levels they require, and the resulting output. The following subsections describe each of
these operations in further detail.
Table 7.1 S29AL032D Device Bus Operations
DQ8–DQ15 (Note 6)
CE#
OE#
WE#
RESET#
WP#(Note 6)/ACC
Addresses
(Note 3)
DQ0–
DQ7
BYTE#
= VIH
Read
L
L
H
H
L/H
AIN
DOUT
DOUT
Write (Note 1)
L
H
L
H
(Note 4)
AIN
(Note 5)
(Note 5)
Accelerated Program
(Note 6)
L
H
L
H
VHH
AIN
(Note 5)
(Note 5)
VCC ±
0.3 V
X
X
VCC ±
0.3 V
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
L/H
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
L/H
X
High-Z
High-Z
High-Z
(Note 5)
X
X
(Note 5)
X
X
(Note 5)
(Note 5)
High-Z
Operation
Standby
Sector Protect (Note 3)
Sector Unprotect
(Note 3)
Temporary Sector
Unprotect
L
H
L
VID
L/H
L
H
L
VID
(Note 4)
X
X
X
VID
(Note 4)
SA, A6 = L,
A1 = H, A0 = L
SA, A6 = H,
A1 = H, A0 = L
AIN
BYTE# = VIL
DQ8–DQ14 =
High-Z, DQ15 =
A-1
Legend
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes
1. When the ACC pin is at VHH, the device enters the accelerated program mode. See
2. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).
3. The sector protect and sector unprotect functions may also be implemented via programming equipment.
4. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection depends on whether they were
last protected or unprotected. If WP#/ACC = VHH, all sectors are unprotected.
5. DIN or DOUT as required by command sequence, data polling, or sector protection algorithm.
6. Models 03, 04 only
7.1
Word/Byte Configuration (Models 03, 04 Only)
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word
configuration. If the BYTE# pin is set at logic 1, the device is in word configuration, DQ15–DQ0 are active and
controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used
as an input for the LSB (A-1) address function.
12
S29AL032D
S29AL032D_00_A9 January 19, 2007
Data
7.2
She et
Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE# should
remain at VIH. The BYTE# pin determines whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses
on the device-address inputs produce valid data on the device-data outputs. The device remains enabled for
read access until the command register contents are altered.
See Reading Array Data on page 32 for more information. Refer to the AC Read Operations on page 49
table for timing specifications and to Figure 17.1 on page 49 for the timing diagram. ICC1 in the DC
Characteristics table represents the active current specification for reading array data.
7.3
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or
words. Refer to Word/Byte Configuration (Models 03, 04 Only) on page 12 for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. Word/
Byte Program Command Sequence on page 33 has details on programming data to the device using both
standard and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Table 7.3 on page 15 and
Table 7.5 on page 17 indicate the address space that each sector occupies. A sector address consists of the
address bits required to uniquely select a sector. The Command Definitions on page 32 contains details on
erasing a sector or the entire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to Autoselect Mode on page 21 and
Autoselect Command Sequence on page 32 for more information.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. AC
Characteristics on page 49 contains timing specification tables and timing diagrams for write operations.
7.4
Program and Erase Operation Status
During an erase or program operation, the system may check the status of the operation by reading the
status bits on DQ7–DQ0. Standard read cycle timings and ICC read specifications apply. Refer to Write
Operation Status on page 40 for more information, and to AC Characteristics on page 49 for timing
diagrams.
7.5
Accelerated Program Operation
The device offers accelerated program operations through the ACC function. This is one of two functions
provided by the WP#/ACC (ACC on Model 00) pin. This function is primarily intended to allow faster
manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device automatically enters the previously mentioned Unlock
Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce
the time required for program operations. The system would use a two-cycle program command sequence as
required by the Unlock Bypass mode. Removing VHH from the WP#/ACC pin returns the device to normal
operation. Note that the WP#/ACC pin must not be at VHH for operations other than accelerated
programming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may result.
January 19, 2007 S29AL032D_00_A9
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7.6
S hee t
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state,
independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device
requires standard access time (tCE) for read access when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the operation
is completed.
In the DC Characteristics table, ICC3 and ICC4 represents the standby current specification.
7.7
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for tASM. The automatic sleep mode is independent of the CE#,
WE#, and OE# control signals. Standard address access timings provide new data when addresses are
changed. While in sleep mode, output data is latched and always available to the system. ICC4 in DC
Characteristics on page 46 represents the automatic sleep mode current specification.
Table 7.2 Automatic Sleep Mode Timing
7.8
Parameter
Description
Max.
Unit
tASM
Automatic Sleep Mode
tACC+30
ns
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the system
drives the RESET# pin to VIL for at least a period of tRP, the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure
data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current
will be greater.
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the
internal reset operation is complete, which requires a time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is
asserted when a program or erase operation is not executing (RY/BY# pin is 1), the reset operation is
completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after the
RESET# pin returns to VIH.
Refer to AC Characteristics on page 49 for RESET# parameters and to Figure 17.2 on page 50 for the timing
diagram.
7.9
Output Disable Mode
When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high
impedance state.
14
S29AL032D
S29AL032D_00_A9 January 19, 2007
Data
7.10
She et
Sector Addresss Tables
Table 7.3 Model 00 Sector Addresses (Sheet 1 of 2)
Sector
A21
A20
A19
A18
A17
A16
Address Range
(in hexadecimal)
SA0
0
0
0
0
0
0
000000–00FFFF
SA1
0
0
0
0
0
1
010000–01FFFF
SA2
0
0
0
0
1
0
020000–02FFFF
SA3
0
0
0
0
1
1
030000–03FFFF
SA4
0
0
0
1
0
0
040000–04FFFF
SA5
0
0
0
1
0
1
050000–05FFFF
SA6
0
0
0
1
1
0
060000–06FFFF
SA7
0
0
0
1
1
1
070000–07FFFF
SA8
0
0
1
0
0
0
080000–08FFFF
SA9
0
0
1
0
0
1
090000–09FFFF
SA10
0
0
1
0
1
0
0A0000–0AFFFF
SA11
0
0
1
0
1
1
0B0000–0BFFFF
SA12
0
0
1
1
0
0
0C0000–0CFFFF
SA13
0
0
1
1
0
1
0D0000–0DFFFF
SA14
0
0
1
1
1
0
0E0000–0EFFFF
SA15
0
0
1
1
1
1
0F0000–0FFFFF
SA16
0
1
0
0
0
0
100000–10FFFF
SA17
0
1
0
0
0
1
110000–11FFFF
SA18
0
1
0
0
1
0
120000–12FFFF
SA19
0
1
0
0
1
1
130000–13FFFF
SA20
0
1
0
1
0
0
140000–14FFFF
SA21
0
1
0
1
0
1
150000–15FFFF
SA22
0
1
0
1
1
0
160000–16FFFF
SA23
0
1
0
1
1
1
170000–17FFFF
SA24
0
1
1
0
0
0
180000–18FFFF
SA25
0
1
1
0
0
1
190000–19FFFF
SA26
0
1
1
0
1
0
1A0000–1AFFFF
SA27
0
1
1
0
1
1
1B0000–1BFFFF
SA28
0
1
1
1
0
0
1C0000–1CFFFF
SA29
0
1
1
1
0
1
1D0000–1DFFFF
SA30
0
1
1
1
1
0
1E0000–1EFFFF
SA31
0
1
1
1
1
1
1F0000–1FFFFF
SA32
1
0
0
0
0
0
200000–20FFFF
SA33
1
0
0
0
0
1
210000–21FFFF
SA34
1
0
0
0
1
0
220000–22FFFF
SA35
1
0
0
0
1
1
230000–23FFFF
SA36
1
0
0
1
0
0
240000–24FFFF
SA37
1
0
0
1
0
1
250000–25FFFF
SA38
1
0
0
1
1
0
260000–26FFFF
SA39
1
0
0
1
1
1
270000–27FFFF
SA40
1
0
1
0
0
0
280000–28FFFF
SA41
1
0
1
0
0
1
290000–29FFFF
SA42
1
0
1
0
1
0
2A0000–2AFFFF
January 19, 2007 S29AL032D_00_A9
S29AL032D
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S hee t
Table 7.3 Model 00 Sector Addresses (Sheet 2 of 2)
Sector
A21
A20
A19
A18
A17
A16
Address Range
(in hexadecimal)
SA43
1
0
1
0
1
1
2B0000–2BFFFF
SA44
1
0
1
1
0
0
2C0000–2CFFFF
SA45
1
0
1
1
0
1
2D0000–2DFFFF
SA46
1
0
1
1
1
0
2E0000–2EFFFF
SA47
1
0
1
1
1
1
2F0000–2FFFFF
SA48
1
1
0
0
0
0
300000–30FFFF
SA49
1
1
0
0
0
1
310000–31FFFF
SA50
1
1
0
0
1
0
320000–32FFFF
SA51
1
1
0
0
1
1
330000–33FFFF
SA52
1
1
0
1
0
0
340000–34FFFF
SA53
1
1
0
1
0
1
350000–35FFFF
SA54
1
1
0
1
1
0
360000–36FFFF
SA55
1
1
0
1
1
1
370000–37FFFF
SA56
1
1
1
0
0
0
380000–38FFFF
SA57
1
1
1
0
0
1
390000–39FFFF
SA58
1
1
1
0
1
0
3A0000–3AFFFF
SA59
1
1
1
0
1
1
3B0000–3BFFFF
SA60
1
1
1
1
0
0
3C0000–3CFFFF
SA61
1
1
1
1
0
1
3D0000–3DFFFF
SA62
1
1
1
1
1
0
3E0000–3EFFFF
SA63
1
1
1
1
1
1
3F0000–3FFFFF
Note
All sectors are 64 Kbytes in size.
Table 7.4 Model 00 Secured Silicon Sector Addresses
16
Sector Address
A21–A7
Sector Size
(bytes)
(x8)
Address Range
000000000000000
128
000000h–00007fh
000000000001000
128
000400h-00047Fh
S29AL032D
S29AL032D_00_A9 January 19, 2007
Data
She et
Table 7.5 Model 03 Sector Addresses (Sheet 1 of 2)
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/
Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
000000xxx
64/32
000000h–00FFFFh
000000h–07FFFh
SA1
000001xxx
64/32
010000h–01FFFFh
008000h–0FFFFh
SA2
000010xxx
64/32
020000h–02FFFFh
010000h–17FFFh
SA3
000011xxx
64/32
030000h–03FFFFh
018000h–01FFFFh
SA4
000100xxx
64/32
040000h–04FFFFh
020000h–027FFFh
SA5
000101xxx
64/32
050000h–05FFFFh
028000h–02FFFFh
SA6
000110xxx
64/32
060000h–06FFFFh
030000h–037FFFh
SA7
000111xxx
64/32
070000h–07FFFFh
038000h–03FFFFh
SA8
001000xxx
64/32
080000h–08FFFFh
040000h–047FFFh
SA9
001001xxx
64/32
090000h–09FFFFh
048000h–04FFFFh
SA10
001010xxx
64/32
0A0000h–0AFFFFh
050000h–057FFFh
SA11
001011xxx
64/32
0B0000h–0BFFFFh
058000h–05FFFFh
SA12
001100xxx
64/32
0C0000h–0CFFFFh
060000h–067FFFh
SA13
001101xxx
64/32
0D0000h–0DFFFFh
068000h–06FFFFh
SA14
001110xxx
64/32
0E0000h–0EFFFFh
070000h–077FFFh
SA15
001111xxx
64/32
0F0000h–0FFFFFh
078000h–07FFFFh
SA16
010000xxx
64/32
100000h–10FFFFh
080000h–087FFFh
SA17
010001xxx
64/32
110000h–11FFFFh
088000h–08FFFFh
SA18
010010xxx
64/32
120000h–12FFFFh
090000h–097FFFh
SA19
010011xxx
64/32
130000h–13FFFFh
098000h–09FFFFh
SA20
010100xxx
64/32
140000h–14FFFFh
0A0000h–0A7FFFh
SA21
010101xxx
64/32
150000h–15FFFFh
0A8000h–0AFFFFh
SA22
010110xxx
64/32
160000h–16FFFFh
0B0000h–0B7FFFh
SA23
010111xxx
64/32
170000h–17FFFFh
0B8000h–0BFFFFh
SA24
011000xxx
64/32
180000h–18FFFFh
0C0000h–0C7FFFh
SA25
011001xxx
64/32
190000h–19FFFFh
0C8000h–0CFFFFh
SA26
011010xxx
64/32
1A0000h–1AFFFFh
0D0000h–0D7FFFh
SA27
011011xxx
64/32
1B0000h–1BFFFFh
0D8000h–0DFFFFh
SA28
011100xxx
64/32
1C0000h–1CFFFFh
0E0000h–0E7FFFh
SA29
011101xxx
64/32
1D0000h–1DFFFFh
0E8000h–0EFFFFh
SA30
011110xxx
64/32
1E0000h–1EFFFFh
0F0000h–0F7FFFh
SA31
011111xxx
64/32
1F0000h–1FFFFFh
0F8000h–0FFFFFh
SA32
100000xxx
64/32
200000h–20FFFFh
100000h–107FFFh
SA33
100001xxx
64/32
210000h–21FFFFh
108000h–10FFFFh
SA34
100010xxx
64/32
220000h–22FFFFh
110000h–117FFFh
SA35
100011xxx
64/32
230000h–23FFFFh
118000h–11FFFFh
SA36
100100xxx
64/32
240000h–24FFFFh
120000h–127FFFh
SA37
100101xxx
64/32
250000h–25FFFFh
128000h–12FFFFh
SA38
100110xxx
64/32
260000h–26FFFFh
130000h–137FFFh
SA39
100111xxx
64/32
270000h–27FFFFh
138000h–13FFFFh
SA40
101000xxx
64/32
280000h–28FFFFh
140000h–147FFFh
SA41
101001xxx
64/32
290000h–29FFFFh
148000h–14FFFFh
SA42
101010xxx
64/32
2A0000h–2AFFFFh
150000h–157FFFh
January 19, 2007 S29AL032D_00_A9
S29AL032D
17
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S hee t
Table 7.5 Model 03 Sector Addresses (Sheet 2 of 2)
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/
Kwords)
SA43
101011xxx
SA44
101100xxx
SA45
SA46
(x8)
Address Range
(x16)
Address Range
64/32
2B0000h–2BFFFFh
158000h–15FFFFh
64/32
2C0000h–2CFFFFh
160000h–167FFFh
101101xxx
64/32
2D0000h–2DFFFFh
168000h–16FFFFh
101110xxx
64/32
2E0000h–2EFFFFh
170000h–177FFFh
SA47
101111xxx
64/32
2F0000h–2FFFFFh
178000h–17FFFFh
SA48
110000xxx
64/32
300000h–30FFFFh
180000h–187FFFh
SA49
110001xxx
64/32
310000h–31FFFFh
188000h–18FFFFh
SA50
110010xxx
64/32
320000h–32FFFFh
190000h–197FFFh
SA51
110011xxx
64/32
330000h–33FFFFh
198000h–19FFFFh
SA52
110100xxx
64/32
340000h–34FFFFh
1A0000h–1A7FFFh
SA53
110101xxx
64/32
350000h–35FFFFh
1A8000h–1AFFFFh
SA54
110110xxx
64/32
360000h–36FFFFh
1B0000h–1B7FFFh
SA55
110111xxx
64/32
370000h–37FFFFh
1B8000h–1BFFFFh
SA56
111000xxx
64/32
380000h–38FFFFh
1C0000h–1C7FFFh
SA57
111001xxx
64/32
390000h–39FFFFh
1C8000h–1CFFFFh
SA58
111010xxx
64/32
3A0000h–3AFFFFh
1D0000h–1D7FFFh
SA59
111011xxx
64/32
3B0000h–3BFFFFh
1D8000h–1DFFFFh
SA60
111100xxx
64/32
3C0000h–3CFFFFh
1E0000h–1E7FFFh
SA61
111101xxx
64/32
3D0000h–3DFFFFh
1E8000h–1EFFFFh
SA62
111110xxx
64/32
3E0000h–3EFFFFh
1F0000h–1F7FFFh
SA63
111111000
8/4
3F0000h–3F1FFFh
1F8000h–1F8FFFh
SA64
111111001
8/4
3F2000h–3F3FFFh
1F9000h–1F9FFFh
SA65
111111010
8/4
3F4000h–3F5FFFh
1FA000h–1FAFFFh
SA66
111111011
8/4
3F6000h–3F7FFFh
1FB000h–1FBFFFh
SA67
111111100
8/4
3F8000h–3F9FFFh
1FC000h–1FCFFFh
SA68
111111101
8/4
3FA000h–3FBFFFh
1FD000h–1FDFFFh
SA69
111111110
8/4
3FC000h–3FDFFFh
1FE000h–1FEFFFh
SA70
111111111
8/4
3FE000h–3FFFFFh
1FF000h–1FFFFFh
Note
The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).
Table 7.6 Model 03 Secured Silicon Sector Addresses
18
Sector Address
A20–A12
Sector Size
(bytes/words)
(x8)
Address Range
(x16)
Address Range
111111111
256/128
3FFF00h–3FFFFFh
1FFF80h–1FFFFFh
S29AL032D
S29AL032D_00_A9 January 19, 2007
Data
She et
Table 7.7 Model 04 Sector Addresses (Sheet 1 of 2)
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/
Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
000000000
8/4
000000h-001FFFh
000000h–000FFFh
SA1
000000001
8/4
002000h-003FFFh
001000h–001FFFh
SA2
000000010
8/4
004000h-005FFFh
002000h–002FFFh
SA3
000000011
8/4
006000h-007FFFh
003000h–003FFFh
SA4
000000100
8/4
008000h-009FFFh
004000h–004FFFh
SA5
000000101
8/4
00A000h-00BFFFh
005000h–005FFFh
SA6
000000110
8/4
00C000h-00DFFFh
006000h–006FFFh
SA7
000000111
8/4
00E000h-00FFFFh
007000h–007FFFh
SA8
000001xxx
64/32
010000h-01FFFFh
008000h–00FFFFh
SA9
000010xxx
64/32
020000h-02FFFFh
010000h–017FFFh
SA10
000011xxx
64/32
030000h-03FFFFh
018000h–01FFFFh
SA11
000100xxx
64/32
040000h-04FFFFh
020000h–027FFFh
SA12
000101xxx
64/32
050000h-05FFFFh
028000h–02FFFFh
SA13
000110xxx
64/32
060000h-06FFFFh
030000h–037FFFh
SA14
000111xxx
64/32
070000h-07FFFFh
038000h–03FFFFh
SA15
001000xxx
64/32
080000h-08FFFFh
040000h–047FFFh
SA16
001001xxx
64/32
090000h-09FFFFh
048000h–04FFFFh
SA17
001010xxx
64/32
0A0000h-0AFFFFh
050000h–057FFFh
SA18
001011xxx
64/32
0B0000h-0BFFFFh
058000h–05FFFFh
SA19
001100xxx
64/32
0C0000h-0CFFFFh
060000h–067FFFh
SA20
001101xxx
64/32
0D0000h-0DFFFFh
068000h–06FFFFh
SA21
001110xxx
64/32
0E0000h-0EFFFFh
070000h–077FFFh
SA22
001111xxx
64/32
0F0000h-0FFFFFh
078000h–07FFFFh
SA23
010000xxx
64/32
100000h-10FFFFh
080000h–087FFFh
SA24
010001xxx
64/32
110000h-11FFFFh
088000h–08FFFFh
SA25
010010xxx
64/32
120000h-12FFFFh
090000h–097FFFh
SA26
010011xxx
64/32
130000h-13FFFFh
098000h–09FFFFh
SA27
010100xxx
64/32
140000h-14FFFFh
0A0000h–0A7FFFh
SA28
010101xxx
64/32
150000h-15FFFFh
0A8000h–0AFFFFh
SA29
010110xxx
64/32
160000h-16FFFFh
0B0000h–0B7FFFh
SA30
010111xxx
64/32
170000h-17FFFFh
0B8000h–0BFFFFh
SA31
011000xxx
64/32
180000h-18FFFFh
0C0000h–0C7FFFh
SA32
011001xxx
64/32
190000h-19FFFFh
0C8000h–0CFFFFh
SA33
011010xxx
64/32
1A0000h-1AFFFFh
0D0000h–0D7FFFh
SA34
011011xxx
64/32
1B0000h-1BFFFFh
0D8000h–0DFFFFh
SA35
011100xxx
64/32
1C0000h-1CFFFFh
0E0000h–0E7FFFh
SA36
011101xxx
64/32
1D0000h-1DFFFFh
0E8000h–0EFFFFh
SA37
011110xxx
64/32
1E0000h-1EFFFFh
0F0000h–0F7FFFh
SA38
011111xxx
64/32
1F0000h-1FFFFFh
0F8000h–0FFFFFh
SA39
100000xxx
64/32
200000h-20FFFFh
100000h–107FFFh
SA40
100001xxx
64/32
210000h-21FFFFh
108000h–10FFFFh
SA41
100010xxx
64/32
220000h-22FFFFh
110000h–117FFFh
SA42
100011xxx
64/32
230000h-23FFFFh
118000h–11FFFFh
January 19, 2007 S29AL032D_00_A9
S29AL032D
19
D at a
S hee t
Table 7.7 Model 04 Sector Addresses (Sheet 2 of 2)
Sector
Sector Address
A20–A12
Sector Size
(Kbytes/
Kwords)
(x8)
Address Range
(x16)
Address Range
SA43
100100xxx
64/32
240000h-24FFFFh
120000h–127FFFh
SA44
100101xxx
64/32
250000h-25FFFFh
128000h–12FFFFh
SA45
100110xxx
64/32
260000h-26FFFFh
130000h–137FFFh
SA46
100111xxx
64/32
270000h-27FFFFh
138000h–13FFFFh
SA47
101000xxx
64/32
280000h-28FFFFh
140000h–147FFFh
SA48
101001xxx
64/32
290000h-29FFFFh
148000h–14FFFFh
SA49
101010xxx
64/32
2A0000h-2AFFFFh
150000h–157FFFh
SA50
101011xxx
64/32
2B0000h-2BFFFFh
158000h–15FFFFh
SA51
101100xxx
64/32
2C0000h-2CFFFFh
160000h–167FFFh
SA52
101101xxx
64/32
2D0000h-2DFFFFh
168000h–16FFFFh
SA53
101110xxx
64/32
2E0000h-2EFFFFh
170000h–177FFFh
SA54
101111xxx
64/32
2F0000h-2FFFFFh
178000h–17FFFFh
SA55
111000xxx
64/32
300000h-30FFFFh
180000h–187FFFh
SA56
110001xxx
64/32
310000h-31FFFFh
188000h–18FFFFh
SA57
110010xxx
64/32
320000h-32FFFFh
190000h–197FFFh
SA58
110011xxx
64/32
330000h-33FFFFh
198000h–19FFFFh
SA59
110100xxx
64/32
340000h-34FFFFh
1A0000h–1A7FFFh
SA60
110101xxx
64/32
350000h-35FFFFh
1A8000h–1AFFFFh
SA61
110110xxx
64/32
360000h-36FFFFh
1B0000h–1B7FFFh
SA62
110111xxx
64/32
370000h-37FFFFh
1B8000h–1BFFFFh
SA63
111000xxx
64/32
380000h-38FFFFh
1C0000h–1C7FFFh
SA64
111001xxx
64/32
390000h-39FFFFh
1C8000h–1CFFFFh
SA65
111010xxx
64/32
3A0000h-3AFFFFh
1D0000h–1D7FFFh
SA66
111011xxx
64/32
3B0000h-3BFFFFh
1D8000h–1DFFFFh
SA67
111100xxx
64/32
3C0000h-3CFFFFh
1E0000h–1E7FFFh
SA68
111101xxx
64/32
3D0000h-3DFFFFh
1E8000h–1EFFFFh
SA69
111110xxx
64/32
3E0000h-3EFFFFh
1F0000h–1F7FFFh
SA70
111111xxx
64/32
3F0000h-3FFFFFh
1F8000h–1FFFFFh
Note
The address range is A20:A-1 in byte mode (BYTE#=VIL) or A20:A0 in word mode (BYTE#=VIH).
Table 7.8 Model 04 Secured Silicon Sector Addresses
20
Sector Address
A20–A12
Sector Size
(bytes/words)
(x8)
Address Range
(x16)
Address Range
000000000
256/128
000000h-0000FFh
00000h-0007Fh
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7.11
She et
Autoselect Mode
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This mode is primarily intended for programming equipment to
automatically match a device to be programmed with its corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the command register.
When using programming equipment, the autoselect mode requires VID (11.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in Table 7.9. In addition, when verifying sector protection, the
sector address must appear on the appropriate highest order address bits (see Table 7.3 on page 15 and
Table 7.5 on page 17). Table 7.9 shows the remaining address bits that are don’t care. When all necessary
bits have been set as required, the programming equipment may then read the corresponding identifier code
on DQ7-DQ0.
To access the autoselect codes in-system, the host system can issue the autoselect command via the
command register, as shown in Table 11.2 on page 38. This method does not require VID. See Command
Definitions for details on using the autoselect mode.
Table 7.9 S29AL032D Autoselect Codes (High Voltage Method)
A11
to
A10
A9
A8
to
A7
A6
A5 to
A4
A3
to
A2
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
CE#
OE#
WE#
A21
to
A12
L
L
H
X
X
VID
X
L
X
L
L
L
X
01h
Byte
L
L
H
X
X
VID
X
L
X
L
L
H
N/A
A3h
Device ID:
S29AL032D
(Model 03)
Word
L
L
H
22h
F6h
L
H
X
VID
X
L
X
L
L
H
Byte
L
X
X
F6h
Device ID:
S29AL032D
(Model 04)
Word
L
L
H
22h
F9h
X
X
VID
X
L
X
L
L
H
X
F9h
Description
Mode
Manufacturer ID:
Spansion
Device ID:
S29AL032D
(Model 00)
Byte
Sector Protection
Verification
Secured Silicon Sector
Indicator Bit (DQ7)
L
L
H
L
L
H
SA
X
VID
X
L
X
L
H
L
L
L
H
X
X
VID
X
L
X
L
H
H
L
L
H
X
X
VID
X
L
X
L
H
H
L
L
H
X
X
VID
X
L
X
L
H
H
(Model 00)
Secured Silicon Sector
Indicator Bit (DQ7)
(Model 03)
Secured Silicon Sector
Indicator Bit (DQ7)
(Model 04)
X
01h (protected)
X
00h (unprotected)
X
85 (factory locked)
X
05 (not factory
locked)
X
8D (factory locked)
X
1D (not factory
locked)
X
9D (factory locked)
X
0D (not factory
locked)
Legend
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Note
The autoselect codes may also be accessed in-system via command sequences. See Table 11.2 on page 38.
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7.12
S hee t
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors.
The device is shipped with all sectors unprotected. Spansion offers the option of programming and protecting
sectors at its factory prior to shipping the device through the Spansion ExpressFlash™ Service. Contact a
Spansion representative for further details.
It is possible to determine whether a sector is protected or unprotected. See Autoselect Mode for details.
Sector protection/unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin only, and can be implemented either in-system or via
programming equipment. Figure 7.1 on page 25 shows the algorithms and Figure 17.13 on page 57 shows
the timing diagram. This method uses standard microprocessor bus cycle timing. For sector unprotect, all
unprotected sectors must first be protected prior to the first sector unprotect write cycle.
The alternate method intended only for programming equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines written for earlier 3.0-volt-only Spansion flash devices.
Details on this method are provided in a supplement, publication number 21468. Contact a Spansion
representative to request a copy.
Table 7.10 Sector Block Addresses for Protection/Unprotection — Model 00
Sector/Sector Block
22
A21–A16
Sector/Sector Block Size
SA0
000000
64 Kbytes
SA1-SA3
000001, 000010, 000011
192 (3x64) Kbytes
SA4-SA7
000100, 000101, 000110, 000111
256 (4x64) Kbytes
SA8-SA11
001000, 001001, 001010, 001011
256 (4x64) Kbytes
SA12-SA15
001100, 001101, 001110, 001111
256 (4x64) Kbytes
SA16-SA19
010000, 010001, 010010, 010011
256 (4x64) Kbytes
SA20-SA23
010100, 010101, 010110, 010111
256 (4x64) Kbytes
SA24-SA27
011000, 011001, 011010, 011011
256 (4x64) Kbytes
SA28-SA31
011100, 011101, 011110, 011111
256 (4x64) Kbytes
SA32-SA35
100000, 100001, 100010, 100011
256 (4x64) Kbytes
SA36-SA39
100100, 100101, 100110, 100111
256 (4x64) Kbytes
SA40-SA43
101000, 101001, 101010, 101011
256 (4x64) Kbytes
SA44-SA47
101100, 101101, 101110, 101111
256 (4x64) Kbytes
SA48-SA51
110000, 110001, 110010, 110011
256 (4x64) Kbytes
SA52-SA55
110100, 110101, 110110, 110111
256 (4x64) Kbytes
SA56-SA59
111000, 111001, 111010, 111011
256 (4x64) Kbytes
SA60-SA62
111100, 111101, 111110
192 (4x64) Kbytes
SA63
111111
64 Kbytes
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Table 7.11 Sector Block Addresses for Protection/Unprotection — Model 03
Sector / Sector Block
A20–A12
Sector/Sector Block Size
SA0-SA3
000000XXX, 000001XXX, 000010XXX, 000011XXX
256 (4x64) Kbytes
SA4-SA7
0001XXXXX
256 (4x64) Kbytes
SA8-SA11
0010XXXXX
256 (4x64) Kbytes
SA12-SA15
0011XXXXX
256 (4x64) Kbytes
SA16-SA19
0100XXXXX
256 (4x64) Kbytes
SA20-SA23
0101XXXXX
256 (4x64) Kbytes
SA24-SA27
0110XXXXX
256 (4x64) Kbytes
SA28-SA31
0111XXXXX
256 (4x64) Kbytes
SA32-SA35
1000XXXXX
256 (4x64) Kbytes
SA36-SA39
1001XXXXX
256 (4x64) Kbytes
SA40-SA43
1010XXXXX
256 (4x64) Kbytes
SA44-SA47
1011XXXXX
256 (4x64) Kbytes
SA48-SA51
1100XXXXX
256 (4x64) Kbytes
SA52-SA55
1101XXXXX
256 (4x64) Kbytes
SA56-SA59
1110XXXXX
256 (4x64) Kbytes
SA60-SA62
111100XXX, 111101XXX, 111110XXX
192 (3x64) Kbytes
SA63
111111000
8 Kbytes
SA64
111111001
8 Kbytes
SA65
111111010
8 Kbytes
SA66
111111011
8 Kbytes
SA67
111111100
8 Kbytes
SA68
111111101
8 Kbytes
SA69
111111110
8 Kbytes
SA70
111111111
8 Kbytes
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Table 7.12 Sector Block Addresses for Protection/Unprotection — Model 04
24
Sector / Sector Block
A20–A12
Sector/Sector Block Size
SA70-SA67
111111XXX, 111110XXX, 111101XXX, 111100XXX
256 (4x64) Kbytes
SA66-SA63
1110XXXXX
256 (4x64) Kbytes
SA62-SA59
1101XXXXX
256 (4x64) Kbytes
SA58-SA55
1100XXXXX
256 (4x64) Kbytes
SA54-SA51
1011XXXXX
256 (4x64) Kbytes
SA50-SA47
1010XXXXX
256 (4x64) Kbytes
SA46-SA43
1001XXXXX
256 (4x64) Kbytes
SA42-SA39
1000XXXXX
256 (4x64) Kbytes
SA38-SA35
0111XXXXX
256 (4x64) Kbytes
SA34-SA31
0110XXXXX
256 (4x64) Kbytes
SA30-SA27
0101XXXXX
256 (4x64) Kbytes
SA26-SA23
0100XXXXX
256 (4x64) Kbytes
SA22–SA19
0011XXXXX
256 (4x64) Kbytes
SA18-SA15
0010XXXXX
256 (4x64) Kbytes
SA14-SA11
0001XXXXX
256 (4x64) Kbytes
SA10-SA8
000011XXX, 000010XXX, 000001XXX
192 (3x64) Kbytes
SA7
000000111
8 Kbytes
SA6
000000110
8 Kbytes
SA5
000000101
8 Kbytes
SA4
000000100
8 Kbytes
SA3
000000011
8 Kbytes
SA2
000000010
8 Kbytes
SA1
000000001
8 Kbytes
SA0
000000000
8 Kbytes
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Figure 7.1 In-System Sector Protect/Unprotect Algorithms
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 ms
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 ms
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Temporary Sector
Unprotect Mode
Yes
Yes
Set up sector
address
No
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
All sectors
protected?
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
No
Reset
PLSCNT = 1
Wait 15 ms
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Yes
Yes
No
Yes
Device failed
PLSCNT
= 1000?
Protect another
sector?
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Protect
Algorithm
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Sector Protect
complete
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
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7.13
S hee t
Write Protect (WP#) — Models 03, 04 Only
The Write Protect function provides a hardware method of protecting certain boot sectors without using VID.
This function is one of two provided by the WP#/ACC pin.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two
outermost 8-Kbyte boot sectors independently of whether those sectors were protected or unprotected using
the method described in Sector Protection/Unprotection on page 22. The two outermost 8-Kbyte boot
sectors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two
sectors containing the highest addresses in a top-boot-configured device.
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8-KByte boot
sectors were last set to be protected or unprotected. That is, sector protection or unprotection for these two
sectors depends on whether they were last protected or unprotected using the method described in Sector
Protection/Unprotection on page 22.
Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may
result.
7.14
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to VID. During this mode, formerly protected
sectors can be programmed or erased by selecting the sector addresses. Once VID is removed from the
RESET# pin, all the previously protected sectors are protected again. shows the algorithm, and Figure 17.11
on page 56 shows the timing diagrams, for this feature.
Figure 7.2 Temporary Sector Unprotect Operation
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Notes
1. All protected sectors unprotected.
2. All previously protected sectors are protected once again.
8. Secured Silicon Sector Flash Memory Region
The Secured Silicon Sector feature provides a 256-byte Flash memory region that enables permanent part
identification through an Electronic Serial Number (ESN). The Secured Silicon Sector uses a Secured Silicon
Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from
the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a
factory-locked part. This ensures the security of the ESN once the product is shipped to the field.
Spansion offers the device with the Secured Silicon Sector either factory-locked or customer-lockable. The
factory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector
26
S29AL032D
S29AL032D_00_A9 January 19, 2007
Data
She et
Indicator Bit permanently set to a 1. The customer-lockable version is shipped with the Secured Silicon
Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The customerlockable version has the Secured Silicon Sector Indicator Bit permanently set to a 0. Thus, the Secured
Silicon Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are
factory locked.
The system accesses the Secured Silicon Sector through a command sequence (see Enter Secured Silicon
Sector/Exit Secured Silicon Sector Command Sequence on page 33). After the system writes the Enter
Secured Silicon Sector command sequence, it may read the Secured Silicon Sector by using the addresses
normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit
Secured Silicon Sector command sequence, or until power is removed from the device. On power-up, or
following a hardware reset, the device reverts to sending commands to the boot sectors.
8.1
Factory Locked: Secured Silicon Sector Programmed
and Protected at the Factory
In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the
factory. The Secured Silicon Sector cannot be modified in any way. The device is available pre-programmed
with one of the following:
„ A random, secure ESN only.
„ Customer code through the ExpressFlash service.
„ Both a random, secure ESN and customer code through the ExpressFlash service.
In devices that have an ESN, a Bottom Boot device has the 16-byte (8-word) ESN in sector 0 at addresses
00000h–0000Fh in byte mode (or 00000h–00007h in word mode). In the Top Boot device, the ESN is in
sector 70 at addresses 3FFF00h–3FFF0Fh in byte mode (or 1FFF80h–1FFF87h in word mode). In the
Uniform device, the ESN is in sector 63 at addresses 3FFF00h-3FFF0Fh in byte mode (or 1FFF80h-1FFF87h
in word mode).
Customers may opt to have their code programmed by Spansion through the Spansion ExpressFlash
service. Spansion programs the customer’s code, with or without the random ESN. The devices are then
shipped from the Spansion factory with the Secured Silicon Sector permanently locked. Contact a Spansion
representative for details on using the Spansion ExpressFlash service.
8.2
Customer Lockable: Secured Silicon Sector NOT Programmed
or Protected at the Factory
The customer lockable version allows the Secured Silicon Sector to be programmed once, and then
permanently locked after it ships from Spansion. Note that the accelerated programming (ACC) and unlock
bypass functions are not available when programming the Secured Silicon Sector.
The Secured Silicon Sector area can be protected using the following procedures:
„ Write the three-cycle Enter Secured Silicon Region command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 7.1 on page 25, except that RESET# may be at either VIH or
VID. This allows in-system protection of the Secured Silicon Sector without raising any device pin to a high
voltage. Note that this method is only applicable to the Secured Silicon Sector.
„ To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure
8.1 on page 28.
Once the Secured Silicon Sector is locked and verified, the system must write the Exit Secured Silicon Sector
Region command sequence to return to reading and writing the remainder of the array.
The Secured Silicon Sector protection must be used with caution since, once protected, there is no procedure
available for unprotecting the Secured Silicon Sector area, and none of the bits in the Secured Silicon Sector
memory space can be modified in any way.
January 19, 2007 S29AL032D_00_A9
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27
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Figure 8.1 Secured Silicon Sector Protect Verify
START
RESET# =
VIH or VID
Wait 1 ms
Write 60h to
any address
Write 40h to SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
Read from SecSi
Sector address
with A6 = 0,
A1 = 1, A0 = 0
If data = 00h,
SecSi Sector is
unprotected.
If data = 01h,
SecSi Sector is
protected.
Remove VIH or VID
from RESET#
Write reset
command
SecSi Sector
Protect Verify
complete
9. Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data protection
against inadvertent writes (refer to Table 11.2 on page 38 for command definitions). In addition, the following
hardware data protection measures prevent accidental erasure or programming, which might otherwise be
caused by spurious system level signals during VCC power-up and power-down transitions, or from system
noise.
9.1
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register and all internal program/erase circuits are disabled, and
the device resets. Subsequent writes are ignored until VCC is greater than VLKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
9.2
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle.
9.3
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a logical one.
9.4
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
28
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10. Common Flash Memory Interface (CFI)
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system
can read CFI information at the addresses given in Tables 10.1–10.4. In word mode, the upper address bits
(A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset command.
The system can also write the CFI query command when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 10.1–10.4.
The system must write the reset command to return the device to the autoselect mode.
For further information, please contact a Spansion representative for a copy of this document.
Table 10.1 CFI Query Identification String
Addresses
Addresses
(Models 03, 04
Byte Mode Only)
Data
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string QRY
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
Description
Table 10.2 System Interface String
Addresses
Addresses
(Models 03, 04
Byte Mode Only)
Data
1Bh
36h
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
38h
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
Description
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0004h
Typical timeout per single byte/word write 2N µs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
January 19, 2007 S29AL032D_00_A9
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Table 10.3 Device Geometry Definition
Addresses
30
Addresses
(Models 03, 04
Byte Mode Only)
Data
Description
N
27h
4Eh
0016h
Device Size = 2 byte
28h
29h
50h
52h
000xh
0000h
Flash Device Interface description (refer to CFI publication 100)
(0 = Model 00, 2 = Models 03, 04)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch
58h
000xh
Number of Erase Block Regions within device
(1 = Model 00, 2 = Models 03, 04)
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
00xxh
0000h
00x0h
000xh
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
(003F, 0000, 0000, 0001) = Model 00
31h
32h
33h
34h
62h
64h
66h
68h
00xxh
0000h
0020h
000xh
Erase Block Region 2 Information
(0000, 0000, 0000, 0000) = Model 00
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
(0007, 0000, 0020, 0000) = Models 03, 04
(003E, 0000, 0000, 0001) = Models 03, 04
S29AL032D
S29AL032D_00_A9 January 19, 2007
Data
She et
Table 10.4 Primary Vendor-Specific Extended Query
Addresses
Addresses
(Models 03, 04
Byte Mode Only)
Data
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
86h
0031h
Major version number, ASCII
44h
88h
0031h
Minor version number, ASCII
45h
8Ah
000xh
Address Sensitive Unlock
0 = Required (Models 03, 04), 1 = Not Required (Model 00)
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
90h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
4Ah
94h
0000h
Simultaneous Operation
00 = Not Supported, 01 = Supported
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
9Ah
00B5h
4Eh
9Ch
00C5h
4Fh
9Eh
000xh
January 19, 2007 S29AL032D_00_A9
Description
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
(0 = Model 00, 3 = Model 03, 2 = Model 04)
S29AL032D
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11. Command Definitions
Writing specific address and data commands or sequences into the command register initiates device
operations. Table 11.2 on page 38 defines the valid register command sequences. Writing incorrect address
and data values or writing them in the improper sequence resets the device to reading array data.
All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams under AC
Characteristics.
11.1
Reading Array Data
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within erasesuspended sectors, the device outputs status data. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same exception. See Erase Suspend/
Erase Resume Commands on page 35 for more information on this mode.
The system must issue the reset command in order to re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See Reset Command on page 32.
See also Requirements for Reading Array Data on page 13 for more information. The Read Operations on
page 49 provides the read parameters, and Figure 17.1 on page 49 shows the timing diagram.
11.2
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t care
for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in a program command sequence before
programming begins. This resets the device to reading array data (also applies to programming in Erase
Suspend mode). Once programming begins, however, the device ignores reset commands until the operation
is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to
reading array data (also applies during Erase Suspend).
11.3
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices codes,
and determine whether a sector is protected. Table 11.2 on page 38 shows the address and data
requirements. This method is an alternative to that shown in Table on page 21, which is intended for PROM
programmers and requires VID on address bit A9.
The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect mode, and the system may read at any address any
number of times, without initiating another command sequence.
A read cycle at address 0XXX00h retrieves the manufacturer code. A read cycle at address 0XXX01h returns
the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in
byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Table 7.3 on page 15
and Table 7.5 on page 17 for valid sector addresses.
The system must write the reset command to exit the autoselect mode and return to reading array data.
32
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11.4
She et
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence
The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic
serial number (ESN). The system can access the Secured Silicon Sector region by issuing the three-cycle
Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon
Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit
Secured Silicon Sector command sequence returns the device to normal operation. Table 11.1 on page 37
and Table 11.2 on page 38 show the addresses and data requirements for both command sequences. Note
that the ACC function and unlock bypass modes are not available when the device enters the Secured Silicon
Sector. See also Secured Silicon Sector Flash Memory Region on page 26 for further information.
11.5
Word/Byte Program Command Sequence
Models 03, 04 may program the device by word or byte, depending on the state of the BYTE# pin. Model 00
may program the device by byte only. Programming is a four-bus-cycle operation. The program command
sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The
program address and data are written next, which in turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or timings. The device automatically generates the program
pulses and verifies the programmed cell margin. Table 11.2 on page 38 shows the address and data
requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and
addresses are no longer latched. The system can determine the status of the program operation by using
DQ7, DQ6, or RY/BY#. See Write Operation Status on page 40 for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programming operation. The Byte Program command sequence
should be reinitiated once the device has reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from
a 0 back to a 1. Attempting to do so may halt the operation and set DQ5 to 1, or cause the Data# Polling
algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still
0. Only erase operations can convert a 0 to a 1.
11.6
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to the device faster than using the
standard program command sequence. The unlock bypass command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. The device
then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is
required to program in this mode. The first cycle in this sequence contains the unlock bypass program
command, A0h; the second cycle contains the program address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial two unlock cycles required in the standard program
command sequence, resulting in faster total programming time. Table 11.2 on page 38 shows the
requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands are
valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset command
sequence. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are don’t care
for both cycles. The device then returns to reading array data.
Figure 11.1 on page 34 illustrates the algorithm for the program operation. See the Erase/Program
Operations on page 52 for parameters, and to Figure 17.5 on page 53 for timing diagrams.
January 19, 2007 S29AL032D_00_A9
S29AL032D
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Figure 11.1 Program Operation
START
Write Program
Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
Last Address?
Yes
Programming
Completed
Note
See Table 11.2 for program command sequence.
11.7
Chip Erase Command Sequence
Chip erase is a six bus-cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations. Table 11.2 on page 38 shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command
sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write
Operation Status on page 40 for information on these status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and addresses are no longer latched.
Figure 11.2 on page 36 illustrates the algorithm for the erase operation. See Erase/Program Operations on
page 52 for parameters, and to Figure 17.6 on page 53 for timing diagrams.
34
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11.8
She et
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector erase command. Table 11.2 on page 38 shows the
address and data requirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase. The Embedded Erase
algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 50 µs, otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the DQ3: Sector
Erase Timer section.) The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the sector erase operation immediately terminates the
operation. The Sector Erase command sequence should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. (Refer to Write Operation Status for information on these status bits.)
Figure 11.2 on page 36 illustrates the algorithm for the erase operation. Refer to Erase/Program
Operations on page 52 for parameters, and to Figure 17.6 on page 53 for timing diagrams.
11.9
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the sector
erase operation, including the 50-µs time-out period during the sector erase command sequence. The Erase
Suspend command is ignored if it is written during the chip erase operation or Embedded Program algorithm.
Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out
period and suspends the erase operation. Addresses are don’t cares when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written
during the sector erase time-out, the device immediately terminates the time-out period and suspends the
erase operation.
After the erase operation has been suspended, the system can read array data from or program data to any
sector not selected for erasure. (The device erase suspends all sectors selected for erasure.) Normal read
and write timings and command definitions apply. Reading at any address within erase-suspended sectors
produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a
sector is actively erasing or is erase-suspended. See Write Operation Status on page 40 for information on
these status bits.
After an erase-suspended program operation is complete, the system can once again read array data within
non-suspended sectors. The system can determine the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program operation. See Write Operation Status on page 40 for more
information.
January 19, 2007 S29AL032D_00_A9
S29AL032D
35
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The system may also write the autoselect command sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes
are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the
Erase Suspend mode, and is ready for another valid operation. See Autoselect Command Sequence on
page 32 for more information.
The system must write the Erase Resume command (address bits are don’t care) to exit the erase suspend
mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another
Erase Suspend command can be written after the device has resumed erasing.
Figure 11.2 Erase Operation
START
Write Erase
Command Sequence
Data Poll
from System
Embedded
Erase
algorithm
in progress
No
Data = FFh?
Yes
Erasure Completed
Notes
1. See Table 11.2 for erase command sequence.
2. See DQ3: Sector Erase Timer on page 44 for more information.
36
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She et
11.10 Command Definitions Table
Command Sequence
(Note 1)
Cycles
Table 11.1 S29AL032D Command Definitions — Model 00
Bus Cycles (Notes 2–3)
First
Second
Addr
Data
1
RA
RD
Reset (Note 7)
1
XXX
F0
Autoselect
(Note 6)
Read (Note 4)
Third
Fourth
Addr
Data
Addr
Data
Addr
Fifth
Data
Manufacturer ID (Note 7)
4
XXX
AA
XXX
55
0XXXXX
90
0XXX00
01
Device ID (Note 7)
4
XXX
AA
XXX
55
0XXXXX
90
0XXX01
A3
Secured Silicon Sector Factory
Protect (Note 14)
4
AAA
AA
555
55
AAA
90
X06
85/05
Sector Protect Verify
(Note 8)
4
55
0XXXXX
or
2XXXXX
90
SA
X02
XXX
XXX
AA
XXX
XXX
3
XXX
AA
XXX
55
XXX
88
XXX
4
XXX
AA
XXX
55
XXX
90
XXX
00
PA
PD
4
XXX
AA
XXX
55
XXX
A0
3
XXX
AA
XXX
55
XXX
20
Unlock Bypass Program
(Note 9)
2
XXX
A0
PA
PD
Unlock Bypass Reset
(Note 10)
2
XXX
90
XXX
00
Addr
Data
01
Exit Secured Silicon Sector Region
Unlock Bypass
Data
00
Enter Secured Silicon Sector Region
Byte Program
Sixth
Addr
Chip Erase
6
XXX
AA
XXX
55
XXX
80
XXX
AA
XXX
55
XXX
10
Sector Erase
6
XXX
AA
XXX
55
XXX
80
XXX
AA
XXX
55
SA
30
Erase Suspend (Note 11)
1
XXX
B0
Erase Resume (Note 12)
1
XXX
30
CFI Query (Note 13)
1
XXX
98
Legend
PD = Data to be programmed at location PA. Data is latched on the rising edge
of WE# or CE# pulse, whichever happens first.
X = Don’t care
RA = Address of the memory location to be read
RD = Data read from location RA during read operation
PA = Address of the memory location to be programmed. Addresses are latched
on the falling edge of the WE# or CE# pulse, whichever happens later.
SA = Address of the sector to be erased or verified. Address bits A21–A16
uniquely select any sector.
Notes
1. See Table 7.1 on page 12 for descriptions of bus operations.
2. All values are in hexadecimal. Except when reading array or autoselect data,
all bus cycles are write operations.
3. Address bits are don’t care for unlock and command cycles, except when PA
or SA is required.
4. No unlock or command cycles required when device is in read mode.
5. The Reset command is required to return to the read mode when the device
is in the autoselect mode or if DQ5 goes high.
6. The fourth cycle of the autoselect command sequence is a read cycle.
7. In the third and fourth cycles of the command sequence, set A21 to 0.
8. In the third cycle of the command sequence, address bit A21 must be set to
0 if verifying sectors 0–31, or to 1 if verifying sectors 32–64. The data in the
fourth cycle is 00h for an unprotected sector/sector block and 01h for a
protected sector/sector block.
January 19, 2007 S29AL032D_00_A9
9. The Unlock Bypass command is required prior to the Unlock Bypass
Program command.
10. The Unlock Bypass Reset command is required to return to reading array
data when the device is in the Unlock Bypass mode.
11. The system may read and program functions in non-erasing sectors, or enter
the autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
12. The Erase Resume command is valid only during the Erase Suspend mode.
13. Command is valid when device is ready to read array data or when device is
in autoselect mode.
14. The data is 85h for factory locked and 05h for not factory locked.
S29AL032D
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Command Sequence
(Note 1)
Cycles
Table 11.2 S29AL032D Command Definitions, x8 Mode — Models 03, 04
Bus Cycles (Notes 2–5)
First
Second
Addr
Data
Third
Fourth
Fifth
Addr
Data
Addr
Data
Addr
Data
1
RA
RD
Reset (Note 7)
1
XXX
F0
Manufacturer ID
4
AAA
AA
555
55
AAA
90
X00
01
Device ID, Model 03
4
AAA
AA
555
55
AAA
90
X02
22F6
Device ID, Model 04
4
AAA
AA
555
55
AAA
90
X02
F9
Secured Silicon Sector Factory
Protect, Model 03 (Note 9)
4
AAA
AA
555
55
AAA
90
X06
8D/1D
Secured Silicon Sector Factory
Protect, Model 04 (Note 9)
4
AAA
AA
555
55
AAA
90
X06
9D/0D
4
AAA
AA
555
55
AAA
90
(SA)X04
(Note 10)
Enter Secured Silicon Sector Region
3
AAA
AA
555
55
AAA
88
Exit Secured Silicon Sector Region
4
AAA
AA
555
55
AAA
90
XXX
00
CFI Query (Note 11)
1
AA
98
Program
4
AAA
AA
555
55
AAA
A0
PA
PD
Unlock Bypass
3
AAA
AA
555
55
AAA
20
Unlock Bypass Program (Note 12)
2
XXX
A0
PA
PD
Autoselect (Note 8)
Read (Note 6)
Sector Protect Verify
(Note 10)
Sixth
Addr
Data
Addr
Data
Unlock Bypass Reset (Note 13)
2
XXX
90
XXX
00
Chip Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
AAA
10
Sector Erase
6
AAA
AA
555
55
AAA
80
AAA
AA
555
55
SA
30
Erase Suspend (Note 14)
1
XXX
B0
Erase Resume (Note 15)
1
XXX
30
Legend
X = Don’t care
PD = Data to be programmed at location PA. Data is latched on the rising edge
of WE# or CE# pulse, whichever happens first.
RA = Address of the memory location to be read
RD = Data read from location RA during read operation
PA = Address of the memory location to be programmed. Addresses are latched
on the falling edge of the WE# or CE# pulse, whichever happens later.
SA = Address of the sector to be erased or verified. Address bits A19–A12
uniquely select any sector.
Notes
1. See Table 7.1 on page 12 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command
sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A19–A11 are don’t cares for unlock and command cycles,
unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device
is in the autoselect mode, or if DQ5 goes high (while the device is providing
status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. For Model 03, the data is 8Dh for factory locked and 0Dh for not factory
locked. For Model 04, the data is 9Dh for factory locked and 1Dh for not
factory locked.
10. The data is 00h for an unprotected sector and 01h for a protected sector.
See “Autoselect Command Sequence”for more information.
11. Command is valid when device is ready to read array data or when device is
in autoselect mode.
12. The Unlock Bypass command is required prior to the Unlock Bypass
Program command.
13. The Unlock Bypass Reset command is required to return to reading array
data when the device is in the unlock bypass mode. F0h is also acceptable.
14. The system may read and program in non-erasing sectors, or enter the
autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
15. The Erase Resume command is valid only during the Erase Suspend mode.
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She et
Command Sequence
(Note 1)
Cycles
Table 11.3 S29AL032D Command Definitions, x16 Mode — Models 03, 04
Bus Cycles (Notes 2–5)
First
Second
Addr
Data
Third
Fourth
Addr
Data
Addr
Data
Addr
Fifth
Data
1
RA
RD
Reset (Note 7)
1
XXX
F0
Manufacturer ID
4
555
AA
2AA
55
555
90
X00
01
Device ID, Model 03
4
555
AA
2AA
55
555
90
X01
22F6
Device ID, Model 04
4
555
AA
2AA
55
555
90
X01
22F9
Secured Silicon Sector Factory
Protect, Model 03 (Note 9)
4
555
AA
2AA
55
555
90
X03
8D/0D
Secured Silicon Sector Factory
Protect, Model 04 (Note 9)
4
555
AA
2AA
55
555
90
X03
9D/1D
Sector Protect Verify
(Note 10)
4
555
AA
2AA
55
555
90
(SA)X02
(Note 10)
Enter Secured Silicon Sector Region
3
555
AA
2AA
55
555
88
Exit Secured Silicon Sector Region
4
555
AA
2AA
55
555
90
XXX
00
CFI Query (Note 11)
1
55
98
Program
4
555
AA
2AA
55
555
A0
PA
PD
555
20
Autoselect (Note 8)
Read (Note 6)
Sixth
Addr
Data
Addr
Data
Unlock Bypass
3
555
AA
2AA
55
Unlock Bypass Program (Note 12)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 13)
2
XXX
90
XXX
00
Chip Erase
6
555
AA
2AA
55
555
80
555
AA
2AA
55
555
10
2AA
55
555
80
555
AA
2AA
55
SA
30
Sector Erase
6
555
AA
Erase Suspend (Note 14)
1
XXX
B0
Erase Resume (Note 15)
1
XXX
30
Legend
PD = Data to be programmed at location PA. Data is latched on the rising edge
of WE# or CE# pulse, whichever happens first.
X = Don’t care
RA = Address of the memory location to be read
RD = Data read from location RA during read operation
PA = Address of the memory location to be programmed. Addresses are latched
on the falling edge of the WE# or CE# pulse, whichever happens later.
SA = Address of the sector to be erased or verified. Address bits A19–A12
uniquely select any sector.
Notes
1. See Table 7.1 on page 12 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect command
sequence, all bus cycles are write cycles.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command cycles.
5. Address bits A19–A11 are don’t cares for unlock and command cycles,
unless SA or PA required.
6. No unlock or command cycles required when reading array data.
7. The Reset command is required to return to reading array data when device
is in the autoselect mode, or if DQ5 goes high (while the device is providing
status data).
8. The fourth cycle of the autoselect command sequence is a read cycle.
9. For Model 03, the data is 8Dh for factory locked and 0Dh for not factory
locked. For Model 04, the data is 9Dh for factory locked and 1Dh for not
factory locked.
10. The data is 00h for an unprotected sector and 01h for a protected sector.
See “Autoselect Command Sequence”for more information.
11. Command is valid when device is ready to read array data or when device is
in autoselect mode.
12. The Unlock Bypass command is required prior to the Unlock Bypass
Program command.
13. The Unlock Bypass Reset command is required to return to reading array
data when the device is in the unlock bypass mode. F0 is also acceptable.
14. The system may read and program in non-erasing sectors, or enter the
autoselect mode, when in the Erase Suspend mode. The Erase Suspend
command is valid only during a sector erase operation.
15. The Erase Resume command is valid only during the Erase Suspend mode.
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12. Write Operation Status
The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and RY/BY#. Table 12.1 on page 44 and the following subsections describe the functions of these bits. DQ7,
RY/BY#, and DQ6 each offer a method for determining whether a program or erase operation is complete or
in progress. These three bits are discussed first.
12.1
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system whether an Embedded Algorithm is in progress or
completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command sequence.
During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum
programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system
must provide the program address to read valid status information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling produces a 0 on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a 1 on DQ7.
This is analogous to the complement/true datum output described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. The
system must provide an address within any of the sectors selected for erasure to read valid status information
on DQ7.
After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the device returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
When the system detects DQ7 has changed from the complement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7 may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 17.8 on page 54, Data# Polling Timings
(During Embedded Algorithms), under AC Characteristics on page 49 illustrates this.
Figure 12.1 on page 44 shows the outputs for Data# Polling on DQ7. Figure 12.2 on page 43 shows the
Data# Polling algorithm.
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Figure 12.1 Data# Polling Algorithm
START
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes
1. VA = Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for
erasure. During chip erase, a valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = 1 because DQ7 may change simultaneously with DQ5.
12.2
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 12.1 on page 44 shows the outputs for RY/BY#. Figures Figure 17.1 on page 49, Figure 17.2 on page
50, Figure 17.5 on page 53 and Figure 17.6 on page 53 shows RY/BY# for read, reset, program, and erase
operations, respectively.
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12.3
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DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for
approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erasesuspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6
toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling on page 40).
If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading array data.
DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Program
algorithm is complete.
Table 12.1 on page 44 shows the outputs for Toggle Bit I on DQ6. Figure 12.2 on page 43 shows the toggle
bit algorithm in flowchart form, and the section Reading Toggle Bits DQ6/DQ2 on page 42 explains the
algorithm. Figure 17.9 on page 55 shows the toggle bit timing diagrams. Figure 17.10 on page 55 shows the
differences between DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.
12.4
DQ2: Toggle Bit II
The Toggle Bit II on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing (that
is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is
valid after the rising edge of the final WE# pulse in the command sequence.
DQ2 toggles when the system reads at addresses within those sectors that have been selected for erasure.
(The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the
sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus,
both status bits are required for sector and mode information. Refer to Table 12.1 on page 44 to compare
outputs for DQ2 and DQ6.
Figure 12.2 on page 43 shows the toggle bit algorithm in flowchart form, and the section Reading Toggle Bits
DQ6/DQ2 on page 42 explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 17.9 on page
55 shows the toggle bit timing diagram. Figure 17.10 on page 55 shows the differences between DQ2 and
DQ6 in graphical form.
12.5
Reading Toggle Bits DQ6/DQ2
Refer to Figure 12.2 on page 43 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling,
the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on
the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as
DQ5 went high. If the toggle bit is no longer toggling, then the device has successfully completed the program
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or erase operation. If it is still toggling, then the device had not complete the operation successfully, and the
system must write the reset command in order to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not
gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous paragraph. Alternatively, it may choose to perform other
system tasks. In this case, the system must start at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 12.2 on page 43).
Figure 12.2 Toggle Bit Algorithm
START
Read DQ7–DQ0
Read DQ7–DQ0
Toggle Bit
= Toggle?
(Note 1)
No
Yes
No
DQ5 = 1?
Yes
(Notes 1, 2)
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Notes
1. Read toggle bit twice to determine whether or not it is toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5 changes to 1. See text.
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DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system tries to program a 1 to a location that is previously
programmed to 0. Only an erase operation can change a 0 back to a 1. Under this condition, the device
halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a 1.
Under both these conditions, the system must issue the reset command to return the device to reading array
data.
12.7
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer does not apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out also applies after each additional sector erase command.
When the time-out is complete, DQ3 switches from 0 to 1. The system may ignore DQ3 if the system can
guarantee that the time between additional sector erase commands will always be less than 50 μs. See
also Sector Erase Command Sequence on page 35.
After the sector erase command sequence is written, the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure that the device accepts the command sequence, and then read DQ3.
If DQ3 is 1, the internally controlled erase cycle has begun; all further commands (other than Erase Suspend)
are ignored until the erase operation is complete. If DQ3 is 0, the device accepts additional sector erase
commands. To ensure that the command has been accepted, the system software should check the status of
DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status
check, the last command might not have been accepted. Table 12.1 shows the outputs for DQ3.
Table 12.1 Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
Embedded Erase Algorithm
0
Toggle
0
1
Toggle
0
Reading within Erase
Suspended Sector
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Operation
Standard
Mode
Erase
Suspend
Mode
Embedded Program Algorithm
Notes
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation exceeds the maximum timing limits. See DQ5: Exceeded Timing Limits on
page 44 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
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13. Absolute Maximum Ratings
Table 13.1 Absolute Maximum Ratings
Parameter
Rating
Storage Temperature, Plastic Packages
–65°C to +150°C
Ambient Temperature with Power Applied
–65°C to +125°C
–0.5 V to +4.0 V
VCC (Note 1)
Voltage with Respect to Ground
A9, OE#, and RESET# (Note 2)
–0.5 V to +12.5 V
–0.5 V to VCC+0.5 V
All other pins (Note 1)
200 mA
Output Short Circuit Current (Note 3)
Notes
1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V for periods of
up to 20 ns. See Figure 13.1 on page 45. Maximum DC voltage on input or I/O pins is VCC +0.5 V. During voltage transitions, input or I/O
pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 13.2 on page 45.
2. Minimum DC input voltage on pins A9, OE#, and RESET# is -0.5 V. During voltage transitions, A9, OE#, and RESET# may overshoot VSS
to –2.0 V for periods of up to 20 ns. See Figure 13.1 on page 45. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to
14.0 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one second.
4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is
not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 13.1 Maximum Negative Overshoot Waveform
20 ns
20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
Figure 13.2 Maximum Positive Overshoot Waveform
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
14. Operating Ranges
Table 14.1 Operating Ranges
Parameter
Ambient Temperature (TA)
VCC Supply Voltages
Range
Industrial (I) Devices
–40°C to +85°C
Extended (N) Devices
–40°C to +125°C
VCC for standard voltage range
2.7 V to 3.6 V
Note
Operating ranges define those limits between which the functionality of the device is guaranteed.
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15. DC Characteristics
Table 15.1 DC Characteristics, CMOS Compatible
Parameter
Description
Test Conditions
Min
ILI
Input Load Current (Note 1)
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
VCC Active Read Current
(Notes 2, 3)
Max
Unit
±1.0
µA
35
µA
±1.0
µA
10 MHz
15
30
5 MHz
9
16
CE# = VIL, OE# = VIH,
Byte Mode
ICC1
Typ
1 MHz
2
4
10 MHz
18
35
5 MHz
9
16
1 MHz
2
4
CE# = VIL, OE# = VIH,
Word Mode
mA
ICC2
VCC Active Write Current
(Notes 3, 4, 6)
CE# = VIL, OE# = VIH
15
35
mA
ICC3
VCC Standby Current (Notes 3, 5)
CE#, RESET# = VCC±0.3 V
0.2
5
µA
ICC4
VCC Standby Current During Reset
(Notes 3, 5)
RESET# = VSS ± 0.3 V
0.2
5
µA
ICC5
Automatic Sleep Mode
(Notes 3, 5, 7)
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V
0.2
5
µA
IACC
ACC Accelerated Program Current,
Word or Byte
CE# = VIL, OE# = VIH
ACC pin
5
10
mA
VCC pin
15
30
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VHH
Voltage for WP#/ACC Sector Protect/
Unprotect and Program Acceleration
VCC = 3.0 V ± 10%
11.5
12.5
V
VID
Voltage for Autoselect and Temporary
Sector Unprotect
VCC = 3.3 V
11.5
12.5
V
VOL
Output Low Voltage
IOL = 4.0 mA, VCC = VCC min
VOH1
VOH2
VLKO
Output High Voltage
0.45
IOH = -2.0 mA, VCC = VCC min
2.4
IOH = -100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage (Note 4)
V
V
V
2.3
2.5
V
Notes
1. On the ACC pin only, the maximum input load current when ACC = VIL is ±5.0 µA.
2. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
3. Maximum ICC specifications are tested with VCC = VCCmax.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. At extended temperature range (>+85°C), maximum current is 15 µA.
6. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA.
7. Not 100% tested.
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Zero Power Flash
Figure 15.1 ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
Supply Current in mA
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note
Addresses are switching at 1 MHz.
Figure 15.2 Typical ICC1 vs. Frequency
10
3.6 V
Supply Current in mA
8
2.7 V
6
4
2
0
1
2
3
Frequency in MHz
4
5
Note
T = 25°C
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16. Test Conditions
Figure 16.1 Test Setup
3.3 V
2.7 kΩ
Device
Under
Test
CL
6.2 kΩ
Note
Diodes are IN3064 or equivalent.
Table 16.1 Test Specifications
Speed Option
70
90
Output Load
Output Load Capacitance, CL
(including jig capacitance)
30
Input Rise and Fall Times
100
pF
5
ns
0.0 or VCC
V
Input timing measurement reference levels
0.5 VCC
V
Output timing measurement reference levels
0.5 VCC
V
Input Pulse Levels
16.1
Unit
1 TTL gate
Key to Switching Waveforms
Waveform
Inputs
Outputs
Steady
Changing from H to L
Changing from L to H
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
Figure 16.2 Input Waveforms and Measurement Levels
VCC
Input
0.5 VCC
Measurement Level
0.5 VCC
Output
0.0 V
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17. AC Characteristics
17.1
Read Operations
Parameter
Speed Options
JEDEC
Std
tAVAV
tRC
tAVQV
Description
Test Setup
Read Cycle Time (Note 1)
tACC
Address to Output Delay
CE# = VIL
OE# = VIL
OE# = VIL
70
90
Unit
Min
70
90
ns
Max
70
90
ns
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
tEHQZ
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
Latency Between Read and Write Operations
tSR/W
tAXQX
Max
70
90
ns
Max
30
35
ns
Min
20
ns
Read
Min
0
ns
Toggle and Data# Polling
Min
10
ns
Min
0
ns
tOEH
Output Enable
Hold Time (Note 1)
tOH
Output Hold Time From Addresses, CE# or OE#, Whichever
Occurs First (Note 1)
Notes
1. Not 100% tested.
2. See Figure 16.1 on page 48 and Table 16.1 on page 48 for test specifications.
Figure 17.1 Read Operations Timings
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
OE#
tOE
tSR/W
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
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17.2
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Hardware Reset (RESET#)
Parameter
JEDEC
Std.
Description
Test Setup
All Speed Options
Unit
tREADY
RESET# Pin Low (During Embedded Algorithms) to
Read or Write (See Note)
Max
20
µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note
Not 100% tested.
Figure 17.2 RESET# Timings
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
tRH
RESET#
tRP
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Word/Byte Configuration (BYTE#) (Models 03, 04 Only)
Parameter
JEDEC
Speed Options
Std.
Description
70
90
Unit
tELFL/tELFH
CE# to BYTE# Switching Low or High
Max
5
ns
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
16
ns
tFHQV
BYTE# Switching High to Output Active
Min
70
90
ns
Figure 17.3 BYTE# Timings for Read Operations
CE#
OE#
BYTE#
BYTE#
Switching
from word
to byte
mode
tELFL
Data Output
(DQ0–DQ14)
DQ0–DQ14
Address
Input
DQ15
Output
DQ15/A-1
Data Output
(DQ0–DQ7)
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Figure 17.4 BYTE# Timings for Write Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note
Refer to the Erase/Program Operations table for tAS and tAH specifications.
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17.4
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Erase/Program Operations
Table 17.1 Erase/Program Operations
Parameter
Speed Options
JEDEC
Std.
Description
70
Unit
90
ns
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
45
ns
tDVWH
tDS
Data Setup Time
Min
35
45
ns
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWHDX
tGHWL
tGHWL
70
90
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
30
ns
tSR/W
Latency Between Read and Write Operations
ns
35
35
ns
Min
20
Byte
Typ
9
Word
Typ
11
Typ
7
µs
tWHWH1
tWHWH1
Programming Operation (Note 2)
tWHWH1
tWHWH1
Accelerated Programming Operation, Word or Byte (Note 2)
tWHWH2
tWHWH2
µs
Sector Erase Operation (Note 2)
Typ
0.7
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Max
90
ns
tBUSY
Notes
1. Not 100% tested.
2. See Erase and Programming Performance on page 60 for more information.
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Figure 17.5 Program Operation Timings
Program Command Sequence (last two cycles)
tAS
tWC
555h
Addresses
Read Status Data (last two cycles)
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
DOUT
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17.6 Chip/Sector Erase Operation Timings
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status on page 40).
2. Illustration shows device in word mode.
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Figure 17.7 Back to Back Read/Write Cycle Timing
tWC
Addresses
tRC
PA
RA
PA
tACC
tAH
tCPH
tCE
CE#
PA
tCP
tOE
tSR/W
OE#
tGHWL
tWP
WE#
tWDH
tDS
Data
tDF
tOH
tDH
Valid In
Valid Out
Valid In
Valid Out
Figure 17.8 Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note
VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
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Figure 17.9 Toggle Bit Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
Valid Status
(first read)
tBUSY
Valid Status
Valid Status
(second read)
(stops toggling)
Valid Data
RY/BY#
Note
VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 17.10 DQ2 vs. DQ6 for Erase and Erase Suspend Operations
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Suspend
Program
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note
The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector.
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Temporary Sector Unprotect
Table 17.2 Temporary Sector Unprotect
Parameter
JEDEC
All Speed Options
Unit
tVIDR
Std.
VID Rise and Fall Time (See Note)
Description
Min
500
ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
µs
Note
Not 100% tested.
Figure 17.11 Temporary Sector Unprotect Timing Diagram
12 V
RESET#
0 or 3 V
Program or Erase Command Sequence
tVIDR
tVIDR
CE#
WE#
tRSP
RY/BY#
Figure 17.12 Accelerated Program Timing Diagram
VHH
WP#/ACC
VIL or VIH
VIL or VIH
tVHH
56
tVHH
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Figure 17.13 Sector Protect/Unprotect Timing Diagram
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Protect/Unprotect
Data
60h
1 µs
Valid*
Verify
60h
40h
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
CE#
WE#
OE#
Note
For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
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Alternate CE# Controlled Erase/Program Operations
Table 17.3 Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std.
Description
70
90
70
90
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
45
ns
tDVEH
tDS
Data Setup Time
Min
35
45
ns
0
ns
ns
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
tELEH
tCP
CE# Pulse Width
Min
tCPH
CE# Pulse Width High
Min
30
ns
tSR/W
Latency Between Read and Write Operations
Min
20
ns
tEHDX
tEHEL
0
35
ns
35
ns
Byte
Typ
9
Word
Typ
11
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
7
µs
Sector Erase Operation (Note 2)
Typ
0.7
sec
tWHWH1
tWHWH1
Programming Operation (Note 2)
tWHWH1
tWHWH1
tWHWH2
tWHWH2
µs
Notes
1. Not 100% tested.
2. See the Erase and Programming Performance on page 60 section for more information.
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Figure 17.14 Alternate CE# Controlled Write Operation Timings
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
PA
Addresses
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes
1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.
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18. Erase and Programming Performance
Parameter
Typ (Note 1)
Max (Note 2)
Sector Erase Time (Note 7)
0.7
10
Chip Erase Time (Note 8)
45
Unit
s
s
Byte Programming Time
9
300
µs
Word Programming Time
11
360
µs
Accelerated Byte/Word Programming Time
7
210
µs
Chip Programming Time
Byte Mode
36
108
s
(Note 3)
Word Mode
24
72
s
Comments
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level overhead
(Note 5)
Notes
1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles, checkerboard data pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum
program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11.2 for further information on
command definitions.
6. The device has a minimum erase and program cycle endurance of 100,000 cycles per sector.
7. At extended temperature range (>+85°C), typical erase time is 1.75 s and maximum erase time is 25 s.
8. At extended temperature range (>+85°C), typical erase time is 112 s.
19. TSOP and BGA Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Package
Typ
Max
Unit
TSOP
6
7.5
pF
BGA
4.2
5.0
pF
TSOP
8.5
12
pF
BGA
5.4
6.5
pF
TSOP
7.5
9
pF
BGA
3.9
4.7
pF
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
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20. Physical Dimensions
20.1
TS040—40-Pin Standard TSOP
Dwg rev AA; 10/99
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TS 048—48-Pin Standard TSOP
2X
0.10
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
2X
2
0.10
0.10
1
A2
N
SEE DETAIL B
A
REVERSE PIN OUT (TOP VIEW)
3
B
1
E 5
e
N
+1
2
N
2
0.25
A1
4
D
2X (N/2 TIPS)
9
5
D1
N
+1
2
N
2
C
SEATING
PLANE
B
A
B
N
SEE DETAIL A
0.08MM
(0.0031")
b
M
C A-B
6
S
7
WITH PLATING
7
(c)
c1
b1
SECTION B-B
BASE METAL
R
(c)
e/2
GAUGE PLANE
0.25MM (0.0098") BSC
q°
PARALLEL TO
SEATING PLANE
L
X
C
X = A OR B
DETAIL A
DETAIL B
NOTES:
Jedec
Symbol
A
A1
A2
b1
b
c1
c
D
D1
E
e
L
0
R
N
MO-142 (D) DD
MIN
NOM
MAX
1.20
0.15
0.05
1.05
0.95 1.00
0.23
0.17 0.20
0.27
0.17 0.22
0.16
0.10
0.21
0.10
19.80 20.00 20.20
18.30 18.40 18.50
11.90 12.00 12.10
0.50 BASIC
0.50 0.60 0.70
8˚
0°
0.20
0.08
48
1
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).
(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)
2
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).
3
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.
4
TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF
CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT
HORIZONTAL SURFACE.
5
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS
0.15mm (.0059") PER SIDE.
6
DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE
0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE
BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").
7
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND
0.25MM (0.0098") FROM THE LEAD TIP.
8
LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.
9
DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
3355 \ 16-038.10c
* For reference only. BSC is an ANSI standard for Basic Space Centering.
62
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VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 10.0 x 6.0 mm
D
D1
A
e
6
e
5
4
+0.20
1.00-0.50
E
7
SE
E1
3
2
Ø0.50
1
H
+0.20
1.00 -0.50
B
A1 ID.
6
G
Øb
F
E
D
C
SD
B
A
7
A1 CORNER
Ø0.08 M C
Ø0.15 M C A B
A
A2
0.10 C
C
0.08 C
SEATING PLANE
A1
NOTES:
PACKAGE
VBN 048
JEDEC
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
N/A
2. ALL DIMENSIONS ARE IN MILLIMETERS.
10.00 mm x 6.00 mm NOM
PACKAGE
SYMBOL
MIN
NOM
MAX
A
---
---
1.00
A1
0.17
---
---
A2
0.62
---
0.73
3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT
AS NOTED).
NOTE
4. e
OVERALL THICKNESS
BALL HEIGHT
SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE
"E" DIRECTION.
BODY THICKNESS
D
10.00 BSC.
BODY SIZE
E
6.00 BSC.
BODY SIZE
N IS THE TOTAL NUMBER OF SOLDER BALLS.
6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL
DIAMETER IN A PLANE PARALLEL TO DATUM C.
D1
5.60 BSC.
BALL FOOTPRINT
E1
4.00 BSC.
BALL FOOTPRINT
MD
8
ROW MATRIX SIZE D DIRECTION
ME
6
ROW MATRIX SIZE E DIRECTION
N
48
fb
0.35
---
0.45
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN
THE OUTER ROW PARALLEL TO THE D OR E DIMENSION,
RESPECTIVELY, SD OR SE = 0.000.
BALL DIAMETER
0.80 BSC.
BALL PITCH
SD / SE
0.40 BSC.
SOLDER BALL PLACEMENT
NONE
7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS
A AND B AND DEFINE THE POSITION OF THE CENTER
SOLDER BALL IN THE OUTER ROW.
TOTAL BALL COUNT
e
REPRESENTS THE SOLDER BALL GRID PITCH.
5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE
"D" DIRECTION.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN
THE OUTER ROW, SD OR SE = e/2
DEPOPULATED SOLDER BALLS
8. NOT USED.
9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED
BALLS.
10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK
MARK, METALLIZED MARK INDENTATION OR OTHER MEANS.
3425\ 16-038.25
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21. Revision History
Section
Description
Revision A0 (January 31, 2005)
Initial release.
Revision A1 (March 16, 2005)
Distinctive Characteristics
Revised Secured Silicon Sector with 128-word information.
Common Flash Memory Interface — (CFI)
Modified Primary Vendor-Specific Extended Query table information for 45h address..
Revision A2 (April 19, 2005)
Valid Combinations Table
Clarified available packing types for TSOP and FBGA package. Modified Note 1.
Added Secured Silicon Sector Addresses—Model 00 table
Device Bus Operations
Modified Top Boot Secured Silicon Sector Addresses—Model 03 and Bottom Boot Secured
Silicon Sector Addresses—Model 04 tables
S29AL032D Command Definitions Model
00 table
Added Secured Silicon Sector Factory Protect information.
Accelerated Program Operation
Added section.
Secured Silicon Sector
Added section.
AC Characteristics
Added ACC programming timing diagram.
Revision A3 (June 13, 2005)
Autoselect Mode
Updated Table 8 to include models 00, 03, and 04.
Common Flash Memory Interface
Updated table headings in table 12, 13, 14, and 15.
Absolute Maximum Rating
Updated figure 8.
DC Characteristics
Updated CMOS Compatible table.
AC Characteristics
Updated Erase/Program Operations table. Added new figure: Back-to-Back Read/Write Cycle
Timing. Updated Alternate CE# Controlled Erase/Program Operations table.
Revision A4 (July 29, 2005)
DS Status
Change of DS status to “Preliminary” from “Advance Information”.
Output Disable Mode
Updated Model 00 Secured Silicon Sector Analysis table.
Autoselect Mode
Updated S29AL032D Autoselect Codes (High Voltage Method) table.
Revision A5 (September 21, 2005)
DS Status
Change of DS status to “Preliminary” from “Advance Information”.
Sector Protection/Unprotection
Corrected “In-System Sector Protect/Unprotect Algorithms” figure.
Revision A6 (May 22, 2006)
AC Characteristics
Added tSR/W parameter to read and erase/program operations tables. Added back-to-back read/
write cycle timing diagram. Changed maximum value for tDF and tFLQZ.
Revision A7 (June 19, 2006)
Ordering Information
Added extended temperature range options to valid combinations.
Common Flash Memory Interface (CFI)
Primary Vendor-Specific Extended Query table: Change description for data at address 4Fh
(address 9Eh on Models 03, 04).
DC Characteristics
Changed Note 4.
Read Operations Timings figure
Connected end of tRC period to start of tOH period.
Erase and Programming Performance
Added Notes 7 and 8 to table.
Revision A8 (November 2, 2006)
Valid Combinations
Updated table.
Revision A9 (January 19, 2007)
Autoselect Code (High Voltage Method)
table; Command Definitions, x8 Mode—
Models 03, 04 table
64
Corrected data for Secured Silicon Sector Sector Indicator Bit.
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Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country,
the prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.
Copyright © 2005–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations
thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.
January 19, 2007 S29AL032D_00_A9
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