JEITA Guideline Compatible Stand-Alone Synchronous Switch-Mode Li-Ion or Li-Polymer

JEITA Guideline Compatible Stand-Alone Synchronous Switch-Mode Li-Ion or Li-Polymer
bq24616
SLUSA49B – APRIL 2010 – REVISED OCTOBER 2011
www.ti.com
JEITA Guideline Compatible Stand-Alone Synchronous Switch-Mode Li-Ion or Li-Polymer
Battery Charger With System Power Selector and Low Iq
Check for Samples: bq24616
FEATURES
– < 15-µA Off-State Battery Discharge Current
– < 1.5-mA Off-State Input Quiescent Current
1
•
•
1
ACP
2
CE
STAT1
5
TS
6
LODRV
22
21
20
19
18 REGN
17 GND
QTJ
ACDRV 3
4
PH
23
16 ACSET
QFN-24
TOP VIEW
15 ISET2
14 SRP
13 SRN
7
8
9
10
11
12
VFB
•
ACN
24
ISET1
•
•
PACKAGE AND PIN-OUT
BTST
•
The bq24616 charges the battery in three phases:
preconditioning,
constant-current,
and
constant-voltage. Charge is terminated when the
current reaches a minimum user-selectable level. A
programmable charge timer provides a safety
backup. The bq24616 automatically restarts the
charge cycle if the battery voltage falls below an
internal threshold, and enters a low-quiescent-current
sleep mode when the input voltage falls below the
battery voltage.
HIDRV
•
The bq24616 is a highly integrated, Japan Electronic
Information
Technology
Association
(JEITA)
guideline-compatible,
Li-ion
or
Li-polymer
switch-mode battery charge controller. It offers a
constant-frequency synchronous switching PWM
controller with high-accuracy charge-current and
-voltage
regulation,
charge
preconditioning,
termination, adapter current regulation, and
charge-status monitoring.
VREF
•
DESCRIPTION
BATDRV
•
•
•
•
•
•
Netbook, Mobile Internet Device and
Ultra-Mobile PC
Industrial and Medical Equipment
Personal Digital Assistants
Handheld Terminals
Portable Equipment
STAT2
•
•
VCC
•
APPLICATIONS
PG
•
Battery Thermistor Sense for JEITA Guideline
Compatible Charger
600-kHz NMOS-NMOS Synchronous Buck
Converter
Stand-Alone Charger Support for Li-Ion or
Li-Polymer
5-V–28-V VCC Input Operating Range and
Supports 1-6 Battery Cells
Up to 10A Charge Current and Adapter Current
High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
Integration
– Automatic System Power Selection From
Adapter or Battery
– Internal Loop Compensation
– Internal Soft Start
– Dynamic Power Management
Safety Protection
– Input Overvoltage Protection
– Battery Detection
– Reverse Protection Input FET
– Programmable Safety Timer
– Charge Overcurrent Protection
– Battery Short Protection
– Battery Overvoltage Protection
– Thermal Shutdown
Status Outputs
– Adapter Present
– Charger Operation Status
Charge Enable Pin
6-V Gate Drive for Synchronous Buck
Converter
30-ns Driver Dead-Time and 99.5% Max
Effective Duty Cycle
24-pin, 4-mm × 4-mm QFN Package
Energy Star Low Quiescent Current Iq
TTC
•
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
bq24616
SLUSA49B – APRIL 2010 – REVISED OCTOBER 2011
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
DESCRIPTION (CONTINUED)
The bq24616 controls external switches to prevent battery discharge back to the input and to connect the battery
to the system using 6-V gate drives for system efficiency. The bq24616 features dynamic power management
(DPM). The DPM reduces battery charge current when the input power limit is reached to avoid overloading the
ac adapter while supplying the load and the battery charger simultaneously. A highly accurate current-sense
amplifier enables precise measurement of input current from the ac adapter to monitor the overall system power.
TYPICAL APPLICATION
Q1 (ACFET)
SI7617DN
R17
10Ω
SYSTEM
P
ADAPTER-
P
R14
100 kW
C16
2.2μF
RAC
0.010 W
Q2 (ACFET)
SI7617DN
C14
0.1 mF
C15
0.1 µF
C3
0.1 µF
C2
0.1 µF
ACN
VCC
BATDRV
ACDRV
R5
100 kW
R18
1 kΩ
R7
100 kW
R6
10 kW
R15
100 kW
PH
ISET2
BTST
R8
22.1 kW
REGN
C6
0.1 µF
C5
1 µF
bq24616
VREF
RSR
0.010 W
C10
0.1 µF
GND
D2
R12 10 kW
D3
C12
C13
10 µF* 10 µF*
C11
0.1 µF
R2
500 kΩ
R13 10 kW
D4
VREF
Pack
Thermistor
Sense
103AT
R9
2.2 kW
Cff
22 pF
STAT1
SRP
ADAPTER +
PACK+
PACK-
CE
R11 10 kW
VBAT
6.8 µH*
Q5
SIS412DN
LODRV
C4
1 µF
Q4
SIS412DN
L1
D1
BAT54
P
Q3 (BATFET)
SI7617DN
R19
1 kΩ
HIDRV
ISET1
ACSET
R4
32.4 kW
C7
1µF
ACP
VREF
R3
100 kW
C9
10 μF
C8
10 µF
N
R20
2Ω
N
ADAPTER+
R1
100 kW
SRN
STAT2
PG
VFB
R16
100 W
C1
0.1 μF
R10
6.8 kW
TS
TTC
PwrPad
CTTC
0.056 μF
VIN = 19 V; 3-cell; Iadapter_limit = 4 A; Ipre-charge = Iterm = 0.3 A; 5-hour safety timer; Icharge = 1.5 A (0–10°C), 3 A
(10°C–60°C); VBAT = 12.6 V (0°C–45°C), 12.3 V (45°C–50°C), 12.15 V (50°C–60°C).
Figure 1. Typical System Schematic
ORDERING INFORMATION
2
PART NUMBER
IC MARKING
PACKAGE
bq24616
QTJ
24-pin 4-mm × 4-mm QFN
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ORDERING NUMBER
(Tape and Reel)
QUANTITY
bq24616RGER
3000
bq24616RGET
250
Copyright © 2010–2011, Texas Instruments Incorporated
Product Folder Link(s): bq24616
bq24616
SLUSA49B – APRIL 2010 – REVISED OCTOBER 2011
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THERMAL INFORMATION
bq24616
THERMAL METRIC (1)
RGE
UNIT
24 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
43
°C/W
θJCtop
Junction-to-case (top) thermal resistance
54.3
°C/W
θJB
Junction-to-board thermal resistance (4)
20
°C/W
ψJT
Junction-to-top characterization parameter (5)
0.6
°C/W
19
°C/W
4
°C/W
(6)
ψJB
Junction-to-board characterization parameter
θJCbot
Junction-to-case (bottom) thermal resistance (7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
VALUE
MAX
–0.3
33
V
PH
–2
36
V
VFB
–0.3
16
V
REGN, LODRV, ACSET, TS, TTC
–0.3
7
V
BTST, HIDRV with respect to GND
–0.3
39
V
VREF, ISET1, ISET2
–0.3
3.6
V
ACP–ACN, SRP–SRN
–0.5
0.5
V
VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1,
STAT2, PG
Voltage range
Maximum difference
voltage
UNIT
MIN
TJ
Junction temperature range
–40
155
°C
Tstg
Storage temperature range
–55
155
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult the
Packaging section of the data sheet for thermal limitations and considerations of packages.
Must have a series resistor between battery pack and VFB if battery-pack voltage is expected to be greater than 16 V. Usually the
resistor-divider top resistor takes care of this.
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RECOMMENDED OPERATING CONDITIONS
VALUE
MAX
–0.3
28
V
PH
–2
30
V
VFB
–0.3
14
V
REGN, LODRV, ACSET, TS, TTC
–0.3
6.5
V
BTST, HIDRV with respect to GND
–0.3
34
V
ISET1, ISET2
–0.3
3.3
V
0
3.3
V
–0.2
0.2
V
VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1,
STAT2, PG
Voltage range
VREF
Maximum difference
voltage
UNIT
MIN
ACP–ACN, SRP–SRN
TJ
Junction temperature range
0
125
°C
Tstg
Storage temperature range
–55
155
°C
4
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bq24616
SLUSA49B – APRIL 2010 – REVISED OCTOBER 2011
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ELECTRICAL CHARACTERISTICS
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VVCC_OP
VCC input voltage operating range
5
28
V
15
μA
VVCC > VSRN, VVCC > VUVLO CE = LOW
5
µA
VVCC > VSRN, VVCC > VVCCLOW CE = HIGH, charge
done
5
µA
QUIESCENT CURRENTS
Total battery discharge current (sum of
currents into VCC, BTST, PH, ACP,
ACN, SRP, SRN, VFB), VFB ≤ VFB_REG
IBAT
IAC
Battery discharge current (sum of
currents into BTST, PH, SRP, SRN,
VFB), VFB ≤ VFB_REG
Adapter supply current (current into
VCC,ACP,ACN pin)
VVCC < VSRN, VVCC > VUVLO (SLEEP)
VVCC > VSRN, VVCC > VUVLO CE = LOW (IC quiescent
current)
1
1.5
VVCC > VSRN, VVCC > VVCCLOW, CE = HIGH, charge
done
2
5
VVCC > VSRN, VVCC > VVCCLOW, CE = HIGH, charging,
Qg_total = 20 nC
mA
25
CHARGE VOLTAGE REGULATION
VFB_REG
Feedback regulation voltage
Charge voltage regulation accuracy
IVFB
Leakage current into VFB pin
VT3 < VTS < VT1
2.1
VT4 < VTS < VT3
2.05
VT5 < VTS < VT4
2.025
V
TJ = 0 to 85°C
–0.5%
–0.5%
TJ = –40 to 125°C
–0.7%
–0.7%
VFB = 2.1 V, 2.05 V, 2.025 V
100
100
nA
CURRENT REGULATION – FAST CHARGE
VISET1
ISET1 voltage range
VIREG_CHG
SRP-SRN current-sense voltage range
VIREG_CHG = VSRP – VSRN
KISET1
Charge-current set factor (amps of
charge current per volt on ISET1 pin)
RSENSE = 10 mΩ
Charge current-regulation accuracy
IISET1
Leakage current into ISET1 pin
2
5
V
mV
A/V
VIREG_CHG = 40 mV
–3%
VIREG_CHG = 20 mV
–4%
4%
VIREG_CHG = 5 mV
–25%
25%
VIREG_CHG = 1.5 mV (VSRN > 3.1 V)
–40%
40%
3%
VISET1 = 2 V
100
nA
2
V
CURRENT REGULATION – PRECHARGE
VISET2
ISET2 voltage range
KISET2
Precharge current-set factor (amps of
RSENSE = 10 mΩ
precharge current per volt on ISET2 pin)
Precharge current-regulation accuracy
IISET2
Leakage current into ISET2 pin
1
A/V
VIREG_PRECH = 20 mV
–4%
4%
VIREG_PRECH = 5 mV
–25%
25%
VIREG_PRECH = 1.5 mV (VSRN < 3.1 V)
–55%
55%
VISET2 = 2V
100
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ELECTRICAL CHARACTERISTICS (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CHARGE TERMINATION
Termination current-set factor (amps of
termination current per volt on ISET2
pin)
KTERM
RSENSE = 10 mΩ
Termination-current accuracy
1
A/V
VITERM = 20 mV
–4%
4%
VITERM = 5 mV
–25%
25%
VITERM = 1.5 mV
–45%
Deglitch time for termination (both edge)
45%
100
tQUAL
Termination qualification time
VBAT> VRECH and ICHG< ITERM
IQUAL
Termination qualification current
Discharge current once termination is detected
ms
250
ms
2
mA
INPUT CURRENT REGULATION
VACSET
ACSET voltage range
VIREG_DPM
ACP-ACN current sense voltage range
VIREG_DPM = VACP – VACN
KACSET
Input current set factor (amps of input
current per volt on ACSET pin)
RSENSE = 10 mΩ
IACSET
Input current regulation accuracy
leakage current in to ACSET pin
IISET1
2
Leakage current in to ACSET pin
100
5
V
mV
A/V
VIREG_DPM = 40 mV
–3%
VIREG_DPM = 20 mV
–4%
4%
VIREG_DPM = 5 mV
–25%
25%
3%
VACSET = 2 V
100
nA
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
VUVLO
AC undervoltage rising threshold
VUVLO_HYS
AC undervoltage hysteresis, falling
Measure on VCC
3.65
3.85
4
350
V
mV
VCC LOWV COMPARATOR
Falling threshold, disable charge
Measure on VCC
4.1
Rising threshold, resume charge
V
4.35
4.5
V
100
150
mV
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP
_FALL
VSLEEP_HYS
SLEEP falling threshold
VVCC – VSRN to enter SLEEP
40
SLEEP hysteresis
500
mV
SLEEP rising delay
VCC falling below SRN, Delay to turn off ACFET
1
μs
SLEEP falling delay
VCC rising above SRN, Delay to turn on ACFET
30
ms
SLEEP rising shutdown deglitch
VCC falling below SRN, Delay to enter SLEEP mode
100
ms
SLEEP falling powerup deglitch
VCC rising above SRN, Delay to exit SLEEP mode
30
ms
ACN / SRN COMPARATOR
VACN-SRN_FALL
ACN to SRN falling threshold
VACN-SRN_HYS
ACN to SRN rising hysteresis
VACN – VSRN to turn on BATFET
100
200
310
mV
100
mV
ACN to SRN rising deglitch
VACN – VSRN > VACN-SRN_RISE
2
ms
ACN to SRN falling deglitch
VACN – VSRN < VACN-SRN_FALL
50
μs
BAT LOWV COMPARATOR
VLOWV
Precharge to fastcharge transition
(LOWV threshold)
VLOWV_HYS
LOWV hysteresis
Measured on VFB pin, rising
1.534
1.55
1.566
V
100
mV
LOWV rising deglitch
VFB falling below VLOWV
25
ms
LOWV falling deglitch
VFB rising above VLOWV + VLOWV_HYS
25
ms
RECHARGE COMPARATOR
VRECHG
6
Recharge threshold (with-respect-to
VREG)
Measured on VFB pin, Falling
Recharge rising deglitch
VFB decreasing below VRECHG
10
ms
Recharge falling deglitch
VFB decreasing above VRECHG
10
ms
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35
50
65
mV
Copyright © 2010–2011, Texas Instruments Incorporated
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bq24616
SLUSA49B – APRIL 2010 – REVISED OCTOBER 2011
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ELECTRICAL CHARACTERISTICS (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
32.96
V
BAT OVERVOLTAGE COMPARATOR
VOV_RISE
Overvoltage rising threshold
As percentage of VFB ,T1 – T5
104%
VOV_FALL
Overvoltage falling threshold
As percentage of VFB,T1 – T5
102%
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV
AC overvoltage rising threshold on VCC
VACOV_HYS
AC overvoltage falling hysteresis
31.04
32
1
V
1
ms
AC overvoltage deglitch (both edges)
Delay to changing the STAT pins
AC overvoltage rising deglitch
Delay to turn-off ACFET, disable charge
1
ms
AC overvoltage falling deglitch
Delay to turn on ACFET, resume charge
20
ms
145
°C
15
°C
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown rising temperature
TSHUT_HYS
Thermal shutdown hysteresis
Temperature increasing
Thermal shutdown rising deglitch
Temperature increasing
100
μs
Thermal shutdown falling deglitch
Temperature decreasing
10
ms
THERMISTOR COMPARATOR
VT1
T1 (0 °C) threshold, charge suspended
below this temperature
VTS rising, as percentage of VVREF
VT1-HYS
Charge back to ICHARGE/2 and VFB = 2.1
V above this temperature.
Hysteresis, VTS falling
VT2
T2 (10 °C) threshold, charge back to
ICHARGE/2 and VFB = 2.1 V below this
temperature.
VTS rising, as percentage of VVREF
VT2-HYS
Charge back to ICHARGE and VFB = 2.1 V
above this temperature.
Hysteresis, VTS falling
VT3
T3 (45 °C) threshold, charge back to
ICHARGE and VFB = 2.05 V above this
temperature.
VTS falling, as percentage of VVREF
VT3-HYS
Charge back to ICHARGE and VFB = 2.1 V
below this temperature.
Hysteresis, VTS rising
VT4
T4 (50 °C) threshold, charge back to
ICHARGE and VFB = 2.025 V above this
temperature.
VTS falling, as percentage of VVREF
VT4-HYS
Charge back to ICHARGE and VFB = 2.05
V below this temperature.
Hysteresis, VTS rising
VT5
T5 (60 °C) threshold, charge suspended
above this temperature.
VTS falling, as percentage of VVREF
VT5-HYS
Charge back to ICHARGE and VFB = 2.025
Hysteresis, VTS rising
V below this temperature.
Deglitch time for temperature
out-of-valid-charge-range detection
VTS < VT5 or VTS > VT1
Deglitch time for temperature
in-valid-range detection
VTS > VT5 + VT5_HYS or VTS < VT1 - VT1_HYS
70.2%
70.8%
71.4%
0.6%
68.0%
68.6%
69.2%
0.8%
55.5%
56.1%
56.7%
0.8%
53.2%
53.7%
54.2%
0.8%
47.6%
48.1%
48.6%
1.2%
400
ms
20
ms
Deglitch time for temperature detection
above/below T2, T3, T4 threshold
25
ms
Charge current when VTS between VT1
and VT2 range
ICHARGE
/2
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
Charge overcurrent falling threshold
VOC
Current rising in non-synchronous mode, measure on
V(SRP-SRN), VSRP < 2 V
Current rising, as percentage of V(IREG_CHG), in
synchronous mode, VSRP > 2.2V
45.5
mV
160%
Charge overcurrent threshold floor
Minimum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2 V
50
mV
Charge overcurrent threshold ceiling
Maximum OCP threshold in synchronous mode,
measure on V(SRP-SRN), VSRP > 2.2 V
180
mV
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ELECTRICAL CHARACTERISTICS (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1
5
9
UNIT
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET
Charge undercurrent falling threshold
Switch from SYNCH to NON-SYNCH, VSRP > 2.2 V
mV
BATTERY SHORTED COMPARATOR (BATSHORT)
VBATSHT
BAT short falling threshold, forced
non-syn mode
VBATSHT_HYS
BAT short rising hysteresis
VBATSHT_DEG
Deglitch on both edges
VSRP falling
2
V
200
mV
1
μs
1.25
mV
1.25
mV
1
μs
LOW CHARGE CURRENT COMPARATOR
VLC
Low charge current (average) falling
threshold to force into non-synchronous
mode
VLC_HYS
Low charge current, rising hysteresis
VLC_DEG
Deglitch on both edge
Measure on V(SRP-SRN)
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VVCC > VUVLO, (0–35 mA load)
IVREF_LIM
VREF current limit
VVREF = 0 V, VVCC > VUVLO
35
3.267
3.3
3.333
V
mA
REGN REGULATOR
VREGN_REG
REGN regulator voltage
VVCC > 10 V, CE = HIGH, (0–40 mA load)
5.7
IREGN_LIM
REGN current limit
VREGN = 0 V, VVCC > VUVLO, CE = HIGH
40
6
6.3
V
mA
TTC INPUT AND SAFETY TIMER
TPRECHG
Precharge safety timer range (1)
Precharge time before fault occurs
TCHARGE
Fast-charge safety-timer range, with
±10% accuracy (1)
Tchg = CTTC × KTTC
Fast-charge timer accuracy
KTTC
(1)
1440
1
0.01 μF ≤ CTTC ≤ 0.11 μF
–10%
Timer multiplier
TTC low threshold
1800
2160
s
10
h
10%
5.6
VTTC below this threshold disables the safety timer and
termination
min/nF
0.4
TTC oscillator high threshold
1.5
TTC oscillator low threshold
V
1
TTC source/sink current
45
50
V
V
55
μA
BATTERY SWITCH (BATFET) DRIVER
RDS_BAT_OFF
BATFET turnoff resistance
VACN > 5 V
150
Ω
RDS_BAT_ON
BATFET turnon resistance
VACN > 5 V
20
kΩ
VBATDRV_REG
BATFET drive voltage
VBATDRV_REG = VACN – VBATDRV when VACN > 5 V and
BATFET is on
7
V
4.2
AC SWITCH (ACFET) DRIVER
RDS_AC_OFF
ACFET turnoff resistance
VVCC > 5 V
30
Ω
RDS_AC_ON
ACFET turnon resistance
VVCC > 5 V
20
kΩ
VACDRV_REG
ACFET drive voltage
VACDRV_REG = VVCC – VACDRV when VVCC > 5 V and
ACFET is on
7
V
4.2
AC / BAT MOSFET DRIVERS TIMING
Driver dead time
(1)
8
Dead time when switching between AC and BAT
10
μs
Verified by design
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ELECTRICAL CHARACTERISTICS (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
200
mA
BATTERY DETECTION
tWAKE
Wake time
Maximum time charge is enabled
IWAKE
Wake current
RSENSE = 10 mΩ
tDISCHARGE
Discharge time
Maximum time discharge current is applied
1
sec
IDISCHARGE
Discharge current
8
mA
IFAULT
Fault current after a time-out fault
2
mA
VWAKE
Wake threshold (with respect to VREG)
Voltage on VFB to detect battery absent during wake
50
mV
Discharge threshold
Voltage on VFB to detect battery absent during
discharge
VDISCH
500
50
125
ms
1.55
V
PWM HIGH-SIDE DRIVER (HIDRV)
RDS_HI_ON
High-side driver (HSD) turnon
resistance
VBTST – VPH = 5.5 V
3.3
6
Ω
RDS_HI_OFF
High-side driver turnoff resistance
VBTST – VPH = 5.5 V
1
1.3
Ω
VBTST_REFRESH
Bootstrap refresh comparator threshold
voltage
VBTST – VPH when low-side refresh pulse is requested
4
4.2
V
PWM LOW-SIDE DRIVER (LODRV)
RDS_LO_ON
Low side driver (LSD) turnon resistance
RDS_LO_OFF
Low side driver turnoff resistance
4.1
7
Ω
1
1.4
Ω
PWM DRIVER TIMING
Driver dead time
Dead time when switching between LSD and HSD, no
load at LSD and HSD
PWM ramp height
As percentage of VCC
30
ns
PWM OSCILLATOR
VRAMP_HEIGHT
7
PWM switching frequency
510
600
%
690
kHz
INTERNAL SOFT START (8 steps to regulation current ICHG)
Soft start steps
Soft start step time
8
step
1.6
ms
1.5
s
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power up
Delay from CE = 1 until charger is allowed to turn on
LOGIC IO PIN CHARACTERISTICS (CE, STAT1, STAT2, PG)
VIN_LO
CE input low-threshold voltage
VIN_HI
CE input high-threshold voltage
0.8
V
VBIAS_CE
CE input bias current
V = 3.3 V (CE has internal 1-MΩ pulldown resistor)
VOUT_LO
STAT1, STAT2, PG output low
saturation voltage
6
μA
Sink current = 5 mA
0.5
V
IOUT_HI
Leakage current
V = 32 V
1.2
µA
2.1
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TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
Figure
Figure 2
Charge Enable
Figure 3
Current Soft-Start (CE = 1)
Figure 4
Charge Disable
Figure 5
Continuous-Conduction Mode-Switching Waveforms
Figure 6
Cycle-by-Cycle Synchronous to Nonsynchronous
Figure 7
Transient System Load (DPM)
Figure 8
Battery Insertion
Figure 9
Batter- to-Ground Short Protection
Figure 10
Battery-to-Ground Short Transition
Figure 11
Efficiency vs Output Current
Figure 12
10 V/div
10 V/div
VREF, REGN, and PG Power Up (CE = 1)
PH
2 A/div
IBAT
REGN
5 V/div
CE
5 V/div
2 V/div
VREF
5 V/div
/PG
2 V/div
VCC
LODRV
t − Time = 200 ms/div
t − Time = 4 ms/div
Figure 3. Charge Enable
10 V/div
10 V/div
Figure 2. VREF, REGN, and PG Power Up (CE = 1)
CE
5 V/div
2 A/div
IBAT
PH
5 V/div 2 A/div
5 V/div
LODRV
5 V/div
PH
LODRV
IL
CE
t − Time = 2 μs/div
t − Time = 4 ms/div
Figure 4. Current Soft-Start (CE = 1)
10
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Figure 5. Charge Disable
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5 V/div
PH
HIDRV
LODRV
1 A/div 5 V/div
PH
2 A/div
5 V/div 20 V/div 20 V/div
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IL
LODRV
IL
t − Time = 100 ns/div
t − Time = 100 ns/div
Figure 7. Cycle-by-Cycle Synchronous to
Nonsynchronous
2 A/div
10 V/div
Figure 6. Continuous-Conduction Mode-Switching
Waveform
PH
5 V/div
2 A/div
IIN
2 A/div
2 A/div
ISYS
IBAT
IL
VBAT
t − Time = 200 μs/div
t − Time = 200 ms/div
Figure 9. Battery Insertion
10 V/div
10 V/div
Figure 8. Transient System Load (DPM)
5 V/div
PH
20 V/div
IL
20 V/div
LODRV
2 A/div
LODRV
2 A/div
5 V/div
PH
VBAT
IL
VBAT
t − Time = 10 μs/div
t − Time = 4 ms/div
Figure 10. Battery-to-GND Short Protection
Figure 11. Battery-to-GND Short Transition
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98
96
94
Efficiency - %
92
90
20 Vin, 4 cell
88
12 Vin, 2 cell
86
20 Vin, 3 cell
84
12 Vin, 1 cell
82
80
0
1
2
5
4
3
IBAT - Output Current - A
6
7
8
Figure 12. Efficiency vs Output Current
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Pin Functions – 24-Pin QFN
PIN
NO.
NAME
FUNCTION DESCRIPTION
I/O
1
ACN
I
Adapter current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to GND for common-mode filtering.
2
ACP
I
Adapter current-sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide
differential-mode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to GND for common-mode filtering.
3
ACDRV
O
AC adapter to system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power
MOSFET and the reverse-conduction-blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a
quick turnoff and slow turnon, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an optional
capacitor from gate to source of the ACFET is used to slow down the ON and OFF times.
4
CE
I
Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1-MΩ pulldown resistor.
5
STAT1
O
Open-drain charge-status pin to indicate various charger operations (See Table 3)
6
TS
I
Temperature qualification voltage input for battery-pack negative-temperature-coefficient thermistor. Program the hot and cold
temperature window with a resistor divider from VREF to TS to GND. (See Figure 17)
7
TTC
I
Fast-charge safety timer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is
LOW, the fast-charge timer and termination are disabled. When this input is HIGH, the fast-charge timer is disabled, but
termination is allowed.
8
PG
O
Open-drain power-good status output. Active-LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode).
Active-HIGH when IC has an invalid VCC. PG can be used to drive an LED or communicate with a host processor.
9
STAT2
O
Open-drain charge-status pin to indicate various charger operations (See Table 3)
10
VREF
O
3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to GND pin close to the IC. This voltage could be
used for programming of voltage and current regulation and for programming the TS threshold.
11
ISET1
I
Fast-charge current-set input. The voltage on the ISET1 pin programs the fast-charge current-regulation set-point. To avoid early
termination during the VT1 and VT2 range, fast-charge current must be higher than 2 times the termination current.
12
VFB
I
Output-voltage analog-feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this
node to adjust the output battery-regulation voltage.
13
SRN
I/O
Charge current-sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide
differential-mode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to GND for common-mode filtering.
14
SRP
I/O
Charge current-sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differential-mode
filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to GND for common-mode filtering.
15
ISET2
I
Pre-charge and termination current-set input. The voltage of ISET2 pin programs the pre-charge current-regulation set-point and
termination-current trigger point.
16
ACSET
I
Adapter current-set input. The voltage on the ACSET pin programs the input current-regulation set-point during dynamic power
management (DPM)
17
GND
18
REGN
O
PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the GND pin, close to the IC.
Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to BTST.
19
LODRV
O
PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
20
PH
I
PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET drain,
high-side power MOSFET source, and output inductor).
21
HIDRV
O
PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
22
BTST
I
PWM high-side driver positive supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap Schottky diode
from REGN to BTST.
23
BATDRV
O
Battery to system MOSFET driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the system
from the battery to prevent current flow from the system to the battery, while allowing a low-impedance path from battery to
system. Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the source of the
FET to the system load-voltage node. Connect the drain of the FET to the battery-pack positive terminal. The internal gate drive
is asymmetrical to allow a quick turnoff and slow turnon, in addition to the internal break-before-make logic with respect to
ACDRV. If needed, an optional capacitor from gate to source of the BATFET is used to slow down the ON and OFF times.
24
VCC
I
IC power positive supply. Connect through a 10-Ω resistor to the common-source (diode-OR) point: source of high-side
P-channel MOSFET and source of reverse-blocking power P-channel MOSFET. Place a 1-μF ceramic capacitor from VCC to
GND pin close to the IC.
Thermal pad
Low-current sensitive analog/digital ground. On PCB layout, connect with thermal underneath the IC.
Exposed pad beneath the IC. Always solder the thermal pad to the board, and have vias on the thermal pad plane
star-connecting to GND and to the ground plane for a high-current power converter. It also serves as a thermal pad to dissipate
the heat.
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BLOCK DIAGRAM
bq24616
VREF
VCC-6 V
ACN ACN-6 V ACN-6 V
LDO
INTERNAL
REFERENCE
VREF
3.3 V
LDO
VCC
-
SRN+100 mV
+
VCC
-
VUVLO
+
ACN
+
VCC
VCC
SLEEP
UVLO
VCC
VCC-6 V
LDO
SLEEP
SRN+200 mV
UVLO
ACN-SRN
ACDRV
SYSTEM
POWER
SELECTOR
LOGIC
VCC-6V
-
ACN
ACOV
CE
BATDRV
1M
ACN-6V
+
20X
-
ACP
20XV(ACP-ACN)
+
COMP
ERROR
AMPLIFIER
ACN
BTST
CE
+
ACSET
+
1V
LEVEL
SHIFTER
PWM
-
VFB
HIDRV
+
VFB_REG
BAT_OVP
20 µA
+
SRP-SRN
IBAT_ REG
PH
160% X IBAT_REG
CHG_OCP
GND
TTC
Safety
Timer
IC Tj
+
145 degC
-
CHARGE
FAULT
STAT 1
STAT1
IBAT_ REG
VFB
+
104% X VFB_REG
-
VT1, VT2
-
TSHUT
STATE
MACHINE
LOGIC
BAT_OVP
STAT 2
STAT2
PG
PG
VFB
+
LOWV
+
- 1.55V
TTC
-
0.4 V
+
VCC
+
DISABLE
TMR/TERM
BATTERY
DETECTION
LOGIC
ACOV
TTC
TTC
VREF
DISCHARGE
VT1
VACOV +-
VFB
-
+
-
+
VT2
RCHRG
+
VT1, VT2
VT3, VT4, VT5
VFB_REG
REGN
LODRV
V(SRP-SRN)
-
ISET2
ISET2
6 V LDO
REFRESH
+
+
+
ISET1
-
CE
4.2V
FAULT
2 mA
ISET1
2
ISET1
PWM
CONTROL
LOGIC
BTST
20µA
8 mA
PH
VCC
+
5 mV -
-
SRN
CHARGE
OR
DISCHARGE
SYNCH
-
V(SRP-SRN)
-
+
20X
-
+
SRP
+
50 mV
RCHRG
20XV(SRP- SRN)
-
ISET2
5
TERM
VT3
+
-
TERM
TS
+
SUSPEND
VT4
TERMINATE CHARGE
2.1V
+
-
2.05V
VFB_REG
VT5
2.025V
+
-
VT3, VT4, VT5
Figure 13. Functional Block Diagram for bq24616
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OPERATIONAL FLOWCHART
POR
Turn on
BATDRV FET
SLEEP MODE
VCC > SRN
No
Indicate SLEEP
Yes
Enable VREF LDO &
Chip Bias
Indicate battery
absent
Turn off BATFET
Turn on ACFET
30ms delay
No
See Enabling and Disabling
Charge Section
Battery
present?
Initiate battery
detect algorithm
Yes
Conditions met
for charge?
Indicate NOT
CHARGING,
Suspend timers
No
No
Conditions met
for charge?
No
Yes
Yes
Regulate
precharge current
VFB < VLOWV
Start 30 minute
precharge timer
Yes
Indicate ChargeIn-Progress
Start Fastcharge
timer
No
VFB < VLOWV
Yes
No
Regulate
fastcharge current
Indicate NOT
CHARGING,
Suspend timers
No
Conditions met
for charge?
Yes
Precharge
timer expired?
Yes
Indicate ChargeIn-Progress
No
Turn off charge,
Enable IDISCHG for 1
second
Yes
Indicate Charge In
Progress
VFB > VRECH
&
ICHG < ITERM
FAULT
Enable IFAULT
No
Fastcharge
Timer Expired?
Charge Complete
VFB < VRECH
No
Yes
Indicate FAULT
No
VFB > VRECH
Yes
Indicate DONE
Battery Removed
Yes
Indicate BATTERY
ABSENT
Figure 14. Operational Flowchart
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DETAILED DESCRIPTION
Regulation Voltage
VRECH
Regulation Current
Precharge
Current
Regulation
Phase
Fastcharge Current
Regulation Phase
Fastcharge Voltage
Regulation Phase
Termination
Charge
Current
Charge
Voltage
VLOWV
IPRECH & I TERM
Precharge
Time
Fastcharge Safety Time
Figure 15. Typical Charging Profile
Battery Voltage Regulation
The bq24616 uses a high-accuracy voltage band gap and regulator for high charging-voltage accuracy. The
charge voltage is programmed via a resistor divider from the battery to ground, with the midpoint tied to the VFB
pin. The voltage at the VFB pin is regulated to 2.1 V in the 0°C–45°C range, giving the following equation for the
regulation voltage:
é R2 ù
V
= 2.1 V ´ ê1+
ú,
BAT
ë R1 û
(1)
where R2 is connected from VFB to the battery and R1 is connected from VFB to GND.
Battery Current Regulation
The ISET1 input sets the maximum fast-charging current in the 10°C–60°C range. Battery-charge current is
sensed by resistor RSR, connected between SRP and SRN. The full-scale differential voltage between SRP and
SRN is 100 mV. Thus, for a 10-mΩ sense resistor, the maximum charging current is 10 A. The equation for
charge current is:
VISET1
ICHARGE =
20 ´ RSR
(2)
VISET1, the input voltage range of ISET1, is between 0 V and 2 V. The SRP and SRN pins are used to sense
voltage across RSR with default value of 10 mΩ; however, resistors of other values can also be used. A larger
sense resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher
conduction loss.
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Input Adapter Current Regulation
The total input from an ac adapter or other dc source is a function of the system supply current and the battery
charging current. System current normally fluctuates as portions of the systems are powered up or down. Without
dynamic power management (DPM), the source must be able to supply the maximum system current and the
maximum charger input current simultaneously. By using DPM, the battery charger reduces the charging current
when the input current exceeds the input current limit set by ACSET. The current capability of the ac adaptor can
be lowered, reducing system cost.
Similar to setting battery regulation current, adaptor current is sensed by resistor RAC connected between ACP
and ACN. Its maximum value is set by ACSET using Equation 3:
VACSET
IDPM =
20 ´ RAC
(3)
VACSET, the input voltage range of ACSET, is between 0 and 2 V. The ACP and ACN pins are used to sense
voltage across RAC with a default value of 10 mΩ; however, resistors of other values can also be used. A larger
sense resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher
conduction loss.
Precharge
On power up, if the battery voltage is below the VLOWV threshold, the bq24616 applies the precharge current to
the battery. This feature is intended to revive deeply discharged cells. If the VLOWV threshold is not reached within
30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the status pins.
The precharge current (IPRECHARGE) is determined by the voltage on the ISET2 pin (VISET2) according to
Equation 4.
VISET2
IPRECHARGE =
100 ´ R SR
(4)
Charge Termination, Recharge, and Safety Timer
The bq24616 monitors the charging current during the voltage regulation phase. When VTTC is valid, termination
is detected while the voltage on the VFB pin is higher than the VRECH threshold AND the charge current is less
than the ITERM threshold, as calculated in Equation 5:
VISET2
ITERM =
100 ´ RSR
(5)
VISET2, the input voltage of ISET2, is between 0 and 2 V. The minimum precharge/termination current is clamped
to be around 125 mA with default 10-mΩ sensing resistor. As a safety backup, the bq24616 also provides a
programmable charge timer. The charge time is programmed by the capacitor connected between the TTC pin
and GND, and is given by Equation 6
tCHARGE = CTTC ´ K TTC
(6)
where CTTC (range from 0.01 µF to 0.11 µF to give 1-h to 10-h safety time) is the capacitor connected from the
TTC pin to GND, and KTTC is the constant multiplier (5.6 min/nF).
A new charge cycle is initiated and the fast-charge safety timer is reset when one of the following conditions
occurs:
• The battery voltage falls below the recharge threshold.
• A power-on-reset (POR) event occurs.
• CE is toggled.
The TTC pin may be taken LOW to disable termination and to disable the safety timer. If TTC is pulled to VREF,
the bq24616 continues to allow termination but disables the safety timer. TTC taken low resets the safety timer.
When ACOV, VCCLOWV, and SLEEP mode resume normal, the safety timer also is reset.
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Power Up
The bq24616 uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be
supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, the bq24616
enables the ACFET and disables BATFET. If all other conditions are met for charging, the bq24616 then
attempts to charge the battery (see Enable and Disable Charging Enable and Disable Charging). If the SRN
voltage is greater than VCC, indicating that the battery is the power source, the bq24616 enables BATFET, and
enters a low-quiescent-current (<15-μA) SLEEP mode to minimize current drain from the battery.
If VCC is below the UVLO threshold, the device is disabled, ACFET turns of, and BATFET turns on.
Enable and Disable Charging
The following conditions must be valid before charge is enabled:
• CE is HIGH.
• The device is not in UVCCLOWV mode.
• The device is not in SLEEP mode.
• The VCC voltage is lower than the ac overvoltage threshold (VCC < VACOV)
• 30-ms delay is complete after initial power up.
• The REGN LDO and VREF LDO voltages are at the correct levels.
• Thermal shut (TSHUT) is not valid.
• TS fault is not detected.
Any of the following conditions stops on-going charging:
• CE is LOW.
• Adapter is removed, causing the device to enter VCCLOWV or SLEEP mode.
• Adapter is over voltage.
• The REGN or VREF LDOs are overloaded.
• TSHUT IC temperature threshold is reached (145°C on rising edge with 15°C hysteresis).
• TS voltage goes out of range, indicating the battery temperature is too hot or too cold.
• TTC safety timer times out.
System Power Selector
The bq24616 automatically switches adapter or battery power to the system load. The battery is connected to the
system by default during power up or during SLEEP mode. The battery is disconnected from the system and
then the adapter is connected to the system 30 ms after exiting SLEEP. An automatic break-before-make logic
prevents shoot-through currents when the selectors switch.
ACDRV is used to drive a pair of back-to-back p-channel power MOSFETs between the adapter and ACP with
sources connected together and to VCC. The FET connected to the adapter prevents reverse discharge from the
battery to the adapter when turned off. The p-channel FET with the drain connected to the adapter input provides
reverse battery discharge protection when off, and also minimizes system power dissipation with its low rDS(on)
compared to a Schottky diode. The other p-channel FET connected to ACP separates the battery from the
adapter, and provides a limited dI/dt when connecting the adapter to the system by controlling the FET turnon
time. The BATDRV controls a p-channel power MOSFET placed between BAT and the system.
When the adapter is not detected, ACDRV is pulled to VCC to keep ACFET off, disconnecting the adapter from
the system. BATDRV stays at ACN-6V to connect the battery to the system.
Approximately 30 ms after the device comes out of SLEEP mode, the system begins to switch from battery to
adapter. The break-before-make logic keeps both ACFET and BATFET off for 10 µs before ACFET turns on.
This prevents shoot-through current or any large discharging current from going into the battery. BATDRV is
pulled up to ACN and the ACDRV pin is set to VCC-6V by an internal regulator to turn on p-channel ACFET,
connecting the adapter to the system.
When the adapter is removed, the system waits until VCC drops back to within 200 mV above SRN to switch
from the adapter back to the battery. The break-before-make logic still keeps 10-μs dead time. The ACDRV is
pulled up to VCC and the BATDRV pin is set to ACN-6V by an internal regulator to turn on p-channel BATFET,
connecting the battery to the system.
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Asymmetrical gate drive (fast turnoff and slow turnon) for the ACDRV and BATDRV drivers provides fast turnoff
and slow turnon of the ACFET and BATFET to help the break-before-make logic and to allow a soft start at
turnon of either FET. The soft-start time can be further increased by putting a capacitor from gate to source of
the p-channel power MOSFETs.
Automatic Internal Soft-Start Charger Current
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping up the charge regulation current in eight evenly divided steps up to the programmed charge current.
Each step lasts around 1.6 ms, for a typical rise time of 12.8ms. No external components are needed for this
function.
Converter Operation
The synchronous buck PWM converter uses a fixed-frequency voltage mode with a feed-forward control scheme.
A type-III compensation network allows using ceramic capacitors at the output of the converter. The
compensation input stage is connected internally between the feedback output (FBO) and the error amplifier
input (EAI). The feedback compensation stage is connected between the error amplifier input (EAI) and error
amplifier output (EAO). The LC output filter is selected to give a resonant frequency of 12 kHz–17 kHz for the
bq24616, where the resonant frequency, fo, is given by:
1
fo =
2 p L o Co
(7)
An internal sawtooth ramp is compared to the internal EAO error-control signal to vary the duty cycle of the
converter. The ramp height is 7% of the input adapter voltage, making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage and simplifies the loop
compensation. The ramp is offset by 300 mV in order to allow zero-percent duty cycle when the EAO signal is
below the ramp. The EAO signal is also allowed to exceed the sawtooth ramp signal in order to get a 100%
duty-cycle PWM request. Internal gate-drive logic allows achieving 99.5% duty cycle while ensuring the
N-channel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below
4.2 V for more than 3 cycles, then the high-side n-channel power MOSFET is turned off and the low-side
n-channel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the
high-side driver returns to 100% duty-cycle operation until the (BTST-PH) voltage is detected to fall low again
due to leakage current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping the switching
frequency out of the audible noise region. Also see Application Information for how to select the inductor,
capacitor and MOSFET.
Synchronous and Non-Synchronous Operation
The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current
for a 10-mΩ sense resistor). During synchronous mode, the internal gate-drive logic ensures there is
break-before-make complementary switching to prevent shoot-through currents. During the 30-ns dead time
where both FETs are off, the body-diode of the low-side power MOSFET conducts the inductor current. Having
the low-side FET turn on keeps the power dissipation low and allows safely charging at high currents. During
synchronous mode, the inductor current is always flowing and the converter operates in continuous-conduction
mode (CCM), creating a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor
current for a 10-mΩ sense resistor). The charger is forced into non-synchronous mode when the battery voltage
is lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV.
During non-synchronous operation, the body diode of the lower-side MOSFET can conduct the positive inductor
current after the high-side n-channel power MOSFET turns off. When the load current decreases and the
inductor current drops to zero, the body diode is naturally turned off and the inductor current becomes
discontinuous. This mode is called discontinuous-conduction mode (DCM). During DCM, the low-side n-channel
power MOSFET turns on for around 80 ns when the bootstrap capacitor voltage drops below 4.2 V; then the
low-side power MOSFET turns off and stays off until the beginning of the next cycle, where the high-side power
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MOSFET is turned on again. The 80-ns low-side MOSFET on-time is required to ensure the bootstrap capacitor
is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important
for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and
can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high- and
low-side MOSFETs) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After 80-ns,
the low-side MOSFET is kept off to prevent negative inductor current from occurring.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor
current during the 80-ns recharge pulse. The charge should be low enough to be absorbed by the input
capacitance. Whenever the converter goes into zero percent duty-cycle, the high-side MOSFET does not turn on,
and the low-side MOSFET does not turn on (only 80-ns recharge pulse) either, and there is almost no discharge
from the battery.
During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.
Cycle-by-Cycle Charge Undercurrent Protection
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current. During DCM, the low-side FET only turns on for at around
80 ns to provide refresh charge for the bootstrap capacitor when the bootstrap capacitor voltage drops below 4.2
V. This is important to prevent negative inductor current from causing a boost effect in which the input voltage
increases as power is transferred from the battery to the input capacitors and leads to an overvoltage stress on
the VCC node and potentially causes damage to the system.
Input Overvoltage Protection (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage
reaches the ACOV threshold, charge is disabled and the system is switched to the battery instead of the adapter.
Input Undervoltage Lockout (UVLO)
The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from
either the input adapter or the battery, because a conduction path exists from the battery to VCC through the
high-side NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC are disabled, and the
gate-drive bias to ACFET and BATFET is disabled. ACFET is OFF and BATFET is ON.
Battery Overvoltage Protection
The converter does not allow the high-side FET to turn on until the BAT voltage goes below 102% of the
regulation voltage. This allows one-cycle response to an overvoltage condition, such as occurs when the load is
removed or the battery is disconnected. An 8-mA current sink from SRP/SRN to GND is on only during charge
and allows discharging the stored output inductor energy that is transferred to the output capacitors. BATOVP
also suspends the safety timer.
Cycle-by-Cycle Charge Overcurrent Protection
The charger has secondary cycle-to-cycle overcurrent protection. It monitors the charge current, and prevents
the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when the
overcurrent is detected, and automatically resumes when the current falls below the overcurrent threshold.
Thermal Shutdown Protection
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As an added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C, then the charger soft-starts again if all other enable charge
conditions are valid. Thermal shutdown also suspends the safety timer.
20
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Temperature Qualification and JEITA Guideline
The controller continuously monitors battery temperature by measuring the voltage between the TS pin and
GND. A negative-temperature-coefficient (NTC) thermistor and an external voltage divider typically develop this
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.
To initiate a charge cycle, the voltage on the TS pin must be within the VT1 to VT5 thresholds. If VTS is outside of
this range, the controller suspends charge and waits until the battery temperature is within the VT1 to VT5 range.
During the charge cycle, the battery temperature must be within the VT1 to VT5 thresholds. If battery temperature
is outside of this range, the controller suspends charge and waits until the battery temperature is within the VT1 to
VT5 range. The controller suspends charge by turning off the PWM charge FETs. If VTS is within the range of VT1
and VT2, charge voltage regulation on VFB pin is 2.1 V and the charge current is reduced to ICHARGE/2 (to avoid
early termination during VT1 and VT2 range, fast-charge current must be higher than 2 times the termination
current); if VTS is within the range of VT2 and VT3, the charge voltage regulation on VFB pin is 2.1 V; if VTS is
within VT3 and VT4, the charge voltage regulation on VFB pin is reduced back to 2.05 V; and if VTS is within VT4
and VT5, the charge voltage regulation on the VFB pin is further reduced to 2.025 V. Figure 16 summarizes the
operation. See the "Li-ion battery-charger solutions for JEITA compliance" journal article (SLYT365).
Charge Voltage
VFB =2.1 V
VFB=2.05 V
VFB=2.025 V
Temperature
Charge Current
Charge
Suspended
Charge
Suspended
I Charge
ICharge /2
Temperature
0 °C
(T1)
10 °C
(T2)
45 °C
(T3)
50°C
(T4)
60 °C
(T5)
Figure 16. Thermistor Sense Thresholds
Assuming a 103AT NTC thermistor on the battery pack as shown in Figure 1, the values of RT1 and RT2 can be
determined by using the following equations:
1 ö
æ 1
VVREF ´ RTHCOLD ´ RTHHOT ´ ç
VT5 ÷ø
è VT1
RT2 =
æV
ö
æV
ö
RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷
è VT5
ø
è VT1
ø
(8)
VVREF
-1
VT1
RT1 =
1
1
+
RT2 RTHCOLD
(9)
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VREF
RT1
bq24616
TS
RT2
RTH
103AT
Figure 17. TS Resistor Network
For example, 103AT NTC thermistors are used to monitor the battery pack temperature. Selecting T1 = 0ºC for
COLD and T5 = 60ºC for HOT resuts in RT2 = 6.8 kΩ and RT1 = 2.2 kΩ as calculated in the bq246xx Calculation
Tool, available in the Tools & Software section of the product folder. A small RC filter is suggested to use for
system-level ESD protection.
Timer Fault Recovery
The bq24616 provides a recovery method to deal with timer fault conditions. The following summarizes this
method:
Condition 1: The battery voltage is above the recharge threshold and a time-out fault occurs.
Recovery Method: The timer fault clears when the battery voltage falls below the recharge threshold, and
battery detection begins. A POR condition or taking CE low also clears the fault.
Condition 2: The battery voltage is below the recharge threshold and a time-out fault occurs.
Recovery Method: Under this scenario, the bq24616 applies the IFAULT current to the battery. This small current
is used to detect a battery-removal condition and remains on as long as the battery voltage stays below the
recharge threshold. If the battery voltage goes above the recharge threshold, the bq24616 disables the fault
current and executes the recovery method described in Condition 1. A POR condition or taking CE low also
clears the fault.
PG Output
The open drain PG (power-good) output indicates whether the VCC voltage is valid or not. The open-drain FET
turns on whenever bq24616 has a valid VCC input (not in UVLO or ACOV or SLEEP mode). The PG pin can be
used to drive an LED or communicate to the host processor.
CE (Charge Enable)
The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables
charge, provided all the other conditions for charge are met (see Enable and Disable Charging). A high-to-low
transition on this pin also resets all timers and fault conditions. There is an internal 1-MΩ pulldown resistor on the
CE pin, so if CE is floated, the charge does not turn on.
Inductor, Capacitor, and Sense Resistor Selection Guidelines
The bq24616 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant
frequency, fo, is approximately 12 kHz to 17 kHz for the bq24616.
The following table provides a summary of typical LC components for various charge currents:
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Table 2. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current for
bq24616 (600 kHz Switching Frequency)
CHARGE CURRENT
2A
4A
6A
8A
10A
Output inductor LO
6.8 μH
6.8 μH
4.7 μH
3.3 μH
3.3 μH
Output capacitor CO
20 μF
20 μF
30 μF
40 μF
40 μF
Sense resistor
10 mΩ
10 mΩ
10 mΩ
10 mΩ
10 mΩ
Charge Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in the Table 3. These
status pins can be used to drive LEDs or communicate with the host processor. Note that OFF indicates that the
open-drain transistor is turned off.
Table 3. STAT Pin Definition for bq24616
STAT1
STAT2
Charge in progress
CHARGE STATE
ON
OFF
Charge complete
OFF
ON
Charge suspend, timer fault, AC over-voltage, sleep mode, battery absent
OFF
OFF
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Battery Detection
For applications with removable battery packs, the bq24616 provides a battery-absent detection scheme to
detect insertion or removal of battery packs reliably.
POR or RECHARGE
The battery detection routine runs on
power up, or if VFB falls below VRECH
due to removing a battery or
discharging a battery
Apply 8mA discharge
current, start 1s timer
VFB < VLOWV
No
Yes
1s timer
expired
No
Yes
Battery Present,
Begin Charge
Disable 8mA
discharge current
Enable 125mA Charge,
Start 0.5s timer
VFB > VRECH
Yes
Disable 125mA
Charge
No
0.5s timer
expired
No
Yes
Battery Present,
Begin Charge
Battery Absent
Figure 18. Battery Detection Flowchart
Once the device has powered up, an 8-mA discharge current is applied to the SRN terminal. If the battery
voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is
turned on at low charge current (125 mA). If the battery voltage goes above the recharge threshold within 500
ms, there is no battery present and the cycle restarts. If either the 500-ms or 1-second timer times out before its
respective threshold is hit, a battery is detected and a charge cycle is initiated.
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Battery not detected
VREG
VRECH
(VWAKE)
Battery
inserted
VLOWV
Battery detected
(VDISH)
tRECH_DEG
tLOWV_DEG
tWAKE
Figure 19. Battery-Detect Timing Diagram
Care must be taken that the total output capacitance at the battery node is not so large that the discharge current
source cannot pull the voltage below the LOWV threshold during the 1-second discharge time. The maximum
output capacitance can be calculated as follows:
CMAX =
IDISCH ´ tDISCH
é R ù
0.5 ´ ê1+ 2 ú
ë R1 û
(10)
where CMAX is the maximum output capacitance, IDISCH is the discharge current, tDISCH is the discharge time, and
R2 and R1 are the voltage feedback resistors from the battery to the VFB pin. The 0.5 factor is the difference
between the RECHARGE and the LOWV thresholds at the VFB pin.
Example
For a 3-cell Li+ charger, with R2 = 500 kΩ, R1 = 100 Ωk (giving 12.6 V for voltage regulation), IDISCH = 8 mA,
tDISCH = 1 second,
8mA ´ 1sec
CMAX =
= 2.7 mF
é 500k ù
0.5 ´ ê1+
ú
ë 100k û
(11)
Based on these calculations, no more than 2.7 mF should be allowed on the battery node for proper operation of
the battery-detection circuit.
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Component List for Typical System Circuit of Figure 1
PART DESIGNATOR
QTY
DESCRIPTION
Q1, Q2, Q3
3
P-channel MOSFET, –30 V, –35 A, PowerPAK 1212-8, Vishay-Siliconix, Si7617DN
Q4, Q5
2
N-channel MOSFET, 30 V, 12 A, PowerPAK 1212-8, Vishay-Siliconix, Sis412DN
D1
1
Diode, dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C
D2, D3, D4
3
LED diode, green, 2.1V, 20mA, LTST-C190GKT
RAC, RSR
2
Sense resistor, 10 mΩ, 2010, Vishay-Dale, WSL2010R0100F
L1
1
Inductor, 6.8 µH, 5.5 A, Vishay-Dale IHLP2525CZ
C8, C9, C12, C13
4
Capacitor, ceramic, 10 µF, 35 V, 20%, X7R
C4, C5
2
Capacitor, ceramic, 1 µF, 16 V, 10%, X7R
C1, C3, C6, C11
4
Capacitor, ceramic, 0.1 µF, 16 V, 10%, X7R
C2, C10
2
Capacitor, ceramic, 0.1 µF, 50 V, 10%, X7R
C7
1
Capacitor, ceramic, 1 µF, 50 V, 10%, X7R
C14, C15 (Optional)
2
Capacitor, ceramic, 0.1 µF, 50 V, 10%, X7R
C16
1
Capacitor, ceramic, 2.2 µF, 35 V, 10%, X7R
Cff
1
Capacitor, ceramic, 22 pF, 25 V, 10%, X7R
CTTC
1
Capacitor, ceramic, 0.056 µF, 16V, 5%, X7R
R1, R3, R5, R7
4
Resistor, chip, 100 kΩ, 1/16W, 0.5%
R2
1
Resistor, chip, 500 kΩ, 1/16W, 0.5%
R4
1
Resistor, chip, 32.4 kΩ, 1/16W, 0.5%
R6
1
Resistor, chip, 10 kΩ, 1/16W, 0.5%
R8
1
Resistor, chip, 22.1 kΩ, 1/16W, 0.5%
R9
1
Resistor, chip, 2.2 kΩ, 1/16W, 1%
R10
1
Resistor, chip, 6.8 kΩ, 1/16W, 1%
R11, R12, R13, R18, R19
5
Resistor, chip, 10 kΩ, 1/16W, 5%
R14, R15 (optional)
2
Resistor, chip, 100 kΩ, 1/16W, 5%
R16
1
Resistor, chip, 100 Ω, 1/16W, 5%
R17
1
Resistor, chip, 10 Ω, 1/4W, 5%
R20
1
Resistor, chip, 2 Ω, 1W, 5%
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APPLICATION INFORMATION
Inductor Selection
The bq24616 has 600-kHz switching frequency to allow the use of small inductor and capacitor values. Inductor
saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE
(12)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fS) and
inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
fS ´ L
(13)
The maximum inductor ripple current happens with D = 0.5 or close to 0.5. For example, the battery-charging
voltage range is from 9 V to 12.6 V for a 3-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives
the maximum inductor ripple current. Another example is a 4-cell battery; the battery-voltage range is from 12 V
to 16.8 V, and 12-V battery voltage gives the maximum inductor ripple current.
Usually inductor ripple is designed in the range of 20%–40% of maximum charging current as a trade-off
between inductor size and efficiency for a practical design.
The bq24616 has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the
charging-current-sensing resistor to prevent negative inductor current. The typical UCP threshold is 5-mV on the
falling edge, corresponding to 0.5-A falling edge for a 10-mΩ charging-current-sensing resistor.
Input Capacitor
Input capacitor should have enough ripple current rating to absorb the input switching-ripple current. The
worst-case rms ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst-case capacitor rms current ICIN occurs where the duty cycle is closest
to 50% and can be estimated by the following equation:
ICIN = ICHG ´
D ´ (1 - D)
(14)
A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be
placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The
voltage rating of the capacitor must be higher than the normal input-voltage level. A 25-V rating or higher
capacitor is preferred for 20-V input voltage. A 10-µF to 20-µF capacitance is suggested for typical of 3-A to 4-A
charging current.
Output Capacitor
The output capacitor also should have enough ripple-current rating to absorb the output switching ripple current.
The output-capacitor rms current ICOUT is given:
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3
(15)
The output-capacitor voltage ripple can be calculated as follows:
DVo =
1
8LCfs
2
æ
V 2
ç VBAT - BAT
ç
VIN
è
ö
÷
÷
ø
(16)
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
The bq24616 has an internal loop compensator. To get good loop stability, the resonant frequency of the output
inductor and output capacitor should be designed between 12 kHz and 17 kHz. The preferred ceramic capacitor
is 25-V or higher rating, X7R or X5R, for 4-cell application.
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Power MOSFET Selection
Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6 V of gate-drive voltage. 30-V or higher voltage-rating MOSFETs are
preferred for 20-V input voltage, and 40-V or higher rating MOSFETs are perfered for 20-V to 28-V input voltage.
Figure of merit (FOM) is usually used for selecting the proper MOSFET, based on a tradeoff between the
conduction loss and switching loss. For a top-side MOSFET, FOM is defined as the product of the MOSFET
on-resistance, rDS(on), and the gate-to-drain charge, QGD. For a bottom-side MOSFET, FOM is defined as the
product of the MOSFET on-resistance, rDS(on), and the total gate charge, QG.
FOM top = RDS(on) ´ QG D
FOMbottom = RDS(on) ´ QG
(17)
The lower the FOM value, the lower the total power loss. Usually lower rDS(on) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D =
VOUT/VIN), charging current (ICHG), MOSFET on-resistance rDS(on)), input voltage (VIN), switching frequency (fS),
turnon time (ton) and turnoff time (toff):
1
Ptop = D ´ ICHG2 ´ RDS(on) +
´ VIN ´ ICHG ´ (t on + t off ) ´ fS
2
(18)
The first item represents the conduction loss. Usually MOSFET rDS(on) increases by 50% with a 100ºC junction
temperature rise. The second term represents the switching loss. The MOSFET turnon and turnoff times are
given by:
Q
Q
ton = SW , t off = SW
Ion
Ioff
(19)
where Qsw is the switching charge, Ion is the turnon gate-driving current and Ioff is the turnoff gate-driving current.
If the switching charge is not given in the MOSFET data sheet, it can be estimated by gate-to-drain charge (QGD)
and gate-to-source charge (QGS):
1
QSW = QGD +
´ QGS
2
(20)
Total gate-driving current can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total
turnon gate resistance (Ron) and turnoff gate resistance Roff) of the gate driver:
VREG N - Vplt
Vplt
Ion =
, Ioff =
Ron
Roff
(21)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
Pbottom = (1 - D) ´ ICHG 2 ´ RDS(on)
(22)
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result, all the freewheeling current goes through the body diode of the bottom-side MOSFET. The maximum
charging current in non-synchronous mode can be up to 0.9 A (0.5 A typ.) for a 10-mΩ charging-current-sensing
resistor, considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body
diode capable of carrying the maximum non-synchronous mode charging current.
MOSFET gate-driver power loss contributes to the dominant losses in the controller IC when the buck converter
is switching. Choosing a MOSFET with a small Qg_total reduces the IC power loss to avoid thermal shutdown.
PICLoss_driver = VIN × Qg_total × fs
(23)
where Qg_total is the total gate charge for both upper and lower MOSFETs at 6-V VREGN.
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Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a
second-order system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and
damage the IC. The input filter must be carefully designed and tested to prevent overvoltage events on the VCC
pin. The ACP/ACN pins must be placed after the input ACFET in order to avoid overvoltage stress on these pins
during hot plug-in.
There are several methods for damping or limiting the overvoltage spike during adapter hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC
maximum pin-voltage rating. A high-current-capability TVS Zener diode can also limit the overvoltage level to an
IC-safe level. However, these two solutions may not have low cost or small size.
A cost-effective and small-size solution is shown in Figure 20. R1 and C1 are comprise a damping RC network to
damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for
reverse voltage protection for the VCC pin (it can be the body diode of the input ACFET). C2 is the VCC pin
decoupling capacitor and it should be placed as close as possible to the VCC pin. R2 and C2 form a damping
RC network to further protect the IC from high-dv/dt and high-voltage spikes. The C2 value should be less than
the C1 value so R1 can be dominant over the ESR of C1 to get enough damping effect for hot plug-in. The R1
and R2 packages must be sized to handle the inrush-current power loss according to resistor manufacturer’s
datasheet. The filter component values always must be verified with the real application, and minor adjustments
may be needed to fit in the real application circuit.
D1
Adapter
connector
R1
2W
C1
2.2 mF
(2010)
R2 (1206)
4.7 -30W
VCC pin
C2
0.1-1 mF
Figure 20. Input Filter
PCB Layout
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize the high-frequency current path loop (see Figure 21) is important to prevent electrical
and magnetic field radiation and high-frequency resonant problems. Here is a PCB layout priority list for proper
layout. Lay out of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to the switching MOSFET supply and ground connections, and
use the shortest-possible copper trace connection. These parts should be placed on the same layer of PCB,
instead of on different layers using vias to make the connection.
2. The IC should be placed close to the switching MOSFET gate terminals. Keep the gate-drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB of switching MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging-current-sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in same layer, close to each other (minimize loop
area), and do not route the sense leads through a high-current path (see Figure 22 for a Kelvin connection
for the best current accuracy). Place decoupling capacitors on these traces next to the IC.
5. Place output capacitor next to the sensing resistor output and ground.
6. Output-capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
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Product Folder Link(s): bq24616
29
bq24616
SLUSA49B – APRIL 2010 – REVISED OCTOBER 2011
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7. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use the copper pour for analog
ground, but avoid the power pins to reduce inductive and capacitive noise coupling. Connect the analog
ground to GND. Connect the analog ground and power ground together using the thermal pad as the single
ground-connection point. Or use a 0-Ω resistor to tie analog ground to power ground (the thermal pad should
tie to analog ground in this case). A star connection under the thermal pad is highly recommended.
8. It is critical that the exposed thermal pad on the back side of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the
other layers.
9. Decoupling capacitors should be placed next to the IC pins. Make trace connections as short as possible.
10. All via sizes and numbers should be adequate for a given current path.
SW
L1
V BAT
R1
High
Frequency
VIN
BAT
Current
C1
Path
PGND
C2
C3
Figure 21. High-Frequency Current Path
Current Direction
R SNS
Current Sensing Direction
To SRP - SRN pin or ACP - ACN pin
Figure 22. Sensing-Resistor PCB Layout
See the EVM design (SLUU396) for the recommended component placement with trace and via locations.
For the QFN information, see SCBA017 and SLUA271.
SPACE
SPACE
REVISION HISTORY
Changes from Revision A (May 2010) to Revision B
Page
•
Changed descriptions of PH and BTST pins ...................................................................................................................... 13
•
Added added text, equations and illustrations from Inductor Selection to PCB Layout ..................................................... 27
•
Corrected equation for caclulating voltage ripple on output capacitor ................................................................................ 27
30
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
BQ24616RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QTJ
BQ24616RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
QTJ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24616RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24616RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24616RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24616RGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
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