Texas Instruments SN74LV4T125 Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter (Rev. B) Datasheet
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SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
SN74LV4T125 Single Power Supply Quadruple Buffer Translator GATE With 3-State
Output CMOS Logic Level Shifter
1 Features
1
• Single-Supply Voltage Translator at
5.0-V, 3.3-V, 2.5-V, and 1.8-V V
CC
• Operating Range of 1.8 V to 5.5 V
• Up Translation
– 1.2 V (1) to 1.8 V at 1.8-V V
CC
– 1.5 V
(1) to 2.5 V at 2.5-V V
CC
– 1.8 V
(1) to 3.3 V at 3.3-V V
CC
– 3.3 V to 5.0 V at 5.0-V V
CC
• Down Translation
– 3.3 V to 1.8 V at 1.8-V V
CC
– 3.3 V to 2.5 V at 2.5-V V
CC
– 5.0 V to 3.3 V at 3.3-V V
CC
• Logic Output is Referenced to V
CC
• Characterized up to 50 MHz at 3.3-V V
CC
• 5.5 V Tolerance on Input Pins
• –40°C to 125°C Operating Temperature Range
• Pb-Free Packages Available: SC-70 (RGY)
– 3.5 × 3.5 × 1 mm
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model (A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
• Supports Standard Logic Pinouts
• CMOS Output B Compatible with AUP125,
LVC125
(1)
Refer the V
IH
/V
IL and output drive for lower V
CC condition.
2 Applications
• Tablet
• Smartphone
• Personal Computer
• Industrial Automotive
3 Description
SN74LV4T125 is a low-voltage CMOS buffer gate that operates at a wider voltage range for portable, telecom, industrial, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
The input is designed with a lower threshold circuit to match 1.8-V input logic at V
CC
= 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5-V tolerant input pins enable down translation
(for example, 3.3 V to 2.5 V output at V
CC
The wide V
CC
= 2.5 V).
range of 1.8 V to 5.5 V allows the generation of desired output levels to connect to controllers or processors.
The SN74LV4T125 device is designed with currentdrive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
PART NUMBER
PACKAGE
TSSOP (14)
BODY SIZE (NOM)
5.00 mm x 4.40 mm
SN74LV4T125
VQFN (14) 3.50 mm x 3.50 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
4 Simplified Application Diagram
1OE
5 V, 3.3 V, 2.5 V, 1.8 V
1.8 V
1A 1Y
4OE
4A
1.8 V, 2.5 V, 3.3 V
3.3 V
4Y
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014 www.ti.com
1 Features ..................................................................
2 Applications ...........................................................
3 Description .............................................................
4 Simplified Application Diagram............................
5 Revision History.....................................................
6 Pin Configuration and Functions .........................
7 Specifications.........................................................
7.1
Absolute Maximum Ratings ......................................
7.2
Handling Ratings.......................................................
7.3
Recommended Operating Conditions .......................
7.4
Thermal Information ..................................................
7.5
Electrical Characteristics...........................................
7.6
Timing Requirements ................................................
7.7
Noise Characteristics ................................................
7.8
Operating Characteristics..........................................
7.9
Typical Characteristics ..............................................
8 Parameter Measurement Information ..................
9 Detailed Description ............................................
Table of Contents
9.1
Overview .................................................................
9.2
Functional Block Diagram .......................................
9.3
Feature Description.................................................
9.4
Device Functional Modes........................................
10 Applications and Implementation......................
10.1
Application Information..........................................
10.2
Typical Application ................................................
11 Power Supply Recommendations .....................
12 Layout...................................................................
12.1
Layout Guidelines .................................................
12.2
Layout Example ....................................................
13 Device and Documentation Support .................
13.1
Documentation Support ........................................
13.2
Trademarks ...........................................................
13.3
Electrostatic Discharge Caution ............................
13.4
Glossary ................................................................
14 Mechanical, Packaging, and Orderable
Information ...........................................................
5 Revision History
Changes from Revision A (March 2014) to Revision B Page
• Updated Features. .................................................................................................................................................................
• Updated Simplified Application Diagram ................................................................................................................................
• Updated Pin Functions table. ................................................................................................................................................
• Updated Detailed Design Procedure section. .....................................................................................................................
Changes from Original (February 2014) to Revision A Page
• Updated 1 page preview document to full version. ...............................................................................................................
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6 Pin Configuration and Functions
PW Package
(TOP VIEW)
1OE
1A
1Y
2OE
2A
2Y
GND
3
4
5
1
2
6
7
14
13
12
11
10
9
8
V
CC
4OE
4A
4Y
3OE
3A
3Y
5
6
7
8
9
NO.
1
2
3
4
10
11
12
13
14
PIN
NAME
1OE
1A
1Y
2OE
2A
2Y
GND
3Y
3A
3OE
4Y
4A
4OE
V
CC
Pin Functions
I/O DESCRIPTION
I
O
—
O
I
O
I
I
I
I
O
I
I
—
Enable 1
Input 1
Output 1
Enable 2
Input 2
Output 2
Ground Pin
Output 3
Input 3
Enable 3
Output 4
Input 4
Enable 4
Power Pin
SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
RGY Package
(Transparent TOP VIEW)
1A
1Y
2OE
2A
2Y
2
3
4
5
6
1
7
14
13
12
11
10
9
4OE
4A
4Y
3OE
3A
8
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SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
7 Specifications
www.ti.com
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
I
I
I
V
V
V
I
CC
O
IK
OK
O
Supply voltage range
Input voltage range
(2)
Voltage range applied to any output in the high-impedance or power-off state
(2)
Voltage range applied to any output in the high or low state
(2)
Input clamp current
Output clamp current
V
I
< 0
V
O
< 0 or V
O
> V
CC
Continuous output current
Continuous current through V
CC or GND
MIN
–0.5
–0.5
–0.5
MAX
7.0
7.0
4.6
–0.5
V
CC
+ 0.5
–20
±50
±35
±70
UNIT
V
V
V mA mA mA mA
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
T
V stg
(ESD)
Storage temperature range
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins
(2)
MIN
–65
0
0
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
MAX
150
2
1
UNIT
°C kV
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SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
I
I
V
V
V
I
CC
O
OH
OL
∆t/∆v
Supply voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
High or Low State
H-Z
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5.0 V
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
CC
= 5.0 V
V
CC
= 1.6 V to 2.0 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V or 3.6 V
V
CC
= 4.5 V to 5.0 V
MIN
1.6
0
0
0
MAX UNIT
5.5
V
5.5
V
V V
CC
V
CC
–3
–5
V mA
–8
–16
16
20
3
5
8 mA
20
20
20
125 ns/V
°C T
A
Operating free-air temperature –40
(1) All unused inputs of the device must be held at V
CC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004 .
7.4 Thermal Information
R
θJA
R
θJCtop
R
θJB
ψ
JT
ψ
JB
R
θJCbot
THERMAL METRIC
Junction-to-ambient thermal resistance
(1)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
PW
14 PINS
SN74LV4T125
RGY
14 PINS
126.9
54.2
68.6
7.5
68.0
—
52.9
67.8
29.0
2.6
29.1
9.3
UNIT
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report ( SPRA953 ).
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SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
7.5 Electrical Characteristics
∆I
CC
I
OZ
I off
C i
C o over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
T
A
= 25°C
MIN TYP
V
IH
V
IL
V
OH
High-level input voltage
Low-level input voltage
I
OH
= –50 µA
I
OH
= –2 mA
I
OH
= –3 mA
I
OH
= –5 mA
I
OH
= –8 mA
I
OH
= –8 mA
I
OH
= –16 mA
I
OH
= –16 mA
I
OL
= 50 µA
V
CC
= 1.65 V to 1.9 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.0 V
V
CC
= 1.65 V to 1.9 V
V
CC
= 2.3 V to 2.77 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 1.65 V to 5.5 V
V
CC
= 1.65 V
V
CC
= 2.3 V
V
CC
= 3.0 V
V
CC
= 4.5 V
I
OH
= 2 mA
I
OH
= 3 mA
V
CC
= 5.0 V
V
CC
= 1.65 V to 5.5 V
V
CC
= 1.65 V
V
CC
= 1.8 V
V
CC
= 2.3 V
V
CC
= 2.5 V
0.95
1.1
1.3
2
V
CC
– 0.1
1.4
2.05
2.7
2.6
3.7
3.8
4.4
V
OL
I
OH
= 5 mA
I
OH
= 8 mA
I
OH
= 8 mA
I
OH
= 8 mA
I
OH
= 16 mA
I
OH
= 16 mA
V
CC
= 3.0 V
V
CC
= 3.3 V
V
CC
= 4.5 V
I
I
I
CC
A input V
I
=0 V or V
CC
V
I
I
O
= 0 V or V
CC
,
= 0; open on loading
V
CC
= 5.0 V
V
CC
= 0 V, 1.8 V,
2.5 V, 3.3 V, 5.5 V
V
CC
= 5.0 V
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
= 1.8 V
One input at 0.3 V or 3.4 V
Other inputs at 0 or V
CC
,
I
O
= 0
One input at 0.3 V or 1.1 V
Other inputs at 0 or V
CC
,
I
O
= 0
V
O
= V
CC or GND
V
O or V
I
= 0 to 5.5 V
V
I
= V
CC or GND
V
O
= V
CC or GND
V
CC
= 5.5 V
V
CC
= 1.8 V
V
CC
= 5.5 V
V
CC
= 0 V
V
CC
= 3.3 V
V
CC
= 3.3 V
1.6
4.8
1.35
±0.25
0.5
±0.1
2
2
2
2
MAX
0.55
0.7
0.85
0.9
0.1
0.1
0.2
0.2
0.25
0.35
0.4
0.45
0.50
0.55
0.55
T
A
= –40°C to 125°C
MIN MAX
1
1.2
1.35
2
0.5
0.6
0.75
0.85
V
CC
– 0.1
1.35
2.0
2.6
2.5
3.6
3.7
4.3
0.1
0.1
0.3
0.3
0.3
0.4
0.45
0.5
0.55
0.55
0.55
±1
20
20
20
20
1.6
4.8
1.5
±2.5
5 www.ti.com
UNIT
V
V
V
V
V
V
μA
V
V
V
V
V
V
V
V
V
μA
μA
μA
μA pF pF
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SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
7.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted) (see
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
FREQUENCY
(TYP)
V
CC
C
L
MIN
T
A
= 25°C
TYP t pd t
PZH t
PZL t
PHZ t
PLZ
Any In
OE
OE
OE
OE
Y
Y
Y
Y
Y
DC to 50 MHz
DC to 50 MHz
DC to 30 MHz
DC to 50 MHz
DC to 50 MHz
DC to 30 MHz
DC to 50 MHz
DC to 50 MHz
DC to 30 MHz
DC to 50 MHz
DC to 50 MHz
DC to 30 MHz
DC to 50 MHz
DC to 50 MHz
DC to 30 MHz
5.0 V
3.3 V
2.5 V
1.8 V
5.0 V
3.3 V
2.5 V
1.8 V
5.0 V
3.3 V
2.5 V
1.8 V
5.0 V
3.3 V
2.5 V
1.8 V
5.0 V
3.3 V
2.5 V
1.8 V
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
18
3
3.5
8
9
17
8
14.5
15.5
3
3.5
5.3
5.8
10
11
3.5
3.8
5
5.5
7.5
2.8
3
4
5
5.5
6.5
2
2.3
2.8
3.3
4
5
6.5
3.5
5
5.5
7.5
7.5
11
2 t sk
Any In Y
DC to 50 MHz
DC to 30 MHz
5.0 V to
2.5 V
1.8 V
15 pF
15 pF
3.5
4
5.6
6.2
8.5
9.5
17.5
5.8
6
8
8.5
15
16
MAX
3.2
3.5
4.5
5.5
6.5
7
11
12
4
4.2
8
12
2.5
3
2.8
3.2
18.5
3.5
4
6
8
4
6
3.8
4.3
5.5
7
1 1
UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
T
A
= –65°C to 125°C
MIN TYP MAX
3
3
5
3.5
4.5
5.5
5.5
7
7.5
11
12.5
3.5
4
6.5
7.5
8.5
12
13
4
4.5
3.5
4
6
7
9
10.5
18
5.8
5.7
8.5
9
15.5
16
4
4.5
6.2
7.5
9.5
11
18.5
6.1
6.5
9
9.5
16.5
17
2
2.5
3.3
8
12
2
3.8
4.2
5
7
19
3.5
4
4.5
6.5
6
8
8.5
13
2.7
3.2
3.2
4
4.2
5
5.7
8.5
20
4
4.5
6.5
9
5
7
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SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
7.7 Noise Characteristics
V
CC
= 3.3 V, C
L
= 50 pF, T
A
= 25°C (1)
PARAMETER
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
Quiet output, maximum dynamic V
OL
Quiet output, minimum dynamic V
OL
Quiet output, minimum dynamic V
OH
High-level dynamic input voltage
Low-level dynamic input voltage
(1) Characteristics are for surface-mount packages only.
7.8 Operating Characteristics
V
CC
= 5 V, T
A
= 25°C
C pd
PARAMETER
Power dissipation capacitance
7.9 Typical Characteristics
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
± 0.5
0
MIN
2.31
TEST CONDITIONS
C
L
= 50 pF, f = 10 MHz
5 10
Time - ns
Figure 1. Switching Characteristics at 50 MHz
Excellent Signal Integrity (1.8 V to 3.3 V at 3.3-V V
CC
)
15
TYP
0.4
–0.3
3
TYP
16
Output
Input www.ti.com
MAX
0.8
–0.8
0.99
UNIT
V
V
V
V
V
UNIT pF
20
C001
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8 Parameter Measurement Information
SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
From Output
Under Test
CL
(see Note A)
Test
Point
From Output
Under Test
CL
(see Note A)
RL = 1 kΩ
S1
VCC
Open
GND
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH
Open Drain
S1
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
Timing Input 1.5 V
3 V
0 V tw th
3 V tsu
1.5 V
3 V
Input
1.5 V 1.5 V
Data Input
1.5 V
0 V 0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
In-Phase
Output tPLH
1.5 V 1.5 V
50% VCC
3 V
0 V tPHL
VOH
50% VCC
VOL tPLH tPHL
Out-of-Phase
Output
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V 1.5 V
3 V
Output
Control
0 V
Output
Waveform 1
S1 at VCC
(see Note B) tPZL tPZH
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
50% VCC tPLZ
VOL + 0.3 V
VOL tPHZ
VOH − 0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
≈VCC
VOH
≈0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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SN74LV4T125
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9 Detailed Description
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9.1 Overview
The SN74LVxTxx family was created to allow up- or down-voltage translation with only one power rail. The family has over-voltage tolerant inputs that allow down translation from up to 5.5 V to the V
CC level that can be as low as 1.8 V. The family SN74LVxTxx also has a lowered switching threshold that allows it to translate up to the V
CC level that can be as high as 5.5 V.
9.1.1 Translating Down
Using these parts to translate down is very simple. Because the inputs are tolerant to 5.5 V at any valid V
CC can be used to down translate. The input can be any level above V
CC
I
V
CC
CC current will remain less than or equal to the specified value.
, they up to 5.5 V and the output will equal the level, which can be as low as 1.8 V. One important advantage to down translating using this part is that the
Down translation possibilities with SN74LVxTxx:
• With 1.8-V V
CC
• With 2.5-V V
CC
• With 3.3-V V
CC from 2.5 V, 3.3 V, or 5 V down to 1.8 V.
from 3.3 V or 5 V down to 2.5 V.
from 5 V down to 3.3 V.
9.1.2 Translating Up
Using the SN74LVxTxx family to translate up is very simple. The input switching threshold is lowered so the high level of the input voltage can be much lower than a typical CMOS V
IH
. For instance, If the V
CC is 3.3 V then the typical CMOS switching threshold would be V
CC
V
CC
/ 2 or 1.65 V. This means the input high level must be at least
× 0.7 or 2.31 V. On the LVxT devices the input threshold for 3.3-V V
CC is approximately 1 V. This allows a signal with a 1.8-V V
IH to be translated up to the V
CC level of 3.3 V.
Up translation possibilities with SN74LVxTxx:
• With 2.5-V V
CC from 1.8 V to 2.5 V.
•
• With 3.3-V V
CC
With 5-V V
CC from 1.8 V or 2.5 V to 3.3 V.
From 2.5 V or 3.3 V to 5 V.
9.2 Functional Block Diagram
1OE
1A 1Y
2OE
2A
3OE
3A
4OE
4A
2Y
3Y
4Y
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9.3 Feature Description
This part is a single supply buffer that is capable up or down translation. The output will equal V
CC can vary from 1.2 V to 5.5 V.
while the input
Up Translation Mode:
• 1.2 V to 1.8 V at 1.8-V V
CC
• 1.5 V to 2.5 V at 2.5-V V
CC
• 1.8 V to 3.3 V at 3.3-V V
CC
• 3.3 V to 5.0 V at 5.0-V V
CC
Down Translation Mode:
• 3.3 V to 1.8 V at 1.8-V V
CC
• 3.3 V to 2.5 V at 2.5-V V
CC
• 5.0 V to 3.3 V at 3.3-V V
CC
9.4 Device Functional Modes
This device performs the function of a buffer where input logic level equals the output logic level, while providing buffering and drive to the output. The SN74LV4T125 device will also translate voltages up or down while performing this function.
OE
L
L
H
Table 1. Function Table
(Each Buffer)
INPUTS
A
H
L
X
OUTPUT
Y
H
L
Z
A
Table 2. Supply V
CC
= 3.3 V
INPUT b
(Lower Level Input)
V
IH
(min) = 1.35 V
V
IL
(max) = 0.8 V
B
(V
OUTPUT
CC
CMOS)
Y
V
OH
(min) = 2.9 V
V
OL
(max) = 0.2 V
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SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
10 Applications and Implementation
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
www.ti.com
10.1 Application Information
Based upon the lower-threshold circuit design of the LVxT family, the LVxT family also supports level translation.
For level translation up and down, the LVxT family requires only a single power supply.
1.8V, 3.3V, 5.0V
1.8V, 3.3V, 5.0V
1.8V, 3.3V, 5.0V
Standard Logic Mode 1.8V, 3.3V
10.2 Typical Application
VIH = 2.0V
VIL = 0.8V
Vcc = 5.0V
5.0V
3.3V
System
LV1Txx Logic 5.0V
System
5.0V, 3.3V
2.5V, 1.8V
1.5V, 1.2V
System
VIH = 0.99V
VIL = 0.55V
Vcc = 1.8V
LV1Txx Logic
Vcc = 3.3V
5.0V, 3.3V
2.5V, 1.8V
System
LV1Txx Logic 3.3V
System
1.8V
System
VOH min = 2.4V
VIH min = 1.36V
VIL min = 0.8V
VOL max = 0.4V
Figure 3. Switching Thresholds for 1.8 V to 3.3 V Translation
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Typical Application (continued)
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. The input threshold levels are lowered to allow for up translation. At 5 V the device has equivalent TTL input levels.
10.2.2 Detailed Design Procedure
1. Recommended input conditions:
– Rise time and fall time specifications. See ( Δt/ΔV) in
Recommended Operating Conditions
table.
– Specified high and low levels. See (V
IH and V
IL
) in
Recommended Operating Conditions
table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid V
CC
.
2. Recommend output conditions:
– Load currents should not exceed 35 mA per output and 70 mA total for the part.
– Outputs should not be pulled above V
CC
.
10.2.3 Application Curves
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
± 0.5
0
Input
Output
5 10
Time - ns
15 20
Figure 4. Switching Characteristics at 50 MHz
Excellent Signal Integrity (3.3 V to 3.3 V at 3.3-V V
CC
)
C002
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
± 0.5
0.0
Input
Output
12.5
25.0
37.5
Time - nS
50.0
62.5
75.0
Figure 5. Switching Characteristics at 15 MHz
Excellent Signal Integrity (3.3 V to 1.8 V at 1.8-V V
CC
)
87.5
C001
11 Power Supply Recommendations
The power supply can be any voltage between the Min and Max supply voltage rating located in the
Recommended Operating Conditions
.
Each V
CC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 µF is recommended. If there are multiple V
CC pins, then 0.01 µF or 0.022 µF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 µF and 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results.
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SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
12 Layout
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12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in
are the rules that must be observed under all circumstances.
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
The logic level that should be applied to any particular unused input depends on the function of the device.
Generally they will be tied to GND or V
CC whichever make more sense or is more convenient.
It is generally acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of the IOs so they also cannot float when disabled.
12.2 Layout Example
V
CC
Unused Input
Input
Output
Input
Unused Input Output
Figure 6. Layout Diagram
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13 Device and Documentation Support
SN74LV4T125
SCLS749B – FEBRUARY 2014 – REVISED SEPTEMBER 2014
13.1 Documentation Support
13.1.1 Additional Product Selection
DEVICE
SN74LV1T00
SN74LV1T02
SN74LV1T04
SN74LV1T08
SN74LV1T34
SN74LV1T14
SN74LV1T32
SN74LV1T86
SN74LV1T125
SN74LV1T126
SN74LV4T125
PACKAGE
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV, DRL
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV, DRL
DCK, DBV, DRL
RGY, PW
DESCRIPTION
2-Input Positive-NAND Gate
2-Input Positive-NOR Gate
Inverter Gate
2-Input Positive-AND Gate
Single Buffer Gate
Single Schmitt-Trigger Inverter Gate
2-Input Positive-OR Gate
Single 2-Input Exclusive-Or Gate
Single Buffer Gate with 3-state Output
Single Buffer Gate with 3-state Output
Quadruple Bus Buffer Gate With 3-State Outputs
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
SN74LV4T125PWR
Status
(1)
ACTIVE
Package Type Package
Drawing
TSSOP PW
Pins Package
14
Qty
Eco Plan
(2)
2000 Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
CU SN
MSL Peak Temp
(3)
Level-1-260C-UNLIM
Op Temp (°C)
-40 to 125
Device Marking
(4/5)
LV4T125
SN74LV4T125RGYR ACTIVE VQFN RGY 14 3000 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 125 LVT125
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
10-Jun-2014 www.ti.com
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
6-Jun-2014
*All dimensions are nominal
Device
SN74LV4T125PWR
SN74LV4T125RGYR
Package
Type
Package
Drawing
TSSOP
VQFN
PW
RGY
Pins
14
14
SPQ
2000
3000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
12.4
330.0
12.4
A0
(mm)
6.9
B0
(mm)
5.6
K0
(mm)
1.6
3.75
3.75
1.15
P1
(mm)
8.0
8.0
W
(mm)
12.0
12.0
Pin1
Quadrant
Q1
Q1
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
6-Jun-2014
*All dimensions are nominal
Device
SN74LV4T125PWR
SN74LV4T125RGYR
Package Type Package Drawing Pins
TSSOP
VQFN
PW
RGY
14
14
SPQ
2000
3000
Length (mm) Width (mm) Height (mm)
364.0
367.0
364.0
367.0
27.0
35.0
Pack Materials-Page 2
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