TUSB4020BI Two-Port USB 2.0 Hub 1 Features 3 Description

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TUSB4020BI

SLLSEI0 – JULY 2015

TUSB4020BI Two-Port USB 2.0 Hub

1 Features

1

• Two-Port USB 2.0 Hub

• USB 2.0 Hub Features

– Multi-Transaction Translator (MTT) Hub: Two

Transaction Translators

– Four Asynchronous Endpoint Buffers per

Transaction Translator

• DM/DP Polarity Swap

• Type C Compatible

• Supports Battery Charging

– CDP Mode (Upstream Port Connected)

– DCP Mode (Upstream Port Unconnected)

– DCP Mode Complies With Chinese

Telecommunications Industry Standard YD/T

1591-2009

– D+/D– Divider Mode

• Per Port or Ganged Power Switching and

Overcurrent Notification Inputs

• OTP ROM, Serial EEPROM, or I

2

C/SMBus Slave

Interface for Custom Configurations:

– VID and PID

– Port Customizations

– Manufacturer and Product Strings (Not by OTP

ROM)

– Serial Number (Not by OTP ROM)

• Application Feature Selection Using Terminal

Selection or EEPROM/ or I

2

C/SMBus Slave

Interface

• Provides 128-Bit Universally Unique Identifier

(UUID)

• Supports On-Board and In-System OTP/EEPROM

Programming Through the USB 2.0 Upstream

Port

• Single Clock Input, 24-MHz Crystal or Oscillator

• No Special Driver Requirements; Works

Seamlessly on any Operating System With USB

Stack Support

• 48-Pin HTQFP Package (PHP)

3 Description

The TUSB4020BI is a two-port USB 2.0 hub. It provides USB high-speed/full-speed connections on the upstream port and provides high-speed, fullspeed, or low-speed connections on the two downstream ports. When the upstream port is connected to an electrical environment that supports high-speed and full-speed/low-speed connections, high-speed and full-speed/low-speed USB connectivity is enabled on the downstream ports.

When the upstream port is connected to an electrical environment that only supports full-speed/low-speed connections, high-speed connectivity are disabled on the downstream ports.

The TUSB4020BI supports per port or ganged power switching and overcurrent protection.

An individually port power controlled hub switches power on or off to each downstream port as requested by the USB host. Also when an individually port power controlled hub senses an over-current event, only power to the affected downstream port will be switched off.

A ganged hub switches on power to all its downstream ports when power is required to be on for any port. The power to the downstream ports is not switched off unless all ports are in a state that allows power to be removed. Also when a ganged hub senses an overcurrent event, power to all downstream ports will be switched off.

PART NUMBER

Device Information

(1)

PACKAGE BODY SIZE (NOM)

TUSB4020BI HTQFP (48) 7.00 mm × 7.00 mm

(1) For all available packages, see the orderable addendum at the end of the data sheet.

Personal

Computer

Block Diagram

TUSB4020BI

TUSB4020BI

USB2

WebCAM

Type A

Port

USB 1.1

Keyboard

2 Applications

• Computer Systems

• Docking Stations

• Monitors

• Set-Top Boxes

USB 2.0 Connection USB 2.0 Hub

USB 2.0 Port

USB 2.0 Device

USB 1.1 Device

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TUSB4020BI


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1

Features ..................................................................

1

2

Applications ...........................................................

1

3

Description .............................................................

1

4

Revision History.....................................................

2

5

Description (continued).........................................

3

6

Pin Configuration and Functions .........................

3

7

Specifications.........................................................

7

7.1

Absolute Maximum Ratings .....................................

7

7.2

ESD Ratings..............................................................

7

7.3

Recommended Operating Conditions .......................

7

7.4

Thermal Information ..................................................

7

7.5

3.3-V I/O Electrical Characteristics ...........................

8

7.6

Hub Input Supply Current .........................................

8

7.7

Power-Up Timing Requirements ...............................

9

8

Detailed Description ............................................

10

8.1

Overview .................................................................

10

8.2

Functional Block Diagram .......................................

10

8.3

Feature Description.................................................

11

8.4

Device Functional Modes........................................

12

Table of Contents

8.5

Programming...........................................................

13

8.6

Register Maps .........................................................

14

9

Application and Implementation ........................

26

9.1

Application Information............................................

26

9.2

Typical Applications ................................................

27

10

Power Supply Recommendations .....................

33

10.1

Power Supply ........................................................

33

10.2

Downstream Port Power .......................................

33

10.3

Ground ..................................................................

33

11

Layout...................................................................

34

11.1

Layout Guidelines .................................................

34

11.2

Layout Example ....................................................

35

12

Device and Documentation Support .................

37

12.1

Community Resources..........................................

37

12.2

Trademarks ...........................................................

37

12.3

Electrostatic Discharge Caution ............................

37

12.4

Glossary ................................................................

37

13 Mechanical, Packaging, and Orderable

Information ...........................................................

37

4 Revision History

DATE

July 2015

REVISION

*

NOTES

Initial release.

2

Submit Documentation Feedback

Product Folder Links:

TUSB4020BI

Copyright © 2015, Texas Instruments Incorporated

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TUSB4020BI


5 Description (continued)

The TUSB4020BI downstream ports provide support for battery charging applications by providing battery charging connected downstream port (CDP) handshaking support. It also supports a dedicated charging port

(DCP) mode when the upstream port is not connected. The DCP mode supports USB devices which support the

USB Battery Charging and the Chinese Telecommunications Industry Standard YD/T 1591-2009. In addition, an automatic mode provides transparent support for BC devices and devices supporting Divider Mode charging solutions when the upstream port is unconnected.

The TUSB4020BI provides terminal strap configuration for some features including battery charging support, and also provides customization though OTP ROM, I

2

C EEPROM or through an I

2

C/SMBus slave interface for PID,

VID, and custom port and phy configurations. Custom string support is also available when using an I

2

C

EEPROM or the I

2

C/SMBus slave interface.

The device is available in a 48-pin HTQFP package and is offered in an industrial version for operation over the temperature range of –40°C to 85°C.

6 Pin Configuration and Functions

PHP Package

48-Pin HTQFP

Top View

VDD33

XI

XO

VDD33

USB_DP_DN1

USB_DM_DN1

RSVD

RSVD

VDD

RSVD

RSVD

VDD33

36

37

35 34 33 32 31 30 29 28 27 26 25

24

38

23

22

39

40 21

20 41

42

43

(TOP VIEW)

19

18

17 44

45

16

46

47

48

1 2 3 4 5 6 7 8 9 10 11

15

14

13

12

USB_R1

VDD33

SMBUSz

PWRCTL_POL

RSVD

RSVD

VDD

RSVD

RSVD

USB_DM_DN2

USB_DP_DN2

VDD33



TUSB4020BI


3

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Pin Functions

PIN

NAME NO.

CLOCK AND RESET SIGNALS

TYPE

(1)

DESCRIPTION

GRSTz

XI

XO

11

38

39

I

PU

I

O

Global power reset. This reset brings all of the TUSB4020BI internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional.

Crystal input. This terminal is the crystal input for the internal oscillator. The input may alternately be driven by the output of an external oscillator. When using a crystal a 1-M Ω feedback resistor is required between XI and XO.

Crystal output. This terminal is the crystal output for the internal oscillator. If XI is driven by an external oscillator this pin may be left unconnected. When using a crystal a 1-M Ω feedback resistor is required between XI and XO.

USB UPSTREAM SIGNALS

USB_DP_UP

USB_DM_UP

USB_R1

USB_VBUS

26

27

24

9

I/O

I/O

I

I

USB high-speed differential transceiver (positive)

USB high-speed differential transceiver (negative)

Precision resistor reference. A 9.53-k Ω ±1% resistor should be connected between

USB_R1 and GND.

USB upstream port power monitor. The VBUS detection requires a voltage divider. The signal USB_VBUS must be connected to VBUS through a 90.9-k Ω ±1% resistor, and to ground through a

10-k Ω ±1% resistor from the signal to ground.

USB DOWNSTREAM SIGNALS

USB_DP_DN1

USB_DM_DN1

PWRCTL1/BATEN1

OVERCUR1z

USB_DP_DN2

USB_DM_DN2

PWRCTL2/BATEN2

OVERCUR2z

41

42

4

5

14

15

6

8

I/O

I/O

I/O

PD

PU

I/O

I/O

I/O

PD

I

I

PU

USB high-speed differential transceiver (positive) downstream port 1.

USB high-speed differential transceiver (negative) downstream port 1.

USB port 1 power-on control for downstream power or battery charging enable. The terminal is used for control of the downstream power switch for Port 1.

In addition, the value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging support for Port 1 as indicated in the Battery Charging

Support register.

0 = Battery charging not supported

1 = Battery charging supported

USB DS port 1 overcurrent detection input. This terminal is used to connect the over current output of the downstream port power switch for port 1.

0 = An overcurrent event has occurred

1 = An overcurrent event has not occurred

If power management is enabled, the external circuitry needed should be determined by the power switch. In ganged mode, either OVERCUR1z or OVERCUR2z can be used. In ganged mode, the overcurrent will be reported as a hub event instead of a port event.

USB high-speed differential transceiver (positive) downstream port 2.

USB high-speed differential transceiver (negative) downstream port 2.

Power-on control /battery charging enable for downstream port 2. This terminal is used for control of the downstream power switch for port 2.

The value of the terminal is sampled at the deassertion of reset to determine the value of the battery charging support for port 2 as indicated in the Battery Charging Support register.

0 = Battery charging not supported

1 = Battery charging supported

Overcurrent detection for downstream port 2. This terminal is used to connect the over current output of the downstream port power switch for port 2.

0 = An overcurrent event has occurred

1 = An overcurrent event has not occurred

If power management is enabled, the external circuitry needed should be determined by the power switch. In ganged mode either OVERCUR1z or OVERCUR2z can be used. In ganged mode the overcurrent will be reported as a hub event instead of a port event.

(1) I = input, O = output, I/O = input/output, PU = internal pullup resistor, PD = internal pulldown resistor, and PWR = power signal

4



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TUSB4020BI


PIN

NAME

I

2

C/SMBUS SIGNALS

NO.

TYPE

(1)

Pin Functions (continued)

DESCRIPTION

SCL/SMBCLK

SDA/SMBDAT

SMBUSz

PWRCTL_POL

GANGED/SMBA2/

HS_UP

2

3

22

21

35

I/O

PD

I/O

PD

TEST AND MISCELLANEOUS SIGNALS

I

PU

I/O

PD

I

PU

I

2

C clock/SMBus clock. Function of terminal depends on the setting of the SMBUSz input.

When SMBUSz = 1, this terminal acts as the serial clock interface for an I

2

C

EEPROM.

When SMBUSz = 0, this terminal acts as the serial clock interface for an SMBus host.

This pin must be pulled up to use the OTP ROM.

Can be left unconnected if external interface not implemented.

I

2

C data/SMBus data. Function of terminal depends on the setting of the SMBUSz input.

When SMBUSz = 1, this terminal acts as the serial data interface for an I

2

C

EEPROM.

When SMBUSz = 0, this terminal acts as the serial data interface for an SMBus host.

This pin must be pulled up to use the OTP ROM.

Can be left unconnected if external interface not implemented.

SMBUS mode.

The value of the terminal is sampled at the deassertion of reset to enable I

2

C or SMBus mode.

0 = SMBus mode selected

1 = I

2

C mode selected

After reset, this signal is driven low by the TUSB4020BI. Due to this behavior, it is recommended to not tie directly to supply but instead pull-up or pull-down using external resistor.

Power control polarity.

The value of the terminal is sampled at the deassertion of reset to set the polarity of

PWRCTL[2:1].

0 = PWRCTL polarity is active high.

1 = PWRCTL polarity is active low.


Ganged operation enable/SMBus address bit 2/ high-speed status for upstream port

The value of the terminal is sampled at the deassertion of reset to set the power switch and over current detection mode as follows:

0 = Individual power control supported when power switching is enabled.

1 = Power control gangs supported when power switching is enabled.

When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus slave address bit 2. SMBus slave address bits 2 and 3 are always 1 for the TUSB4020BI.

After reset, this signal indicates the high-speed USB connection status of the upstream port. A value of 1 indicates the upstream port is connected to a high-speed USB capable port.

Note: Individual power control must be enabled for battery charging applications.



TUSB4020BI


5

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Pin Functions (continued)

NAME

PIN

FULLPWRMGMTz/

SMBA1

NO.

36

RSVD

16, 17, 19,

20, 28, 29,

31, 32, 43,

44, 46, 47

10

I/O

TEST

POWER AND GROUND SIGNALS

VDD

1, 12, 18,

30, 34, 45

VDD33

GND

7, 13, 23,

25, 33, 37,

40, 48

PAD

I

PD

PWR

PWR

—

TYPE

(1)

I, PU

DESCRIPTION

Full power management enable/ SMBus Address bit 1.

The value of the terminal is sampled at the deassertion of reset to set the power switch control follows:

0 = Power switching supported

1 = Power switching not supported

Full power management is the ability to control power to the downstream ports of the

TUSB4020BI using PWRCTL[2:1]/BATEN[2:1].

When SMBus mode is enabled using SMBUSz, this terminal sets the value of the SMBus slave address bit 1. SMBus slave address bit 3 is always 1 for the TUSB4020BI.

Can be left unconnected if full power management and SMBus are not implemented.


Note: Power switching must be supported for battery charging applications.

Reserved. These pins are for internal use only and should be left unconnected on PCB.

TEST mode enable. When this terminal is asserted high at reset enables test mode. This terminal is reserved for factory use. It is recommended to pull-down this terminal to ground.

1.1-V power rail

3.3-V power rail

Ground

6



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TUSB4020BI


7 Specifications

7.1 Absolute Maximum Ratings

(1)

over operating free-air temperature (unless otherwise noted)

VDD Steady-state supply voltage

VDD33 Steady-state supply voltage

T stg

Storage temperature

MIN

–0.3

–0.3

–65

MAX

1.4

3.8

150

UNIT

V

V

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

V

(ESD)

Electrostatic discharge

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

(1)

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins

(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

VALUE UNIT

±4000

±1500

V

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

VDD

(1)

T

A

T

J

1.1-V supply voltage

VDD33 3.3-V supply voltage

USB_VBUS Voltage at USB_VBUS pin

Operating free-air temperature range

Operating junction temperature range

MIN

0.99

3

0

–40

–40

(1) A 1.05-V, 1.1-V, or 1.2-V supply may be used as long as minimum and maximum supply conditions are met.

NOM

1.1

3.3

25

25

MAX UNIT

1.26

V

3.6

1.155

V

V

85

105

°C

°C

7.4 Thermal Information

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

R

θJC(bot)

THERMAL METRIC

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

(1)

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

TUSB4020BI

PHP (HTQFP)

48 PINS

31.8

16.1

13

0.5

12.9

0.9

UNIT

°C/W

°C/W

°C/W

°C/W

°C/W

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953 .



TUSB4020BI


7

TUSB4020BI


7.5 3.3-V I/O Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

V

IH

V

IL

V

I

V

O t t

PARAMETER

High-level input voltage

(1)

Low-level input voltage

(1)

Input voltage

Output voltage

(2)

Input transition time (t rise and t fall

)

OPERATION TEST CONDITIONS

VDD33

VDD33

V hys

Input hysteresis

(3)

I

I

V

V

OH

OL

OZ

OZP

High-level output voltage

Low-level output voltage

High-impedance, output current

(2)

High-impedance, output current with internal pullup or pulldown resistor

(4)

Input current

(5)

VDD33

VDD33

VDD33

VDD33

I

I

VDD33

(1) Applies to external inputs and bidirectional buffers

(2) Applies to external outputs and bidirectional buffers

(3) Applies to GRSTz

(4) Applies to pins with internal pullups/pulldowns

(5) Applies to external input buffers

I

OH

= –4 mA

I

OL

= 4 mA

V

I

= 0 to VDD33

V

I

= 0 to VDD33

V

I

= 0 to VDD33

7.6 Hub Input Supply Current

typical values measured at T

A

= 25°C

PARAMETER

LOW-POWER MODES

Power-on (after reset)

Disconnect from host

Suspend

ACTIVE MODES (US STATE / DS STATE)

2.0 host / 1 HS device active

2.0 host / 2 HS devices active

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MIN

2

0

0

0

0

TYP

2.4

MAX UNIT

VDD33 V

0.8

VDD33

V

V

VDD33

25

0.13 ×

VDD33

V ns

V

0.4

±20

V

V

µA

±225

±15

µA

µA

VDD33

3.3 V

48

60

5

5

5

VDD11

1.1 V

39

39

39

71

80

UNIT

mA mA mA mA mA

8



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TUSB4020BI


7.7 Power-Up Timing Requirements

t d1 t d2 t su_io t hd_io t

VDD33_RAMP t

VDD_RAMP

VDD33 stable before VDD stable

(1)

VDD and VDD33 stable before deassertion of GRSTz

Setup for MISC inputs

(3) sampled at the deassertion of GRSTz

Hold for MISC inputs

(3) sampled at the deassertion of GRSTz.

VDD33 supply ramp requirements

VDD supply ramp requirements

MIN

see

(2)

3

0.1

0.1

0.2

0.2

NOM MAX UNIT

ms ms

µs

100

100

µs ms ms

(1) An active reset is required if the VDD33 supply is stable before the VDD11 supply. This active Reset shall meet the 3ms power-up delay counting from both power supplies being stable to the de-assertion of GRSTz.

(2) There is no power-on relationship between VDD33 and VDD unless GRSTz is only connected to a capacitor to GND. Then VDD must be stable minimum of 10 μs before the VDD33.

(3) MISC pins sampled at deassertion of GRSTz: FULLPWRMGMTz, GANGED, PWRCTL_POL, SMBUSz, BATEN[4:1], and AUTOENz.

Td2

GRSTz

VDD33

Td1

VDD

MISC_IO

Tsu_io Thd_io

Figure 1. Power-Up Timing Requirements



TUSB4020BI


9

TUSB4020BI


8 Detailed Description

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8.1 Overview

The TUSB4020BI is a two-port USB 2.0 hub. It provides USB high-speed/full-speed connections on the upstream port and provides USB high-speed, full-speed, or low-speed connections on the downstream ports.

When the upstream port is connected to an electrical environment that supports high-speed and fullspeed/low-speed connections, USB high-speed and full-speed/low-speed connectivity is enabled on the downstream ports. When the upstream port is connected to an electrical environment that only supports fullspeed/low-speed connections, USB high-speed connectivity are disabled on the downstream ports.

8.2 Functional Block Diagram

VDD33

VDD

VSS

Power

Distribution

USB 2.0 Hub

XI

XO

Oscillator

GRSTz

TEST

GANGED/SMBA2/HS_UP

FULLPWRMGMTz/SMBA1

PWRCTL_POL

SMBUSz

SCL/SMBCLK

SDA/SMBDAT

OVERCUR1z

PWRCTL1/BATEN1

OVERCUR2z

PWRCTL2/BATEN2

Clock and

Reset

Distribution

GPIO

I

2

C

SMBUS

VBUS

Detect

Control

Registers

OTP

ROM

10



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8.3 Feature Description

TUSB4020BI


8.3.1 Battery Charging Features

The TUSB4020BI provides support for battery charging. Battery charging support may be enabled on a per port basis through the REG_6h(batEn[1:0]).

Battery charging support includes both charging downstream port (CDP) and dedicated charging port (DCP) modes. The DCP mode is compliant with the Chinese Telecommunications Industry Standard YD/T 1591-2009.

In addition to standard DCP mode, the TUSB4020BI provides a mode (AUTOMODE) which automatically provides support for DCP devices and devices that support custom charging indication. AUTOMODE is disabled by default. When in AUTOMODE, the port automatically switches between a divider mode and the DCP mode depending on the portable device connected. The divider mode places a fixed DC voltage on the ports DP and

DM signals which allows some devices to identify the capabilities of the charger. The default divider mode indicates support for up to 5 W. The divider mode can be configured to report a high-current setting (up to 10 W) through REG_Ah(HiCurAcpModeEn). When AUTOMODE is enabled through REG_Ah(autoModeEnz), the CDP mode is not functional. CDP mode can not be used when AUTOMODE is enabled.

The battery charging mode for each port depends on the state of Reg_6h(batEn[n]), the status of the VBUS input, and the state of REG_Ah(autoModeEnz) upstream port, as identified in

Table 1

. Battery charging can also be enabled through the PWRCTL1/BATEN1 and PWRCTL2/BATEN2 pins.

batEn[n]

0

1

Table 1. TUSB4020BI Battery Charging Modes

VBUS

Don’t care

<4 V

>4 V

autoModeEnz

Don’t care

0

1

1

BC Mode Port x

(x = n + 1)

Don’t care

Automode

(1) (2)

DCP

(3) (4)

CDP

(3)

(1) Auto-mode automatically selects divider-mode or DCP mode.

(2) Divider mode can be configured for high-current mode through register or OTP settings.

(3) USB device is USB Battery Charging Specification Revision 1.2 Compliant

(4) USB device is Chinese Telecommunications Industry Standard YD/T 1591-2009

8.3.2 USB Power Management

The TUSB4020BI can be configured for power switched applications using either per-port or ganged powerenable controls and overcurrent status inputs.

Power switch support is enabled by REG_5h(fullPwrMgmtz) and the per-port or ganged mode is configured by

REG_5h(ganged). It can also be enabled through the FULLPWRMGMTz pin. Also ganged or individual control can be controlled by the GANGED pin.

The TUSB4020BI supports both active-high and active-low power-enable controls. The PWRCTL[2:1] polarity is configured by REG_Ah(pwrctlPol). The polarity can also be configured by the PWRCTL_POL pin.

8.3.3 Clock Generation

The TUSB4020BI accepts a crystal input to drive an internal oscillator or an external clock source. If a crystal is used, a 1-M Ω shunt resistor is required. Keep the XI and XO traces as short as possible and away from any switching leads to minimize noise coupling.



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R1

1M

TUSB4020BI

XI

XO

CL1

24MHz

CL2

Figure 2. TUSB4020BI Clock

8.3.4 Power-Up and Reset

The TUSB4020BI does not have specific power sequencing requirements with respect to the VDD or VDD33 power rails. The VDD or VDD33 power rails may be powered up for an indefinite period of time while the other is not powered up if all of these constraints are met:

• All maximum ratings and recommended operating conditions are observed.

• All warnings about exposure to maximum rated and recommended conditions are observed, particularly junction temperature. These apply to power transitions as well as normal operation.

• Bus contention while VDD33 is powered-up must be limited to 100 hours over the projected lifetime of the device.

• Bus contention while VDD33 is powered-down may violate the absolute maximum ratings.

A supply bus is powered up when the voltage is within the recommended operating range. A supply bus is powered down when it is below that range, either stable or in transition.

A minimum reset duration of 3 ms is required, which is defined as the time when the power supplies are in the recommended operating range to the deassertion of GRSTz. This can be generated using programmable-delay supervisory device or using an RC circuit.

8.4 Device Functional Modes

8.4.1 External Configuration Interface

The TUSB4020BI supports a serial interface for configuration register access. The device may be configured by an attached I

2

C EEPROM or accessed as a slave by a SMBus-capable host controller. The external interface is enabled when both the SCL/SMBCLK and SDA/SMBDAT terminals are pulled up to 3.3 V at the deassertion of reset. The mode, I

2

C master, or SMBus slave is determined by the state of SMBUSz terminal at reset.

12



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8.5 Programming

TUSB4020BI


8.5.1 One-Time Programmable (OTP) Configuration

The TUSB4020BI allows device configuration through OTP non-volatile memory (OTP). The programming of the

OTP is supported using vendor-defined USB device requests. For details using the OTP features, contact your TI representative.

Table 2

provides a list features which may be configured using the OTP. The bit field section in

Table 2

shows which features can be controlled by OTP ROM. The bits not listed in the table are not accessible by the OTP

ROM.

CONFIGURATION REGISTER OFFSET

REG_01h

REG_02h

REG_03h

REG_04h

REG_07h

REG_07h

REG_0Ah

REG_0Ah

REG_F2h

Table 2. OTP Configurable Features

BIT FIELD

[7:0]

[7:0]

[7:0]

[7:0]

[0]

[1]

[1]

[4]

[3:1]

DESCRIPTION

Vendor ID LSB

Vendor ID MSB

Product ID LSB

Product ID MSB

Port removable configuration for downstream ports 1. OTP configuration is inverse of rmbl[1:0], that is:

1 = Not removable

0 = Removable

Port removable configuration for downstream ports 2. OTP configuration is inverse of rmbl[1:0], that is:

1 = Not removable

0 = Removable

Automode enable

High-current divider mode enable.

USB power switch power-on delay.

8.5.2 I

2

C EEPROM Operation

The TUSB4020BI supports a single-master, standard mode (100 kbit/s) connection to a dedicated I

2

C EEPROM when the I

2

C interface mode is enabled. In I

2

C mode, the TUSB4020BI reads the contents of the EEPROM at bus address 1010000b using 7-bit addressing starting at address 0.

If the value of the EEPROM contents at byte 00h equals 55h, the TUSB4020BI loads the configuration registers according to the EEPROM map. If the first byte is not 55h, the TUSB4020BI exits the I

2

C mode and continues execution with the default values in the configuration registers. The hub will not connect on the upstream port until the configuration is completed. If the TUSB4020BI detects an unprogrammed EEPROM (value other than

55h), it enters programming mode and a programming endpoint within the hub is enabled.

Note, the bytes located above offset Ah are optional. The requirement for data in those addresses depends on the options configured in the Device Configuration, Phy Custom Configuration, and Device Configuration 2 registers.

For details on I

2

C operation, refer to the UM10204 I

2

C-bus Specification and User Manual.

8.5.3 SMBus Slave Operation

When the SMBus interface mode is enabled, the TUSB4020BI supports read block and write block protocols as a slave-only SMBus device.

The TUSB4020BI slave address is 1000 1xyz, where:

• x is the state of GANGED/SMBA2/HS_UP terminal at reset

• y is the state of FULLPWRMGMTz/SMBA1 terminal at reset

• z is the read/write bit; 1 = read access, 0 = write access.

If the TUSB4020BI is addressed by a host using an unsupported protocol, it does not respond. The TUSB4020BI waits indefinitely for configuration by the SMBus host and does not connect on the upstream port until the

SMBus host indicates configuration is complete by clearing the CFG_ACTIVE bit.



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For details on SMBus requirements, refer to the System Management Bus Specification.

8.6 Register Maps

8.6.1 Configuration Registers

The internal configuration registers are accessed on byte boundaries. The configuration register values are loaded with defaults but can be overwritten when the TUSB4020BI is in I

2

C or SMBus mode.

BYTE ADDRESS

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh to 0Fh

10h to 1Fh

20h to 21h

22h

23h

24h

25h to 2Fh

30h to 4Fh

50h to 8Fh

90h to CFh

D0 to DFh

F0h

F1h

F2h

F3 to F7h

F8h

F9 to FFh

Table 3. TUSB4020BI Register Map

CONTENTS

ROM Signature Register

Vendor ID LSB

Vendor ID MSB

Product ID LSB

Product ID MSB

Device Configuration Register

Battery Charging Support Register

Device Removable Configuration Register

Port Used Configuration Register

Reserved

Device Configuration Register 2

Reserved

UUID Byte [15:0]

LangID Byte [1:0]

Serial Number String Length

Manufacturer String Length

Product String Length

Reserved

Serial Number String Byte [31:0]

Manufacturer String Byte [63:0]

Product String Byte [63:0]

Reserved

Additional Feature Configuration Register

Reserved

Charging Port Control Register

Reserved

Device Status and Command Register

Reserved

EEPROM CONFIGURABLE

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes, program to 00h

Yes

No

Yes, if customStrings is set

Yes, if customSerNum is set



Yes

Yes, if customSerNum is set



No

Yes

Yes

Yes

No

No

No

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TUSB4020BI


8.6.1.1 ROM Signature Register (offset = 0h) [reset = 0h]

Figure 3. Register Offset 0h

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

LEGEND: R/W = Read/Write; R = Read only; –n = value after reset

Bit

7:0

Field

romSignature

Type

R/W

3

0

R/W

2

0

R/W

1

0

R/W

0

0

R/W

Table 4. ROM Signature Register

Reset Description

0h

ROM Signature Register. This register is used by the TUSB4020BI in I

2

C mode to validate the attached EEPROM has been programmed. The first byte of the

EEPROM is compared to the mask 55h and if not a match, the TUSB4020BI aborts the EEPROM load and executes with the register defaults.

8.6.1.2 Vendor ID LSB Register (offset = 1h) [reset = 51h]


7

0

R/W

6

1

R/W

5

0

R/W

4

1

R/W


3

0

R/W

Bit

7:0

Field

vendorIdLsb

Type

R/W

2

0

R/W

1

0

R/W

0

1

R/W

Table 5. Vendor ID LSB Register


51h

Vendor ID LSB. Least significant byte of the unique vendor ID assigned by the

USB-IF; the default value of this register is 51h representing the LSB of the TI

Vendor ID 0451h. The value may be overwritten to indicate a customer vendor ID.

This field is read/write unless the OTP ROM VID and OTP ROM PID values are non-zero. If both values are non-zero, the value when reading this register shall reflect the OTP ROM value.

8.6.1.3 Vendor ID MSB Register (offset = 2h) [reset = 4h]


7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W


3

0

R/W

Bit

7:0

Field

vendorIdMsb

Type

R/W

2

1

R/W

1

0

R/W

0

0

R/W

4h

Table 6. Vendor ID MSB Register


Vendor ID MSB. Most significant byte of the unique vendor ID assigned by the

USB-IF; the default value of this register is 04h representing the MSB of the TI

Vendor ID 0451h. The value may be overwritten to indicate a customer vendor ID.

This field is read/write unless the OTP ROM VID and OTP ROM PID values are non-zero. If both values are non-zero, the value when reading this register shall reflect the OTP ROM value.



TUSB4020BI


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8.6.1.4 Product ID LSB Register (offset = 3h) [reset = 25h]


7

0

R/W

6

0

R/W

5

1

R/W

4

0

R/W


3

0

R/W

Table 7. Product ID LSB Register

Bit

7:0

Field Type

productIdLsb R/W

Reset

25h

2

1

R/W

1

0

R/W

0

1

R/W

Description

Product ID LSB. Least significant byte of the product ID assigned by TI. The default value of this register is 25h representing the LSB of the product ID assigned by TI. The value reported in the USB 2.0 device descriptor is the value of this register bit wise

XORed with 00000010b. The value may be overwritten to indicate a customer product

ID.

This field is read/write unless the OTP ROM VID and OTP ROM PID values are nonzero. If both values are non-zero, the value when reading this register shall reflect the

OTP ROM value.

8.6.1.5 Product ID MSB Register (offset = 4h) [reset = 80h]


7

1

R/W

6

0

R/W

5

0

R/W

4

0

R/W


3

0

R/W

Bit

7:0

2

0

R/W

1

0

R/W

0

0

R/W

Field Type

productIdLsb R/W

Table 8. Bit Descriptions – Product ID MSB Register

Reset

80h

Description

Product ID MSB. Most significant byte of the product ID assigned by TI; the default value of this register is 80h representing the MSB of the product ID assigned by TI. The value may be overwritten to indicate a customer product ID.

This field is read/write unless the OTP ROM VID and OTP ROM PID values are nonzero. If both values are non-zero, the value when reading this register will reflect the

OTP ROM value.

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TUSB4020BI


8.6.1.6 Device Configuration Register (offset = 5h) [reset = 1Xh]


7

0

R/W

6

0

R/W

5

0

R/W

4

1

R


3

X

R/W

Table 9. Device Configuration Register

2

X

R/W

Bit Field

7

6

5

4

3

2

1

0 customStrings customSernum

RSVD

RSVD ganged fullPwrMgmtz

RSVD

RSVD

Type

R/W

R/W

R/W

R

R/W

R/W

R/W

R

1

0

R/W

0

0

R


1Xh

1Xh

1Xh

1Xh

Custom strings enable. This bit controls the ability to write to the Manufacturer String

Length, Manufacturer String, Product String Length, Product String, and Language ID registers.

0 = The Manufacturer String Length, Manufacturer String, Product String Length, Product

String, and Language ID registers are read only.

1 = The Manufacturer String Length, Manufacturer String, Product String Length, Product

String, and Language ID registers may be loaded by EEPROM or written by SMBus.

The default value of this bit is 0.

Custom serial number enable. This bit controls the ability to write to the serial number registers.

0 = The Serial Number String Length and Serial Number String registers are read only.

1 = The Serial Number String Length and Serial Number String registers may be loaded by EEPROM or written by SMBus.

The default value of this bit is 0.

Reserved. This bit is reserved.

Reserved. This bit is reserved and returns 1 when read.

1Xh

1Xh

1Xh

1Xh

Ganged. This bit is loaded at the deassertion of reset with the value of the

GANGED/SMBA2/HS_UP terminal.

0 = When fullPwrMgmtz = 0, each port is individually power switched and enabled by the

PWRCTL[2:1]/BATEN[2:1] terminals

1 = When fullPwrMgmtz = 0, the power switch control for all ports is ganged and enabled by the PWRCTL1/BATEN1 terminal

When the TUSB4020BI is in I

2

C mode, the TUSB4020BI loads this bit from the contents of the EEPROM.

When the TUSB4020BI is in SMBUS mode, the value may be overwritten by an SMBus host.

Full Power Management. This bit is loaded at the deassertion of reset with the value of the FULLPWRMGMTz/SMBA1 terminal.

0 = Port power switching and over-current status reporting is enabled

1 = Port power switching and over-current status reporting is disabled


2



Reserved. This bit is reserved and should not be altered from the default.

Reserved. This field is reserved and returns 0 when read.



TUSB4020BI


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8.6.1.7 Battery Charging Support Register (offset = 6h) [reset = 0Xh]


7

0

R

6

0

R/W

5

0

R/W

4

0

R/W


3

0

R/W

2

0

R/W

Table 10. Battery Charging Support Register

Bit

7:2

1:0

Field

RSVD

Type

R batEn[1:0] R/W

1

X

R/W

0

X

R/W


0Xh Reserved. Read only, returns 0 when read.

0Xh

Battery Charger Support. The bits in this field indicate whether the downstream port implements the charging port features.

0 = The port is not enabled for battery charging support features

1 = The port is enabled for battery charging support features

Each bit corresponds directly to a downstream port, that is batEn0 corresponds to downstream port 1, and batEN1 corresponds to downstream port 2.

The default value for these bits are loaded at the deassertion of reset with the value of

PWRCTL/BATEN[1:0].

When in I2C/SMBus mode the bits in this field may be overwritten by EEPROM contents or by an SMBus host.

8.6.1.8 Device Removable Configuration Register (offset = 7h) [reset = 0Xh]


7

0

R/W

6

0

R

5

0

R

4

0

R


3

0

R

2

0

R

Bit

7

6:2

1:0

Field

customRmbl

RSVD rmbl[1:0]

1

X

R

0

X

R/W

Table 11. Device Removable Configuration Register

Type

R/W

R

R/W


0Xh

Custom removable status. When this field is a 1, the TUSB4020BI uses rmbl bits in this register to identify removable status for the ports.

0Xh

0Xh

Reserved. Read only, returns 0 when read. Bits 3:2 are RW. They are reserved and return 0 when read.

Removable. The bits in this field indicate whether a device attached to downstream ports 2 through 1 are removable or permanently attached.

0 = The device attached to the port is not removable

1 = The device attached to the port is removable

Each bit corresponds directly to a downstream port n + 1, that is rmbl0 corresponds to downstream port 1, rmbl1 corresponds to downstream port 2, and so forth.

This field is read only unless the customRmbl bit is set to 1. Otherwise the value of this filed reflects the inverted values of the OTP ROM non_rmb[1:0] field.

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TUSB4020BI


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8.6.1.9 Port Used Configuration Register (offset = 8h) [reset = 0h]


7

0

R

6

0

R

5

0

R

4

0

R


3

0

R

2

0

R

Table 12. Port Used Configuration Register

Bit

7:0

Field

RSVD

Type

R

Reset

0h

Description

Reserved. Read only.

1

1

R

TUSB4020BI


0

1

R

8.6.1.10 PHY Custom Configuration Register (offset = 9h) [reset = 0h]


7

0

R

6

0

R

5

0

R/W

4

0

R


3

0

R

2

0

R

Bit

7:6

5

4:2

1:0

Field

RSVD

RSVD

RSVD

RSVD

1

1

R/W

0

1

R/W

Table 13. PHY Custom Configuration Register

Type

R

R/W

R

R/W

Reset

0h

0h

0h

0h

Description

Reserved. Read only, returns 0 when read.



Reserved. This field is reserved and should not be altered from the default.



TUSB4020BI


19

TUSB4020BI


8.6.1.11 Device Configuration Register 2 (offset = Ah)

Figure 13. Register Offset Ah

7

0

R

6

0

RW

5

X

RW

4

0

RW


3

0

RW

2

0

RW

1

0

RW

www.ti.com

0

0

R

Bit

7

6

5

4

3

2

1

0

Field Name

RSVD customBCfeatures pwrctlPol

Table 14. Bit Descriptions – Device Configuration Register 2

Access

RO

RW

RW

HiCurAcpModeEn RO/RW

RSVD dsportEcrEn autoModeEnz

RSVD

RW

RW

RO/RW

RO



Custom Battery Charging Feature Enable. This bit controls the ability to write to the battery charging feature configuration controls.

0 = The HiCurAcpModeEn and AutoModeEnz bits are read only and the values are loaded from the OTP ROM.

1 = The HiCurAcpModeEn and AutoModeEnz bits are read/write and can be loaded by EEPROM or written by SMBus. from this register.

This bit may be written simultaneously with HiCurAcpModeEn and AutoModeEnz.

Power enable polarity. This bit is loaded at the deassertion of reset with the inverse value of the PWRCTL_POL terminal.

0 = PWRCTL polarity is active low

1 = PWRCTL polarity is active high


2



High-current ACP mode enable. This bit enables the high-current tablet charging mode when the automatic battery charging mode is enabled for downstream ports.

0 = High current divider mode disabled

1 = High current divider mode enabled

This bit is read only unless the customBCfeatures bit is set to 1. Otherwise the value of this bit reflects the value of the OTP ROM HiCurAcpModeEn bit.

Reserved

DSPort ECR enable. This bit enables full implementation of the DSPORT ECR (April

2013).

0 = DSPort ECR (April 2013) is enabled with the exception of changes related to the CCS bit is set upon entering U0, and changes related to avoiding or reporting compliance mode entry.

1 = The full DSport ECR (April 2013) is enabled.

Automatic Mode Enable. This bit is loaded from the OTP ROM.

The automatic mode only applies to downstream ports with battery charging enabled when the upstream port is not connected. Under these conditions:

0 = Automatic mode battery charging features are enabled. Only battery charging DCP and custom BC (divider mode) is enabled.

1 = Automatic mode is disabled; only battery charging DCP and CDP mode is supported.

Note: When the upstream port is connected, battery charging CDP mode is supported on all ports when this field is one.

This bit is read only unless the customBCfeatures bit is set to 1. Otherwise the value of this bit reflects the value of the OTP ROM AutoModeEnz bit.


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8.6.1.12 UUID Registers (offset = 10h to 1Fh)

Figure 14. Register Offset 10h to 1Fh

7

X

R

6

X

R

5

X

R

4

X

R


3

X

R

2

X

R

1

X

R

TUSB4020BI


0

X

R

Bit

7:0

Field Name Access

uuidByte[n] RO

Table 15. Bit Descriptions – UUID Byte N Register


UUID byte N. The UUID returned in the Container ID descriptor. The value of this register is provided by the device and is meets the UUID requirements of Internet Engineering

Task Force (IETF) RFC 4122 A UUID URN Namespace.

8.6.1.13 Language ID LSB Register (offset = 20h)


7

0

6

0

5

0

4

0

R/W R/W R/W R/W


3

1

R/W

2

0

R/W

1

0

R/W

0

1

R/W

Bit

7:0

Table 16. Bit Descriptions – Language ID LSB Register

Field Name Access Reset

langIdLsb RW

Description

Language ID least significant byte. This register contains the value returned in the

LSB of the LANGID code in string index 0. The TUSB4020BI only supports one language ID. The default value of this register is 09h representing the LSB of the

LangID 0409h indicating English United States. When customStrings is 1, this field may be overwritten by the contents of an attached EEPROM or by an SMBus host.

8.6.1.14 Language ID MSB Register (offset = 21h)


7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W


3

0

R/W

2

1

R/W

1

0

R/W

0

0

R/W

Bit

7:0

Field Name Access

Table 17. Bit Descriptions – Language ID MSB Register

Reset

langIdMsb RO/RW

Description

Language ID most significant byte. This register contains the value returned in the MSB of the LANGID code in string index 0. The TUSB4020BI only supports one language ID. The default value of this register is 04h representing the MSB of the LangID 0409h indicating

English United States.

When customStrings is 1, this field may be overwritten by the contents of an attached

EEPROM or by an SMBus host.



TUSB4020BI


21

TUSB4020BI


8.6.1.15 Serial Number String Length Register (offset = 22h)


7

0

R/W

6

0

R/W

5

0

R/W

4

1

R/W


3

1

R/W

2

0

R/W

1

0

R/W

www.ti.com

0

0

R/W

Bit

7:6

5:0

Field Name

RSVD

Table 18. Bit Descriptions – Serial Number String Length Register

Access Reset

RO serNumStringLen RO/RW

Description


Serial number string length. The string length in bytes for the serial number string. The default value is 18h indicating that a 24-byte serial number string is supported. The maximum string length is 32 bytes.

When customSernum is 1, this field may be overwritten by the contents of an attached


When the field is non-zero, a serial number string of serNumbStringLen bytes is returned at string index 1 from the data contained in the Serial Number String registers.

8.6.1.16 Manufacturer String Length Register (offset = 23h)


7

0

R

6

0

R/W

5

0

R/W

4

0

R/W


3

0

R/W

2

0

R/W

1

0

R/W

0

0

R/W

Bit

7

6:0

Field Name

RSVD

Bit Descriptions – Manufacturer String Length Register

Access Reset Description

RO mfgStringLen RO/RW


Manufacturer string length. The string length in bytes for the manufacturer string. The default value is 0, indicating that a manufacturer string is not provided. The maximum string length is

64 bytes.



When the field is non-zero, a manufacturer string of mfgStringLen bytes is returned at string index 3 from the data contained in the Manufacturer String registers.

8.6.1.17 Product String Length Register (offset = 24h)


7

0

R

6

0

R/W

5

0

R/W

4

0

R/W


3

0

R/W

2

0

R/W

1

0

R/W

0

0

R/W

Bit

7

6:0

Field Name

RSVD

Bit Descriptions – Product String Length Register

Access Reset Description

RO prodStringLen RO/RW


Product string length. The string length in bytes for the product string. The default value is

0, indicating that a product string is not provided. The maximum string length is 64 bytes.



When the field is non-zero, a product string of prodStringLen bytes is returned at string index 2 from the data contained in the Product String registers.

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8.6.1.18 Serial Number Registers (offset = 30h to 4Fh)


7

X

R/W

6

X

R/W

5 x

R/W

4 x

R/W


3 x

R/W

2 x

R/W

1 x

R/W

TUSB4020BI


0 x

R/W

Bit Field Name Access

7:0 serialNumber[n] RO/RW

Table 19. Bit Descriptions – Serial Number Registers


Serial Number byte N. The serial number returned in the Serial Number string descriptor at string index 1. The default value of these registers is set by TI. When customSernum is

1, these registers may be overwritten by EEPROM contents or by an SMBus host.

8.6.1.19 Manufacturer String Registers (offset = 50h to 8Fh)


7

0

6

0

5

0

4

0

R/W R/W R/W R/W


3

0

R/W

2

0

R/W

1

0

R/W

0

0

R/W

Bit Field Name

Table 20. Bit Descriptions – Manufacturer String Registers

Access Reset

7:0 mfgStringByte[n] RO/RW

Description

Manufacturer string byte N. These registers provide the string values returned for string index 3 when mfgStringLen is greater than 0. The number of bytes returned in the string is equal to mfgStringLen.

The programmed data should be in UNICODE UTF-16LE encodings as defined by The

Unicode Standard, Worldwide Character Encoding, Version 5.0.

8.6.1.20 Product String Registers (offset = 90h to CFh)

Figure 22. Register Offset 90h to CFh

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W


3

0

R/W

2

0

R/W

1

0

R/W

0

0

R/W

Bit

7:0

Field Name

prodStringByte[n]

Table 21. Bit Descriptions – Product String Byte N Register

Access Reset

RW

Description

Product string byte N. These registers provide the string values returned for string index 2 when prodStringLen is greater than 0. The number of bytes returned in the string is equal to prodStringLen.

The programmed data should be in UNICODE UTF-16LE encodings as defined by

The Unicode Standard, Worldwide Character Encoding, Version 5.0.



TUSB4020BI


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8.6.1.21 Additional Feature Configuration Register (offset = F0h)

Figure 23. Register Offset F0h

7

0

R

6

0

R/W

5

0

R/W

4

0

R/W


3

0

R/W

2

0

R/W

1

0

R/W

www.ti.com

0

0

R/W

Bit

7:1

0

Field Name

RSVD

RSVD

Table 22. Bit Descriptions – Additional Feature Configuration Register

Access Reset

RO

Description


Reserved

RW

This bit is loaded at the deassertion of reset with the value of the SCL/SMBCLK terminal.

8.6.1.22 Charging Port Control Register (offset = F2h)


7

0

R

6

0

R

5

0

R

4

0

R


3

0

R/W

2

0

R/W

1

0

R/W

0

0

R/W

Bit

7:4

3:1

0

Table 23. Bit Descriptions – Charging Port Control Register

Field Name Access Reset

RSVD RO pwronTime

RSVD

RW

RW

Description


Power-On Delay Time. When dsportEcrEn is set, this field sets the delay time from the removal disable of PWRCTL to the enable of PWRCTL when transitioning battery charging modes. For example, when disabling the power on a transition from custom charging mode to Dedicated Charging Port Mode. The nominal timing is defined as follows:

TPWRON_EN = (pwronTime + 1) × 200 ms (1)

These registers may be overwritten by EEPROM contents or by an SMBus host.


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8.6.1.23 Device Status and Command Register (offset = F8h)


7

0

R

6

0

R

5

0

R

4

0

R


3

0

R

2

0

R

1

0

RSU

TUSB4020BI


0

0

RCU

Bit

7:2

1

0

Field Name

RSVD smbusRst cfgActive

Table 24. Bit Descriptions – Device Status and Command Register

Access

R

RSU

RCU



SMBus interface reset. This bit loads the registers back to their GRSTz values.

This bit is set by writing a 1 and is cleared by hardware on completion of the reset. A write of 0 has no effect.

Configuration active. This bit indicates that configuration of the TUSB4020BI is currently active. The bit is set by hardware when the device enters the I

2

C or SMBus mode. The

TUSB4020BI will not connect on the upstream port while this bit is 1.

When in the SMBus mode, this bit must be cleared by the SMBus host to exit the configuration mode and allow the upstream port to connect.

The bit is cleared by a writing 1. A write of 0 has no effect.



TUSB4020BI


25

TUSB4020BI


9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

www.ti.com

9.1 Application Information

The TUSB4020BI is a two-port USB 2.0 hub. It provides USB high-speed/full-speed connections on the upstream port and provides USB high-speed, full-speed, or low-speed connections on the downstream port. The

TUSB4020BI can be used in any application that needs additional USB compliant ports. For example, a specific notebook may only have two downstream USB ports. By using the TUSB4020BI, the notebook can increase the downstream port count to three.

DC

PWR

USB

Type B

Connector

US Port

TUSB4020BI

USB

PWR

SWITCH

DS Port 1

USB Type A

Connector

DS Port 2

USB Type A

Connector

Figure 26. Discrete USB Hub Product

9.1.1 Crystal Requirements

The crystal must be fundamental mode with load capacitance of 12 to 24 pF and frequency stability rating of

±100 PPM or better. To ensure proper startup oscillation condition, TI recommends a maximum crystal equivalent series resistance (ESR) of 50 Ω. A parallel load capacitor should be used if a crystal source is used.

The exact load capacitance value used depends on the crystal vendor. Refer to application note Selection and

Specification of Crystals for Texas Instruments USB 2.0 Devices ( SLLA122 ) for details on how to determine the load capacitance value.

26



TUSB4020BI


www.ti.com

TUSB4020BI


Application Information (continued)

9.1.2 Input Clock Requirements

When using an external clock source such as an oscillator, the reference clock should have a ±100 PPM or better frequency stability and have less than 50-ps absolute peak-to-peak jitter. XI should be tied to the 1.8-V clock source and XO should be left floating.

9.2 Typical Applications

A common application for the TUSB4020BI is as a self-powered standalone USB hub product. The product is powered by an external 5-V DC power adapter. In this application using a USB cable, TUSB4020BI device’s upstream port is plugged into a USB host controller. The downstream ports of the TUSB4020BI are exposed to users for connecting USB hard drives, camera, flash drive, and so forth.

9.2.1 Upstream Port Implementation

Figure 27. Upstream Port Implementation Schematic

9.2.1.1 Design Requirements

Table 25. Input Parameters

VDD supply

VDD33 supply

DESIGN PARAMETER

Upstream port USB support (HS, FS)

Downstream port 1 USB support (HS, FS, LS)

Downstream port 2 USB support (HS, FS, LS)

Number of removable downstream ports

Number of non-removable downstream ports

Full power management of downstream ports

Individual control of downstream port power switch

Power switch enable polarity

Battery charge support for downstream port 1

Battery charge support for downstream port 2

I

2

C EEPROM support

24-MHz clock source

EXAMPLE VALUE

1.1 V

3.3 V

HS, FS

HS, FS, LS

HS, FS, LS

2

0

Yes (FULLPWRMGMTZ = 0)

Yes (GANGED = 0)

Active high (PWRCTL_POL = 0)

Yes

Yes

No

Crystal



TUSB4020BI


27

TUSB4020BI


www.ti.com

9.2.1.2 Detailed Design Procedure

The upstream of the TUSB4020BI is connected to a USB2 type B connector. This particular example has

GANGED terminal and FULLPWRMGMTZ terminal pulled low, which results in individual power support each downstream port. The VBUS signal from the USB2 type B connector is fed through a voltage divider. The purpose of the voltage divider is to make sure the level meets USB_VBUS input requirements.

9.2.1.3 Application Curves

Figure 28. HighSpeed TX Eye for Downstream Port 1 Figure 29. HighSpeed TX Eye for Downstream Port 2

28



TUSB4020BI


www.ti.com

TUSB4020BI


9.2.2 Downstream Port 1 Implementation

The downstream port 1 of the TUSB4020BI is connected to a USB2 type A connector. With BATEN1 terminal pulled up, battery charge support is enabled for port 1. If battery charge support is not needed, then the pullup resistor on BATEN1 should be uninstalled. The PWRCTL_POL is pulled-down, which results in active-high power enable (PWRCTL1 and PWRCTL2) for a USB VBUS power switch.

Figure 30. Downstream Port 1 Implementation Schematic

9.2.3 Downstream Port 2 Implementation

The downstream port 2 of the TUSB4020BI is connected to a USB2 type A connector. With BATEN2 terminal pulled up, battery charge support is enabled for port 2. If battery charge support is not needed, then the pullup resistor on BATEN2 should be uninstalled.

Figure 31. Downstream Port 2 Implementation Schematic



TUSB4020BI


29

TUSB4020BI


www.ti.com

9.2.4 VBUS Power Switch Implementation

This particular example uses the TI TPS2561 dual-channel precision adjustable current-limited power switch. For details on this power switch or other power switches available from TI, refer to www.ti.com

.

Figure 32. Power Switch Implementation Schematic

30



TUSB4020BI


www.ti.com

9.2.5 Clock, Reset, and Miscellaneous

TUSB4020BI


Figure 33. Clock, Reset, and Miscellaneous Schematic



TUSB4020BI


31

TUSB4020BI


9.2.6 Power Implementation

Figure 34. Power Implementation Schematic www.ti.com

32



TUSB4020BI


www.ti.com

10 Power Supply Recommendations

TUSB4020BI


10.1 Power Supply

V

DD should be implemented as a single power plane, as should V

DD33

.

• The V

DD terminals of the TUSB4020BI supply 1.1-V (nominal) power to the core of the TUSB4020BI. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.

• The DC resistance of the ferrite bead on the core power rail can affect the voltage provided to the device due to the high current draw on the power rail. The output of the core voltage regulator may need to be adjusted to account for this or a ferrite bead with low DC resistance (less than 0.05

Ω) can be selected.

• The V

DD33 terminals of the TUSB4020BI supply 3.3-V power rail to the I/O of the TUSB4020BI. This power rail can be isolated from all other power rails by a ferrite bead to reduce noise.

• All power rails require a 10-µF capacitor or 1-µF capacitors for stability and noise immunity. These bulk capacitors can be placed anywhere on the power rail. The smaller decoupling capacitors should be placed as close to the TUSB4020BI power pins as possible with an optimal grouping of two of differing values per pin.

10.2 Downstream Port Power

• The downstream port power, VBUS, must be supplied by a source capable of supplying 5 V and at least

500 mA per port. Downstream port power switches can be controlled by the TUSB4020BI signals. It is possible to leave the downstream port power always enabled.

• Each downstream port’s VBUS requires a large bulk low-ESR capacitor of 22 µF or larger to limit in-rush current.

• TI recommends ferrite beads on the VBUS pins of the downstream USB port connections for both ESD and

EMI reasons. A 0.1-µF capacitor on the USB connector side of the ferrite provides a low-impedance path to ground for fast rise time ESD current that might have coupled onto the VBUS trace from the cable.

10.3 Ground

TI recommends to use only one board ground plane in the design. This provides the best image plane for signal traces running above the plane. The thermal pad of the TUSB4020BI and any of the voltage regulators should be connected to this plane with vias. An earth or chassis ground is only implemented near the USB port connectors on a different plane for EMI and ESD purposes.



TUSB4020BI


33

TUSB4020BI


11 Layout

www.ti.com

11.1 Layout Guidelines

11.1.1 Placement

1. A 9.53-k Ω ±1% resistor connected to terminal USB_R1 should be placed as close as possible to the

TUSB4020BI.

2. A 0.1-µF capacitor should be placed as close as possible on each V

DD and V

DD33 power pin.

3. The ESD and EMI protection devices (if used) should also be placed as possible to the USB connector.

4. If a crystal is used, it must be placed as close as possible to the TUSB4020BI device’s XI and XO terminals.

5. Place voltage regulators as far away as possible from the TUSB4020BI, crystal, and differential pairs.

6. In general, the large bulk capacitors associated with each power rail should be placed as close as possible to the voltage regulators.

11.1.2 Package Specific

1. The TUSB4020BI package has a 0.5-mm pin pitch.

2. The TUSB4020BI package has a 3.6-mm × 3.6-mm thermal pad. This thermal pad must be connected to ground through a system of vias.

3. All vias under device, except for those connected to thermal pad, should be solder masked to avoid potential issues with thermal pad layouts.

11.1.3 Differential Pairs

This section describes the layout recommendations for all of the TUSB4020BI differential pairs: USB_DP_XX,

USB_DM_XX.

• Must be designed with a differential impedance of 90 Ω ±10%.

• To minimize crosstalk, TI recommends to keep high-speed signals away from each other. Each pair should be separated by at least 5× the signal trace width. Separating with ground as depicted in the layout example also helps minimize crosstalk.

• Route all differential pairs on the same layer adjacent to a solid ground plane.

• Do not route differential pairs over any plane split.

• Adding test points causes impedance discontinuity, and therefore, negatively impacts signal performance. If test points are used, they should be placed in series and symmetrically. They must not be placed in a manner that causes stub on the differential pair.

• Avoid 90° turns in trace. The use of bends in differential traces should be kept to a minimum. When bends are used, the number of left and right bends should be as equal as possible and the angle of the bend should be ≥135°. Taking this action minimizes any length mismatch caused by the bends, and therefore, minimizes the impact bends have on EMI.

• Minimize the trace lengths of the differential pair traces. Eight inches is the maximum recommended trace length for USB 2.0 differential-pair signals. Longer trace lengths require very careful routing to assure proper signal integrity.

• Match the etch lengths of the differential pair traces (that is DP and DM). The USB 2.0 differential pairs should not exceed 50-mils relative trace length difference.

• Minimize the use of vias in the differential-pair paths as much as possible. If this is not practical, ensure that the same via type and placement are used for both signals in a pair. Any vias used should be placed as close as possible to the TUSB4020BI device.

• Do not place power fuses across the differential-pair traces.

34



TUSB4020BI


www.ti.com

TUSB4020BI


11.2 Layout Example

Figure 35

shows an example layout of the upstream port to a USB3 Type B connector. The routing to a USB2

Type B connector will be similar.

Figure 35. Upstream Port



TUSB4020BI


35

TUSB4020BI


www.ti.com

Layout Example (continued)

Figure 36

shows an example layout of the Downstream Port to a USB3 Type A connector. The routing to a USB2

Type A connector will be similar.

Figure 36. Downstream Port

Figure 37. Thermal Pad

36



TUSB4020BI


www.ti.com

12 Device and Documentation Support

TUSB4020BI


12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use .

TI E2E™ Online Community

TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers.

Design Support

TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

12.2 Trademarks

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.



TUSB4020BI


37

PACKAGE OPTION ADDENDUM

www.ti.com

23-Oct-2015

PACKAGING INFORMATION

Orderable Device

TUSB4020BIPHP

Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

HTQFP PHP 48 250

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU

MSL Peak Temp

(3)

Level-3-260C-168 HR

Op Temp (°C)

-40 to 85

Device Marking

(4/5)

T4020BI

TUSB4020BIPHPR ACTIVE HTQFP PHP 48 1000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

-40 to 85 T4020BI

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

23-Oct-2015 www.ti.com

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TUSB4020BI :

•

Automotive: TUSB4020BI-Q1

NOTE: Qualified Version Definitions:

•

Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

23-Oct-2015

*All dimensions are nominal

Device

TUSB4020BIPHPR

Package

Type

Package

Drawing

HTQFP PHP

Pins

48

SPQ

1000

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

16.4

A0

(mm)

9.6

B0

(mm)

9.6

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

1.5

12.0

16.0

Q2

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

23-Oct-2015

*All dimensions are nominal

Device

TUSB4020BIPHPR

Package Type Package Drawing Pins

HTQFP PHP 48

SPQ

1000

Length (mm) Width (mm) Height (mm)

336.6

336.6

31.8

Pack Materials-Page 2

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