LTC4007-1 4A, High Efficiency, Li-Ion Battery Charger DESCRIPTIO

LTC4007-1 4A, High Efficiency, Li-Ion Battery Charger DESCRIPTIO
LTC4007-1
4A, High Efficiency,
Li-Ion Battery Charger
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FEATURES
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DESCRIPTIO
Charger Controller for 3- or 4-Cell
Lithium-Ion Batteries
High Conversion Efficiency: Up to 96%
Output Currents Exceeding 4A
±0.8% Charging Voltage Accuracy
Built-In Charge Termination for Li-Ion Batteries
AC Adapter Current Limiting Maximizes Charge Rate*
Thermistor Input for Temperature Qualified Charging
Wide Input Voltage Range: 6V to 28V
0.5V Dropout Voltage; Maximum Duty Cycle: 98%
Programmable Charge Current: ±4% Accuracy
Indicator Outputs for Charging, C/10 Current
Detection, AC Adapter Present, Low Battery, Input
Current Limiting and Faults
Charging Current Monitor Output
Available in a 24-Pin 4mm × 5mm QFN Package
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APPLICATIO S
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Notebook Computers
Portable Instruments
Battery-Backup Systems
Li-Ion Chargers
The output float voltage is pin programmed for cell count
(3 cells or 4 cells) and chemistry (4.2V/4.1V). A timer,
programmed by an external resistor, sets the total charge
time.
The LTC4007-1 includes a thermistor input, which suspends charging if an unsafe temperature condition is detected. If the cell voltage is less than 3.25V, a low-battery
indicator asserts and can be used to program a trickle charge
current to safely charge depleted batteries. The FAULT pin
is also asserted and charging terminates if the low-battery
condition persists for more than 1/4 of the total charge time.
, LTC and LT are registered trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
*Protected by U.S. Patents including 5723970.
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The LTC®4007-1 is a constant-current/constant-voltage
charger controller for 3- or 4-cell lithium-ion batteries.
The PWM controller uses a synchronous, quasi-constant
frequency, constant off-time architecture that will not
generate audible noise even when using ceramic capacitors. Charging current is programmable to ±4% accuracy
using a programming resistor. Charging current can also
be monitored as a voltage across the programming
resistor.
TYPICAL APPLICATIO
12.6V, 4A Li-Ion Battery Charger
INPUT SWITCH
DCIN
0V TO 28V
AUTO
RESTART
LOW BATTERY
THRESHOLD (Per Cell)
(4.2V/4.1V)
LTC4007-1
NO
3.25V/3.173V
LTC4007
YES
2.5V/2.44V
0.1µF
4.99k
VLOGIC
100k
100k
100k
LOBAT
3C4C
DCIN
CHEM
INFET
LOBAT
CLP
ICL
ACP
TGATE
SHDN
SHDN
BGATE
FAULT
FAULT
PGND
CHG
CHG
FLAG
32.4k
NTC
THERMISTOR
10k
NTC
RT
0.47µF
309k
0.025Ω
SYSTEM
LOAD
LTC4007-1 CLN
ICL
ACP
FLAG
15nF
PART
10µH
Q2
0.025Ω
20µF
Li-Ion
BATTERY
CSP
3.01k
BAT
3.01k
PROG
CHARGING
CURRENT
MONITOR
ITH
GND
TIMING RESISTOR
(~2 HOURS)
20µF
Q1
6.04k
0.12µF
0.0047µF
Q1: Si4431BDY
Q2: FDC645N
26.7k
40071 TA01
40071f
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LTC4007-1
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PACKAGE/ORDER INFORMATION
BGATE
INFET
SHDN
DCIN
CHG
TOP VIEW
24 23 22 21 20
ACP 1
19 NC
RT 2
18 PGND
FAULT 3
17 TGATE
25
GND 4
16 CLN
3C4C 5
15 CLP
LOBAT 6
14 FLAG
NTC 7
13 CHEM
BAT
CSP
9 10 11 12
ICL
8
ITH
W W
W
Voltage from DCIN, CLP, CLN to GND ....... + 32V/– 0.3V
PGND with Respect to GND ................................. ±0.3V
CSP, BAT to GND ....................................... +28V/– 0.3V
CHEM, 3C4C, RT to GND .............................. +7V/– 0.3V
NTC ............................................................ +10V/– 0.3V
ACP, SHDN, CHG, FLAG,
FAULT, LOBAT, ICL .............................................. + 32V/– 0.3V
CLP to CLN ........................................................... ±0.5V
Operating Ambient Temperature Range
(Note 4) ............................................. – 40°C to 85°C
Operating Junction Temperature ......... – 40°C to 125°C
Storage Temperature Range ................. – 65°C to 125°C
PROG
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(Note 1)
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ABSOLUTE MAXIMUM RATINGS
UFD PACKAGE
24-LEAD (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 90°C/W
EXPOSED PAD (PIN 25), GND AND PGND SHOULD BE CONNECTED
TOGETHER WITH A LOW OHMIC CONNECTION.
ORDER PART NUMBER
UFD PART MARKING
40071
LTC4007EUFD-1
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range (Note 4), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
DCIN Operating Range
IQ
Operating Current
Sum of Current from CLP, CLN , DCIN
VTOL
Charge Voltage Accuracy
Nominal Values: 12.3V, 12.6V, 16.4V, 16.8V
●
(Note 2)
ITOL
Charge Current Accuracy (Note 3)
VCSP – VBAT Target = 100mV
3
MAX
UNITS
28
V
5
mA
–0.8
–1.0
0.8
1.0
%
%
●
–4
–5
4
5
%
%
%
%
60
ms
20
35
10
µA
µA
±60
±35
VBAT < 6V, VCSP – VBAT Target = 10mV
6V ≤ VBAT ≤ VLOBAT, VCSP – VBAT
Target = 10mV
TSAMPLE
TYP
6
Measured Sample Time
RRT = 1190k
●
42
Battery Leakage Current
DCIN = 0V
SHDN = 3V
●
●
–10
DCIN Rising, VBAT = 0
●
4.2
4.7
5.5
V
●
1
1.6
2.5
V
Shutdown
UVLO
Undervoltage Lockout Threshold
Shutdown Threshold at SHDN
SHDN Pin Current
Operating Current in Shutdown
µA
– 10
VSHDN = 0V, Sum of Current from CLP,
CLN, DCIN
2
3
mA
40071f
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LTC4007-1
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range (Note 4), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Current Sense Amplifier, CA1
Input Bias Current Into BAT Pin
µA
11.67
CMSL
CA1/I1 Input Common Mode Low
●
CMSH
CA1/I1 Input Common Mode High
●
0
V
VCLN – 0.2
V
Current Comparators ICMP and IREV
ITMAX
Maximum Current Sense Threshold (VCSP – VBAT)
ITREV
Reverse Current Threshold (VCSP – VBAT)
VITH = 2.5V
●
140
165
200
–30
mV
mV
Current Sense Amplifier, CA2
Transconductance
1
mmho
Source Current
Measured at ITH, VITH = 1.4V
– 40
µA
Sink Current
Measured at ITH, VITH = 1.4V
40
µA
Current Limit Amplifier
Transconductance
VCLP
Current Limit Threshold
ICLP
CLP Input Bias Current
1.4
●
93
100
mmho
107
100
mV
nA
Voltage Error Amplifier, EA
Transconductance
Sink Current
OVSD
Measured at ITH, VITH = 1.4V
Overvoltage Shutdown Threshold as a Percent
of Programmed Charger Voltage
1
mmho
36
µA
●
102
107
110
%
●
0
0.17
0.25
V
25
50
Input P-Channel FET Driver (INFET)
DCIN Detection Threshold (VDCIN – VCLN)
DCIN Voltage Ramping Up
from VCLN – 0.1V
●
Forward Regulation Voltage (VDCIN – VCLN)
DCIN Voltage Ramping Down
●
– 60
– 25
INFET “On” Clamping Voltage (VDCIN – VINFET)
IINFET = 1µA
●
5
5.8
INFET “Off” Clamping Voltage (VDCIN – VINFET)
IINFET = – 25µA
Reverse Voltage Turn-Off Voltage (VDCIN – VCLN)
mV
mV
6.5
V
0.25
V
Thermistor
NTCVR
Reference Voltage During Sample Time
4.5
V
High Threshold
VNTC Rising
●
NTCVR
• 0.48
NTCVR
• 0.5
NTCVR
• 0.52
V
Low Threshold
VNTC Falling
●
NTCVR
• 0.115
NTCVR
• 0.125
NTCVR
• 0.135
V
Thermistor Disable Current
VNTC ≤ 10V
10
µA
Indicator Outputs (ACP, CHG, FLAG, LOBAT, ICL, FAULT
C10TOL
FLAG (C/10) Accuracy
Voltage Falling at PROG
●
0.375
0.397
0.420
V
LBTOL
LOBAT Threshold Accuracy
3C4C = 0V, CHEM = 0V
3C4C = 0V, CHEM = Open
3C4C = Open, CHEM = 0V
3C4C = Open, CHEM = Open
●
●
●
●
9.233
9.458
12.311
12.610
9.519
9.750
12.692
13.000
9.805
10.043
13.074
13.390
V
V
V
V
83
93
1O5
ICL Threshold Accuracy
mV
40071f
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LTC4007-1
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range (Note 4), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT = 12V unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
VOL
Low Logic Level of ACP, CHG, FLAG, LOBAT,
ICL, FAULT
IOL = 100µA
●
VOH
High Logic Level of CHG, LOBAT, ICL
IOH = –1µA
●
IOFF
Off State Leakage Current of ACP, FLAG, FAULT
VOH = 3V
IPO
Pull-Up Current on CHG, LOBAT, ICL
V = 0V
TYP
MAX
UNITS
0.5
V
2.7
V
–1
1
Timer Defeat Threshold at CHG
µA
µA
–10
1
V
Programming Inputs (CHEM and 3C4C)
VIH
High Logic Level
●
VIL
Low Logic Level
●
IPI
Pull-Up Current
3.3
1
V = 0V
V
V
µA
– 14
Oscillator
fOSC
Regulator Switching Frequency
fMIN
Regulator Switching Frequency in Drop Out
DCMAX
Regulator Maximum Duty Cycle
255
300
345
kHz
Duty Cycle ≥ 98%
20
25
kHz
VCSP = VBAT
98
99
%
Gate Drivers (TGATE, BGATE)
VTGATE High (VCLN – VTGATE)
ITGATE = –1mA
50
mV
VBGATE High
CLOAD = 3000pF
4.5
5.6
10
V
VTGATE Low (VCLN – VTGATE)
CLOAD = 3000pF
4.5
5.6
10
V
VBGATE Low
IBGATE = 1mA
50
mV
TGTR
TGTF
TGATE Transition Time
TGATE Rise Time
TGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
50
50
110
100
ns
ns
BGTR
BGTF
BGATE Transition Time
BGATE Rise Time
BGATE Fall Time
CLOAD = 3000pF, 10% to 90%
CLOAD = 3000pF, 10% to 90%
40
40
90
80
ns
ns
VTGATE at Shutdown (VCLN – VTGATE)
ITGATE = –1µA, DCIN = 0V, CLN = 12V
100
mV
VBGATE at Shutdown
IBGATE = 1µA, DCIN = 0V, CLN = 12V
100
mV
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: See Test Circuit.
Note 3: Does not include tolerance of current sense resistor or current
programming resistor.
Note 4: The LTC4007E-1 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
40071f
4
LTC4007-1
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TYPICAL PERFOR A CE CHARACTERISTICS
INFET Response Time to
Reverse Current
VOUT vs IOUT
Line Regulation
Vgs OF PFET (2V/DIV)
Vgs = 0
0.10
0
0.05
–0.5
OUTPUT VOLTAGE ERROR (%)
0
Vs OF PFET (5V/DIV)
VOUT ERROR (%)
–0.05
C3C4 = OPEN
–0.10
–0.15
–0.20
C3C4 = GND
–0.25
–0.30
Vs = 0V
–0.35
Id (REVERSE) OF
PFET (5A/DIV)
–0.45
–2.0
–2.5
–3.0
–3.5
–4.0
3C4C = GND
3C4C = OPEN
–5.0
13
1.25µs/DIV
–1.5
–4.5
–0.40
Id = 0A
–1.0
15
TEST PERFORMED ON DEMOBOARD
VCHARGE = 12.6V
VIN = 15VDC
CHARGER = ON
PFET = 1/2 Si4925DY
ICHARGE = <10mA
40071 G01
17
19
21 23 25
VDCIN (V)
27
29
31
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
OUTPUT CURRENT (A)
40071 G02
Disconnect/Reconnect Battery
(Load Dump)
PWM Frequency vs Duty Cycle
40071 G03
1A Load Step (Battery Present)
350
3A STEP
CHARGER CURRENT (1A/DIV)
250
1A STEP
1A STEP
VFLOAT
1V/DIV
200
150
OUTPUT VOLTAGE (500mV/DIV)
PROGRAMMED CURRENT = 10%
100
3A STEP
LOAD
STATE
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
DUTY CYCLE (VOUT/VIN)
40071 G04
RECONNECT
DISCONNECT
DCIN = 15V
DCIN = 20V
DCIN = 24V
50
LOAD CURRENT = 1A, 2A, 3A
DCIN = 20V
VFLOAT = 12.6V (3C4C = GND, CHEM = OPEN)
DCIN = 20V
VFLOAT = 12.6V
40071 G06
40071 G05
1A Load Step
(Battery Not Present)
Battery Leakage Current vs
Battery Voltage
40
CHARGER CURRENT (500mA/DIV)
OUTPUT VOLTAGE (5V/DIV)
BATTERY LEAKAGE CURRENT (µA)
PWM FREQUENCY (kHz)
300
VDCIN = 0V
35
30
25
20
15
10
5
0
0
DCIN = 20V
VFLOAT = 12.6V
40071 G07
5
10
15
20
BATTERY VOLTAGE (V)
25
30
40071 G08
40071f
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LTC4007-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Efficiency at 19VDC VIN
Efficiency at 12.6V with 15VDC VIN
100
100
16.8V
95
95
EFFICIENCY (%)
EFFICIENCY (%)
12.6V
90
85
80
90
85
80
75
75
0.50
1.00
1.50
2.00
2.50
CHARGE CURRENT (A)
3.00
40071 G10
0.50
1.00
1.50
2.00
2.50
CHARGE CURRENT (A)
3.00
40071 G11
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PI FU CTIO S
ACP(Pin 1): Open-Drain output to indicate if the AC
adapter voltage is adequate for charging. This pin is pulled
low by an internal N-channel MOSFET if DCIN is below
BAT. A pull-up resistor is required. The pin is capable of
sinking at least 100µA.
RT (Pin 2): Timer Resistor. The timer period is set by
placing a resistor, RRT , to GND. This resistor is always
required.
The timer period is tTIMER = (1hour • RRT/154K).
If this resistor is not present, the charger will not start.
FAULT (Pin 3): Active low open-drain output that indicates charger operation has stopped due to a low-battery
conditioning error, or that charger operation is suspended
due to the thermistor exceeding allowed values. A pull-up
resistor is required if this function is used. The pin is
capable of sinking at least 100µA.
GND (Pin 4): Ground for Low Power Circuitry.
3C4C (Pin 5): Select 3-cell or 4-cell float voltage by
connecting this pin to GND or open, respectively. Internal
14µA pull-up to 5.3V. This pin can also be driven with
open-collector/drain logic levels. High: 4 cell. Low: 3 cell.
LOBAT (Pin 6): Low-Battery Indicator. Active low digital
output. Internal 10µA pull-up to 3.5V. If the battery
voltage is below 3.25V/cell (or 3.173V/cell for 4.1V chemistry batteries) LOBAT will be low. The pin is capable of
sinking at least 100µA. If VLOGIC is greater than 3.3V, add
an external pull-up.
NTC (Pin 7): A thermistor network is connected from NTC
to GND. This pin determines if the battery temperature is
safe for charging. The charger and timer are suspended
and the FAULT pin is driven low if the thermistor indicates
a temperature that is unsafe for charging. The thermistor
function may be disabled with a 300k to 500k resistor from
DCIN to NTC.
ITH (Pin 8): Control Signal of the Inner Loop of the Current
Mode PWM. Higher ITH voltage corresponds to higher
charging current in normal operation. A 6k resistor, in
series with a capacitor of at least 0.1µF to GND provides
loop compensation. Typical full-scale output current is
40µA. Nominal voltage range for this pin is 0V to 3V.
40071f
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LTC4007-1
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PI FU CTIO S
PROG (Pin 9): Current Programming/Monitoring Input/
Output. An external resistor to GND programs the peak
charging current in conjunction with the current sensing
resistor. The voltage at this pin provides a linear indication
of charging current. Peak current is equivalent to 1.19V.
Zero current is approximately 0.3V. A capacitor from
PROG to ground is required to filter higher frequency
components. The maximum resistance to ground is 100k.
Values higher than 100k can cause the charger to shut
down.
ICL (Pin 10): Input Current Limit Indicator. Active low
digital output. Internal 10µA pull-up to 3.5V. Pulled low if
the charger current is being reduced by the input current
limiting function. The pin is capable of sinking at least
100µA. If VLOGIC is greater than 3.3V, add an external
pull-up.
CSP (Pin 11): Current Amplifier CA1 Input. The CSP and
BAT pins measure the voltage across the sense resistor,
RSENSE, to provide the instantaneous current signals required for both peak and average current mode operation.
BAT (Pin 12): Battery Sense Input and the Negative
Reference for the Current Sense Resistor. A precision
internal resistor divider sets the final float potential on this
pin. The resistor divider is disconnected during shutdown.
CHEM (Pin 13):Select 4.1V or 4.2V cell chemistry by
connecting the pin to GND or open, respectively. Internal
14µA pull-up to 5.3V. Can also be driven with opencollector/drain logic levels.
FLAG (Pin 14): Active low open-drain output that indicates when charging current has declined to 10% of
maximum programmed current. A pull-up resistor is
required if this function is used. The pin is capable of
sinking at least 100µA.
CLP (Pin 15): Positive input to the supply current limiting
amplifier, CL1. The threshold is set at 100mV above the
voltage at the CLN pin. When used to limit supply current,
a filter is needed to filter out the switching noise. If no
current limit function is desired, connect this pin to CLN.
CLN (Pin 16): Negative Reference for the Input Current
Limit Amplifier, CL1. This pin also serves as the power
supply for the IC. A 10µF to 22µF bypass capacitor should
be connected as close as possible to this pin.
TGATE (Pin 17): Drives the top external P-channel MOSFET
of the battery charger buck converter.
PGND (Pin 18): High Current Ground Return for the BGATE
Driver.
NC (Pin 19): No Connect.
BGATE (Pin 20): Drives the bottom external N-channel
MOSFET of the battery charger buck converter.
INFET (Pin 21): Drives the Gate of the External Input PFET.
SHDN (Pin 22): Charger is shut down and timer is reset
when this pin is HIGH. Internal 10µA pull-up to 3.5V. This
pin can also be used to reset the charger by applying a
positive pulse that is a minimum of 0.1µs long.
DCIN (Pin 23): External DC Power Source Input. Bypass
this pin with at least 0.01µF. See Applications Information.
CHG (Pin 24): Charge Status Output. When the battery is
being charged, the CHG pin is pulled low by an internal
N-channel MOSFET. Internal 10µA pull-up to 3.5V. If
VLOGIC is greater than 3.3V, add an external pull-up. The
timer function can be defeated by forcing this pin below 1V
(or connecting it to GND).
Exposed Pad (Pin 25): The exposed pad, GND and PGND
should be connected together with a low ohmic connection.
40071f
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LTC4007-1
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BLOCK DIAGRA
0.1µF
VIN
DCIN
INFET
Q3
23
5.8V
21
CLN
24 CHG
ACP 1
TIMER/CONTROLLER
SHDN 22
OSCILLATOR
2
THERMISTOR
7
RRT
RT
FAULT 3
TBAD
NTC
32.4k
10k
NTC
0.47µF
–
35mV
+
4
11.67µA
–
GND
397mV
C/10
FLAG 14
3C4C 5
MUX
+
CHEM 13
12
BAT
3.01k
–
+
RSENSE
CA1
LOBAT 6
+
–
11
CSP
20µF
3.01k
921mV
+
1.19V
gm = 1m
Ω
EA
5k
RCL
CLP
CLN
–
15
15nF
Ω
9k
CL1
100mV
16
gm = 1.4m
–
gm = 1m
+
Ω
–
CA2
ICL 10
+
DCIN
OSCILLATOR
WATCHDOG
DETECT tOFF
20µF
1.19V
8
ITH
6K
+
OV
1.28V
÷5
0.12µF
BUFFERED ITH
–
CLN
17
Q
S
R
Q2
BGATE
PGND
20
PWM
LOGIC
ICMP
–+
–
TGATE
+
Q1
CHARGE
18
IREV
–
17mV
L1
+
9
PROG
0.0047µF
RPROG
26.7k
40071 BD
40071f
8
LTC4007-1
TEST CIRCUIT
LTC4007-1
13
5
CHEM
3C4C
11
VREF
+
DIVIDER/
MUX
EA
–
CSP
12
BAT
8
ITH
+
LT1055
–
0.6V
40071 TC
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OPERATIO
Overview
The LTC4007-1 is a synchronous current mode PWM
step-down (buck) switcher battery charger controller. The
charge current is programmed by the combination of a
program resistor (RPROG) from the PROG pin to ground
and a sense resistor (RSENSE) between the CSP and BAT
pins. The final float voltage is programmed to one of four
values (12.3V, 12.6V, 16.4V, 16.8V) with ±1% maximum
accuracy using pins 3C4C and CHEM. Charging begins
when the potential at the DCIN pin rises above the voltage
at BAT (and the UVLO voltage) and the SHDN pin is low; the
CHG pin is set low. At the beginning of the charge cycle, if
the cell voltage is below 3.25V (3.173V if CHEM is low), the
LOBAT pin will be low. The LOBAT indicator can be used
to reduce the charging current to a low value, typically
10% of full scale. If the cell voltage stays below 3.25V for
25% of the total charge time, the charge sequence will be
terminated immediately and the FAULT pin will be set low.
An external thermistor network is sampled at regular
intervals. If the thermistor value exceeds design limits,
charging is suspended and the FAULT pin is set low. If the
thermistor value returns to an acceptable value, charging
resumes and the FAULT pin is set high. An external resistor
on the RT pin sets the total charge time. The timer can be
defeated by forcing the CHG pin to a low voltage.
As the battery approaches the final float voltage, the
charge current will begin to decrease. When the current
drops to 10% of the full-scale charge current, an internal
C/10 comparator will indicate this condition by latching
the FLAG pin low. The charge timer is also reset to 1/4 of
the total charge time when FLAG goes low. If this condition
is caused by an input current limit condition, described
below, then the FLAG indicator will be inhibited. When a
time-out occurs, charging is terminated immediately and
the CHG pin is forced to a high impedance state. To restart
the charge cycle manually, simply remove the input voltage and reapply it, or set the SHDN pin high momentarily.
When the input voltage is not present, the charger goes
into a sleep mode, dropping battery current drain to 15µA.
This greatly reduces the current drain on the battery and
increases the standby time. The charger is inhibited any
time the SHDN pin is high.
Input FET
The input FET circuit performs two functions. It enables
the charger if the input voltage is higher than the CLN pin
and provides the logic indicator of AC present on the ACP
pin. It controls the gate of the input FET to keep a low
forward voltage drop when charging and also prevents
reverse current flow through the input FET.
If the input voltage is less than VCLN, it must go at least
170mV higher than VCLN to activate the charger. When this
occurs the ACP pin is released and pulled up with an
external load to indicate that the adapter is present. The
40071f
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Table 1. Truth Table for LTC4007-1 Operation (Supplemental)
NUMBER
1
2
3
FROM
STATE
Any
TO
STATE
MSD
MODE
Shut Down by Low
Adapter Voltage
Charger Shutdown
Shut Down by
Undervoltage Lockout
DCIN
<BAT
BATTERY
VOLTAGE
PRESENT NEXT
C/10
C/10
LATCH LATCH
0
ACP
LOW
TIMER
STATE
Reset
CHG
HIGH
OFF
OFF
HIGH
HIGH
Reset
Reset
HIGH
HIGH*
HIGH
MSD
SD
SD,
SD
CONDITION,
CHARGE
SD
CONDITION Start Conditioning a
Depleted Battery
>BAT
>BAT
and
<UVL
>BAT
<3.25V/Cell
5
CONDITION CONDITION Input Current Limited
Condition Charging
>BAT
<3.25V/Cell
6
CONDITION CONDITION Conditioning a
Depleted Battery
>BAT
<3.25V/Cell
7
CONDITION CONDITION Timer Defeated (Low
Battery Conditioning
Still Functional)
CONDITION
SD
Charger Paused Due to
Thermistor Out of Range
CONDITION
SD
Timeout in
CONDITION Mode
CONDITION
SD
Shut Down by
ACP/SHDN Pin
CONDITION CHARGE Start Normal Charging
>BAT
<3.25V/Cell
>BAT
<3.25V/Cell
10%
Programmed
Current
<10%
Programmed
Current (Note 2)
10%
Programmed
Current
10%
Programmed
Current
OFF
>BAT
<3.25V/Cell
>BAT
<3.25V/Cell
>BAT
>3.25V/Cell
Timer Defeated (Low
Battery Conditioning
Still Functional)
Top-Off Charging
>BAT
>3.25V/Cell
>BAT
>3.25V/Cell
C/10 Latch is SET
when Battery Current
Is Less than 10% of
Programmed Current
Top-Off Charging
>BAT
>3.25V/Cell
>BAT
>3.25V/Cell
Input Current
Limited Charging
Charger Paused Due to
Thermistor Out of Range
>BAT
>3.25V/Cell
>BAT
>3.25V/Cell
>BAT
>3.25V/Cell
0
OFF
0
4
8
9
10
11
12
CHARGE
CHARGE
13
CHARGE
CHARGE
14
CHARGE
CHARGE
15
CHARGE
CHARGE
16
CHARGE
CHARGE
17
CHARGE
SD
18
CHARGE
SD
19
CHARGE
SD
20
CHARGE
21
CHARGE
0
MAX
BATTERY
CURRENT
OFF
0
HIGH
Running
LOW
HIGH
Running
LOW
HIGH
Ignored
Forced
LOW
HIGH
Paused
OFF
HIGH
>T/4
OFF
Forced
LOW
HIGH
Reset
LOW
(Faulted)
HIGH
(Faulted)
HIGH
Running
HIGH
Ignored
Forced
LOW
HIGH
Running
LOW
HIGH
Reset
25µA
HIGH
Running
25µA
HIGH
Paused
Reset
OFF
Forced
LOW
HIGH
LOW or
25µA
(Faulted)
HIGH
Programmed
Current
Programmed
Current
0
1
1
Programmed
Current
Programmed
Current
Programmed
Current
<Programmed
Current (Note 2)
OFF
HIGH
>BAT
<3.25V/Cell
SD
Shut Down by
ACP/SHDN Pin
Terminated by LowBattery Fault (Note 1)
Terminates After T/4
>BAT
VFLOAT
1
OFF
HIGH
SD
Terminates After T
>BAT
VFLOAT*
0
OFF
HIGH
*Most probable condition
Note 1: If a depleted battery is inserted while the charger is in this state, the
charger must be reset to initiate charging.
Note 2: See section on “Adapter Limiting”.
LOW
>T/4 then HIGH
Reset (Faulted)
>T/4 then HIGH
Reset
>T then
HIGH
Reset
Note 3: Blank fields indicate no change, not considered, or other states impact
value.
Note 4: Battery voltage thresholds do not include comparator hysterisis.
Thresholds specify the VLH value.
40071f
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LTC4007-1: State Diagram
MASTER
SHUTDOWN
1
ANY
2
SHUTDOWN
4
5, 6, 7
3, 8,
9, 10
3, 17, 18,
19, 20, 21
CONDITION
11
CHARGE
12, 13, 14, 15, 16
gate of the input FET is driven to a voltage sufficient to keep
a low forward voltage drop from drain to source. If the
voltage between DCIN and CLN drops to less than 25mV,
the input FET is turned off slowly. If the voltage between
DCIN and CLN is ever less than – 25mV, then the input FET
is turned off in less than 10µs to prevent significant
reverse current from flowing in the input FET. In this
condition, the ACP pin is driven low and the charger is
disabled.
Battery Charger Controller
The LTC4007-1 charger controller uses a constant offtime, current mode step-down architecture. During normal operation, the top MOSFET is turned on each cycle
when the oscillator sets the SR latch and turned off when
the main current comparator ICMP resets the SR latch.
While the top MOSFET is off, the bottom MOSFET is turned
on until either the inductor current trips the current comparator IREV or the beginning of the next cycle. The
oscillator uses the equation:
tOFF =
VDCIN – VBAT
VDCIN • fOSC
40071 TBL01
to set the bottom MOSFET on time. The result is a nearly
constant switching frequency over a wide input/output
voltage range. This activity is diagrammed in Figure 1.
The peak inductor current, at which ICMP resets the SR
latch, is controlled by the voltage on ITH. ITH is in turn
controlled by several loops, depending upon the situation
at hand. The average current control loop converts the
voltage between CSP and BAT to a representative current.
Error amp CA2 compares this current against the desired
current programmed by RPROG at the PROG pin and
OFF
TGATE
ON
ON
tOFF
BGATE
OFF
TRIP POINT SET BY ITH VOLTAGE
INDUCTOR
CURRENT
40071 F01
Figure 1
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adjusts ITH until:
If the charging current decreases below 10% to 15% of
programmed current while engaged in input current limiting, BGATE will be forced low to prevent the charger from
discharging the battery. Audible noise can occur in this
mode of operation.
VREF
V
– V + 11.67µA • 3.01kΩ
= CSP BAT
RPROG
3.01kΩ
therefore,
⎛ V
⎞ 3.01kΩ
ICHARGE(MAX) = ⎜ REF – 11.67µA⎟ •
⎝ RPROG
⎠ RSENSE
The voltage at BAT is divided down by an internal resistor
divider and is used by error amp EA to decrease ITH if the
divider voltage is above the 1.19V reference. When the
charging current begins to decrease, the voltage at PROG
will decrease in direct proportion. The voltage at PROG is
then given by:
VPROG = (ICHARGE • RSENSE + 11.67µA • 3.01kΩ) •
RPROG
3.01kΩ
VPROG is plotted in Figure 2.
The amplifier CL1 monitors and limits the input current,
normally from the AC adapter to a preset level (100mV/
RCL). At input current limit, CL1 will decrease the ITH
voltage, thereby reducing charging current. The ICL indicator output will go low when this condition is detected and
the FLAG indicator will be inhibited if it is not already LOW.
1.2
1.19V
1.0
VPROG (V)
0.8
0.6
An overvoltage comparator guards against voltage transient overshoots (>7% of programmed value). In this
case, both MOSFETs are turned off until the overvoltage
condition is cleared. This feature is useful for batteries
which “load dump” themselves by opening their protection switch to perform functions such as calibration or
pulse mode charging.
PWM Watchdog Timer
There is a watchdog timer that observes the activity on the
BGATE and TGATE pins. If TGATE stops switching for
more than 40µs, the watchdog activates and turns off the
top MOSFET for about 400ns. The watchdog engages to
prevent very low frequency operation in dropout—a potential source of audible noise when using ceramic input
and output capacitors.
Charger Start-Up
When the charger is enabled, it will not begin switching
until the ITH voltage exceeds a threshold that assures
initial current will be positive. This threshold is 5% to 15%
of the maximum programmed current. After the charger
begins switching, the various loops will control the current
at a level that is higher or lower than the initial current. The
duration of this transient condition depends upon the loop
compensation, but is typically less than 100µs.
0.4
0.309V
Thermistor Detection
0.2
0
0
60
80
20
40
ICHARGE (% OF MAXIMUM CURRENT)
100
40071 F02
Figure 2. VPROG vs ICHARGE
The thermistor detection circuit is shown in Figure 3. It
requires an external resistor and capacitor in order to
function properly.
The thermistor detector performs a sample-and-hold function. An internal clock, whose frequency is determined by
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tHOLD = 10 • RRT • 17.5pF = 54µs,
the timing resistor connected to RT, keeps switch S1
closed to sample the thermistor:
for RRT = 309k
tSAMPLE = 127.5 • 20 • RRT • 17.5pF = 13.8ms,
When the tHOLD interval ends the result of the thermistor
testing is stored in the D flip-flop (DFF). If the voltage at
NTC is within the limits provided by the resistor divider
feeding the comparators, then the NOR gate output will be
low and the DFF will set TBAD to zero and charging will
continue. If the voltage at NTC is outside of the resistor
divider limits, then the DFF will set TBAD to one, the charger
will be shut down, FAULT pin is set low and the timer will
be suspended until TBAD returns to zero (see Figure 4).
for RRT = 309k
The external RC network is driven to approximately 4.5V
and settles to a final value across the thermistor of:
VRTH(FINAL) =
4.5V • RTH
RTH + R9
This voltage is stored by C7. Then the switch is opened for
a short period of time to read the voltage across the
thermistor.
LTC4007-1
R9
32.4k
–
7
RTH
10k
NTC
C7
0.47µF
CLK
NTC
S1
+
~4.5V
60k
+
–
45k
–
+
15k
D
TBAD
Q
C
40071 F03
Figure 3
CLK
(NOT TO
SCALE)
tHOLD
VOLTAGE ACROSS THERMISTOR
tSAMPLE
COMPARATOR HIGH LIMIT
VNTC
COMPARATOR LOW LIMIT
40071 F04
Figure 4
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Battery Detection
LTC4007-1
It is generally not good practice to connect a battery while
the charger is running. The timer is in an unknown state
and the charger could provide a large surge current into
the battery for a brief time. The Figure 5 circuit keeps the
charger shut down and the timer reset while a battery is not
connected.
LTC4007-1
ADAPTER
POWER
22 SHDN
40071 F05
Figure 5
Charger Current Programming
The basic formula for charging current is:
ICHARGE(MAX) =
VREF • 3.01kΩ / RPROG – 0.035V
RSENSE
VREF = 1.19V
This leaves two degrees of freedom: RSENSE and RPROG.
The 3.01k input resistors must not be altered since internal
currents and voltages are trimmed for this value. Pick
RSENSE by setting the average voltage between CSP and
BAT to be close to 100mV during maximum charger
current. Then RPROG can be determined by solving the
above equation for RPROG.
RPROG =
9
CPROG
RPROG
RZ
102k
5V
0V
Q1
2N7002
40071 F06
Figure 6. PWM Current Programming
23 DCIN
SWITCH CLOSED
WHEN BATTERY
CONNECTED
PROG
VREF • 3.01kΩ
RSENSE • ICHARGE(MAX) + 0.035V
Table 2. Recommended RSNS and RPROG Resistor Values
IMAX (A)
RSENSE (Ω) 1%
RSENSE (W)
RPROG (kΩ) 1%
1.0
0.100
0.25
26.7
2.0
0.050
0.25
26.7
3.0
0.033
0.5
26.7
4.0
0.025
0.5
26.7
Charging current can be programmed by pulse width
modulating RPROG with a switch Q1 to RPROG at a frequency higher than a few kHz (Figure 6). CPROG must be
increased to reduce the ripple caused by the RPROG
switching. The compensation capacitor at ITH will probably need to be increased also to improve stability and
prevent large overshoot currents during start-up conditions. Charging current will be proportional to the duty
cycle of the switch with full current at 100% duty cycle and
zero current when Q1 is off.
Maintaining C/10 Accuracy
The C/10 comparator threshold that drives the FLAG pin
has a fixed threshold of approximately VPROG = 400mV.
This threshold works well when RPROG is 26.7k, but will
not yield a 10% charging current indication if RPROG is a
different value. There are situations where a standard
value of RSENSE will not allow the desired value of charging
current when using the preferred RPROG value. In these
cases, where the full-scale voltage across RSENSE is within
±20mV of the 100mV full-scale target, the input resistors
connected to CSP and BAT can be adjusted to provide the
desired maximum programming current as well as the
correct FLAG trip point.
For example, the desired max charging current is 2.5A but
the best RSENSE value is 0.033Ω. In this case, the voltage
across RSENSE at maximum charging current is only
82.5mV, normally RPROG would be 30.1k but the nominal
FLAG trip point is only 5% of maximum charging current.
If the input resistors are reduced by the same amount as
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the full-scale voltage is reduced then, R4 = R5 = 2.49k and
RPROG = 26.7k, the maximum charging current is still 2.5A
but the FLAG trip point is maintained at 10% of full scale.
Charger Voltage Programming
Pins CHEM and C3C4 are used to program the charger final
output voltage. The CHEM pin programs Li-Ion battery
chemistry for 4.1V/cell (low) or 4.2V/cell (high). The C3C4
pin selects either 3 series cells (low) or 4 series cells
(high). It is recommended that these pins be shorted to
ground (logic low) or left open (logic high) to effect the
desired logic level. Use open-collector or open-drain outputs when interfacing to the CHEM and 3C4C pins from a
logic control circuit.
Table 3. Charger Voltage Programming
VFINAL (V)
3C4C
CHEM
12.3
LOW
LOW
12.6
LOW
HIGH
16.4
HIGH
LOW
16.8
HIGH
HIGH
Setting the Timer Resistor
The charger termination timer is designed for a range of
1hour to 3 hour with a ±15% uncertainty. The timer is
programmed by the resistor RRT using the following
equation:
tTIMER = 10 • 227 • RRT • 17.5pF (seconds)
400
tTIMER (MINUTES)
There are other effects to consider. The voltage across the
current comparator is scaled to obtain the same values as
the 100mV sense voltage target, but the input referred
sense voltage is reduced, causing some careful consideration of the ripple current. Input referred maximum comparator threshold is 117mV, which is the same ratio of 1.4x
the DC target. Input referred IREV threshold is scaled back
to –24mV. The current at which the switcher starts will be
reduced as well so there is some risk of boost activity.
These concerns can be addressed by using a slightly larger
inductor to compensate for the reduction of tolerance to
ripple current.
500
450
350
300
250
200
150
100
50
0
100
300
500
700
900
RRT (kΩ)
1100
1300
40071 F07
Figure 7. tTIMER vs RRT
It is important to keep the parasitic capacitance on the RT
pin to a minimum. The trace connecting RT to RRT should
be as short as possible.
Soft-Start
The LTC4007-1 is soft started by the 0.12µF capacitor on
the ITH pin. On start-up, ITH pin voltage will rise quickly to
0.5V, then ramp up at a rate set by the internal 40µA pullup current and the external capacitor. Battery charging
current starts ramping up when ITH voltage reaches 0.8V
and full current is achieved with ITH at 2V. With a 0.12µF
capacitor, time to reach full charge current is about 2ms
and it is assumed that input voltage to the charger will
reach full value in less than 2ms. The capacitor can be
increased up to 1µF if longer input start-up times are
needed.
Input and Output Capacitors
The input capacitor (C2) is assumed to absorb all input
switching ripple current in the converter, so it must have
adequate ripple current rating. Worst-case RMS ripple
current will be equal to one half of output charging current.
Actual capacitance value is not critical. Solid tantalum low
ESR capacitors have high ripple current rating in a relatively small surface mount package, but caution must be
40071f
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used when tantalum capacitors are used for input or
output bypass. High input surge currents can be created
when the adapter is hot-plugged to the charger or when a
battery is connected to the charger. Solid tantalum capacitors have a known failure mechanism when subjected to
very high turn-on surge currents. Only Kemet T495 series
of “Surge Robust” low ESR tantalums are rated for high
surge conditions such as battery to ground.
The relatively high ESR of an aluminum electrolytic for C1,
located at the AC adapter input terminal, is helpful in
reducing ringing during the hot-plug event. Refer to AN88
for more information.
Highest possible voltage rating on the capacitor will minimize problems. Consult with the manufacturer before use.
Alternatives include new high capacity ceramic (at least
20µF) from Tokin, United Chemi-Con/Marcon, et al. Other
alternative capacitors include OS-CON capacitors from
Sanyo.
The output capacitor (C3) is also assumed to absorb
output switching current ripple. The general formula for
capacitor current is:
IRMS
⎛
⎞
V
0.29(VBAT )⎜ 1 – BAT ⎟
⎝ VDCIN ⎠
=
(L1)( f)
For example:
VDCIN = 19V, VBAT = 12.6V, L1 = 10µH, and
f = 300kHz, IRMS = 0.41A.
EMI considerations usually make it desirable to minimize
ripple current in the battery leads, and beads or inductors
may be added to increase battery impedance at the 300kHz
switching frequency. Switching ripple current splits between the battery and the output capacitor depending on
the ESR of the output capacitor and the battery impedance. If the ESR of C3 is 0.2Ω and the battery impedance
is raised to 4Ω with a bead or inductor, only 5% of the
current ripple will flow in the battery.
Inductor Selection
Higher operating frequencies allow the use of smaller
inductor and capacitor values. A higher frequency generally results in lower efficiency because of MOSFET gate
charge losses. In addition, the effect of inductor value on
ripple current and low current operation must also be
considered. The inductor ripple current ∆IL decreases
with higher frequency and increases with higher VIN.
∆IL =
⎛ V ⎞
1
VOUT ⎜ 1– OUT ⎟
( f)(L) ⎝ VIN ⎠
Accepting larger values of ∆IL allows the use of low
inductances, but results in higher output voltage ripple
and greater core losses. A reasonable starting point for
setting ripple current is ∆IL = 0.4(IMAX). In no case should
∆IL exceed 0.6(IMAX) due to limits imposed by IREV and
CA1. Remember the maximum ∆IL occurs at the maximum input voltage. In practice 10µH is the lowest value
recommended for use.
Lower charger currents generally call for larger inductor
values. Use Table 4 as a guide for selecting the correct
inductor value for your application.
Table 4
MAX AVERAGE
CURRENT (A)
INPUT VOLTAGE (V)
MINIMUM INDUCTOR
VALUE (µH)
1
≤20
40 ±20%
1
>20
56 ±20%
2
≤20
20 ±20%
2
>20
30 ±20%
3
≤20
15 ±20%
3
>20
20 ±20%
4
≤20
10 ±20%
4
>20
15 ±20%
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Charger Switching Power MOSFET
and Diode Selection
Two external power MOSFETs must be selected for use
with the charger: a P-channel MOSFET for the top (main)
switch and an N-channel MOSFET for the bottom (synchronous) switch.
The peak-to-peak gate drive levels are set internally. This
voltage is typically 6V. Consequently, logic-level threshold
MOSFETs must be used. Pay close attention to the BVDSS
specification for the MOSFETs as well; many of the logic
level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “ON”
resistance RDS(ON), total gate capacitance QG, reverse
transfer capacitance CRSS, input voltage and maximum
output current. The charger is operating in continuous
mode at moderate to high currents so the duty cycles for
the top and bottom MOSFETs are given by:
Main Switch Duty Cycle = VOUT/VIN
Synchronous Switch Duty Cycle = (VIN – VOUT)/VIN.
The MOSFET power dissipations at maximum output
current are given by:
PMAIN = VOUT/VIN(IMAX)2(1 + δ∆T)RDS(ON)
+ k(VIN)2(IMAX)(CRSS)(fOSC)
PSYNC = (VIN – VOUT)/VIN(IMAX)2(1 + δ∆T)RDS(ON)
Where δ∆T is the temperature dependency of RDS(ON) and
k is a constant inversely related to the gate drive current.
Both MOSFETs have I2R losses while the PMAIN equation
includes an additional term for transition losses, which are
highest at high input voltages. For VIN < 20V the high
current efficiency generally improves with larger MOSFETs,
while for VIN > 20V the transition losses rapidly increase
to the point that the use of a higher RDS(ON) device with
lower CRSS actually provides higher efficiency. The synchronous MOSFET losses are greatest at high input voltage or during a short circuit when the duty cycle in this
switch in nearly 100%. The term (1 + δ∆T) is generally
given for a MOSFET in the form of a normalized RDS(ON) vs
temperature curve, but δ = 0.005/°C can be used as an
approximation for low voltage MOSFETs. CRSS = QGD/∆VDS
is usually specified in the MOSFET characteristics. The
constant k = 2 can be used to estimate the contributions of
the two terms in the main switch dissipation equation.
If the charger is to operate in low dropout mode or with a
high duty cycle greater than 85%, then the topside
P-channel efficiency generally improves with a larger
MOSFET. Using asymmetrical MOSFETs may achieve cost
savings or efficiency gains.
The Schottky diode D1, shown in the Typical Application
on the back page, conducts during the dead-time between
the conduction of the two power MOSFETs. This prevents
the body diode of the bottom MOSFET from turning on and
storing charge during the dead-time, which could cost as
much as 1% in efficiency. A 1A Schottky is generally a
good size for 4A regulators due to the relatively small
average current. Larger diodes can result in additional
transition losses due to their larger junction capacitance.
The diode may be omitted if the efficiency loss can be
tolerated.
Calculating IC Power Dissipation
The power dissipation of the LTC4007-1 is dependent
upon the gate charge of the top and bottom MOSFETs
(QG1 & QG2 respectively) The gate charge is determined
from the manufacturer’s data sheet and is dependent upon
both the gate voltage swing and the drain voltage swing of
the MOSFET. Use 6V for the gate voltage swing and VDCIN
for the drain voltage swing.
PD = VDCIN • (fOSC (QG1 + QG2) + IQ)
Example:
VDCIN = 19V, fOSC = 345kHz, QG1 = QG2 = 15nC,
IQ = 5mA
PD = 292mW
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Adapter Limiting
An important feature of the LTC4007-1 is the ability to
automatically adjust charging current to a level which
avoids overloading the wall adapter. This allows the product to operate at the same time that batteries are being
charged without complex load management algorithms.
Additionally, batteries will automatically be charged at the
maximum possible rate of which the adapter is capable.
This feature is created by sensing total adapter output
current and adjusting charging current downward if a
preset adapter current limit is exceeded. True analog
control is used, with closed-loop feedback ensuring that
adapter load current remains within limits. Amplifier CL1
in Figure 8 senses the voltage across RCL, connected
between the CLP and CLN pins. When this voltage exceeds
100mV, the amplifier will override programmed charging
current to limit adapter current to 100mV/RCL. A lowpass
filter formed by 5kΩ and 15nF is required to eliminate
switching noise. If the current limit is not used, CLP should
be connected to CLN.
Note that the ICL pin will be asserted when the voltage
across RCL is 93mV, before the adapter limit regulation
threshold.
LTC4007-1
100mV
–
+
CLP
15
15nF
CL1
5k
+
RCL*
CLN
16
*RCL =
100mV
ADAPTER CURRENT LIMIT
+
AC ADAPTER
INPUT
VIN
CIN
input current limit tolerance and use that current to determine the resistor value.
RCL = 100mV/ILIM
ILIM = Adapter Min Current –
(Adapter Min Current • 7%)
Table 5. Common RCL Resistor Values
ADAPTER
RATING (A)
RCL VALUE*
(Ω) 1%
RCL POWER
DISSIPATION (W)
RCL POWER
RATING (W)
1.5
0.06
0.135
0.25
1.8
0.05
0.162
0.25
2
0.045
0.18
0.25
2.3
0.039
0.206
0.25
2.5
0.036
0.225
0.5
2.7
0.033
0.241
0.5
3
0.03
0.27
0.5
* Values shown above are rounded to nearest standard value.
As is often the case, the wall adapter will usually have at
least a +10% current limit margin and many times one can
simply set the adapter current limit value to the actual
adapter rating (see Table 5).
Designing the Thermistor Network
There are several networks that will yield the desired
function of voltage vs temperature needed for proper
operation of the thermistor. The simplest of these is the
voltage divider shown in Figure 9. Unfortunately, since the
HIGH/LOW comparator thresholds are fixed internally,
there is only one thermistor type that can be used in this
network; the thermistor must have a HIGH/LOW resistance ratio of 1:7. If this happy circumstance is true for
you, then simply set R9 = RTH(LOW).
40071 F08
Figure 8. Adapter Current Limiting
LTC4007-1
R9
NTC 7
C7
Setting Input Current Limit
RTH
40071 F09
To set the input current limit, you need to know the
minimum wall adapter current rating. Subtract 7% for the
Figure 9. Voltage Divider Thermistor Network
40071f
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LTC4007-1
Example #2: 100kΩ NTC
R9
NTC 7
C7
R9A
RTH
40071 F10
Figure 10. General Thermistor Network
If you are using a thermistor that doesn’t have a 1:7 HIGH/
LOW ratio, or you wish to set the HIGH/LOW limits to
different temperatures, then the more generic network in
Figure 10 should work.
Once the thermistor, RTH, has been selected and the
thermistor value is known at the temperature limits, then
resistors R9 and R9A are given by:
For NTC thermistors:
R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(LOW) – RTH(HIGH))
R9A = 6 RTH(LOW) • RTH(HIGH)/(RTH(LOW) – 7 • RTH(HIGH))
Where RTH(LOW) > 7 • RTH(HIGH)
For PTC thermistors:
R9 = 6 RTH(LOW) • RTH(HIGH)/(RTH(HIGH) – RTH(LOW))
R9A = 6 RTH(LOW) • RTH(HIGH)/(RTH(HIGH) – 7 • RTH(LOW))
Where RTH(HIGH) > 7 • RTH(LOW)
Example #1: 10kΩ NTC with custom limits
TLOW = 0°C, THIGH = 50°C
RTH = 10k at 25°C,
RTH(LOW) = 32.582k at 0°C
RTH(HIGH) = 3.635k at 50°C
R9 = 24.55k → 24.3k (nearest 1% value)
R9A = 99.6k → 100k (nearest 1% value)
TLOW = 5°C, THIGH = 50°C
RTH = 100k at 25°C,
RTH(LOW) = 272.05k at 5°C
RTH(HIGH) = 33.195k at 50°C
R9 = 226.9k → 226k (nearest 1% value)
R9A = 1.365M → 1.37M (nearest 1% value)
Example #3: 22kΩ PTC
TLOW = 0°C, THIGH = 50°C
RTH = 22k at 25°C,
RTH(LOW) = 6.53k at 0°C
RTH(HIGH) = 61.4k at 50°C
R9 = 43.9k → 44.2k (nearest 1% value)
R9A = 154k
Sizing the Thermistor Hold Capacitor
During the hold interval, C7 must hold the voltage across
the thermistor relatively constant to avoid false readings.
A reasonable amount of ripple on NTC during the hold
interval is about 10mV to 15mV. Therefore, the value of C7
is given by:
C7 = tHOLD/(R9/7 • –ln(1 – 8 • 15mV/4.5V))
= 10 • RRT • 17.5pF/(R9/7 • – ln(1 – 8 • 15mV/4.5V)
Example:
R9 = 24.3k
RRT = 309k (~2 hour timer)
C7 = 0.57µF → 0.56µF (nearest value)
40071f
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Disabling the Thermistor Function
General Rules
If the thermistor is not needed, connecting a resistor
between DCIN and NTC will disable it. The resistor should
be sized to provide at least 10µA with the minimum voltage
applied to DCIN and 10V at NTC. Do not exceed 30µA.
Generally, a 301k resistor will work for DCIN less than 15V.
A 499k resistor is recommended for DCIN between 15V
and 24V.
1. Input capacitors need to be placed as close as possible
to switching FET’s supply and ground connections.
Shortest copper trace connections possible. These
parts must be on the same layer of copper. Vias must
not be used to make this connection.
Conditioning Depleted Batteries
Severely depleted batteries, with less than 3.25V/cell,
should be conditioned with a trickle charge to prevent
possible damage. This trickle charge is typically 10% of
the 1C rate of the battery. The LTC4007-1 can automatically trickle charge depleted batteries using the circuit in
Figure 11. If the battery voltage is less than 3.25V/cell
(3.173V/cell if CHEM is low) then the LOBAT indicator will
be low and Q4 is off. This programs the charging current
with RPROG = R6 + R14. Charging current is approximately
300mA. When the cell voltage becomes greater than 3.25V
the LOBAT indicator goes high, Q4 shorts out R13, then
RPROG = R6. Charging current is then equal to 3A.
PCB Layout Considerations
For maximum efficiency, the switch node rise and fall
times should be minimized. To prevent magnetic and
electrical field radiation and high frequency resonant problems, proper layout of the components connected to the IC
is essential. (See Figure 12.) Here is a PCB layout priority
list for proper layout. Layout the PCB using this specific
order.
2. The control IC needs to be close to the switching FET’s
gate terminals. Keep the gate drive signals short for a
clean FET drive. This includes IC supply pins that connect to the switching FET source pins. The IC can be
placed on the opposite side of the PCB relative to above.
3. Place inductor input as close as possible to switching
FET’s output connection. Minimize the surface area of
this trace. Make the trace width the minimum amount
needed to support current—no copper fills or pours.
Avoid running the connection using multiple layers in
parallel. Minimize capacitance from this node to any
other trace or plane.
4. Place the output current sense resistor right next to
the inductor output but oriented such that the IC’s
current sense feedback traces going to resistor are not
long. The feedback traces need to be routed together
as a single pair on the same layer at any given time with
smallest trace spacing possible. Locate any filter
component on these traces next to the IC and not at the
sense resistor location.
5. Place output capacitors next to the sense resistor
output and ground.
6. Output capacitor ground connections need to feed
into same copper that connects to the input capacitor
ground before tying back into system ground.
40071f
20
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General Rules (Continued)
7. Connection of switching ground to system ground or
internal ground plane should be single point. If the
system has an internal system ground plane, a good
way to do this is to cluster vias into a single star point
to make the connection.
8. Route analog ground as a trace tied back to IC ground
(analog ground pin if present) before connecting to
any other ground. Avoid using the system ground
plane. CAD trick: make analog ground a separate
ground net and use a 0Ω resistor to tie analog ground
to system ground.
9. A good rule of thumb for via count for a given high
current path is to use 0.5A per via. Be consistent.
10. If possible, place all the parts listed above on the same
PCB layer.
11. Copper fills or pours are good for all power connections except as noted above in Rule 3. You can also use
copper planes on multiple layers in parallel too—this
helps with thermal management and lower trace inductance improving EMI performance further.
12. For best current programming accuracy provide a
Kelvin connection from RSENSE to CSP and BAT. See
Figure 12 as an example.
It is important to keep the parasitic capacitance on the RT,
CSP and BAT pins to a minimum. The traces connecting
these pins to their respective resistors should be as short
as possible.
40071f
21
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Q3
INPUT SWITCH
DCIN
0V TO 20V
3A
C1
0.1µF
VLOGIC
R10
100k
R11
100k
R12
100k
*
3C4C
DCIN
*
CHEM
INFET
LOBAT
CLP
LOBAT
ICL
ACP
TGATE
SHDN
SHDN
BGATE
FAULT
FAULT
PGND
FLAG
CHG
R9 32.4k 1%
FLAG
NTC
THERMISTOR
C7
0.47µF
RT
309k
1%
RCL
0.033Ω
1%
C4
15nF
C2
20µF
LTC4007-1 CLN
ICL
ACP
CHG
R1
4.99k
1%
RT
L1
15µH 3A
Q2
D1
RSENSE
0.033Ω
1%
BAT
R4
3.01k
1%
CSP
BAT
C3
20µF
R5 3.01k 1%
PROG
ITH
GND
TIMING RESISTOR
(~2 HOURS)
Q1
SYSTEM
LOAD
R7
6.04k
1%
C6
0.12µF
C5
0.0047µF
R14
52.3k
1%
R6
26.7k
1%
Q4
*PIN OPEN
D1: MBRM140T3
Q1: Si4431BDY
Q2: FDC645N
Q4: 2N7002 OR BSS138
MONITOR
(CHARGING
CURRENT
MONITOR)
40071 F11
Figure 11. Circuit Application (16.8V/3A) to Automatically Trickle Charge Depleted Batteries
40071f
22
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SWITCH NODE
L1
DIRECTION OF CHARGING CURRENT
VBAT
C2
VIN
HIGH
FREQUENCY
CIRCULATING
PATH
D1
C3
RSENSE
BAT
40071 F13
CSP
40071 F12
Figure 12. High Speed Switching Path
BAT
Figure 13. Kelvin Sensing of Charging Current
U
PACKAGE DESCRIPTION
UFD Package
24-Lead Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1696)
2.65 ± 0.10
(2 SIDES)
4.00 ± 0.10
(2 SIDES)
R = 0.115
TYP
23 24
0.75 ± 0.05
PIN 1 NOTCH
R = 0.30 TYP
0.70 ±0.05
0.40 ± 0.05
PIN 1
TOP MARK
(NOTE 6)
4.50 ± 0.05
3.10 ± 0.05
5.00 ± 0.10
(2 SIDES)
2.65 ± 0.05
(2 SIDES)
0.25 ±0.05
0.50 BSC
3.65 ± 0.05
(2 SIDES)
4.10 ± 0.05
5.50 ± 0.05
1
2
3.65 ± 0.10
(2 SIDES)
(UFD25) QFN 0504
PACKAGE OUTLINE
0.200 REF
0.00 – 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
0.25 ± 0.05
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
40071f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC4007-1
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TYPICAL APPLICATIO
12.6V, 4A Li-Ion Battery Charger
Q3
INPUT SWITCH
DCIN
0V TO 20V
3A
C1
0.1µF
VLOGIC
R10
100k
R11
100k
R12
100k
*
LOBAT
3C4C
DCIN
CHEM
INFET
LOBAT
CLP
ICL
ACP
TGATE
SHDN
SHDN
BGATE
FAULT
FAULT
PGND
CHG
CHG
CSP
FLAG
FLAG
BAT
NTC
THERMISTOR
10k
NTC
RRT
309k
1%
RCL
0.033Ω
1%
GND
TIMING RESISTOR
(~2 HOURS)
SYSTEM
LOAD
C2
20µF
RSENSE
L1
0.025Ω
10µH 4A
1%
Q1
BAT
Q2
D1
R4
3.01k 1%
C3
20µF
R5 3.01k 1%
PROG
ITH
RT
C7
0.47µF
C4
15nF
LTC4007-1 CLN
ICL
ACP
R9 32.4k 1%
R1
4.99k
1%
R7
6.04k
1%
C6
0.12µF
C5
0.0047µF
RPROG
26.7k
1%
CHARGING
CURRENT
MONITOR
*PIN OPEN
D1: MBRS130T3
Q1: Si4431BDY
Q2: FDC645N
40071 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT 1511
Constant-Current/Constant-Voltage 3A Battery
Charger with Input Current Limiting
High Efficiency Current Mode PWM with 4A Internal Switch
LT1513
SEPIC Constant- or Programmable-Current/
Constant-Voltage Battery Charger
Charger Input Voltage May Be Higher, Equal to or Lower Than Battery Voltage;
Charges Any Number of Cells Up to 20V, 500kHz Switching Frequency
LT1571
1.5A Switching Charger
1- or 2-Cell Li-Ion, 500kHz or 200kHz Switching Frequency, Termination Flag
LTC1628-PG
2-Phase, Dual Synchronous Step-Down Controller
Minimizes CIN and COUT, Power Good Output, 3.5V ≤ VIN ≤ 36V
LTC1709
2-Phase, Dual Synchronous Step-Down Controller
with VID
Up to 42A Output, Minimum CIN and COUT, Uses Smallest Components for
Intel and AMD Processors
LT1769
2A Switching Battery Charger
Constant-Current/Constant-Voltage Switching Regulator, Input Current
Limiting Maximizes Charge Current
LTC1778
Wide Operating Range, No RSENSE Synchronous
Step-Down Controller
2% to 90% Duty Cycle at 200kHz, Stable with Ceramic COUT
LTC1960
Dual Battery Charger/Selector with SPI Interface
Simultaneous Charge or Discharge of Two Batteries, DAC Programmable
Current and Voltage, Input Current Limiting Maximizes Charge Current
LTC3711
No RSENSETM Synchronous Step-Down Controller
with VID
3.5V ≤ VIN ≤ 36V, 0.925V ≤ VOUT ≤ 2V, for Transmeta, AMD and Intel
Mobile Processors
LTC4006
Small, High Efficiency, Fixed Voltage,
Lithium-Ion Battery Charger
Constant-Current/Constant-Voltage Switching Regulator with Termination
Timer, AC Adapter Current Limit and Thermistor Sensor in a Small
16-Pin Package
LTC4007
4A High Efficiency, Standalone Li-Ion Battery Charger Complete Charger for 3- or 4-Cell Li-Ion Batteries, AC Adapter Current Limit
and Thermistor Sensor, 16-Pin Narrow SSOP Package
LTC4008
High Efficiency, Programmable Voltage/Current
Battery Charger
Constant-Current/Constant-Voltage Switching Regulator, Resistor Voltage/
Current Programming, AC Adapter Current Limit and Thermistor Sensor
LTC4100
Smart Battery Charger Controller
100% Compliant SMBus 1.1 Support, VIN: 6.4V to 26V, VDROPOUT = 0.5V,
High Efficiency Synchronous Buck Charger
®
No RSENSE is a trademark of Linear Technology Corporation.
40071f
24 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
LT/TP 1005 500 • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2005
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