TRIPLE-OUTPUT LCD SUPPLY WITH LINEAR REGULATOR AND VCOM BUFFER TPS65100-Q1 FEATURES DESCRIPTION

TRIPLE-OUTPUT LCD SUPPLY WITH LINEAR REGULATOR AND VCOM BUFFER TPS65100-Q1 FEATURES DESCRIPTION
TPS65100-Q1
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SLVS849A – JULY 2008 – REVISED APRIL 2012
TRIPLE-OUTPUT LCD SUPPLY WITH LINEAR REGULATOR AND VCOM BUFFER
Check for Samples: TPS65100-Q1
FEATURES
1
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23
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Qualified for Automotive Applications
2.7-V to 5.8-V Input Voltage Range
1.6-MHz Fixed Switching Frequency
Three Independently Adjustable Outputs
Main Output of up to 15 V With < 1% Output
Voltage Accuracy
Virtual Synchronous Converter Technology
Negative Regulated Charge Pump Driver VO2
Positive Charge Pump Converter VO3
Integrated VCOM Buffer
Auxiliary 3.3-V Linear Regulator Controller
Internal Soft Start
Internal Power-On Sequencing
Fault Detection of all Outputs
Thermal Shutdown
Available in TSSOP-24 PowerPAD™ Package
APPLICATIONS
•
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TFT LCD Displays for Notebooks
TFT LCD Displays for Monitors
Portable DVD Players
Tablet PCs
Car Navigation Systems
Industrial Displays
VIN
2.7 V to 5.8 V
DESCRIPTION
The TPS65100 offers a compact and small power
supply solution that provides all three voltages
required by thin-film transistor (TFT) LCD displays.
The auxiliary linear regulator controller can be used
to generate a 3.3-V logic power rail for systems
powered by a 5-V supply rail only.
The main output, VO1, is a 1.6-MHz fixed-frequency
PWM boost converter providing the source-drive
voltage for the LCD display. The TPS65100 has a
typical switch current limit of 2.3 A. A fully integrated
adjustable charge pump doubler/tripler provides the
positive LCD gate-drive voltage. An externally
adjustable negative charge pump provides the
negative gate-drive voltage. Due to the high 1.6-MHz
switching frequency of the charge pumps,
inexpensive and small 220-nF capacitors can be
used.
The TPS65100 has an integrated VCOM buffer to
power the LCD backplane. For LCD panels powered
by 5 V only, the TPS65100 has a linear regulator
controller using an external transistor to provide a
regulated 3.3-V output for the digital circuits. For
maximum safety, the TPS65100 goes into shutdown
as soon as one of the outputs is out of regulation.
The device can be enabled again by toggling the
input or the enable (EN) pin to GND.
Boost
Converter
VO1
Up to 15 V / 400 mA
Positive Charge
Pump
VO3
Up to 30 V / 20 mA
Negative
Charge Pump
VO2
Up to 12 V / 20 mA
VCOM Buffer
VCOM
Linear Regulator
Controller
VO4
3.3 V
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2012, Texas Instruments Incorporated
TPS65100-Q1
SLVS849A – JULY 2008 – REVISED APRIL 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL APPLICATION CIRCUIT
L1
4.7 µH
VI
2.7 to 5.8 V
C3
22 µF
TPS65100
VIN
COMP
R7
C1
0.22 µF
R8
VO2
Up to 12 V/20 mA
D2
C12
C4
22 µF
0.22 µF
SW
SW
VCOMIN
FB1
EN
SUP
C2
ENR
D3
R3
C6
0.22 µF
C5
R1
C11
10 nF
VO1
VO1
Up to 15 V/350 mA
D1
C2+
C2−/MODE
C1+
C1−
0.22 µF
R2
Vo3
up to 30 V/20 mA
OUT3
DRV
FB3
FB2
VCOM
REF
FB4
PGND
R5
PGND
BASE
C7
0.22 µF
GND
R4
R6
C11
220 nF
Q1
BCP68
VI
C9
1 µF
VO4
3.3 V
Vcom
C8
1 µF
C10
4.7 µF
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
2
TSSOP – PWP
Reel of 2000
ORDERABLE PART NUMBER
TPS65100QPWPRQ1
TOP-SIDE MARKING
65100Q
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
Voltage range on pin VIN (2)
–0.3 V to 6 V
Voltage range on pins VO1, SUP, PG
(2)
–0.3 V to 15.5 V
Voltage range on pins EN, MODE, ENR (2)
–0.3 V to VI + 0.3 V
Voltage on pin VCOMIN
14 V
Voltage on pin SW (2)
20 V
Continuous power dissipation
See Dissipation Ratings Table
Operating junction temperature range
–40°C to 150°C
Storage temperature range
–65°C to 150°C
Lead temperature (soldering, 10 seconds)
260°C
Electrostatic discharge (ESD) rating
(1)
(2)
Human-Body Model (HBM)
2000 V
Machine Model (MM)
100 V
Charged-Device Model (CDM)
1000 V
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
DISSIPATION RATINGS
PACKAGE
RθJA
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
24-pin TSSOP
30.13°C/W (PWP soldered)
3.3 W
1.83 W
1.32 W
THERMAL INFORMATION
THERMAL METRIC (1)
TPS65100-Q1
PWP (24 PINS)
θJA
Junction-to-ambient thermal resistance
37.2
θJCtop
Junction-to-case (top) thermal resistance
19.5
θJB
Junction-to-board thermal resistance
16.7
ψJT
Junction-to-top characterization parameter
0.4
ψJB
Junction-to-board characterization parameter
16.6
θJCbot
Junction-to-case (bottom) thermal resistance
2.1
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
MIN
TYP
5.8
UNIT
VIN
Input voltage
L
Inductor (1)
TA
Operating free-air temperature
–40
125
°C
TJ
Operating virtual-junction temperature
–40
125
°C
(1)
2.7
MAX
V
μH
4.7
See the Application Information section for further information.
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ELECTRICAL CHARACTERISTICS
Vin = 3.3 V, EN = VIN, VO1 = 10 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
Vi
Input voltage
2.7
5.8
V
0.7
0.9
mA
VO1 = SUP = 10 V, VO3 = 2 × VO1
1.7
2.7
VO1 = SUP = 10 V, VO3 = 3 × VO1
3.9
6
ENR = VCOMIN = GND, VO3 = 2 × VO1,
Boost converter not switching
IQ
Quiescent current into VIN
IQCharge
Charge pump quiescent current
into SUP
IQVCOM
VCOM quiescent current into SUP ENR = GND, VO1 = SUP = 10 V
750
1300
μA
IQEN
LDO controller quiescent current
into VIN
ENR = VIN, EN = GND
300
800
μA
ISD
Shutdown current into VIN
EN = ENR = GND
1
10
μA
VUVLO
Undervoltage lockout threshold
VIN falling
2.2
2.4
V
Thermal shutdown
Temperature rising
160
mA
°C
LOGIC SIGNALS EN, ENR
VIH
High-level input voltage
VIL
Low-level input voltage
IIleak
Input leakage current
1.5
EN = GND or VIN
V
0.01
0.4
V
0.1
μA
15
V
MAIN BOOST CONVERTER
VO1
Output voltage range
5
VO1 – VI
Minimum input to output
voltage difference
1
VREF
Reference voltage
1.205
1.213
1.223
VFB
Feedback regulation voltage
1.133
1.146
1.154
V
IFB
Feedback input bias current
10
100
nA
rDS(ON)
N-MOSFET on-resistance (Q1)
VO1 = 10 V, Isw = 500 mA
195
290
VO1 = 5 V, Isw = 500 mA
285
420
ILIM
N-MOSFET switch current limit
(Q1)
2.3
2.7
rDS(ON)
P-MOSFET on-resistance (Q2)
VO1 = 10 V, Isw = 100 mA
9
15
VO1 = 5 V, Isw = 100 mA
14
22
IMAX
Maximum P-MOSFET peak
switch current
Ileak
Switch leakage current
fSW
Oscillator frequency
1.6
Vsw = 15 V
V
10
2.1
–40°C ≤ TA ≤ 125°C
1.191
1.6
2.1
0 mA ≤ IO ≤ 300 mA
Ω
μA
1
1.6
Load regulation
A
A
1.295
2.7 V ≤ VI ≤ 5.7 V, Iload = 100 mA
mΩ
1
0°C ≤ TA ≤ 125°C
Line regulation
V
MHz
0.012
%/V
0.2
%/A
NEGATIVE CHARGE PUMP VO2
VO2
Output voltage range
Vref
Reference voltage
VFB
Feedback regulation voltage
IFB
Feedback input bias current
rDS(ON)
IO
4
Q8 P-channel switch rDS(ON)
Q9 N-channel switch rDS(ON)
–2
1.205
1.213
1.219
–36
0
36
mV
10
100
nA
IO = 20 mA
Maximum output current
V
4.3
8
2.9
4.4
20
Line regulation
7 V ≤ VO1 ≤ 15 V, Iload = 10 mA, VO2 = –5 V
Load regulation
1 mA ≤ IO ≤ 20 mA, VO2 = –5 V
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V
Ω
mA
0.09
%/V
0.126
%/mA
Copyright © 2008–2012, Texas Instruments Incorporated
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SLVS849A – JULY 2008 – REVISED APRIL 2012
ELECTRICAL CHARACTERISTICS (continued)
Vin = 3.3 V, EN = VIN, VO1 = 10 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POSITIVE CHARGE PUMP VO3
VO3
Output voltage range
30
V
Vref
Reference voltage
1.205
1.213
1.219
V
VFB
Feedback regulation voltage
1.187
1.214
1.238
V
IFB
Feedback input bias current
10
100
nA
Q3 P-channel switch rDS(ON)
9.9
15.5
1.1
1.8
4.6
8.5
1.2
2.2
610
720
rDS(ON)
Q4 N-channel switch rDS(ON)
Q5 P-channel switch rDS(ON)
IO = 20 mA
Q6 N-channel switch rDS(ON)
Vd
D1–D4 Shottky diode
forward voltage
IO
Maximum output current
ID1–D4 = 40 mA
Ω
mV
20
mA
Line regulation
10 V ≤ VO1 ≤ 15 V, Iload = 10 mA, VO3 = 27 V
0.56
%/V
Load regulation
1 mA ≤ IO ≤ 20 mA, VO3 = 27 V
0.05
%/mA
LINEAR REGULATOR CONTROLLER VO4
VO4
Output voltage
IBASE
Maximum base drive current
4.5 V ≤ VI ≤ 5.5 V, 10 mA ≤ IO ≤ 500 mA
VI – VO4 – VBE ≥ 0.5 V
(1)
VI – VO4 – VBE ≥ 0.75 V
(1)
3.2
3.3
13.5
19
20
27
Line regulation
4.75 V ≤ VI ≤ 5.5 V, Iload = 500 mA
0.186
Load regulation
1 mA ≤ IO ≤ 500 mA, VI = 5 V
0.064
Start up current
VO4 ≤ 0.8 V
11
20
3.4
V
mA
%/V
%/A
25
mA
VCOM BUFFER
Vcm
Common mode input range
Vos
Input offset voltage
DC Load regulation
2.25
(VO1) – 2
IO = 0 mA
–25
+25
IO = ±25 mA
–30
37
IO = ±50 mA
–45
55
IO = ±100 mA
–72
85
IO = ±150 mA
IB
VCOMIN Input bias current
Ipeak
Peak output current
–97
–300
V
mV
mV
110
–30
300
nA
VO1 = 15 V
1.2
A
VO1 = 10 V
0.65
A
VO1 = 5 V
0.15
A
VO1 Rising
–12
–8.75%
VO1
–6
V
VO2 Rising
–13
–9% VO2
–5
V
VO3 Rising
–11
–8% VO3
–5
V
FAULT PROTECTION THRESHOLDS
V(th, Vo1)
V(th, Vo2)
Shutdown threshold
V(th, Vo3)
(1)
With VI = supply voltage of the TPS65100, VO4 = output voltage of the regulator, VBE = basis emitter voltage of external transistor
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PWP PACKAGE
(TOP VIEW)
1
24
2
23
3
22
4
21
5
6
20
19
7
8
Thermal Pad
FB1
FB4
BASE
VIN
SW
SW
PGND
PGND
SUP
VCOM
VCOMIN
FB3
18
17
9
16
10
15
11
14
12
13
EN
ENR
COMP
FB2
REF
GND
DRV
C1C1+
C2-/MODE
C2+
OUT3
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
VIN
4
I
Input voltage pin of the device
EN
24
I
Enable pin of the device. This pin should be terminated and not be left floating. A logic high enables the
device and a logic low shuts down the device.
COMP
22
VCOMIN
11
I
Positive input terminal of the VCOM buffer. When the VCOM buffer is not used, this terminal can be
connected to GND to reduce the overall quiescent current of the IC.
ENR
23
I
Enable pin of the linear regulator controller. This pin should be terminated and not be left floating. Logic
high enables the regulator and a logic low puts the regulator in shutdown.
C1+
16
C1–
17
DRV
18
FB2
REF
FB4
Compensation pin for the main boost converter. A small capacitor is connected to this pin.
Positive terminal of the charge pump flying capacitor
Negative terminal of the charge pump flying capacitor
O
External charge pump driver
21
I
Feedback pin of negative charge pump
20
O
Internal reference output typically 1.23 V
2
I
Feedback pin of the linear regulator controller. The linear regulator controller is set to a fixed output
voltage of 3.3 V or 3 V depending on the version.
BASE
3
O
Base drive output for the external transistor
GND
19
Ground
PGND
7, 8
Power ground
VCOM
10
O
VCOM buffer output
FB3
12
I
Feedback pin of positive charge pump
OUT3
13
O
Positive charge pump output
C2–/MODE
15
Negative terminal of the charge pump flying capacitor and charge pump MODE pin. If the flying
capacitor is connected to this pin, the converter operates in a voltage tripler mode. If the charge pump
needs to operate in a voltage doubler mode, the flying capacitor is removed and the C2–/MODE pin
should be connected to GND.
C2+
14
Positive terminal for the charge pump flying capacitor. If the device runs in voltage doubler mode, this
pin should be left open.
SUP
9
I
Supply of the positive and negative charge pump, boost converter gate-drive circuit, and VCOM buffer.
Should be connected to the output of the main boost converter and cannot be connected to any other
voltage source. For performance reasons, do not connect a bypass capacitor directly to this pin.
FB1
1
I
Feedback pin of the boost converter
SW
5, 6
I
Switch pin of the boost converter
Thermal pad
6
The exposed thermal pad should be connected to the power ground (PGND).
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FUNCTIONAL BLOCK DIAGRAM
VIN
SW
SW
Q2
FB1
FB2
FB3
Bias Vref = 1.213 V
Thermal Shutdown
Start-Up Sequencing
Undervoltage Detection
Short-Circuit Protection
S
D
Main boost
converter
EN
Current Limit
and
Soft Start
1.6-MHz
Oscillator
SUP
Control Logic
Gate Drive Circuit
D
Q1
S
COMP
GM Amplifier
Comparator
Sawtooth
Generator
FB1
VFB
1.146 V
SUP
SUP
(VO)
FB3
Positive
Charge Pump
GM Amplifier
Low Gain
VFB
1.146 V
Vref
1.214 V
Negative
Charge Pump
SUP
Q8
D
Q3
S
Current
Control
C1−
Gain Select
(Doubler or
Tripple Mode)
D
Q4
S
SUP
Soft Start
D
C1+
Current
Control
Soft Start
S
DRV
D
Q7
S
D
Q9
SUP
SUP
S
Vo3
D1
D2
D Q5
D4
S
C2+
FB2
D
Vref
0V
S
D3
Q6
C2−
Reference
Output
REF
Vref
1.213 V
SUP
Vin
Soft Start
Iref = 20 mA
Soft Start
Short Circuit
Detect
D
Q11
S
~1 V
FB4
VCOM
D
Linear
Regulator
Controller
S
Vref
1.213 V
D
Q12
S
Q10
Disable
VCOM
Buffer
ENR
BASE
VCOMIN
GND
PGND
PGND
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Main Boost Converter
η
Efficiency, main boost converter VO1
vs Load current
1
Efficiency, main boost converter VO1
vs Load current
2
Efficiency
vs Input voltage
3
fsw
Switching frequency
vs Free-air temperature
4
rDS(on)
rDS(on) N-channel main switch Q1
vs Free-air temperature
5
PWM operation, continuous mode
6
PWM operation at light load
7
Load transient response, CO = 22 μF
8
Load transient response, CO = 2 × 22 μF
9
Power-up sequencing
10
Soft start VO1
11
Negative Charge Pump
Imax
VO2 Maximum load current
vs Output voltage VO1
12
Positive Charge Pump
Imax
VO3 Maximum load current
vs Output voltage VO1 (doubler mode)
13
Imax
VO3 Maximum load current
vs Output voltage VO1 (tripler mode)
14
8
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EFFICIENCY
vs
LOAD CURRENT
100
100
90
90
Efficiency - %
Vo1 = 15 V
40
Vo1 = 10 V
60
50
Vo1 = 15 V
40
30
Vo1 = 6 V
90
Vo1 = 10 V
85
Vo1 = 15 V
80
30
VI = 3.3 V
Vo2, Vo3 = No Load, Switching
20
10
10
100
1k
1
100
1k
70
2.5
3
3.5
4
4.5
5
5.5
6
IL − Load Current − mA
Figure 1.
Figure 2.
Figure 3.
SWITCHING FREQUENCY
vs
FREE-AIR TEMPERATURE
rDS(on) N-CHANNEL MAIN SWITCH
vs
FREE-AIR TEMPERATURE
PWM OPERATION CONTINUOUS
MODE
VI - Input V oltage - V
r
− N−Channel Main Switch − mΩ
DS(on)
350
1.8
VI = 2.7 V
VI = 3.3 V
1.6
VI = 5.8 V
1.5
1.4
1.3
−40
10
IL − Load Current − mA
1.9
1.7
75
VI = 5 V
Vo2, Vo3 = No Load, Switching
20
10
1
Switching Frequency − MHz
ILoad at Vo1 = 100 mA
Vo2, Vo3 = No Load, Switching
70
Efficiency − %
60
50
100
80
Vo1 = 10 V
70
EFFICIENCY
vs
INPUT VOLTAGE
95
Vo1 = 6 V
80
Efficiency − %
EFFICIENCY
vs
LOAD CURRENT
−20
0
20
40
60
80
100
VSW
10 V/div
300
Vo1 = 5 V
250
VO
50 mV/div
200
Vo1 = 10 V
150
IL
1 A/div
Vo1 = 15 V
100
−40
−20
0
20
40
60
80
VI = 3.3 V
VO = 10 V/300 mA
100
250 ns/div
TA − Free-Air Temperature − °C
TA − Free-Air Temperature − °C
Figure 4.
Figure 5.
Figure 6.
PWM OPERATION AT LIGHT LOAD
LOAD TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
VI = 3.3 V
Vo1 = 10 V, CO= 2*22 µF
Vo1
200 mV/div
VSW
10 V/div
Vo1
100 mV/div
VO
50 mV/div
VI = 3.3 V
VO = 10 V/10 mA
IO
50 mA to 250 mA
IL
500 mA/div
VI = 3.3 V
Vo1 = 10 V, CO= 22 µF
100 µs/div
IO
50 mA to 250 mA
100 µs/div
250 ns/div
Figure 7.
Figure 8.
Figure 9.
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POWER-UP SEQUENCING
SOFT START VO1
VO2 MAXIMUM LOAD CURRENT
0.20
VI = 3.3 V
VO = 10 V,
IO = 300 mA
Vo2 = −8 V
0.18
I O − Output Current − A
Vo1
5 V/div
Vo1
5 V/div
Vo2
5 V/div
Vo3
10 V/div
II
500
mA/div
VI = 3.3 V
VO = 10 V,
VCOM CI = 1 nF
VCOM
2 V/div
0.14
TA = 85°C
0.12
0.10
TA = 25°C
0.08
0.06
0.04
0.02
0
8.8
500 µs/div
500 µs/div
TA = −40°C
0.16
9.8
10.8
11.8
12.8
13.8
14.8
Vo1 − Output Voltage − V
Figure 10.
0.14
Figure 11.
Figure 12.
VO3 MAXIMUM LOAD CURRENT
0.12
VO3 MAXIMUM LOAD CURRENT
TA = −40°C
Vo3 = 18 V (Doubler Mode)
0.10
TA = −40°C
I O − Output Current − A
I O − Output Current − A
0.12
TA = 85°C
0.10
TA = 25°C
0.08
0.06
0.04
TA = 25°C
0.08
TA = 85°C
0.06
0.04
0.02
0.02
Vo3 = 28 V (Tripler Mode)
0
9
10
11
12
13
14
15
9
10
11
12
13
14
15
Vo1 − Output Voltage − V
Vo1 − Output Voltage − V
Figure 13.
10
0
Figure 14.
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DETAILED DESCRIPTION
The TPS65100 consists of a main boost converter operating with a fixed switching frequency of 1.6 MHz to allow
for small external components. The boost converter output voltage VO1 is also the input voltage, connected via
the pin SUP, for the positive and negative charge pumps and the bias supply for the VCOM buffer. The linear
regulator controller is independent from this system with its own enable pin. This design allows the linear
regulator controller to continue to operate while the other supply rails are disabled or in shutdown due to a fault
condition on one of their outputs. See the functional block diagram for more information.
Main Boost Converter
The main boost converter operates with PWM and a fixed switching frequency of 1.6 MHz. The converter uses a
unique fast-response voltage-mode controller scheme with input voltage feedforward. This achieves excellent line
and load regulation (0.2%/A load regulation typical) and allows the use of small external components. To add
higher flexibility to the selection of external component values the device uses external loop compensation.
Although the boost converter looks like a nonsynchronous boost converter topology operating in discontinuous
mode at light load, the TPS65100 maintains continuous conduction even at light load currents. This is
accomplished using the Virtual Synchronous Converter Technology for improved load transient response. This
architecture uses an external Schottky diode and an integrated MOSFET in parallel connected between SW and
SUP (see the functional block diagram). The integrated MOSFET Q2 allows the inductor current to become
negative at light load conditions. For this purpose, a small integrated P-channel MOSFET with typically 10-Ω
rDSon is sufficient. When the inductor current is positive, the external Schottky diode with the lower forward
voltage conducts the current. This causes the converter to operate with a fixed frequency in continuous
conduction mode over the entire load current range. This avoids the ringing on the switch pin as seen with a
standard nonsynchronous boost converter and allows a simpler compensation for the boost converter.
VCOM Buffer
VCOMIN is the input of the VCOM buffer. If the VCOM buffer is not required for certain applications, it is possible
to shut down the VCOM buffer by connecting VCOMIN to ground, reducing the overall quiescent current. The
VCOM buffer features soft start, avoiding a large voltage drop at VO1 during start-up. The VCOMIN cannot be
pulled dynamically to ground during operation.
Enable and Power On Sequencing (EN, ENR)
The device has two enable pins. These pins should be terminated and should not be left floating to prevent
unpredictable operation. Pulling the enable pin (EN) high enables the device and starts the power-on sequencing
with the main boost converter VO1 coming up first, then the negative and positive charge pump and the VCOM
buffer. If the VCOMIN pin is held low, the VCOM buffer remains disabled. The linear regulator has an
independent enable pin (ENR). Pulling this pin low disables the regulator, and pulling this pin high enables this
regulator.
If the enable pin EN is pulled high, the device starts its power on sequencing. The main boost converter starts up
first with its soft start. If the output voltage has reached 91.25% of its output voltage, the negative charge pump
comes up next. The negative charge pump starts with a soft start and when the output voltage has reached 91%
of the nominal value, the positive charge pump comes up with a soft start. The VCOM buffer is enabled as soon
as the positive charge pump has reached its nominal value and VCOMIN is greater than typically 1.0 V. Pulling
the enable pin low shuts down the device. Depended on load current and output capacitance, each of the
outputs goes down.
Positive Charge Pump
The TPS65100 has a fully regulated integrated positive charge pump generating VO3. The input voltage for the
charge pump is applied to the SUP pin that is equal to the output of the main boost converter VO1. The charge
pump is capable of supplying a minimum load current of 20 mA. Depending on the voltage difference between
VO1 and VO3 higher load currents are possible (see Figure 13 and Figure 14).
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Negative Charge Pump
The TPS65100 has a regulated negative charge pump using two external Schottky diodes. The input voltage for
the charge pump is applied to the SUP pin that is connected to the output of the main boost converter VO1. The
charge pump inverts the main boost converter output voltage and is capable of supplying a minimum load current
of 20 mA. Depending on the voltage difference between VO1 and VO2, higher load currents are possible (see
Figure 12).
Linear Regulator Controller
The TPS65100 includes a linear regulator controller to generate a 3.3-V rail which is useful when the system is
powered from a 5-V supply. The regulator is independent from the other voltage rails of the device and has its
own enable (ENR). Since most of the systems require this voltage rail to come up first it is recommended to use
a R-C delay on EN. This delays the start-up of the main boost converter which will reduce the inrush current as
well.
Soft Start
The main boost converter as well as the charge pumps, linear regulator, and VCOM buffer have an internal soft
start. This avoids heavy voltage drops at the input voltage rail or at the output of the main boost converter VO1
during start-up caused by high inrush currents (see Figure 10 and Figure 11). During softstart of the main boost
converter VO1, the internal current limit threshold is increased in three steps. The device starts with the first step,
where the current limit is set to 2/5 of the typical current limit (2/5 of 2.3 A) for 1024 clock cycles, then increased
to 3/5 of the current limit for 1024 clock cycles, and finally raised to the full current limit.
Fault Protection
All the outputs of the TPS65100 have short-circuit detection that can force the device into shutdown. The main
boost converter has overvoltage and undervoltage protection. If the output voltage VO1 rises above the
overvoltage protection threshold of 5% of VO1 (typical), the device stops switching but remains operational. When
the output voltage falls below this threshold again, the converter continues operation. When the output voltage
falls below power good threshold of 8.75% of VO1 (typical), in case of a short-circuit condition, then the
TPS65100 goes into shutdown. Because there is a direct pass from the input to the output through the diode, the
short-circuit condition remains. If this condition needs to be avoided, a fuse at the input or an output disconnect
using a single transistor and resistor is required. The negative and positive charge pumps have an undervoltage
lockout to protect the LCD panel from possible latchup conditions in the event of a short-circuit condition or faulty
operation. When the negative output voltage is above 9.5% (typical) of its output voltage (closer to ground), the
device enters shutdown. When the positive charge pump output voltage VO3 is below 8% (typical) of its output
voltage, the device goes into shutdown as well. See the electrical characteristics table under fault protection
thresholds. The device can be enabled again by toggling the enable pin (EN) below 0.4 V or by cycling the input
voltage below the UVLO of 1.7 V. The linear regulator reduces the output current to typical 20 mA under a shortcircuit condition when the output voltage is < 1 V (typical). See the functional block diagram. The linear regulator
does not go into shutdown under a short-circuit condition.
Thermal Shutdown
A thermal shutdown is implemented to prevent damage due to excessive heat and power dissipation. Typically,
the thermal shutdown threshold is 160°C. If this temperature is reached, the device goes into shutdown. The
device can be enabled by toggling the enable pin to low and back to high or by cycling the input voltage to GND
and back to VI again.
12
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APPLICATION INFORMATION
BOOST CONVERTER DESIGN PROCEDURE
The first step in the design procedure is to calculate the maximum possible output current of the main boost
converter under certain input and output voltage conditions. This example is for a 3.3-V to 10-V conversion:
Vin = 3.3 V, Vout = 10 V, Switch voltage drop Vsw = 0.5 V, Schottky diode forward voltage VD = 0.8 V
1. Duty cycle
Vout ) V * V
D
in + 10 V ) 0.8 V * 3.3 V + 0.73
D+
V out ) V * V sw
10 V ) 0.8 V * 0.5 V
D
2. Average inductor current
I
I + out + 300 mA + 1.11 A
L
1 * 0.73
1*D
3. Inductor peak-to-peak ripple current
Di +
L
ƪVin * Vswƫ
fs
L
D
+
(3.3 V * 0.5 V) 0.73
+ 304 mA
1.6 MHz 4.2 mH
4. Peak switch current
Di
I
+ I ) L + 1.11 A ) 304 mA + 1.26 A
swpeak
L
2
2
The integrated switch, the inductor, and the external Schottky diode must be able to handle the peak switch
current. The calculated peak switch current must be equal to or lower than the minimum N-MOSFET switch
current limit specified in electrical characteristics. If the peak switch current is higher, the converter cannot
support the required load current. This calculation must be done for the minimum input voltage, where the peak
switch current is highest. The calculation includes conduction losses like switch rDSon (0.5 V) and diode forward
drop voltage losses (0.8 V). Additional switching losses, inductor core and winding losses, etc., require a slightly
higher peak switch current in the actual application. This calculation still allows for good design and component
selection.
Inductor Selection
Several inductors work with the TPS65100 and, particularly with the external compensation, performance can be
adjusted to application requirements. The main parameter for inductor selection is the saturation current of the
inductor, which should be higher than the peak switch current as previously calculated, with additional margin to
allow for heavy load transients and extreme start-up conditions. Another method is to choose an inductor with a
saturation current at least as high as the minimum switch current limit of 1.6 A. The different switch-current limits
allow selection of a physically smaller inductor when less output current is required. Another important parameter
is inductor dc resistance. Usually, the lower the dc resistance, the higher the efficiency. However, inductor dc
resistance is not the only parameter determining the efficiency. Especially for a boost converter where the
inductor is the energy storage element, the type and material of the inductor influences the efficiency as well. At
the high switching frequency of 1.6 MHz, inductor core losses, proximity effects, and skin effects are more
important. Usually, an inductor with a larger form factor yields higher efficiency. The efficiency difference
between different inductors can vary between 2% to 10%. Inductor values between 3.3 μH and 6.8 μH are a
good choice, but other values can be used. Possible inductors are shown in Table 1.
Table 1. Inductor Selection
INDUCTOR VALUE
COMPONENT SUPPLIER
DIMENSIONS (mm)
ISAT/DCR
4.7 μH
Coilcraft DO1813P-472HC
8,89 × 6,1 × 5
2.6 A/54 mΩ
4.2 μH
Sumida CDRH5D28 4R2
5,7 × 5,7 × 3
2.2 A/23 mΩ
4.7 μH
Sumida CDC5D23 4R7
6 × 6 × 2,5
1.6 A/48 mΩ
3.3 μH
Wuerth Elektronik 744042003
4,8 × 4,8 × 2
1.8 A/65 mΩ
4.2 μH
Sumida CDRH6D12 4R2
6,5 × 6,5 × 1,5
1.8 A/60 mΩ
3.3 μH
Sumida CDRH6D12 3R3
6,5 × 6,5 × 1,5
1.9 A/50 mΩ
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Output Capacitor Selection
For the best output voltage filtering, a low ESR output capacitor is recommended. Ceramic capacitors have a low
ESR value, but depending on the application, tantalum capacitors can be used as well. A 22-μF ceramic output
capacitor works for most of the applications. Higher capacitor values can be used to improve the load transient
regulation. See Table 2 for selection of the output capacitor. The output voltage ripple can be calculated as:
I
DV out + out
Cout
ƪ
ƫ
Ip L
1*
) Ip
f s Vout ) V * V
d
in
ESR
with:
IP = Peak switch current as calculated in the previous section with ISW(peak).
L = Selected inductor value
IOUT = Normal load current
fs = Switching frequency
Vd = Rectifier diode forward voltage (typical 0.3 V)
COUT = Selected output capacitor
ESR = Output capacitor ESR value
Input Capacitor Selection
For good input voltage filtering, low ESR ceramic capacitors are recommended. A 22-μF ceramic input capacitor
is sufficient for most of the applications. For better input voltage filtering, this value can be increased. See
Table 2 and the typical applications for input capacitor recommendations.
Table 2. Input and Output Capacitors Selection
CAPACITOR
VOLTAGE RATING
COMPONENT SUPPLIER
COMMENTS
22 μF/1210
16 V
Taiyo Yuden EMK325BY226MM
Cout
22 μF/1206
6.3 V
Taiyo Yuden JMK316BJ226
Cin
Rectifier Diode Selection
To achieve high efficiency, a Schottky diode should be used. The voltage rating should be higher than the
maximum output voltage of the converter. The average forward current should be equal to the average inductor
current of the converter. The main parameter influencing the efficiency of the converter is the forward voltage and
the reverse leakage current of the diode; both should be as low as possible. Possible diodes are: On
Semiconductor MBRM120L, Microsemi UPS120E, and Fairchild Semiconductor MBRS130L.
Converter Loop Design and Stability
The TPS65100 converter loop can be externally compensated and allows access to the internal
transconductance error amplifier output at the COMP pin. A small feedforward capacitor across the upper
feedback resistor divider speeds up the circuit as well. To test the converter stability and load transient
performance of the converter, a load step from 50 mA to 250 mA is applied, and the output voltage of the
converter is monitored. Applying load steps to the converter output is a good tool to judge the stability of such a
boost converter.
14
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Design Procedure Quick Steps
1.
2.
3.
4.
Select the feedback resistor divider to set the output voltage.
Select the feedforward capacitor to place a zero at 50 kHz.
Select the compensation capacitor on pin COMP. The smaller the value, the higher the low frequency gain.
Use a 50-kΩ potentiometer in series to Cc and monitor Vout during load transients. Fine tune the load
transient by adjusting the potentiometer. Select a resistor value that comes closest to the potentiometer
resistor value. This needs to be done at the highest Vin and highest load current since the stability is most
critical at these conditions.
Setting the Output Voltage and Selecting the Feedforward Capacitor
The output voltage is set by the external resistor divider and is calculated as:
V out + 1.146 V
ƫ
ƪ1 ) R1
R2
Across the upper resistor a bypass capacitor is required to speed up the circuit during load transients as shown
in Figure 15.
VO1
Up to 10 V/150 mA
D1
C8
6.8 pF
SW
SW
R1
430 kΩ
C4
22 µF
FB1
SUP
C2+
C2−/MODE
C2
0.22 µF
R2
56 kΩ
Figure 15. Feedforward Capacitor
Together with R1 the bypass capacitor C8 sets a zero in the control loop at approximately 50 kHz:
1
ƒz +
2 p C8 R1
A value closest to the calculated value should be used. Larger feedforward capacitor values reduce the load
regulation of the converter and cause load steps as shown in Figure 16.
Load Step
Figure 16. Load Step Caused By A Too Large Feedforward Capacitor Value
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Compensation
The regulator loop can be compensated by adjusting the external components connected to the COMP pin. The
COMP pin is connected to the output of the internal transconductance error amplifier. A typical compensation
scheme is shown in Figure 17.
RC
15 kΩ
CC
VIN
COMP
1 nF
Figure 17. Compensation Network
The compensation capacitor CC adjusts the low frequency gain and the resistor value adjusts the high frequency
gain. The formula below calculates at what frequency the resistor increases the high frequency gain.
1
fz +
2 p Cc Rc
Lower input voltages require a higher gain and therefore a lower compensation capacitor value. A good start is
CC = 1 nF for a 3.3-V input and CC = 2.2 nF for a 5-V input. If the device operates over the entire input voltage
range from 2.7 V to 5.8 V, a large compensation capacitor up to 10 nF is recommended. Figure 18 shows the
load transient with a larger compensation capacitor, and Figure 19 shows a smaller compensation capacitor.
Figure 18. Cc = 4.7 nF
Figure 19. Cc = 1 nF
Finally, Rc needs to be selected. A good practice is to use a 50-kΩ potentiometer and adjust the potentiometer
for best load transient where no oscillations should occur. These tests have to be done at the highest Vin and
highest load current because converter stability is most critical under these conditions. Figure 20, Figure 21, and
Figure 22 show the fine tuning of the loop with Rc.
16
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Figure 20. Overcompensated (Damped Oscillation), Rc Is Too Large
Figure 21. Undercompensated (Loop Is Too Slow), Rc Is Too Small
Figure 22. Optimum, Rc Is Ideal
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Negative Charge Pump
The negative charge pump provides a regulated output voltage by inverting the main output voltage VO1. The
negative charge pump output voltage is set with external feedback resistors.
The maximum load current of the negative charge pump depends on the voltage drop across the external
Schottky diodes, the internal on resistance of the charge pump MOSFETS Q8 and Q9, and the impedance of the
flying capacitor C12. When the voltage drop across these components is larger than the voltage difference from
VO1 to VO2, the charge pump is in dropout, providing the maximum possible output current. Therefore, the higher
the voltage difference between VO1 and VO2, the higher the possible load current. See Figure 12 for the possible
output current versus boost converter voltage VO1.
VO (min) = –(VO – 2 VD – Io (2 × rDS(on)Q8 + 2 × rDS(on)Q9 + Xcfly))
Setting the output voltage:
VOUT = -VREF x R3 = -1.213 V x R3
R4
R4
|VOUT|
|VOUT|
R3 = R4 x
= R4 x
VREF
1.213
The lower feedback resistor value R4 should be in a range between 40 kΩ to 120 kΩ or the overall feedback
resistance should be within 500 kΩ to 1 MΩ. Smaller values load the reference too heavily and larger values may
cause stability problems. The negative charge pump requires two external Schottky diodes. The peak current
rating of the Schottky diode has to be twice the load current of the output. For a 20-mA output current, the dual
Schottky diode BAT54 or similar is a good choice.
Positive Charge Pump
The positive charge pump can be operated in a voltage doubler mode or a voltage tripler mode depending on the
configuration of the C2+ and C2-/MODE pins. Leaving the C2+ pin open and connecting C2-/MODE to GND
forces the positive charge pump to operate in a voltage doubler mode. If higher output voltages are required, the
positive charge pump can be operated as a voltage tripler. To operate the charge pump in the voltage tripler
mode, a flying capacitor needs to be connected to C2+ and C2-/MODE.
The maximum load current of the positive charge pump depends on the voltage drop across the internal Schottky
diodes, the internal on resistance of the charge pump MOSFETS, and the impedance of the flying capacitor.
When the voltage drop across these components is larger than the voltage difference VO1 × 2 to VO3 (doubler
mode) or VO1 × 3 to VO3 (tripler mode), then the charge pump is in dropout, providing the maximum possible
output current. Therefore, the higher the voltage difference between VO1 × 2 (doubler) or VO1 × 3 (tripler) to VO3,
the higher the possible load current. See Figure 13 and Figure 14 for the output current versus boost converter
voltage VO1 and the following calculations.
Voltage doubler:
VO3max = 2 × VO1 – (2 VD + 2 × Io × (2 × rDS(on)Q5 + rDS(on)Q3 + rDS(on)Q4 + XC1))
Voltage tripler:
VO3max = 3 × VO1 – (3 × VD + 2 × Io × (3 × rDS(on)Q5 + rDS(on)Q3 + rDS(on)Q4 + XC1 + XC2))
The output voltage is set by the external resistor divider and is calculated as:
ƫ
ƪ1 ) R5
R6
V out + 1.214
R5 + R6
18
ƪ
Vout
V
FB
ƫ
*1
+ R6
(1)
ƪ
V out
1.214
ƫ
*1
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VCOM Buffer
The VCOM buffer is typically used to drive the backplane of a TFT panel. The VCOM output voltage is typically
set to half of the main output voltage VO1 plus a small shift to implement the specific compensation voltage. The
TFT video signal gets coupled through the TFT storage capacitor plus the LCD cell capacitance to the output of
the VCOM buffer. Because of these, short current pulses in the positive and negative direction appear at the
output of the VCOM buffer. To minimize the output voltage ripple caused by the current pulses, a
transconductance amplifier having a current source output and an output capacitor is used. The output capacitor
supports the high frequency part of the current pulses drawn from the LCD panel. The VCOM buffer only needs
to handle the low frequency portion of the current pulses. A 1-μF ceramic output capacitor is sufficient for most of
the applications. When using other output capacitor values it is important to keep in mind that the output
capacitor is part of the VCOM buffer loop stabilization.
The VCOM buffer has an integrated soft start to avoid voltage drops on VO1 during start-up. The soft start is
implemented as such that the VCOMIN is held low until the VCOM buffer is fully biased and the common mode
range is reached. Then the positive input is released and the VCOM buffer output slowly comes up. Usually a 1nF capacitor on VCOMIN to GND is used to filter high frequency noise coupled in from VO1. The size of this
capacitor together with the upper feedback resistor value determines the start-up time. The larger the capacitor
from VCOMIN to GND, the slower the soft start.
Linear Regulator Controller
The TPS65100 includes a linear regulator controller to generate a 3.3-V rail when the system is powered from a
5-V supply. Because an external npn transistor is required, the input voltage of the TPS65100 applied to VIN
needs to be higher than the output voltage of the regulator. To provide a minimum base drive current of 13.5 mA,
a minimum internal voltage drop of 500 mV from Vin to Vbase is required. This can be translated into a minimum
input voltage on VIN for a certain output voltage as the following calculation shows:
VINmin= VO4 + VBE + 0.5 V
The base drive current together with the hFE of the external transistor determines the possible output current.
Using a standard npn transistor like the BCP68 allows an output current of 1 A and using the BCP54 allows a
load current of 337 mA for an input voltage of 5 V. Other transistors can be used as well depending on the
required output current, power dissipation, and PCB space. The device is stable with a 4.7-μF ceramic output
capacitor. Larger output capacitor values can be used to improve the load transient response when higher load
currents are required.
Layout Considerations
For all switching power supplies, the layout is an important step in the design, especially at high-peak currents
and switching frequencies. If the layout is not carefully designed, the regulator might show stability and EMI
problems. Therefore, the traces carrying high-switching currents should be routed first using wide and short
traces. The input filter capacitor should be placed as close as possible to the input pin VIN of the IC. See the
evaluation module (EVM) for a layout example.
Thermal Information
An influential component of thermal performance of a package is board design. To take full advantage of the
heat dissipation abilities of the PowerPAD package with exposed thermal die, a board that acts similar to a heat
sink and allows the use of an exposed (and solderable) deep downset pad should be used. For further
information, see the Texas Instruments application reports PowerPAD Thermally Enhanced Package (SLMA002)
and PowerPAD Made Easy (SLMA004).
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VI
3.3 V
L1
3.3 µH
C3
22 µF
Vo1
R9
15 kΩ
R7
500 kΩ
C14
1 nF
C5
0.22 µF
VIN
COMP
R8
500 kΩ
D2
VO2
−5 V/20 mA
R3
620 kΩ
C8
6.8 pF
TPS65100
C9
1 nF
C1
0.22 µF
C12
0.22 µF
D3
SW
SW
VCOMIN
FB1
EN
SUP
ENR
C1+
C1−
DRV
C2+
C2−/MODE
C2
0.22 µF
R1
430 kΩ
VO3
23 V/20 mA
FB3
VCOM
REF
FB4
PGND
C4
22 µF
R2
56 kΩ
OUT3
FB2
BASE
VO1
10 V/300 mA
D1
R5
1M
PGND
C6
0.22 µF
GND
R3
150 kΩ
R6
56 kΩ
C11
220 nF
Vcom
5V
C7
1 µF
Figure 23. Typical Application, Notebook supply
20
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L1
4.7 µH
CDRH5D18−4R1
Vin
5V
C3
22 µF
R9
4.3 kΩ
R7
500 kΩ
VO1
VIN
COMP
VCOMIN
C14
1 nF
VO2
−7 V/20 mA
R8
500 kΩ
C1
0.22 µF
C12
0.22 µF
D2
C6
0.22 µF
C5
3.3 pF
TPS65100
C9
2.2 nF
R3
750 kΩ
D3
EN
ENR
C1+
C1−
DRV
FB2
REF
FB4
BASE
VO1
13.5 V/400 mA
D1
SW
SW
FB1
SUP
C2+
C2−/MODE
R2
75 kΩ
VO3
23 V/20 mA
OUT3
FB3
VCOM
PGND
PGND
GND
C7
0.22 µF
R5
1 MΩ
R4
130 kΩ
C11
220 nF
C4
22 µF
R1
820 kΩ
R6
56 kΩ
Q1
BCP68
Vin
C12
1 µF
Vcom
7V
VO4
3.3 V/500 mA
C10
4.7 µF
C8
1 µF
Figure 24. Typical Application, Monitor Supply
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Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65100-Q1
21
TPS65100-Q1
SLVS849A – JULY 2008 – REVISED APRIL 2012
www.ti.com
REVISION HISTORY
Changes from Original (July, 2008) to Revision A
•
22
Page
Added thermal table for PWP package. ............................................................................................................................... 3
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Copyright © 2008–2012, Texas Instruments Incorporated
Product Folder Link(s): TPS65100-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TPS65100QPWPRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
HTSSOP
PWP
24
2000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-3-260C-168 HR
(4)
-40 to 125
65100Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS65100-Q1 :
• Catalog: TPS65100
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TPS65100QPWPRQ1
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
24
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Jan-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65100QPWPRQ1
HTSSOP
PWP
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
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