16-Bit, 1.33 MSPS PulSAR ADC in MSOP/QFN AD7983

16-Bit, 1.33 MSPS PulSAR ADC in MSOP/QFN AD7983
16-Bit, 1.33 MSPS PulSAR ADC in
MSOP/QFN
AD7983
APPLICATION DIAGRAM
2.9V TO 5V
16-bit resolution with no missing codes
Throughput: 1.33 MSPS
Low power dissipation: 10.5 mW typical @ 1.33 MSPS
INL: ±0.6 LSB typical, ±1.0 LSB maximum
SINAD: 91.6 dB @ 10 kHz
THD: −115 dB @ 10 kHz
Pseudo differential analog input range
0 V to VREF with VREF between 2.9 V to 5.5 V
Any input range and easy to drive with the ADA4841
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
Serial interface SPI-/QSPI™-/MICROWIRE™-/DSP-compatible
Daisy-chain multiple ADCs and busy indicator
10-lead MSOP (MSOP-8 size) and 10-lead 3 mm × 3 mm QFN
(LFCSP), SOT-23 size
Wide operating temperature range: −40°C to +85°C
0 TO VREF
IN+
IN–
2.5V
REF VDD VIO
SDI
AD7983
SCK
SDO
GND
1.8V TO 5V
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
CNV
06974-001
FEATURES
Figure 1.
GENERAL DESCRIPTION
APPLICATIONS
The AD7983 is a 16-bit, successive approximation, analog-todigital converter (ADC) that operates from a single power
supply, VDD. It contains a low power, high speed, 16-bit
sampling ADC and a versatile serial interface port. On the CNV
rising edge, it samples an analog input IN+ between 0 V to REF
with respect to a ground sense IN−. The reference voltage, REF,
is applied externally and can be set independent of the supply
voltage, VDD. Its power scales linearly with throughput.
Battery-powered equipment
Communications
ATE
Data acquisitions
Medical instruments
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional busy indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7983 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC
Type
14-Bit
16-Bit
100 kSPS
AD7940
AD7680
AD7683
AD7684
18-Bit
1
250 kSPS
AD79421
AD76851
AD76871
AD7694
AD7691 1
400 kSPS to 500 kSPS
AD79461
AD76861
AD76881
AD76931
AD76901
≥1000 kSPS
ADC Driver
AD79801
AD79831
ADA4941
ADA4841
AD79821
AD79841
ADA4941
ADA4841
Pin-for-pin compatible.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD7983
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 14
Applications ....................................................................................... 1
Voltage Reference Input ............................................................ 15
Application Diagram ........................................................................ 1
Power Supply............................................................................... 15
General Description ......................................................................... 1
Digital Interface .......................................................................... 16
Revision History ............................................................................... 2
CS MODE, 3-Wire Without Busy Indicator ........................... 17
Specifications..................................................................................... 3
CS Mode, 3-Wire with Busy Indicator .................................... 18
Timing Specifications....................................................................... 5
CS Mode, 4-Wire Without Busy Indicator ............................. 19
Absolute Maximum Ratings............................................................ 6
CS Mode, 4-Wire with Busy Indicator .................................... 20
ESD Caution .................................................................................. 6
Chain Mode Without Busy Indicator ...................................... 21
Pin Configurations and Function Descriptions ........................... 7
Chain Mode with Busy Indicator ............................................. 22
Typical Performance Characteristics ............................................. 8
Application Hints ........................................................................... 23
Terminology .................................................................................... 11
Layout .......................................................................................... 23
Theory of Operation ...................................................................... 12
Evaluating the Performance of the AD7983............................... 23
Circuit Information .................................................................... 12
Outline Dimensions ....................................................................... 24
Converter Operation .................................................................. 12
Ordering Guide .......................................................................... 24
Typical Connection Diagram ................................................... 13
Analog Inputs .............................................................................. 14
REVISION HISTORY
3/10—Rev. 0 to Rev. A
Deleted Endnote 1 from Features Section, General Description
Section, and Table 1 .......................................................................... 1
Changes to Table 5 ............................................................................ 6
Deleted Endnote 1 from Figure 5 Caption .................................... 7
Changes to Figure 21 ...................................................................... 12
Deleted Endnote 1 from Circuit Information Section............... 12
Changes to Figure 41 Caption....................................................... 24
Changes to Ordering Guide .......................................................... 24
11/07—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD7983
SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = –40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Analog Input CMRR
Leakage Current @ 25°C
Input Impedance
ACCURACY
No Missing Codes
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error, TMIN to TMAX 3
Gain Error Temperature Drift
Zero Error, TMIN to TMAX3
Zero Temperature Drift
Power Supply Sensitivity
THROUGHPUT
Conversion Rate
Transient Response
AC ACCURACY
Dynamic Range
Signal-to-Noise Ratio, SNR
Spurious-Free Dynamic Range, SFDR
Total Harmonic Distortion, THD
Signal-to-(Noise + Distortion), SINAD
1
2
3
Conditions
Min
16
IN+ − IN−
IN+
IN−
fIN = 100 kHz
Acquisition phase
0
−0.1
−0.1
Typ
Unit
Bits
VREF
VREF + 0.1
+0.1
V
V
V
dB 1
nA
60
1
See the Analog Inputs section
16
−0.9
−1.0
−0.9
VDD = 2.5 V ± 5%
±0.4
±0.6
0.52
±2
±0.41
±0.44
0.54
±0.1
0
90.5
+0.9
+1.0
+0.9
1.33
290
Full-scale step
fIN = 1 kHz
fIN = 10 kHz
fIN = 10 kHz
fIN = 10 kHz
Max
93
92
114
−115
91.6
All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 μV.
See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.
Rev. A | Page 3 of 24
Bits
LSB 2
LSB2
LSB2
LSB2
ppm/°C
mV
ppm/°C
LSB2
MSPS
ns
dB1
dB1
dB1
dB1
dB1
AD7983
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, REF = 5 V, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
VIH
VIL
VIH
IIL
IIH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Conditions
VOL
VOH
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current 1, 2
Power Dissipation
Energy per Conversion
TEMPERATURE RANGE 3
Specified Performance
ISINK = 500 μA
ISOURCE = −500 μA
Min
Typ
Max
Unit
5.1
500
V
μA
10
2.0
MHz
ns
2.9
1.33 MSPS
VIO > 3V
VIO > 3V
VIO ≤ 3V
VIO ≤ 3V
Specified performance
–0.3
0.7 × VIO
–0.3
0.9 × VIO
−1
−1
Serial 16 bits straight binary
Conversion results available immediately
after completed conversion
0.4
VIO − 0.3
2.375
2.3
1.8
VDD and VIO = 2.5 V
1.33 MSPS throughput
TMIN to TMAX
0.3 × VIO
VIO + 0.3
0.1 × VIO
VIO + 0.3
+1
+1
2.5
0.35
10.5
7.9
−40
1
With all digital inputs forced to VIO or GND as required.
During the acquisition phase.
3
Contact sales for extended temperature range.
2
Rev. A | Page 4 of 24
2.625
5.5
5.5
12
+85
V
V
V
V
μA
μA
V
V
V
V
V
nA
mW
nJ/sample
°C
AD7983
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise noted. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Period (Chain Mode)
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 3 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
IOL
tSCKL
tSCKH
tHSDO
tDSDO
tDIS
tSSDICNV
tHSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
IOH
10.5
12
13
15
ns
ns
ns
ns
11.5
13
14
16
4.5
4.5
3
ns
ns
ns
ns
ns
ns
ns
9.5
11
12
14
ns
ns
ns
ns
10
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
2
0
5
5
2
3
15
tDELAY
VIH2
VIL2
1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
2MINIMUM V AND MAXIMUM V USED. SEE DIGITAL INPUTS
IH
IL
06974-002
500µA
SPECIFICATIONS IN TABLE 3.
Figure 2. Load Circuit for Digital Interface Timing
Figure 3. Voltage Levels for Timing
Rev. A | Page 5 of 24
Unit
ns
ns
ns
ns
Y% VIO1
VIH2
VIL2
1.4V
Max
500
tEN
X% VIO1
CL
20pF
Typ
tSCK
tDELAY
TO SDO
Min
300
250
750
10
06974-003
500µA
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
AD7983
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Analog Inputs
IN+, 1 IN−1 to GND
Supply Voltage
REF, VIO to GND
VDD to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
10-Lead MSOP
10-Lead QFN (LFCSP)
θJC Thermal Impedance
10-Lead MSOP
10-Lead QFN (LFCSP)
Lead Temperature
Vapor Phase (60 sec)
Infrared (15 sec)
1
Rating
−0.3 V to VREF + 0.3 V or ±130 mA
−0.3 V to +6 V
−0.3 V to +3 V
+3 V to −6 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
200°C/W
48.7°C/W
44°C/W
2.96°C/W
215°C
220°C
See the Analog Inputs section.
Rev. A | Page 6 of 24
AD7983
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
9
SDI
8
SCK
7
SDO
6
CNV
IN+ 3
IN– 4
AD7983
TOP VIEW
(Not to Scale)
GND 5
REF 1
10 VIO
VDD 2
9 SDI
IN+ 3
IN– 4
GND 5
AD7983
TOP VIEW
(Not to Scale)
8 SCK
7 SDO
6 CNV
06974-005
10 VIO
06974-004
REF 1
VDD 2
Figure 5. 10-Lead QFN (LFCSP) Pin Configuration
Figure 4. 10-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
Mnemonic
REF
Type 1
AI
2
3
VDD
IN+
P
AI
4
5
6
IN−
GND
CNV
AI
P
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
10
VIO
P
1
Description
Reference Input Voltage. The REF range is from 2.9 V to 5.1 V. It is referred to the GND pin. This pin should
be decoupled closely to the pin with a 10 μF capacitor.
Power Supply.
Analog Input. It is referred to IN−. The voltage range, for example, the difference between IN+ and IN−, is
0 V to VREF.
Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Convert Input. This input has multiple functions. On its risng edge, it initiates the conversions and
selects the interface mode of the part: chain or CS mode. In CS mode, it enables the SDO pin when low.
In chain mode, the data should be read when CNV is high.
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low; if SDI or CNV is low when the conversion is complete,
the busy indicator feature is enabled.
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. A | Page 7 of 24
AD7983
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, REF = 5 V, VIO = 3.3 V, unless otherwise noted.
1.25
1.00
POSITIVE INL: 0.30LSB
NEGATIVE INL: –0.37LSB
1.00
POSITIVE DNL: 0.14LSB
NEGATIVE DNL: –0.14LSB
0.75
0.75
0.50
0.25
DNL (LSB)
INL (LSB)
0.50
0
–0.25
0.25
0
–0.25
–0.50
–0.50
–0.75
0
16384
32768
–1.00
65536
49152
06974-029
–1.25
–0.75
06974-026
–1.00
0
16384
32768
CODE
65536
49152
CODE
Figure 6. Integral Nonlinearity vs. Code
Figure 9. Differential Nonlinearity vs. Code
120k
80k
67532
70k
96765
100k
61565
60k
50k
COUNTS
COUNTS
80k
60k
40k
30k
40k
20k
0
0
0
0
58
55
0
0
0
0
10k
0
0
7FB6 7FB7 7FB8 7FB9 7FBA 7FBB 7FBC 7FBD 7FBE 7FBF 7FC0 7FC1 7FC2
0
0
CODE IN HEX
94
93
SNR (dB)
92
–80
–100
–120
91
90
89
88
–140
0
100
200
300
400
500
06974-032
87
–160
–180
0
95
06974-028
AMPLITUDE (dB of Full Scale)
–60
0
CODE IN HEX
SNR = 91.6dB
THD = –114.9dB
SFDR = 113.8dB
SINAD = 91.6dB
–40
0
Figure 10. Histogram of a DC Input at the Code Transition
fS = 1.33MSPS
fIN = 10kHz
–20
0
7FF7 7FF8 7FF9 7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003
Figure 7. Histogram of a DC Input at the Code Center
0
1146 0
829
0
06974-042
0
17590
06974-041
16604
20k
86
85
–10
600
FREQUENCY (kHz)
–9
–8
–7
–6
–5
–4
–3
INPUT LEVEL (dB of Full Scale)
Figure 8. FFT Plot
Figure 11. SNR vs. Input Level
Rev. A | Page 8 of 24
–2
–1
0
–110
95
–112
93
–114
91
SNR (dB)
–116
89
06974-038
–35
–15
5
25
45
65
85
105
85
–55
125
–35
–15
5
25
45
65
85
105
Figure 12. THD vs. Temperature
Figure 15. SNR vs. Temperature
–105
130
–110
125
16
100
15
SNR
ENOB
SNR, SINAD (dB)
115
SFDR (dB)
120
THD
–120
90
SFDR
SINAD
85
14
13
110
–130
2.5
3.0
3.5
4.0
4.5
5.0
105
5.5
REFERENCE VOLTAGE (V)
80
2.5
06974-033
–125
3.0
3.5
4.0
4.5
5.0
12
5.5
REFERENCE VOLTAGE (V)
Figure 13. THD, SFDR vs. Reference Voltage
Figure 16. SNR, SINAD, and ENOB vs. Reference Voltage
–70
100
–75
95
–80
90
–85
THD (dB)
85
80
–90
–95
–100
–105
75
65
1
10
100
06974-037
–110
70
06974-034
SINAD (dB)
THD (dB)
95
–115
125
TEMPERATURE (°C)
TEMPERATURE (°C)
ENOB (Bits)
–120
–55
06974-035
87
–118
06974-031
THD (dB)
AD7983
–115
–120
1000
1
10
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 14. SINAD vs. Frequency
Figure 17. THD vs. Frequency
Rev. A | Page 9 of 24
1000
AD7983
1.5
2.5
1.4
1.3
2.0
STANDBY CURRENTS (mA)
1.5
1.0
IREF
0
2.375
06974-036
IVIO
2.425
2.475
2.525
2.575
2.625
1.0
0.9
0.8
2.5
IVDD
2.0
1.5
1.0
IREF
–15
5
25
06974-039
IVIO
–35
45
0.5
–55
–35
–15
5
25
45
65
85
Figure 20. Standby Currents vs. Temperature
Figure 18. Operating Currents vs. Supply
0.5
0.6
TEMPERATURE (°C)
VDD VOLTAGE (V)
OPERATING CURRENTS (mA)
IVDD + IVIO
1.1
0.7
0.5
0
–55
1.2
06974-040
OPERATING CURRENTS (mA)
IVDD
65
85
105
125
TEMPERATURE (°C)
Figure 19. Operating Currents vs. Temperature
Rev. A | Page 10 of 24
105
125
AD7983
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 22).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 μV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should
occur for an analog voltage 1½ LSB below the nominal full
scale (4.999886 V for the 0 V to 5 V range). The gain error is
the deviation of the actual level of the last transition from the
ideal level after the offset is adjusted out.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in dB. It is measured
with a signal at −60 dBFS to include all noise sources and DNL
artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Aperture Delay
Aperture delay is the measurement of the acquisition performance.
It is the time between the rising edge of the CNV input and
when the input signal is held for a conversion.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD as follows:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which
it is impossible to distinctly resolve individual codes. It is
calculated as
Transient Response
Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function is
applied.
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Rev. A | Page 11 of 24
AD7983
THEORY OF OPERATION
IN+
MSB
LSB
32,768C
16,384C
4C
2C
C
SWITCHES CONTROL
SW+
C
BUSY
REF
COMP
GND
32,768C
16,384C
4C
2C
C
CONTROL
LOGIC
OUTPUT CODE
C
LSB
SW+
CNV
06974-006
MSB
IN–
Figure 21. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7983 is a fast, low power, single-supply, precise 16-bit
ADC that uses a successive approximation architecture.
The AD7983 is capable of converting 1,000,000 samples per
second (1 MSPS) and powers down between conversions. When
operating at 10 kSPS, for example, it consumes 70 μW typically,
making it ideal for battery-powered applications.
The AD7983 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7983 can be interfaced to any 1.8 V to 5 V digital logic
family. It is available in a 10-lead MSOP or a tiny 10-lead QFN
(LFCSP) that allows space savings and flexible configurations.
It is pin-for-pin compatible with the 18-bit AD7982.
CONVERTER OPERATION
The AD7983 is a successive approximation ADC based on a
charge redistribution DAC. Figure 21 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
input of the comparator are connected to GND via SW+ and
SW−. All independent switches are connected to the analog
inputs. Therefore, the capacitor arrays are used as sampling
capacitors and acquire the analog signal on the IN+ and IN−
inputs. When the acquisition phase is complete and the CNV
input goes high, a conversion phase is initiated. When the
conversion phase begins, SW+ and SW− are opened first. The two
capacitor arrays are then disconnected from the inputs and
connected to the GND input. Therefore, the differential voltage
between the inputs IN+ and IN− captured at the end of the
acquisition phase is applied to the comparator inputs, causing
the comparator to become unbalanced. By switching each
element of the capacitor array between GND and REF, the
comparator input varies by binary weighted voltage steps
(VREF/2, VREF/4 … VREF/65,536). The control logic toggles these
switches, starting with the MSB, to bring the comparator back
into a balanced condition. After the completion of this process,
the part returns to the acquisition phase and the control logic
generates the ADC output code and a busy signal indicator.
Because the AD7983 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. A | Page 12 of 24
AD7983
Transfer Functions
Table 7. Output Codes and Ideal Input Voltages
The ideal transfer characteristic for the AD7983 is shown in
Figure 22 and Table 7.
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
111 ... 101
1
2
Analog Input
Digital Output Code (Hex)
FFFF1
8001
8000
7FFF
0001
00002
This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
000 ... 010
Figure 23 shows an example of the recommended connection
diagram for the AD7983 when multiple supplies are available.
000 ... 001
–FSR –FSR + 1LSB
–FSR + 0.5LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
ANALOG INPUT
Figure 22. ADC Ideal Transfer Function
REF1
V+
2.5V
10µF2
100nF
V+
1.8V TO 5V
100nF
20Ω
REF
0 TO VREF
2.7nF
V–
VDD
VIO
IN+
SDI
SCK
AD7983
4
IN–
GND
3- OR 4-WIRE INTERFACE
SDO
CNV
1SEE THE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2C
REF IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
3SEE THE DRIVER AMPLIFIER CHOICE SECTION.
4OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION.
5SEE THE DIGITAL INTERFACE SECTION FOR THE MOST CONVENIENT INTERFACE MODE.
Figure 23. Typical Application Diagram with Multiple Supplies
Rev. A | Page 13 of 24
06974-008
000 ... 000
06974-007
ADC CODE (STRAIGHT BINARY)
111 ... 111
111 ... 110
VREF = 5 V
4.999924 V
2.500076 V
2.5 V
2.499924 V
76.3 μV
0V
AD7983
ANALOG INPUTS
DRIVER AMPLIFIER CHOICE
Figure 24 shows an equivalent circuit of the input structure of
the AD7983.
Although the AD7983 is easy to drive, the driver amplifier
needs to meet the following requirements:
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes these diodes to become forwardbiased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions could eventually occur when the supplies of
the input buffer (U1) are different from VDD. In such a case
(for example, an input buffer with a short circuit), the current
limitation can be used to protect the part.
•
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7983. The noise coming from
the driver is filtered by the AD7983 analog input circuit’s
1-pole, low-pass filter made by RIN and CIN or by the external
filter, if one is used. Because the typical noise of the AD7983 is
39.7 μV rms, the SNR degradation due to the amplifier is
SNRLOSS
REF
D1
IN+
OR IN–
CIN
D2
GND
Figure 24. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination of
capacitor, CPIN, and the network formed by the series connection of
RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component made up of some serial
resistors and the on resistance of the switches. CIN is typically
30 pF and is mainly the ADC sampling capacitor. During the
conversion phase, where the switches are opened, the input
impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass
filter that reduces undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7983 can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
⎞
⎟
⎟
⎟
⎟
⎠
where:
f–3dB is the input bandwidth in MHz of the AD7983
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
06974-009
CPIN
RIN
⎛
⎜
39.7
= 20 log ⎜
⎜
π
2
2
⎜ 39.7 + f −3dB (Ne N )
2
⎝
•
For ac applications, the driver should have a THD
performance commensurate with the AD7983.
•
For multichannel multiplexed applications, the driver
amplifier and the AD7983 analog input circuit must settle
for a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the data sheet of the amplifier, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier
ADA4841-x
AD8021
AD8022
OP184
AD8655
AD8605, AD8615
Rev. A | Page 14 of 24
Typical Application
Very low noise, small and low power
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
5 V single-supply, low noise
5 V single-supply, low power
AD7983
VOLTAGE REFERENCE INPUT
POWER SUPPLY
The AD7983 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
The AD7983 uses two power supply pins: a core supply (VDD) and
a digital input/output interface supply (VIO). VIO allows direct
interface with any logic between 1.8 V and 5.0 V. To reduce the
number of supplies needed, VIO and VDD can be tied together.
The AD7983 is independent of power supply sequencing between
VIO and VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 25.
80
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
PSRR (dB)
If desired, a reference-decoupling capacitor value as small as
2.2 μF can be used with a minimal impact on performance,
especially DNL.
75
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
70
65
60
55
1
10
100
FREQUENCY (kHz)
1000
06974-010
When REF is driven by a very low impedance source, for example,
a reference buffer using the AD8031 or the AD8605, a ceramic
chip capacitor is appropriate for optimum performance.
Figure 25. PSRR vs. Frequency
To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example, if REF is 5.0 V,
VDD should be set to 2.5 V (±5%).
Rev. A | Page 15 of 24
AD7983
DIGITAL INTERFACE
Though the AD7983 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7983 is compatible with SPI, QSPI,
and digital hosts. This interface can use either a 3-wire or a 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections useful, for instance, in
isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates the conversions,
to be independent of the readback timing (SDI). This is useful
in low jitter sampling or simultaneous sampling applications.
The AD7983, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected,
the chain mode is always selected.
In either mode, the AD7983 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
The busy indicator feature is enabled
• In CS mode if CNV or SDI is low when the ADC conversion
ends (see Figure 29 and Figure 33).
• In chain mode if SCK is high during the CNV rising edge
(see Figure 37).
Rev. A | Page 16 of 24
AD7983
When CNV goes low, the MSB is output onto SDO. The
remaining data bits are then clocked by subsequent SCK falling
edges. The data is valid on both SCK edges. Although the rising
edge can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate provided that it has an
acceptable hold time. After the 16th SCK falling edge or when
CNV goes high, whichever is earlier, SDO returns to high
impedance.
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 26, and the corresponding timing is given in
Figure 27.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. When a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for example, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
high for the maximum conversion time to avoid the generation
of the busy signal indicator. When the conversion is complete, the
AD7983 enters the acquisition phase and goes into standby mode.
CONVERT
DIGITAL HOST
CNV
VIO
SDI
AD7983
SDO
DATA IN
06974-012
SCK
CLK
Figure 26. CS Mode, 3-Wire Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
2
3
14
tHSDO
16
tSCKH
tEN
SDO
15
tDSDO
D15
D14
D13
tDIS
D1
D0
Figure 27. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Rev. A | Page 17 of 24
06974-013
1
SCK
AD7983
If multiple AD7983s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended that this contention be
kept as short as possible to limit extra power dissipation.
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host that has an interrupt input.
The connection diagram is shown in Figure 28, and the
corresponding timing is given in Figure 29.
CONVERT
SDI = 1
VIO
CNV
VIO
SDI
AD7983
DIGITAL HOST
47kΩ
SDO
DATA IN
SCK
IRQ
06974-014
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data read back controlled by the
digital host. The AD7983 then enters the acquisition phase and
goes into standby mode. The data bits are then clocked out,
MSB first, by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
optional 17th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CLK
Figure 28. CS Mode, 3-Wire with Busy Indicator
Connection Diagram (SDI High)
tCYC
tCNVH
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
1
2
3
15
tHSDO
16
17
tSCKH
tDIS
tDSDO
SDO
D15
D14
D1
D0
Figure 29. CS Mode, 3-Wire with Busy Indicator Serial Interface Timing (SDI High)
Rev. A | Page 18 of 24
06974-015
SCK
AD7983
When the conversion is complete, the AD7983 enters the
acquisition phase and goes into standby mode. Each ADC result
can be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
16th SCK falling edge or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7983
can be read.
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7983s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7983s is shown in
Figure 30, and the corresponding timing is given in Figure 31.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum conversion
time to avoid the generation of the busy signal indicator.
CS2
CS1
CONVERT
CNV
SDI
AD7983
DIGITAL HOST
CNV
SDO
SDI
AD7983
SCK
SDO
SCK
06974-016
DATA IN
CLK
Figure 30. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI(CS1)
tHSDICNV
SDI(CS2)
tSCK
tSCKL
1
2
3
14
tHSDO
SDO
tEN
tDSDO
D15
D14
D13
15
16
17
18
30
31
32
tSCKH
tDIS
D1
D0
D15
D14
Figure 31. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Rev. A | Page 19 of 24
D1
D0
06974-017
SCK
AD7983
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7983 then enters the acquisition phase
and goes into standby mode. The data bits are clocked out, MSB
first, by subsequent SCK falling edges. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host using the SCK falling edge allows a faster
reading rate provided it has an acceptable hold time. After the
optional 17th SCK falling edge or SDI going high, whichever is
earlier, the SDO returns to high impedance.
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7983 is connected
to an SPI-compatible digital host that has an interrupt input,
and when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the
data reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 32, and the
corresponding timing is given in Figure 33.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers, but
SDI must be returned low before the minimum conversion time
elapses and then held low for the maximum conversion time to
guarantee the generation of the busy signal indicator. When the
conversion is complete, SDO goes from high impedance to low.
CS1
CONVERT
VIO
CNV
AD7983
SDO
DATA IN
SCK
IRQ
06974-018
SDI
DIGITAL HOST
47kΩ
CLK
Figure 32. CS Mode, 4-Wire with Busy Indicator Connection Diagram
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
2
3
15
tHSDO
16
17
tSCKH
tDIS
tDSDO
tEN
SDO
D15
D14
D1
Figure 33. CS Mode, 4-Wire with Busy Indicator Serial Interface Timing
Rev. A | Page 20 of 24
D0
06974-019
1
SCK
AD7983
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7983 enters the acquisition phase and
goes into standby mode. The remaining data bits stored in the
internal shift register are clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first, and 16 × N clocks are
required to readback the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host using the SCK falling edge allows a faster
reading rate and, consequently, more AD7983s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate can be reduced due to the total
readback time.
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7983s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7983s is shown in
Figure 34, and the corresponding timing is given in Figure 35.
CONVERT
CNV
SDI
DIGITAL HOST
CNV
AD7983
SDO
SDI
AD7983
A
SCK
SDO
DATA IN
B
SCK
06974-020
CLK
Figure 34. Chain Mode Without Busy Indicator Connection Diagram
SDIA = 0
tCYC
CNV
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
2
3
14
16
17
18
30
31
32
DA1
DA0
tSCKH
tHSDISCK
tEN
SDOA = SDIB
15
tSSDISCK
tHSCKCNV
DA15
DA14
DA13
DA1
DA0
DB1
DB0
tHSDO
SDOB
DB14
DB13
DA15
DA14
Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. A | Page 21 of 24
06974-021
tDSDO
DB15
AD7983
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest
to the digital host (see the AD7983 ADC labeled C in Figure 36)
is driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7983 then enters the acquisition phase and goes
into standby mode. The data bits stored in the internal shift
register are clocked out, MSB first, by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in the
chain outputs its data MSB first, and 16 × N + 1 clocks are required
to readback the N ADCs. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate and, consequently, more AD7983s in
the chain, provided the digital host has an acceptable hold time.
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7983s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7983s is shown
in Figure 36, and the corresponding timing is given in Figure 37.
CONVERT
SDI
AD7983
CNV
SDO
SDI
DIGITAL HOST
CNV
AD7983
SDO
AD7983
SDI
A
B
C
SCK
SCK
SCK
SDO
DATA IN
IRQ
06974-022
CNV
CLK
Figure 36. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDIA
ACQUISITION
tCONV
tACQ
CONVERSION
ACQUISITION
tSCK
tSCKH
tSSCKCNV
1
2
3
4
15
16
tSSDISCK
tHSCKCNV
DA15
SDOA = SDIB
DA14
DA13
18
19
31
32
33
34
35
tSCKL
tHSDISCK
tEN
17
DA1
DB15
DB14
DB13
tDSDOSDI
DB1
DB0
DA15
DA14
DA1
DA0
tDSDOSDI
SDOC
49
DA0
tDSDO
SDOB = SDIC
48
tDSDOSDI
tHSDO
tDSDOSDI
47
tDSDODSI
DC15
DC14
DC13
DC1
DC0
DB15
DB14
DB1
DB0
Figure 37. Chain Mode with Busy Indicator Serial Interface Timing
Rev. A | Page 22 of 24
DA15
DA14
DA1
DA0
06974-023
SCK
AD7983
APPLICATION HINTS
LAYOUT
The printed circuit board (PCB) that houses the AD7983
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. The pinout of
the AD7983, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
AD7983
At least one ground plane should be used. It can be common or
split between the digital and analog section. In the latter case,
the planes should be joined underneath the AD7983.
06974-024
Avoid running digital lines under the device because these couple
noise onto the die, unless a ground plane under the AD7983 is
used as a shield. Fast switching signals, such as CNV or clocks,
should never run near analog signal paths. Crossover of digital
and analog signals should be avoided.
Figure 38. Example Layout of the AD7983 (Top Layer)
The AD7983 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the AD7983 power supplies, VDD and VIO, should be
decoupled with ceramic capacitors, typically 100 nF, placed
close to the AD7983 and connected using short and wide traces
to provide low impedance paths and to reduce the effect of
glitches on the power supply lines.
EVALUATING THE PERFORMANCE OF THE AD7983
Other recommended layouts for the AD7983 are outlined
in the documentation of the evaluation board for the AD7983
(EVAL-AD7983CBZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD.
Rev. A | Page 23 of 24
06974-025
An example of a layout following these rules is shown in
Figure 38 and Figure 39.
Figure 39. Example Layout of the AD7983 (Bottom Layer)
AD7983
OUTLINE DIMENSIONS
3.10
3.00
2.90
6
10
3.10
3.00
2.90
1
5
5.15
4.90
4.65
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.05
0.33
0.17
SEATING
PLANE
0.80
0.60
0.40
8°
0°
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 40.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
0.30
0.23
0.18
0.50 BSC
10
6
PIN 1 INDEX
AREA
*EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
5
TOP VIEW
0.80 MAX
0.55 NOM
0.80
0.75
0.70
SEATING
PLANE
1
2.48
2.38
2.23
0.05 MAX
0.02 NOM
0.20 REF
1.74
1.64
1.49
PIN 1
INDICATOR
(R 0.19)
*PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
ELECTRICAL PERFORMANCES.
101207-B
3.00
BSC SQ
Figure 41. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD7983BRMZ
AD7983BRMZRL7
AD7983BCPZ-R2
AD7983BCPZ-RL
AD7983BCPZ-RL7
EVAL-AD7983CBZ 2
EVAL-CONTROL BRD 3
1
2
3
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead QFN (LFCSP_WD)
10-Lead QFN (LFCSP_WD)
10-Lead QFN (LFCSP_WD)
Evaluation Board
Controller Board
Package Option
RM-10
RM-10
CP-10-9
CP-10-9
CP-10-9
Ordering Quantity
Tube, 50
Reel, 1000
Reel, 250
Reel, 1000
Reel, 5000
Z = RoHS Compliant Part.
This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.
This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator.
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06974-0-3/10(A)
Rev. A | Page 24 of 24
Branding
C5Y
C5Y
C5Y
C5Y
C5Y
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