STM32F767xx STM32F768Ax STM32F769xx

STM32F767xx STM32F768Ax STM32F769xx
STM32F767xx STM32F768Ax
STM32F769xx
ARM®-based Cortex®-M7 32b MCU+FPU, 462DMIPS, up to 2MB Flash/512+16+4KB
RAM, USB OTG HS/FS, ethernet, 18 TIMs, 3 ADCs, 28 com itf, cam, LCD, DSI
Data brief
Features
&"'!
• Core: ARM® 32-bit Cortex®-M7 CPU with
DPFPU, ART Accelerator™ and L1-cache:
16 KB I/D cache, allowing 0-wait state
execution from embedded Flash and external
memories, up to 216 MHz, MPU,
462 DMIPS/2.14 DMIPS/MHz (Dhrystone 2.1),
and DSP instructions.
• Memories
– Up to 2 MB of Flash memory organized into
two banks allowing read-while-write
– SRAM: 512 KB (including 128 KB of data
TCM RAM for critical real-time data) +
16 KB of instruction TCM RAM (for critical
real-time routines) + 4 KB of backup SRAM
– Flexible external memory controller with up
to 32-bit data bus: SRAM, PSRAM,
SDRAM/LPSDR SDRAM, NOR/NAND
memories
• Dual mode Quad-SPI
• Graphics
– Chrom-ART Accelerator™ (DMA2D),
graphical hardware accelerator enabling
enhanced graphical user interface
– Hardware JPEG codec
– LCD-TFT controller supporting up to XGA
resolution
– MIPI® DSI host controller supporting up to
720p 30 Hz resolution
• Clock, reset and supply management
– 1.7 V to 3.6 V application supply and I/Os
– POR, PDR, PVD and BOR
– Dedicated USB power
– 4-to-26 MHz crystal oscillator
– Internal 16 MHz factory-trimmed RC (1%
accuracy)
– 32 kHz oscillator for RTC with calibration
– Internal 32 kHz RC with calibration
• Low-power
– Sleep, Stop and Standby modes
– VBAT supply for RTC, 32×32 bit backup
registers + 4 KB backup SRAM
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels
• Digital filters for sigma delta modulator
(DFSDM)
• 2×12-bit D/A converters
• General-purpose DMA: 16-stream DMA
controller with FIFOs and burst support
• Up to 18 timers: up to thirteen 16-bit (1x lowpower 16-bit timer available in Stop mode) and
two 32-bit timers, each with up to 4 IC/OC/PWM
or pulse counter and quadrature (incremental)
March 2016
LQFP100 (14 × 14 mm)
LQFP144 (20 × 20 mm) UFBGA176 (10 x 10 mm) WLCSP180
LQFP176 (24 × 24 mm)
TFBGA216 (13 x 13 mm) (0.4 mm pitch)
LQFP208 (28 x 28 mm)
•
•
•
•
•
•
•
•
•
encoder input. All 15 timers running up to
216 MHz. 2x watchdogs, SysTick timer
Debug mode
– SWD & JTAG interfaces
– Cortex®-M7 Trace Macrocell™
Up to 168 I/O ports with interrupt capability
– Up to 164 fast I/Os up to 108 MHz
– Up to 166 5 V-tolerant I/Os
Up to 28 communication interfaces
– Up to 4 I2C interfaces (SMBus/PMBus)
– Up to 4 USARTs/4 UARTs (27 Mbit/s,
ISO7816 interface, LIN, IrDA, modem
control)
– Up to 6 SPIs (up to 50 Mbit/s), 3 with muxed
simplex I2S for audio
– 2 x SAIs (serial audio interface)
– 3 × CANs (2.0B Active) and 2x SDMMCs
– SPDIFRX interface
– HDMI-CEC
– MDIO slave interface
Advanced connectivity
– USB 2.0 full-speed device/host/OTG
controller with on-chip PHY
– USB 2.0 high-speed/full-speed
device/host/OTG controller with dedicated
DMA, on-chip full-speed PHY and ULPI
– 10/100 Ethernet MAC with dedicated DMA:
supports IEEE 1588v2 hardware, MII/RMII
8- to 14-bit camera interface up to 54 Mbyte/s
True random number generator
CRC calculation unit
RTC: subsecond accuracy, hardware calendar
96-bit unique ID
Table 1. Device summary
Reference
STM32F767xx
STM32F767BG, STM32F767BI, STM32F767IG,
STM32F767II, STM32F767NG, STM32F767NI,
STM32F767VG, STM32F767VI, STM32F767ZG,
STM32F767ZI
STM32F768Ax
STM32F768AI
STM32F769xx
STM32F769AG, STM32F769AI, STM32F769BG,
STM32F769BI, STM32F769IG, STM32F769II,
STM32F769NG, STM32F769NI
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Part number
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Contents
STM32F767xx STM32F768Ax STM32F769xx
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1
2
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.1
ARM® Cortex®-M7 with FPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 15
2.5
Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.6
AXI-AHB bus matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.7
DMA controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.8
Flexible memory controller (FMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.9
Quad-SPI memory interface (QUADSPI) . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.10
LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.11
Chrom-ART Accelerator™ (DMA2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.12
Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . 19
2.13
JPEG codec (JPEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.14
External interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.15
Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.16
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.17
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.18
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.19
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Full compatibility throughout the family . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.18.1
Internal reset ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.18.2
Internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.19.1
Regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.19.2
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.19.3
Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 27
2.20
Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . . 27
2.21
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.22
VBAT operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.23
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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3
Contents
2.23.1
Advanced-control timers (TIM1, TIM8) . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.23.2
General-purpose timers (TIMx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.23.3
Basic timers TIM6 and TIM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.23.4
Low-power timer (LPTIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.23.5
Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.23.6
Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.23.7
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.24
Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.25
Universal synchronous/asynchronous receiver transmitters (USART) . . 34
2.26
Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) . 35
2.27
Serial audio interface (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.28
SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.29
Audio PLL (PLLI2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.30
Audio and LCD PLL (PLLSAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.31
SD/SDIO/MMC card host interface (SDMMC) . . . . . . . . . . . . . . . . . . . . . 37
2.32
Ethernet MAC interface with dedicated DMA and IEEE 1588 support . . . 37
2.33
Controller area network (bxCAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.34
Universal serial bus on-the-go full-speed (OTG_FS) . . . . . . . . . . . . . . . . 38
2.35
Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . . 38
2.36
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.37
Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.38
Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . . 40
2.39
Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.40
General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.41
Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.42
Digital filter for Sigma-Delta Modulators (DFSDM) . . . . . . . . . . . . . . . . . . 41
2.43
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.44
Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.45
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.46
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
2.47
DSI Host (DSIHOST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Contents
STM32F767xx STM32F768Ax STM32F769xx
4
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6
5.1
LQFP100 14x 14 mm, low-profile quad flat package information . . . . . . 100
5.2
LQFP144 20 x 20 mm, low-profile quad flat package information . . . . . 103
5.3
LQFP176 24 x 24 mm, low-profile quad flat package information . . . . . 106
5.4
WLCSP 180-bump, 5.5 x 6 mm, wafer level chip scale
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
5.5
LQFP208 28 x 28 mm low-profile quad flat package information . . . . . . .114
5.6
UFBGA176+25, 10 x 10, 0.65 mm ultra thin fine-pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
5.7
TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.8
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Appendix A Recommendations when using internal reset OFF . . . . . . . . . . . 126
A.1
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts . . . . . 10
Voltage regulator configuration mode versus device operating mode . . . . . . . . . . . . . . . . 24
Regulator ON/OFF and internal reset ON/OFF availability. . . . . . . . . . . . . . . . . . . . . . . . . 27
Voltage regulator modes in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions. . . . . . . . . . . . 55
FMC pin definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping . . . . . . . . 82
STM32F767xx, STM32F768Ax and STM32F769xx register boundary addresses. . . . . . . 96
LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical data. . . . . . . . 101
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules
(0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
UFBGA176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA) . . . . . . . . . . . . . 119
TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
TFBGA216 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 122
Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Limitations depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . . . 126
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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List of figures
STM32F767xx STM32F768Ax STM32F769xx
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
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Compatible board design for LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STM32F767xx, STM32F768Ax and STM32F769xx block diagram . . . . . . . . . . . . . . . . . 13
STM32F767xx, STM32F768Ax and STM32F769xx AXI-AHB bus matrix architecture(1) . . 16
Power supply supervisor interconnection with internal reset OFF . . . . . . . . . . . . . . . . . . . 22
PDR_ON control with internal reset OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Regulator OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . . . 26
Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization . . . . . . . . . . . . . . . . . . . . . . 26
STM32F767xx LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
STM32F767xx LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STM32F767xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STM32F769xx LQFP176 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STM32F769xx/STM32F768Ax WLCSP180 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STM32F767xx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STM32F769xx LQFP208 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
STM32F767xx UFBGA176 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
STM32F767xx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
STM32F769xx TFBGA216 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 100
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 103
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
LQFP144, 20 x 20mm, 144-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 106
LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
WLCSP180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 114
LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
UFBGA176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
List of figures
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
UFBGA176+25, 10 × 10 × 0.6 mm ultra thin fine-pitch ball grid array
package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
TFBGA216, 13 x 13 mm, 0.8 mm pitch, thin fine-pitch ball grid array
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
TFBGA216, 13 × 13 × 0.8mm thin fine-pitch ball grid array
package top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
DocID027972 Rev 5
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7
Description
1
STM32F767xx STM32F768Ax STM32F769xx
Description
The STM32F767xx, STM32F768Ax and STM32F769xx devices are based on the highperformance ARM® Cortex®-M7 32-bit RISC core operating at up to 216 MHz frequency.
The Cortex®-M7 core features a floating point unit (FPU) which supports ARM® doubleprecision and single-precision data-processing instructions and data types. It also
implements a full set of DSP instructions and a memory protection unit (MPU) which
enhances application security.
The STM32F767xx, STM32F768Ax and STM32F769xx devices incorporate high-speed
embedded memories with a Flash memory up to 2 Mbytes, 512 Kbytes of SRAM (including
128 Kbytes of Data TCM RAM for critical real-time data), 16 Kbytes of instruction TCM RAM
(for critical real-time routines), 4 Kbytes of backup SRAM available in the lowest power
modes, and an extensive range of enhanced I/Os and peripherals connected to two APB
buses, two AHB buses, a 32-bit multi-AHB bus matrix and a multi layer AXI interconnect
supporting internal and external memories access.
All the devices offer three 12-bit ADCs, two DACs, a low-power RTC, twelve generalpurpose 16-bit timers including two PWM timers for motor control, two general-purpose 32bit timers, a true random number generator (RNG). They also feature standard and
advanced communication interfaces.
•
Up to four I2Cs
•
Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S
peripherals can be clocked via a dedicated internal audio PLL or via an external clock
to allow synchronization.
•
Four USARTs plus four UARTs
•
An USB OTG full-speed and a USB OTG high-speed with full-speed capability (with the
ULPI)
•
Three CANs
•
Two SAI serial audio interfaces
•
Two SDMMC host interfaces
•
Ethernet and camera interfaces
•
LCD-TFT display controller
•
Chrom-ART Accelerator™
•
SPDIFRX interface
•
HDMI-CEC
Advanced peripherals include two SDMMC interfaces, a flexible memory control (FMC)
interface, a Quad-SPI Flash memory interface, a camera interface for CMOS sensors. Refer
to Table 2: STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral
counts for the list of peripherals available on each part number.
The STM32F767xx, STM32F768Ax and STM32F769xx devices operate in the –40 to
+105 °C temperature range from a 1.7 to 3.6 V power supply. Dedicated supply inputs for
USB (OTG_FS and OTG_HS) and SDMMC2 (clock, command and 4-bit data) are available
on all packages except LQFP100 for greater power supply choice.
The supply voltage can drop to 1.7 V with the use of an external power supply supervisor
(refer to Section 2.18.2: Internal reset OFF). A comprehensive set of power-saving mode
allows the design of low-power applications.
8/129
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STM32F767xx STM32F768Ax STM32F769xx
Description
The STM32F767xx, STM32F768Ax and STM32F769xx devices offer devices in 10
packages ranging from 100 pins to 216 pins. The set of included peripherals changes with
the device chosen.
These features make the STM32F767xx, STM32F768Ax and STM32F769xx
microcontrollers suitable for a wide range of applications:
•
Motor drive and application control
•
Medical equipment
•
Industrial applications: PLC, inverters, circuit breakers
•
Printers, and scanners
•
Alarm systems, video intercom, and HVAC
•
Home audio appliances
•
Mobile applications, Internet of Things
•
Wearable devices: smartwatches.
Figure 2 shows the general block diagram of the device family
DocID027972 Rev 5
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44
Peripherals
Flash memory in Kbytes
SRAM in Kbytes
STM32F76xVx
STM32F76xZx
STM32F769Ax
1024
1024
1024
2048
2048
STM32F768Ax
2048
2048
512(368+16+128)
Instruction
16
Backup
4
Yes
No
1024
1024
2048
2048
Yes
10
Advanced-control
2
Basic
2
Low-power
1
SPI /
Yes
I2S
4/3
(simplex)(2)
6/3 (simplex)(2)
I2C
4
USART/UART
4/4
USB OTG FS
Yes
USB OTG HS
Yes
CAN
3
SAI
2
SPDIFRX
4 inputs
SDMMC1
Yes
SDMMC2
Yes(3)
Camera interface
Yes
Host(4)
No
Yes
LCD-TFT
Yes
Chrom-ART Accelerator™ (DMA2D)
Yes
JPEG codec
Yes
82
114
140
168
STM32F767xx STM32F768Ax STM32F769xx
DocID027972 Rev 5
General-purpose
Random number generator
GPIOs
STM32F76xNx
Yes
Ethernet
MIPI-DSI
2048
STM32F76xBx
Yes(1)
Quad-SPI
Communication
interfaces
1024
System
FMC memory controller
Timers
STM32F76xIx
Description
10/129
Table 2. STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts
Peripherals
STM32F76xVx
STM32F76xZx
STM32F769Ax
STM32F768Ax
12-bit ADC
Number of channels
STM32F76xBx
STM32F76xNx
LQFP208
TFBGA216
3
16
24
Yes
2
12-bit DAC
Number of channels
216 MHz(5)
Maximum CPU frequency
1.7 to 3.6 V(6)
Operating voltage
Ambient temperatures: –40 to +85 °C /–40 to +105 °C
Operating temperatures
Package
STM32F76xIx
Junction temperature: –40 to + 125 °C
LQFP100
LQFP144
WLCSP180
UFBGA176(7)
LQFP176
1. For the LQFP100 package, only FMC Bank1 is available. Bank1 can only support a multiplexed NOR/PSRAM memory using the NE1 Chip Select.
DocID027972 Rev 5
2. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio mode.
3. SDMMC2 supports a dedicated power rail for clock, command and data 0..4 lines, feature available starting from 144 pin package.
STM32F767xx STM32F768Ax STM32F769xx
Table 2. STM32F767xx, STM32F768Ax and STM32F769xx features and peripheral counts (continued)
4. DSI host interface is only available on STM32F769x sales types.
5. 216 MHz maximum frequency for - 40°C to + 85°C ambient temperature range (200 MHz maximum frequency for - 40°C to + 105°C ambient temperature range).
6. VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to Section 2.18.2: Internal reset OFF).
7. UFBGA176 is not available for STM32F769x sales types.
Description
11/129
Description
1.1
STM32F767xx STM32F768Ax STM32F769xx
Full compatibility throughout the family
The STM32F767xx, STM32F768Ax and STM32F769xx devices are fully pin-to-pin,
compatible with the STM32F4xxxx devices, allowing the user to try different peripherals,
and reaching higher performances (higher frequency) for a greater degree of freedom
during the development cycle.
Figure 1 give compatible board designs between the STM32F7xx and STM32F4xx families.
Figure 1. Compatible board design for LQFP100 package
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The STM32F76x LQFP144, LQFP176, LQFP208, TFBGA216, UFBGA176 packages are
fully pin to pin compatible with STM32F4xx devices.
12/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Description
Figure 2. STM32F767xx, STM32F768Ax and STM32F769xx block diagram
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1. The timers connected to APB2 are clocked from TIMxCLK up to 216 MHz, while the timers connected to APB1 are clocked
from TIMxCLK either up to 108 MHz or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR register.
DocID027972 Rev 5
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44
Functional overview
STM32F767xx STM32F768Ax STM32F769xx
2
Functional overview
2.1
ARM® Cortex®-M7 with FPU
The ARM® Cortex®-M7 with FPU processor is the latest generation of ARM processors for
embedded systems. It was developed to provide a low-cost platform that meets the needs of
MCU implementation, with a reduced pin count and low-power consumption, while
delivering outstanding computational performance and low interrupt latency.
The Cortex®-M7 processor is a highly efficient high-performance featuring:
–
Six-stage dual-issue pipeline
–
Dynamic branch prediction
–
Harvard caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)
–
64-bit AXI4 interface
–
64-bit ITCM interface
–
2x32-bit DTCM interfaces
The processor supports the following memory interfaces:
•
Tightly Coupled Memory (TCM) interface.
•
Harvard instruction and data caches and AXI master (AXIM) interface.
•
Dedicated low-latency AHB-Lite peripheral (AHBP) interface.
The processor supports a set of DSP instructions which allow efficient signal processing and
complex algorithm execution.
It supports single and double precision FPU (floating point unit) speeds up software
development by using metalanguage development tools, while avoiding saturation.
Figure 2 shows the general block diagram of the STM32F76xxx family.
Note:
Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.
2.2
Memory protection unit
The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task. This memory area is organized into up to 8 protected areas that can in turn be divided
up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4
gigabytes of addressable memory.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (realtime operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
14/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
2.3
Functional overview
Embedded Flash memory
The STM32F767xx, STM32F768Ax and STM32F769xx devices embed a Flash memory of
up to 2 Mbytes available for storing programs and data.
2.4
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
2.5
Embedded SRAM
All the devices feature:
•
•
System SRAM up to 512 Kbytes:
–
SRAM1 on AHB bus Matrix: 368 Kbytes
–
SRAM2 on AHB bus Matrix: 16 Kbytes
–
DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 128 Kbytes for
critical real-time data.
Instruction RAM (ITCM-RAM) 16 Kbytes:
–
It is mapped on TCM interface and reserved only for CPU Execution/Instruction
useful for critical real-time routines.
The Data TCM RAM is accessible by the GP-DMAs and peripherals DMAs through specific
AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is accessed at
CPU clock speed with 0 wait states.
•
4 Kbytes of backup SRAM
This area is accessible only from the CPU. Its content is protected against possible
unwanted write accesses, and is retained in Standby or VBAT mode.
2.6
AXI-AHB bus matrix
The STM32F767xx, STM32F768Ax and STM32F769xx system architecture is based on 2
sub-systems:
•
•
An AXI to multi AHB bridge converting AXI4 protocol to AHB-Lite protocol:
–
3x AXI to 32-bit AHB bridges connected to AHB bus matrix
–
1x AXI to 64-bit AHB bridge connected to the embedded Flash memory
A multi-AHB Bus-Matrix
–
The 32-bit multi-AHB bus matrix interconnects all the masters (CPU, DMAs,
Ethernet, USB HS, LCD-TFT, and DMA2D) and the slaves (Flash memory, RAM,
FMC, Quad-SPI, AHB and APB peripherals) and ensures a seamless and efficient
operation even when several high-speed peripherals work simultaneously.
DocID027972 Rev 5
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44
Functional overview
STM32F767xx STM32F768Ax STM32F769xx
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2.7
DMA controller (DMA)
The devices feature two general-purpose dual-port DMAs (DMA1 and DMA2) with 8
streams each. They are able to manage memory-to-memory, peripheral-to-memory and
memory-to-peripheral transfers. They feature dedicated FIFOs for APB/AHB peripherals,
support burst transfer and are designed to provide the maximum peripheral bandwidth
(AHB/APB).
The two DMA controllers support circular buffer management, so that no specific code is
needed when the controller reaches the end of the buffer. The two DMA controllers also
have a double buffering feature, which automates the use and switching of two memory
buffers without requiring any special code.
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Functional overview
Each stream is connected to dedicated hardware DMA requests, with support for software
trigger on each stream. Configuration is made by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals:
2.8
•
SPI and I2S
•
I2C
•
USART
•
General-purpose, basic and advanced-control timers TIMx
•
DAC
•
SDMMC
•
Camera interface (DCMI)
•
ADC
•
SAI
•
SPDIFRX
•
Quad-SPI
•
HDMI-CEC
•
JPEG codec
•
DFSDM
Flexible memory controller (FMC)
The Flexible memory controller (FMC) includes three memory controllers:
•
The NOR/PSRAM memory controller
•
The NAND/memory controller
•
The Synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) controller
The main features of the FMC controller are the following:
•
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR Flash memory/OneNAND Flash memory
–
PSRAM (4 memory banks)
–
NAND Flash memory with ECC hardware to check up to 8 Kbytes of data
•
Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories
•
8-,16-,32-bit data bus width
•
Independent Chip Select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
•
Read FIFO for SDRAM controller
•
The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is
HCLK/2
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Functional overview
STM32F767xx STM32F768Ax STM32F769xx
LCD parallel interface
The FMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to
specific LCD interfaces. This LCD parallel interface capability makes it easy to build costeffective graphic applications using LCD modules with embedded controllers or high
performance solutions using external controllers with dedicated acceleration.
2.9
Quad-SPI memory interface (QUADSPI)
All the devices embed a Quad-SPI memory interface, which is a specialized communication
interface targetting Single, Dual or Quad-SPI Flash memories. It can work in:
•
Direct mode through registers
•
External flash status register polling mode
•
Memory mapped mode.
Up to 256 Mbytes external flash are memory mapped, supporting 8, 16 and 32-bit access.
Code execution is supported.
The opcode and the frame format are fully programmable. Communication can be either in
Single Data Rate or Dual Data Rate.
2.10
LCD-TFT controller
The LCD-TFT display controller provides a 24-bit parallel digital RGB (Red, Green, Blue)
and delivers all signals to interface directly to a broad range of LCD and TFT panels up to
XGA (1024x768) resolution with the following features:
2.11
•
2 display layers with dedicated FIFO (64x32-bit)
•
Color Look-Up table (CLUT) up to 256 colors (256x24-bit) per layer
•
Up to 8 input color formats selectable per layer
•
Flexible blending between two layers using alpha value (per pixel or constant)
•
Flexible programmable parameters for each layer
•
Color keying (transparency color)
•
Up to 4 programmable interrupt events
Chrom-ART Accelerator™ (DMA2D)
The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit
blitting, row data copy and pixel format conversion. It supports the following functions:
•
Rectangle filling with a fixed color
•
Rectangle copy
•
Rectangle copy with pixel format conversion
•
Rectangle composition with blending and pixel format conversion
Various image format coding are supported, from indirect 4bpp color mode up to 32bpp
direct color. It embeds dedicated memory to store color lookup tables.
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Functional overview
An interrupt can be generated when an operation is complete or at a programmed
watermark.
All the operations are fully automatized and are running independently from the CPU or the
DMAs.
2.12
Nested vectored interrupt controller (NVIC)
The devices embed a nested vectored interrupt controller able to manage 16 priority levels,
and handle up to 110 maskable interrupt channels plus the 16 interrupt lines of the Cortex®M7 with FPU core.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support tail chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimum interrupt
latency.
2.13
JPEG codec (JPEG)
The JPEG codec provides an fast and simple hardware compressor and decompressor of
JPEG images with full management of JPEG headers.
The JPEG codec main features:
•
8-bit/channel pixel depths
•
Single clock per pixel encoding and decoding
•
Support for JPEG header generation and parsing
•
Up to four programmable quantization tables
•
Fully programmable Huffman tables (two AC and two DC)
•
Fully programmable minimum coded unit (MCU)
•
Encode/decode support (non simultaneous)
•
Single clock Huffman coding and decoding
•
Two-channel interface: Pixel/Compress In, Pixel/Compressed Out
•
Stallable design
•
Support for single, greyscale component
•
Functionality to enable/disable header processing
•
Internal register interface
•
Fully synchronous design
•
Configured for high-speed decode mode
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2.14
STM32F767xx STM32F768Ax STM32F769xx
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 25 edge-detector lines used to generate
interrupt/event requests. Each line can be independently configured to select the trigger
event (rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 168 GPIOs can be connected
to the 16 external interrupt lines.
2.15
Clocks and startup
On reset the 16 MHz internal HSI RC oscillator is selected as the default CPU clock. The
16 MHz internal RC oscillator is factory-trimmed to offer 1% accuracy. The application can
then select as system clock either the RC oscillator or an external 4-26 MHz clock source.
This clock can be monitored for failure. If a failure is detected, the system automatically
switches back to the internal RC oscillator and a software interrupt is generated (if enabled).
This clock source is input to a PLL thus allowing to increase the frequency up to 216 MHz.
Similarly, full interrupt management of the PLL clock entry is available when necessary (for
example if an indirectly used external oscillator fails).
Several prescalers allow the configuration of the two AHB buses, the high-speed APB
(APB2) and the low-speed APB (APB1) domains. The maximum frequency of the two AHB
buses is 216 MHz while the maximum frequency of the high-speed APB domains is
108 MHz. The maximum allowed frequency of the low-speed APB domain is 54 MHz.
The devices embed two dedicated PLL (PLLI2S and PLLSAI) which allow to achieve audio
class performance. In this case, the I2S and SAI master clock can generate all standard
sampling frequencies from 8 kHz to 192 kHz.
2.16
Boot modes
At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option
bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF
which includes:
•
All Flash address space mapped on ITCM or AXIM interface
•
All RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface
•
The System memory bootloader
The boot loader is located in system memory. It is used to reprogram the Flash memory
through a serial interface. Refer to STM32 microcontroller system memory boot mode
application note (AN2606) for details.
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2.17
Functional overview
Power supply schemes
•
VDD = 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when
enabled), provided externally through VDD pins.
•
VSSA, VDDA = 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset
blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
•
VDDUSB can be connected either to VDD or an external independent power supply
(3.0 to 3.6V) for USB transceivers. For example, when device is powered at 1.8V, an
independent power supply 3.3V can be connected to VDDUSB.
•
VDDSDMMC can be connected either to VDD or an external independent power
supply (1.8 to 3.6V) for SDMMC2 pins (clock, command, and 4-bit data). For example,
when device is powered at 1.8V, an independent power supply 2.7V can be connected
to VDDSDMMC.
•
VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and
backup registers (through power switch) when VDD is not present.
Note:
VDD/VDDA minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 2.18.2: Internal reset OFF). Refer to Table 3: Voltage regulator configuration mode
versus device operating mode to identify the packages supporting this option.
2.18
Power supply supervisor
2.18.1
Internal reset ON
On packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
The device has an integrated power-on reset (POR)/ power-down reset (PDR) circuitry
coupled with a Brownout reset (BOR) circuitry. At power-on, POR/PDR is always active and
ensures proper operation starting from 1.8 V. After the 1.8 V POR threshold level is
reached, the option byte loading process starts, either to confirm or modify default BOR
thresholds, or to disable BOR permanently. Three BOR thresholds are available through
option bytes. The device remains in reset mode when VDD is below a specified threshold,
VPOR/PDR or VBOR, without the need for an external reset circuit.
The device also features an embedded programmable voltage detector (PVD) that monitors
the VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is
higher than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
2.18.2
Internal reset OFF
This feature is available only on packages featuring the PDR_ON pin. The internal power-on
reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor VDD and NRST and should maintain
the device in reset mode as long as VDD is below a specified threshold. PDR_ON should be
connected to VSS. Refer to Figure 4: Power supply supervisor interconnection with internal
reset OFF.
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STM32F767xx STM32F768Ax STM32F769xx
Figure 4. Power supply supervisor interconnection with internal reset OFF
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The VDD specified threshold, below which the device must be maintained under reset, is
1.7 V (see Figure 5).
A comprehensive set of power-saving mode allows to design low-power applications.
When the internal reset is OFF, the following integrated features are no more supported:
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
•
The brownout reset (BOR) circuitry must be disabled
•
The embedded programmable voltage detector (PVD) is disabled
•
VBAT functionality is no more available and VBAT pin should be connected to VDD.
All the packages, except for the LQFP100, allow to disable the internal reset through the
PDR_ON signal when connected to VSS.
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Functional overview
Figure 5. PDR_ON control with internal reset OFF
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2.19
Voltage regulator
The regulator has four operating modes:
•
•
2.19.1
Regulator ON
–
Main regulator mode (MR)
–
Low power regulator (LPR)
–
Power-down
Regulator OFF
Regulator ON
On packages embedding the BYPASS_REG pin, the regulator is enabled by holding
BYPASS_REG low. On all other packages, the regulator is always enabled.
There are three power modes configured by software when the regulator is ON:
•
MR mode used in Run/sleep modes or in Stop modes
–
In Run/Sleep modes
The MR mode is used either in the normal mode (default mode) or the over-drive
mode (enabled by software). Different voltages scaling are provided to reach the
best compromise between maximum frequency and dynamic power consumption.
The over-drive mode allows operating at a higher frequency than the normal mode
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STM32F767xx STM32F768Ax STM32F769xx
for a given voltage scaling.
–
In Stop modes
The MR can be configured in two ways during stop mode:
MR operates in normal mode (default mode of MR in stop mode)
MR operates in under-drive mode (reduced leakage mode).
•
LPR is used in the Stop modes:
The LP regulator mode is configured by software when entering Stop mode.
Like the MR mode, the LPR can be configured in two ways during stop mode:
•
–
LPR operates in normal mode (default mode when LPR is ON)
–
LPR operates in under-drive mode (reduced leakage mode).
Power-down is used in Standby mode.
The Power-down mode is activated only when entering in Standby mode. The regulator
output is in high impedance and the kernel circuitry is powered down, inducing zero
consumption. The contents of the registers and SRAM are lost.
Refer to Table 3 for a summary of voltage regulator modes versus device operating modes.
Two external ceramic capacitors should be connected on VCAP_1 and VCAP_2 pin.
All packages have the regulator ON feature.
Table 3. Voltage regulator configuration mode versus device operating mode(1)
Voltage regulator
configuration
Run mode
Sleep mode
Stop mode
Standby mode
Normal mode
MR
MR
MR or LPR
-
Over-drive
mode(2)
MR
MR
-
-
Under-drive mode
-
-
MR or LPR
-
Power-down
mode
-
-
-
Yes
1. ‘-’ means that the corresponding configuration is not available.
2. The over-drive mode is not available when VDD = 1.7 to 2.1 V.
2.19.2
Regulator OFF
This feature is available only on packages featuring the BYPASS_REG pin. The regulator is
disabled by holding BYPASS_REG high. The regulator OFF mode allows to supply
externally a V12 voltage source through VCAP_1 and VCAP_2 pins.
Since the internal voltage scaling is not managed internally, the external voltage value must
be aligned with the targeted maximum frequency.The two 2.2 µF ceramic capacitors should
be replaced by two 100 nF decoupling capacitors.
When the regulator is OFF, there is no more internal monitoring on V12. An external power
supply supervisor should be used to monitor the V12 of the logic power domain. PA0 pin
should be used for this purpose, and act as power-on reset on V12 power domain.
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Functional overview
In regulator OFF mode, the following features are no more supported:
•
PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power
domain which is not reset by the NRST pin.
•
As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As
a consequence, PA0 and NRST pins must be managed separately if the debug
connection under reset or pre-reset is required.
•
The over-drive and under-drive modes are not available.
•
The Standby mode is not available.
Figure 6. Regulator OFF
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The following conditions must be respected:
Note:
•
VDD should always be higher than VCAP_1 and VCAP_2 to avoid current injection
between power domains.
•
If the time for VCAP_1 and VCAP_2 to reach V12 minimum value is faster than the time for
VDD to reach 1.7 V, then PA0 should be kept low to cover both conditions: until VCAP_1
and VCAP_2 reach V12 minimum value and until VDD reaches 1.7 V (see Figure 7).
•
Otherwise, if the time for VCAP_1 and VCAP_2 to reach V12 minimum value is slower
than the time for VDD to reach 1.7 V, then PA0 could be asserted low externally (see
Figure 8).
•
If VCAP_1 and VCAP_2 go below V12 minimum value and VDD is higher than 1.7 V, then a
reset must be asserted on PA0 pin.
The minimum value of V12 depends on the maximum frequency targeted in the application.
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Figure 7. Startup in regulator OFF: slow VDD slope
- power-down reset risen after VCAP_1/VCAP_2 stabilization
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Figure 8. Startup in regulator OFF mode: fast VDD slope
- power-down reset risen before VCAP_1/VCAP_2 stabilization
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2.19.3
Functional overview
Regulator ON/OFF and internal reset ON/OFF availability
Table 4. Regulator ON/OFF and internal reset ON/OFF availability
Package
Regulator ON
Regulator OFF
LQFP100
LQFP144,
LQFP208
LQFP176,
UFBGA176,
TFBGA216
WLCSP180
Yes
Internal reset ON
Internal reset OFF
Yes
No
No
Yes
Yes
Yes
Yes
BYPASS_REG set BYPASS_REG set
PDR_ON set to VDD PDR_ON set to VSS
to VDD
to VSS
Yes(1)
1. Available only on dedicated part number. Refer to Section 6: Part numbering.
2.20
Real-time clock (RTC), backup SRAM and backup registers
The RTC is an independent BCD timer/counter. It supports the following features:
•
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.
•
Automatic correction for 28, 29 (leap year), 30, and 31 days of the month.
•
Two programmable alarms.
•
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
•
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
•
Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy.
•
Three anti-tamper detection pins with programmable filter.
•
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event, or by a switch to
VBAT mode.
•
17-bit auto-reload wakeup timer (WUT) for periodic events with programmable
resolution and period.
The RTC and the 32 backup registers are supplied through a switch that takes power either
from the VDD supply when present or from the VBAT pin.
The backup registers are 32-bit registers used to store 128 bytes of user application data
when VDD power is not present. They are not reset by a system or power reset, or when the
device wakes up from Standby mode.
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The RTC clock sources can be:
•
A 32.768 kHz external crystal (LSE)
•
An external resonator or oscillator(LSE)
•
The internal low power RC oscillator (LSI, with typical frequency of 32 kHz)
•
The high-speed external clock (HSE) divided by 32
The RTC is functional in VBAT mode and in all low-power modes when it is clocked by the
LSE. When clocked by the LSI, the RTC is not functional in VBAT mode, but is functional in
all low-power modes.
All RTC events (Alarm, WakeUp Timer, Timestamp or Tamper) can generate an interrupt
and wakeup the device from the low-power modes.
2.21
Low-power modes
The devices support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
•
Stop mode
The Stop mode achieves the lowest power consumption while retaining the contents of
SRAM and registers. All clocks in the 1.2 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled.
The voltage regulator can be put either in main regulator mode (MR) or in low-power
mode (LPR). Both modes can be configured as follows (see Table 5: Voltage regulator
modes in stop mode):
–
Normal mode (default mode when MR or LPR is enabled)
–
Under-drive mode.
The device can be woken up from the Stop mode by any of the EXTI line (the EXTI line
source can be one of the 16 external lines, the PVD output, the RTC alarm / wakeup /
tamper / time stamp events, the USB OTG FS/HS wakeup or the Ethernet wakeup and
LPTIM1 asynchronous interrupt).
Table 5. Voltage regulator modes in stop mode
•
Voltage regulator
configuration
Main regulator (MR)
Low-power regulator (LPR)
Normal mode
MR ON
LPR ON
Under-drive mode
MR in under-drive mode
LPR in under-drive mode
Standby mode
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire 1.2 V domain is powered off. The
PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering
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Functional overview
Standby mode, the SRAM and register contents are lost except for registers in the
backup domain and the backup SRAM when selected.
The device exits the Standby mode when an external reset (NRST pin), an IWDG reset,
a rising or falling edge on one of the 6 WKUP pins (PA0, PA2, PC1, PC13, PI8, PI11),
or an RTC alarm / wakeup / tamper /time stamp event occurs.
The Standby mode is not supported when the embedded voltage regulator is bypassed
and the 1.2 V domain is controlled by an external power.
2.22
VBAT operation
The VBAT pin allows to power the device VBAT domain from an external battery, an external
supercapacitor, or from VDD when no external battery and an external supercapacitor are
present.
VBAT operation is activated when VDD is not present.
The VBAT pin supplies the RTC, the backup registers and the backup SRAM.
Note:
When the microcontroller is supplied from VBAT, external interrupts and RTC alarm/events
do not exit it from VBAT operation.
When PDR_ON pin is connected to VSS (Internal Reset OFF), the VBAT functionality is no
more available and VBAT pin should be connected to VDD.
2.23
Timers and watchdogs
The devices include two advanced-control timers, eight general-purpose timers, two basic
timers and two watchdog timers.
All timer counters can be frozen in debug mode.
Table 6 compares the features of the advanced-control, general-purpose and basic timers.
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STM32F767xx STM32F768Ax STM32F769xx
Table 6. Timer feature comparison
Max
Max
DMA
Capture/ Complem
interface timer
request
compare
entary
clock
clock
generation channels
output
(MHz)
(MHz)(1)
Timer
type
Timer
Counter Counter Prescaler
resolution
type
factor
Advanced
-control
TIM1,
TIM8
16-bit
Any
Up,
integer
Down,
between 1
Up/down
and 65536
Yes
4
Yes
108
216
32-bit
Any
Up,
integer
Down,
between 1
Up/down
and 65536
Yes
4
No
54
108/216
16-bit
Any
Up,
integer
Down,
between 1
Up/down
and 65536
Yes
4
No
54
108/216
16-bit
Up
Any
integer
between 1
and 65536
No
2
No
108
216
Up
Any
integer
between 1
and 65536
No
1
No
108
216
Up
Any
integer
between 1
and 65536
No
2
No
54
108/216
Up
Any
integer
between 1
and 65536
No
1
No
54
108/216
Up
Any
integer
between 1
and 65536
Yes
0
No
54
108/216
TIM2,
TIM5
TIM3,
TIM4
TIM9
General
purpose
TIM10,
TIM11
TIM12
TIM13,
TIM14
Basic
TIM6,
TIM7
16-bit
16-bit
16-bit
16-bit
1. The maximum timer clock is either 108 or 216 MHz depending on TIMPRE bit configuration in the RCC_DCKCFGR
register.
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2.23.1
Functional overview
Advanced-control timers (TIM1, TIM8)
The advanced-control timers (TIM1, TIM8) can be seen as three-phase PWM generators
multiplexed on 6 channels. They have complementary PWM outputs with programmable
inserted dead times. They can also be considered as complete general-purpose timers.
Their 4 independent channels can be used for:
•
Input capture
•
Output compare
•
PWM generation (edge- or center-aligned modes)
•
One-pulse mode output
If configured as standard 16-bit timers, they have the same features as the general-purpose
TIMx timers. If configured as 16-bit PWM generators, they have full modulation capability (0100%).
The advanced-control timer can work together with the TIMx timers via the Timer Link
feature for synchronization or event chaining.
TIM1 and TIM8 support independent DMA request generation.
2.23.2
General-purpose timers (TIMx)
There are ten synchronizable general-purpose timers embedded in the STM32F76xxx
devices (see Table 6 for differences).
•
TIM2, TIM3, TIM4, TIM5
The STM32F76xxx include 4 full-featured general-purpose timers: TIM2, TIM5, TIM3,
and TIM4.The TIM2 and TIM5 timers are based on a 32-bit auto-reload
up/downcounter and a 16-bit prescaler. The TIM3 and TIM4 timers are based on a 16bit auto-reload up/downcounter and a 16-bit prescaler. They all feature 4 independent
channels for input capture/output compare, PWM or one-pulse mode output. This gives
up to 16 input capture/output compare/PWMs on the largest packages.
The TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together, or with the
other general-purpose timers and the advanced-control timers TIM1 and TIM8 via the
Timer Link feature for synchronization or event chaining.
Any of these general-purpose timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation. They are
capable of handling quadrature (incremental) encoder signals and the digital outputs
from 1 to 4 hall-effect sensors.
•
TIM9, TIM10, TIM11, TIM12, TIM13, and TIM14
These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.
TIM10, TIM11, TIM13, and TIM14 feature one independent channel, whereas TIM9
and TIM12 have two independent channels for input capture/output compare, PWM or
one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4, TIM5
full-featured general-purpose timers. They can also be used as simple time bases.
2.23.3
Basic timers TIM6 and TIM7
These timers are mainly used for DAC trigger and waveform generation. They can also be
used as a generic 16-bit time base.
TIM6 and TIM7 support independent DMA request generation.
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2.23.4
STM32F767xx STM32F768Ax STM32F769xx
Low-power timer (LPTIM1)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
2.23.5
•
16-bit up counter with 16-bit autoreload register
•
16-bit compare register
•
Configurable output: pulse, PWM
•
Continuous / one-shot mode
•
Selectable software / hardware input trigger
•
Selectable clock source:
•
Internal clock source: LSE, LSI, HSI or APB clock
•
External clock source over LPTIM input (working even with no internal clock source
running, used by the Pulse Counter Application)
•
Programmable digital glitch filter
•
Encoder mode
Independent watchdog
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 32 kHz internal RC and as it operates independently from the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes.
2.23.6
Window watchdog
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
2.23.7
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a standard
downcounter. It features:
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•
A 24-bit downcounter
•
Autoreload capability
•
Maskable system interrupt generation when the counter reaches 0
•
Programmable clock source
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2.24
Functional overview
Inter-integrated circuit interface (I2C)
The device embeds 4 I2C. Refer to table Table 7: I2C implementation for the features
implementation.
The I2C bus interface handles communications between the microcontroller and the serial
I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.
The I2C peripheral supports:
•
•
I2C-bus specification and user manual rev. 5 compatibility:
–
Slave and master modes, multimaster capability
–
Standard-mode (Sm), with a bitrate up to 100 kbit/s
–
Fast-mode (Fm), with a bitrate up to 400 kbit/s
–
Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and 20 mA output drive I/Os
–
7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
–
Programmable setup and hold times
–
Optional clock stretching
System Management Bus (SMBus) specification rev 2.0 compatibility:
–
Hardware PEC (Packet Error Checking) generation and verification with ACK
control
–
Address resolution protocol (ARP) support
–
SMBus alert
•
Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility
•
Independent clock: a choice of independent clock sources allowing the I2C
communication speed to be independent from the PCLK reprogramming.
•
Programmable analog and digital noise filters
•
1-byte buffer with DMA capability
Table 7. I2C implementation
I2C features(1)
I2C1
I2C2
I2C3
I2C4
Standard-mode (up to 100 kbit/s)
X
X
X
X
Fast-mode (up to 400 kbit/s)
X
X
X
X
Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
X
X
X
X
Programmable analog and digital noise filters
X
X
X
X
SMBus/PMBus hardware support
X
X
X
X
Independent clock
X
X
X
X
1. X: supported.
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2.25
STM32F767xx STM32F768Ax STM32F769xx
Universal synchronous/asynchronous receiver transmitters
(USART)
The device embeds USART. Refer to Table 8: USART implementation for the features
implementation.
The universal synchronous asynchronous receiver transmitter (USART) offers a flexible
means of full-duplex data exchange with external equipment requiring an industry standard
NRZ asynchronous serial data format.
The USART peripheral supports:
•
Full-duplex asynchronous communications
•
Configurable oversampling method by 16 or 8 to give flexibility between speed and
clock tolerance
•
Dual clock domain allowing convenient baud rate programming independent from the
PCLK reprogramming
•
A common programmable transmit and receive baud rate of up to 27 Mbit/s when
USART clock source is system clock frequency (max is 216 MHz) and oversampling by
8 is used.
•
Auto baud rate detection
•
Programmable data word length (7 or 8 or 9 bits) word length
•
Programmable data order with MSB-first or LSB-first shifting
•
Progarmmable parity (odd, even, no parity)
•
Configurable stop bits (1 or 1.5 or 2 stop bits)
•
Synchronous mode and clock output for synchronous communications
•
Single-wire half-duplex communications
•
Separate signal polarity control for transmission and reception
•
Swappable Tx/Rx pin configuration
•
Hardware flow control for modem and RS-485 transceiver
•
Multiprocessor communications
•
LIN master synchronous break send capability and LIN slave break detection capability
•
IrDA SIR encoder decoder supporting 3/16 bit duration for normal mode
•
Smartcard mode ( T=0 and T=1 asynchronous protocols for Smartcards as defined in
the ISO/IEC 7816-3 standard)
•
Support for Modbus communication
The table below summarizes the implementation of all U(S)ARTs instances
Table 8. USART implementation
features(1)
USART1/2/3/6
Data Length
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UART4/5/7/8
7, 8 and 9 bits
Hardware flow control for modem
X
X
Continuous communication using DMA
X
X
Multiprocessor communication
X
X
Synchronous mode
X
-
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Functional overview
Table 8. USART implementation (continued)
features(1)
USART1/2/3/6
UART4/5/7/8
Smartcard mode
X
-
Single-wire half-duplex communication
X
X
IrDA SIR ENDEC block
X
X
LIN mode
X
X
Dual clock domain
X
X
Receiver timeout interrupt
X
X
Modbus communication
X
X
Auto baud rate detection
X
X
Driver Enable
X
X
1. X: supported.
2.26
Serial peripheral interface (SPI)/inter- integrated sound
interfaces (I2S)
The devices feature up to six SPIs in slave and master modes in full-duplex and simplex
communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 50 Mbit/s,
SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master
mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces
support NSS pulse mode, TI mode and Hardware CRC calculation. All SPIs can be served
by the DMA controller.
Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They
can be operated in master or slave mode, in simplex communication modes, and can be
configured to operate with a 16-/32-bit resolution as an input or output channel. Audio
sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the
I2S interfaces is/are configured in master mode, the master clock can be output to the
external DAC/CODEC at 256 times the sampling frequency.
All I2Sx can be served by the DMA controller.
2.27
Serial audio interface (SAI)
The devices embed two serial audio interfaces.
The serial audio interface is based on two independent audio subblocks which can operate
as transmitter or receiver with their FIFO. Many audio protocols are supported by each
block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output,
supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be
configured in master or in slave mode.
In master mode, the master clock can be output to the external DAC/CODEC at 256 times of
the sampling frequency.
The two sub-blocks can be configured in synchronous mode when full-duplex mode is
required.
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SAI1 and SAI2 can be served by the DMA controller
2.28
SPDIFRX Receiver Interface (SPDIFRX)
The SPDIFRX peripheral, is designed to receive an S/PDIF flow compliant with IEC-60958
and IEC-61937. These standards support simple stereo streams up to high sample rate,
and compressed multi-channel surround sound, such as those defined by Dolby or DTS (up
to 5.1).
The main features of the SPDIFRX are the following:
•
Up to 4 inputs available
•
Automatic symbol rate detection
•
Maximum symbol rate: 12.288 MHz
•
Stereo stream from 32 to 192 kHz supported
•
Supports Audio IEC-60958 and IEC-61937, consumer applications
•
Parity bit management
•
Communication using DMA for audio samples
•
Communication using DMA for control and user channel information
•
Interrupt capabilities
The SPDIFRX receiver provides all the necessary features to detect the symbol rate, and
decode the incoming data stream. The user can select the wanted SPDIF input, and when a
valid signal will be available, the SPDIFRX will re-sample the incoming signal, decode the
manchester stream, recognize frames, sub-frames and blocks elements. It delivers to the
CPU decoded data, and associated status flags.
The SPDIFRX also offers a signal named spdif_frame_sync, which toggles at the S/PDIF
sub-frame rate that will be used to compute the exact sample rate for clock drift algorithms.
2.29
Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S and SAI applications. It allows
to achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S/SAI sample rate change
without disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 KHz to 192 KHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the
I2S/SAI flow with an external PLL (or Codec output).
2.30
Audio and LCD PLL (PLLSAI)
An additional PLL dedicated to audio and LCD-TFT is used for SAI1 peripheral in case the
PLLI2S is programmed to achieve another audio sampling frequency (49.152 MHz or
11.2896 MHz) and the audio application requires both sampling frequencies simultaneously.
The PLLSAI is also used to generate the LCD-TFT clock.
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Functional overview
SD/SDIO/MMC card host interface (SDMMC)
SDMMCs host interface are available, that supports MultiMediaCard System Specification
Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 50 MHz, and is compliant with the SD Memory
Card Specification Version 2.0.
The SDMMC Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDMMC/MMC4.2 card at any one time and a
stack of MMC4.1 or previous.
The SDMMC can be served by the DMA controller
2.32
Ethernet MAC interface with dedicated DMA and IEEE 1588
support
The devices provide an IEEE-802.3-2002-compliant media access controller (MAC) for
ethernet LAN communications through an industry-standard medium-independent interface
(MII) or a reduced medium-independent interface (RMII). The microcontroller requires an
external physical interface device (PHY) to connect to the physical LAN bus (twisted-pair,
fiber, etc.). The PHY is connected to the device MII port using 17 signals for MII or 9 signals
for RMII, and can be clocked using the 25 MHz (MII) from the microcontroller.
The devices include the following features:
2.33
•
Supports 10 and 100 Mbit/s rates
•
Dedicated DMA controller allowing high-speed transfers between the dedicated SRAM
and the descriptors
•
Tagged MAC frame support (VLAN support)
•
Half-duplex (CSMA/CD) and full-duplex operation
•
MAC control sublayer (control frames) support
•
32-bit CRC generation and removal
•
Several address filtering modes for physical and multicast address (multicast and
group addresses)
•
32-bit status code for each transmitted or received frame
•
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the
receive FIFO are both 2 Kbytes.
•
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 2008
(PTP V2) with the time stamp comparator connected to the TIM2 input
•
Triggers interrupt when system time becomes greater than target time
Controller area network (bxCAN)
The three CANs are compliant with the 2.0A and B (active) specifications with a bit rate up
to 1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
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CAN is used). 256 bytes of SRAM are allocated for CAN1 and CAN2. 512 bytes of SRAM
are dedicated for CAN3.
2.34
Universal serial bus on-the-go full-speed (OTG_FS)
The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated
transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and
with the OTG 2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
•
Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints
•
12 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
OTG 2.0 Supports ADP (Attach detection Protocol)
•
USB 2.0 LPM (Link Power Management) support
•
Battery Charging Specification Revision 1.2 support
•
Internal FS OTG PHY support
•
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.35
Universal serial bus on-the-go high-speed (OTG_HS)
The device embeds a USB OTG high-speed (up to 480 Mbit/s) device/host/OTG peripheral.
The USB OTG HS supports both full-speed and high-speed operations. It integrates the
transceivers for full-speed operation (12 Mbit/s) and features a UTMI low-pin interface
(ULPI) for high-speed operation (480 Mbit/s). When using the USB OTG HS in HS mode, an
external PHY device connected to the ULPI is required.
The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG
2.0 specification. It has software-configurable endpoint setting and supports
suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is
generated by a PLL connected to the HSE oscillator.
The major features are:
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•
Combined Rx and Tx FIFO size of 4 Kbytes with dynamic FIFO sizing
•
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
•
8 bidirectional endpoints
•
16 host channels with periodic OUT support
•
Software configurable to OTG1.3 and OTG2.0 modes of operation
•
OTG 2.0 Supports ADP (Attach detection Protocol)
•
USB 2.0 LPM (Link Power Management) support
•
Battery Charging Specification Revision 1.2 support
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2.36
Functional overview
•
Internal FS OTG PHY support
•
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
•
Internal USB DMA
•
HNP/SNP/IP inside (no need for any external resistor)
•
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
High-definition multimedia interface (HDMI) - consumer
electronics control (CEC)
The device embeds a HDMI-CEC controller that provides hardware support for the
Consumer Electronics Control (CEC) protocol (Supplement 1 to the HDMI standard).
This protocol provides high-level control functions between all audiovisual products in an
environment. It is specified to operate at low speeds with minimum processing and memory
overhead. It has a clock domain independent from the CPU clock, allowing the HDMI-CEC
controller to wakeup the MCU from Stop mode on data reception.
2.37
Digital camera interface (DCMI)
The devices embed a camera interface that can connect with camera modules and CMOS
sensors through an 8-bit to 14-bit parallel interface, to receive video data. The camera
interface can sustain a data transfer rate up to 54 Mbyte/s in 8-bit mode at 54 MHz. It
features:
•
Programmable polarity for the input pixel clock and synchronization signals
•
Parallel data communication can be 8-, 10-, 12- or 14-bit
•
Supports 8-bit progressive video monochrome or raw bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
•
Supports continuous mode or snapshot (a single frame) mode
•
Capability to automatically crop the image
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2.38
STM32F767xx STM32F768Ax STM32F769xx
Management Data Input/Output (MDIO) slaves
The device embed a MDIO slave interface it includes the following features:
•
–
32 x 16-bit firmware read/write, MDIO read-only output data registers
–
32 x 16-bit firmware read-only, MDIO write-only input data registers
•
Configurable slave (port) address
•
Independently maskable interrupts/events:
•
2.39
32 MDIO Registers addresses, each of which is managed using separate input and
output data registers:
–
MDIO Register write
–
MDIO Register read
–
MDIO protocol error
Able to operate in and wake up from STOP mode
Random number generator (RNG)
All the devices embed an RNG that delivers 32-bit random numbers generated by an
integrated analog circuit.
2.40
General-purpose input/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
alternate functions. All GPIOs are high-current-capable and have speed selection to better
manage internal noise, power consumption and electromagnetic emission.
The I/O configuration can be locked if needed by following a specific sequence in order to
avoid spurious writing to the I/Os registers.
Fast I/O handling allowing maximum I/O toggling up to 108 MHz.
2.41
Analog-to-digital converters (ADCs)
Three 12-bit analog-to-digital converters are embedded and each ADC shares up to 16
external channels, performing conversions in the single-shot or scan mode. In scan mode,
automatic conversion is performed on a selected group of analog inputs.
Additional logic functions embedded in the ADC interface allow:
•
Simultaneous sample and hold
•
Interleaved sample and hold
The ADC can be served by the DMA controller. An analog watchdog feature allows very
precise monitoring of the converted voltage of one, some or all selected channels. An
interrupt is generated when the converted voltage is outside the programmed thresholds.
To synchronize A/D conversion and timers, the ADCs could be triggered by any of TIM1,
TIM2, TIM3, TIM4, TIM5, or TIM8 timer.
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Functional overview
Digital filter for Sigma-Delta Modulators (DFSDM)
The device embeds one DFSDM with 4 digital filters modules and 8 external input serial
channels (transceivers) or alternately 8 internal parallel inputs support. The DFSDM
peripheral is dedicated to interface the external Σ∆ modulators to microcontroller and then to
perform digital filtering of the received data streams (which represent analog value on Σ∆
modulators inputs). DFSDM can also interface PDM (Pulse Density Modulation)
microphones and perform PDM to PCM conversion and filtering in hardware. DFSDM
features optional parallel data stream inputs from microcontrollers memory (through
DMA/CPU transfers into DFSDM). DFSDM transceivers support several serial interface
formats (to support various Σ∆ modulators). DFSDM digital filter modules perform digital
processing according user selected filter parameters with up to 24-bit final ADC resolution.
The DFSDM peripheral supports:
•
•
8 multiplexed input digital serial channels:
–
Configurable SPI interface to connect various SD modulator(s)
–
Configurable Manchester coded 1 wire interface support
–
PDM (Pulse Density Modulation) microphone input support
–
Maximum input clock frequency up to 20 MHz (10 MHz for Manchester coding)
–
Clock output for SD modulator(s): 0..20 MHz
Alternative inputs from 8 internal digital parallel channels (up to 16 bit input resolution):
–
•
internal sources: device memory data streams (DMA)
4 digital filter modules with adjustable digital signal processing:
–
Sincxfilter: filter order/type (1..5), oversampling ratio (up to 1..1024)
–
integrator: oversampling ratio (1..256)
•
Up to 24-bit output data resolution, signed output data format
•
Automatic data offset correction (offset stored in register by user)
•
Continuous or single conversion
•
Start-of-conversion triggered by:
•
•
–
Software trigger
–
Internal timers
–
External events
–
Start-of-conversion synchronously with first digital filter module (DFSDM0)
Analog watchdog feature:
–
Low value and high value data threshold registers
–
Dedicated configurable Sincx digital filter (order = 1..3, oversampling ratio = 1..32)
–
Input from final output data or from selected input digital serial channels
–
Continuous monitoring independently from standard conversion
Short circuit detector to detect saturated analog input values (bottom and top range):
–
Up to 8-bit counter to detect 1..256 consecutive 0’s or 1’s on serial data stream
–
Monitoring continuously each input serial channel
•
Break signal generation on analog watchdog event or on short circuit detector event
•
Extremes detector:
–
Storage of minimum and maximum values of final conversion data
–
Refreshed by software
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2.43
STM32F767xx STM32F768Ax STM32F769xx
•
DMA capability to read the final conversion data
•
Interrupts: end of conversion, overrun, analog watchdog, short circuit, input serial
channel clock absence
•
“regular” or “injected” conversions:
–
“regular” conversions can be requested at any time or even in continuous mode
without having any impact on the timing of “injected” conversions
–
“injected” conversions for precise timing and with high conversion priority
Temperature sensor
The temperature sensor has to generate a voltage that varies linearly with temperature. The
conversion range is between 1.7 V and 3.6 V. The temperature sensor is internally
connected to the same input channel as VBAT, ADC1_IN18, which is used to convert the
sensor output voltage into a digital value. When the temperature sensor and VBAT
conversion are enabled at the same time, only VBAT conversion is performed.
As the offset of the temperature sensor varies from chip to chip due to process variation, the
internal temperature sensor is mainly suitable for applications that detect temperature
changes instead of absolute temperatures. If an accurate temperature reading is needed,
then an external temperature sensor part should be used.
2.44
Digital-to-analog converter (DAC)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs.
This dual digital Interface supports the following features:
•
two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
•
left or right data alignment in 12-bit mode
•
synchronized update capability
•
noise-wave generation
•
triangular-wave generation
•
dual DAC channel independent or simultaneous conversions
•
DMA capability for each channel
•
external triggers for conversion
•
input voltage reference VREF+
Eight DAC trigger inputs are used in the device. The DAC channels are triggered through
the timer update outputs that are also connected to different DMA streams.
2.45
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
Debug is performed using 2 pins only instead of 5 required by the JTAG (JTAG pins could
be re-use as GPIO with alternate function): the JTAG TMS and TCK pins are shared with
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Functional overview
SWDIO and SWCLK, respectively, and a specific sequence on the TMS pin is used to
switch between JTAG-DP and SW-DP.
2.46
Embedded Trace Macrocell™
The ARM Embedded Trace Macrocell provides a greater visibility of the instruction and data
flow inside the CPU core by streaming compressed data at a very high rate from the
STM32F76xxx through a small number of ETM pins to an external hardware trace port
analyzer (TPA) device. The TPA is connected to a host computer using USB, Ethernet, or
any other high-speed channel. Real-time instruction and data flow activity can be recorded
and then formatted for display on the host computer that runs the debugger software. TPA
hardware is commercially available from common development tool vendors.
The Embedded Trace Macrocell operates with third party debugger software tools.
2.47
DSI Host (DSIHOST)
The DSI Host is a dedicated peripheral for interfacing with MIPI® DSI compliant displays. It
includes a dedicated video interface internally connected to the LTDC and a generic APB
interface that can be used to transmit information to the display.
These interfaces are as follows:
•
•
•
LTDC interface:
–
Used to transmit information in Video mode, in which the transfers from the host
processor to the peripheral take the form of a real-time pixel stream (DPI).
–
Through a customized for mode, this interface can be used to transmit information
in full bandwidth in the Adapted Command mode (DBI).
APB slave interface:
–
Allows the transmission of generic information in Command mode, and follows a
proprietary register interface.
–
Can operate concurrently with either LTDC interface in either Video mode or
Adapted Command mode.
Video mode pattern generator:
–
Allows the transmission of horizontal/vertical color bar and D-PHY BER testing
pattern without any kind of stimuli.
The DSI Host main features:
•
Compliant with MIPI® Alliance standards
•
Interface with MIPI® D-PHY
•
Supports all commands defined in the MIPI® Alliance specification for DCS:
–
Transmission of all Command mode packets through the APB interface
–
Transmission of commands in low-power and high-speed during Video mode
•
Supports up to two D-PHY data lanes
•
Bidirectional communication and escape mode support through data lane 0
•
Supports non-continuous clock in D-PHY clock lane for additional power saving
•
Supports Ultra Low-power mode with PLL disabled
•
ECC and Checksum capabilities
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44
Functional overview
STM32F767xx STM32F768Ax STM32F769xx
•
Support for End of Transmission Packet (EoTp)
•
Fault recovery schemes
•
3D transmission support
•
Configurable selection of system interfaces:
•
–
AMBA APB for control and optional support for Generic and DCS commands
–
Video Mode interface through LTDC
–
Adapted Command mode interface through LTDC
Independently programmable Virtual Channel ID in
–
Video mode
–
Adapted Command mode
–
APB Slave
Video Mode interfaces features:
•
LTDC interface color coding mappings into 24-bit interface:
–
16-bit RGB, configurations 1, 2, and 3
–
18-bit RGB, configurations 1 and 2
–
24-bit RGB
•
Programmable polarity of all LTDC interface signals
•
Extended resolutions beyond the DPI standard
•
Maximum resolution of 800x480 pixels:
•
Maximum resolution is limited by available DSI physical link bandwidth:
–
Number of lanes: 2
–
Maximum speed per lane: 500 Mbps1Gbps
Adapted interface features
Support for sending large amounts of data through the memory_write_start(WMS) and
memory_write_continue(WMC) DCS commands
•
LTDC interface color coding mappings into 24-bit interface:
–
16-bit RGB, configurations 1, 2, and 3
–
18-bit RGB, configurations 1 and 2
–
24-bit RGB
Video mode pattern generator:
44/129
•
Vertical and horizontal color bar generation without LTDC stimuli
•
BER pattern without LTDC stimuli
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
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Pinouts and pin description
D^ǀϯϰϭϳϭsϭ
1. The above figure shows the package top view.
DocID027972 Rev 5
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94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
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46/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
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1. The above figure shows the package top view.
DocID027972 Rev 5
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94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
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48/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Figure 13. STM32F769xx/STM32F768Ax WLCSP180 ballout
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DocID027972 Rev 5
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94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
ϭ
Ϯ
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Figure 14. STM32F767xx LQFP208 pinout
1. The above figure shows the package top view.
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STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
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06Y9
1. The above figure shows the package top view.
DocID027972 Rev 5
51/129
94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Figure 16. STM32F767xx UFBGA176 ballout
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1. The above figure shows the package top view.
52/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Figure 17. STM32F767xx TFBGA216 ballout
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1. The above figure shows the package top view.
DocID027972 Rev 5
53/129
94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Figure 18. STM32F769xx TFBGA216 ballout
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1. The above figure shows the package top view.
54/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 9. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function during and after
reset is the same as the actual pin name
Pin name
Pin type
I/O structure
Notes
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TTa
3.3 V tolerant I/O directly connected to ADC
B
Dedicated BOOT pin
RST
Bidirectional reset pin with weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
-
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions
1
A3
PE2
I/O FT
-
2
2
A1
2
2
A2
F10
2
2
A2
PE3
I/O FT
-
TRACED0, SAI1_SD_B,
FMC_A19, EVENTOUT
TFBGA216
1
LQFP208
E10
LQFP176
A3
WLCSP180
1
TFBGA216
1
LQFP208
A2
LQFP176
1
UFBGA176
1
TRACECLK, SPI4_SCK,
SAI1_MCLK_A,
QUADSPI_BK1_IO2,
ETH_MII_TXD3,
FMC_A23, EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
I/O structure
Pin type
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
DocID027972 Rev 5
Additional
functions
-
-
55/129
94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
3
4
B2
3
4
3
4
A1
B1
C12
D12
3
4
3
4
A1
B1
PE4
PE5
I/O structure
Pin type
TFBGA216
LQFP208
LQFP176
TFBGA216
LQFP208
LQFP176
UFBGA176
B1
I/O FT
I/O FT
Alternate functions
Additional
functions
-
TRACED1, SPI4_NSS,
SAI1_FS_A,
DFSDM_DATIN3,
FMC_A20, DCMI_D4,
LCD_B0, EVENTOUT
-
-
TRACED2, TIM9_CH1,
SPI4_MISO, SAI1_SCK_A,
DFSDM_CKIN3,
FMC_A21, DCMI_D6,
LCD_G0, EVENTOUT
-
-
TRACED3, TIM1_BKIN2,
TIM9_CH2, SPI4_MOSI,
SAI1_SD_A,
SAI2_MCLK_B, FMC_A22,
DCMI_D7, LCD_G1,
EVENTOUT
-
5
5
B3
5
5
B2
E11
5
5
B2
PE6
-
-
-
-
-
G6
-
-
-
G6
VSS
S
-
-
-
-
-
-
-
-
-
F5
-
-
-
F5
VDD
S
-
-
-
-
6
6
C1
6
6
C1
C13
6
6
C1
VBAT
S
-
-
-
-
-
-
D2
7
7
C2
-
7
7
C2
PI8
I/O FT
(1)
EVENTOUT
RTC_TAMP2/
RTC_TS/WK
UP5
7
7
D1
8
8
D1
D13
8
8
D1
PC13
I/O FT
(1)
EVENTOUT
RTC_TAMP1/
RTC_TS/
RTC_OUT/
WKUP4
8
8
E1
9
9
E1
E12
9
9
E1
PC14OSC32_I
N
I/O FT
EVENTOUT
OSC32_IN
9
9
F1
10
10
F1
E13
10
10
F1
PC15OSC32_O I/O FT
UT
(2)
EVENTOUT
OSC32_OUT
-
-
-
-
-
G5
-
-
-
G5
-
-
-
56/129
VDD
I/O FT
Notes
4
LQFP144
LQFP100
3
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
S
DocID027972 Rev 5
-
(1)
(2)
(1)
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
Pin Number
STM32F768Ax
STM32F769xx
LQFP176
LQFP208
TFBGA216
WLCSP180
LQFP176
LQFP208
TFBGA216
Pin name (function after reset)
Pin type
Notes
-
-
D3
11
11
E4
G1
0
11
11
E4
PI9
I/O FT
-
UART4_RX, CAN1_RX,
FMC_D30, LCD_VSYNC,
EVENTOUT
-
-
-
E3
12
12
D5
H10
12
12
D5
PI10
I/O FT
-
ETH_MII_RX_ER,
FMC_D31, LCD_HSYNC,
EVENTOUT
-
-
-
E4
13
13
F3
F11
13
13
F3
PI11
I/O FT
-
LCD_G6,
OTG_HS_ULPI_DIR,
EVENTOUT
WKUP6
-
-
F2
14
14
F2
F13
14
14
F2
VSS
S
-
-
-
-
-
-
F3
15
15
F4
F12
15
15
F4
VDD
S
-
-
-
-
-
10
E2
16
16
D2
G11
16
16
D2
PF0
I/O FT
-
I2C2_SDA, FMC_A0,
EVENTOUT
-
-
11
H3
17
17
E2
G1
2
17
17
E2
PF1
I/O FT
-
I2C2_SCL, FMC_A1,
EVENTOUT
-
-
12
H2
18
18
G2
G1
3
18
18
G2
PF2
I/O FT
-
I2C2_SMBA, FMC_A2,
EVENTOUT
-
-
-
-
-
19
E3
-
-
19
E3
PI12
I/O FT
-
LCD_HSYNC, EVENTOUT
-
-
-
-
-
20
G3
-
-
20
G3
PI13
I/O FT
-
LCD_VSYNC, EVENTOUT
-
-
-
-
-
21
H3
-
-
21
H3
PI14
I/O FT
-
LCD_CLK, EVENTOUT
-
-
13
J2
19
22
H2
H11
19
22
H2
PF3
I/O FT
-
FMC_A3, EVENTOUT
ADC3_IN9
-
14
J3
20
23
J2
H12
20
23
J2
PF4
I/O FT
-
FMC_A4, EVENTOUT
ADC3_IN14
-
15
K3
21
24
K3
H13
21
24
K3
PF5
I/O FT
-
FMC_A5, EVENTOUT
ADC3_IN15
10
16
G2
22
25
H6
J13
22
25
H6
VSS
S
-
-
-
-
11
17
G3
23
26
H5
J12
23
26
H5
VDD
S
-
-
-
-
-
18
K2
24
27
K2
-
24
27
K2
PF6
-
TIM10_CH1, SPI5_NSS,
SAI1_SD_B, UART7_RX,
QUADSPI_BK1_IO3,
EVENTOUT
ADC3_IN4
I/O structure
LQFP144
UFBGA176
Alternate functions
LQFP100
STM32F767xx
I/O FT
DocID027972 Rev 5
Additional
functions
57/129
94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
K1
28
K1
-
25
28
K1
PF7
I/O structure
Pin type
TFBGA216
LQFP208
LQFP176
TFBGA216
LQFP208
LQFP176
25
I/O FT
Notes
19
UFBGA176
LQFP144
LQFP100
-
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
TIM11_CH1, SPI5_SCK,
SAI1_MCLK_B,
UART7_TX,
QUADSPI_BK1_IO2,
EVENTOUT
ADC3_IN5
ADC3_IN6
-
20
L3
26
29
L3
-
26
29
L3
PF8
I/O FT
-
SPI5_MISO, SAI1_SCK_B,
UART7_RTS, TIM13_CH1,
QUADSPI_BK1_IO0,
EVENTOUT
-
21
L2
27
30
L2
-
27
30
L2
PF9
I/O FT
-
SPI5_MOSI, SAI1_FS_B,
UART7_CTS, TIM14_CH1,
QUADSPI_BK1_IO1,
EVENTOUT
ADC3_IN7
-
22
L1
28
31
L1
K11
28
31
L1
PF10
I/O FT
-
QUADSPI_CLK,
DCMI_D11, LCD_DE,
EVENTOUT
ADC3_IN8
12
23
G1
29
32
G1
K12
29
32
G1
PH0OSC_IN
I/O FT
(2)
EVENTOUT
OSC_IN
13
24
H1
30
33
H1
K13
30
33
H1
PH1OSC_OU I/O FT
T
(2)
EVENTOUT
OSC_OUT
14
25
J1
31
34
J1
L11
31
34
J1
-
-
-
-
DFSDM_CKIN0,
DFSDM_DATIN4,
SAI2_FS_B,
OTG_HS_ULPI_STP,
FMC_SDNWE, LCD_R5,
EVENTOUT
ADC1_IN10,
ADC2_IN10,
ADC3_IN10
-
TRACED0,
DFSDM_DATIN0,
SPI2_MOSI/I2S2_SD,
SAI1_SD_A,
DFSDM_CKIN4,
ETH_MDC, MDIOS_MDC,
EVENTOUT
ADC1_IN11,
ADC2_IN11,
ADC3_IN11,
RTC_TAMP3/
WKUP3
15
16
26
27
58/129
M2
M3
32
33
35
36
M2
M3
L12
L13
32
33
35
36
M2
M3
NRST
PC0
PC1
I/O
RS
T
I/O FT
I/O FT
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
M4
37
M4
-
34
37
M4
PC2
I/O structure
Pin type
TFBGA216
LQFP208
LQFP176
TFBGA216
LQFP208
LQFP176
34
I/O FT
Alternate functions
Additional
functions
-
DFSDM_CKIN1,
SPI2_MISO,
DFSDM_CKOUT,
OTG_HS_ULPI_DIR,
ETH_MII_TXD2,
FMC_SDNE0, EVENTOUT
ADC1_IN12,
ADC2_IN12,
ADC3_IN12
-
DFSDM_DATIN1,
SPI2_MOSI/I2S2_SD,
OTG_HS_ULPI_NXT,
ETH_MII_TX_CLK,
FMC_SDCKE0,
EVENTOUT
ADC1_IN13,
ADC2_IN13,
ADC3_IN13
18
29
M5
35
38
L4
-
35
38
L4
PC3
-
30
-
36
39
J5
-
36
39
J5
VDD
S
-
-
-
-
-
-
-
-
-
J6
-
-
-
J6
VSS
S
-
-
-
-
19
31
M1
37
40
M1
M11
37
40
M1
VSSA
S
-
-
-
-
-
-
N1
-
-
N1
-
-
-
N1
VREF-
S
-
-
-
-
20
32
P1
38
41
P1
-
38
41
P1
VREF+
S
-
-
-
-
21
33
R1
39
42
R1
M1
2
39
42
R1
VDDA
S
-
-
-
-
(3)
TIM2_CH1/TIM2_ETR,
TIM5_CH1, TIM8_ETR,
USART2_CTS,
UART4_TX, SAI2_SD_B,
ETH_MII_CRS,
EVENTOUT
ADC1_IN0,
ADC2_IN0,
ADC3_IN0,
WKUP1
-
TIM2_CH2, TIM5_CH2,
USART2_RTS,
UART4_RX,
QUADSPI_BK1_IO3,
SAI2_MCLK_B,
ETH_MII_RX_CLK/ETH_R
MII_REF_CLK, LCD_R2,
EVENTOUT
ADC1_IN1,
ADC2_IN1,
ADC3_IN1
22
23
34
35
N3
N2
40
41
43
44
N3
N2
M1
3
J11
40
41
43
44
N3
N2
PA0WKUP
PA1
I/O FT
Notes
28
UFBGA176
LQFP144
LQFP100
17
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
I/O FT
I/O FT
DocID027972 Rev 5
59/129
94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
36
-
F4
42
43
45
46
P2
K4
J10
L10
42
43
45
46
P2
K4
PA2
PH2
I/O structure
Pin type
TFBGA216
LQFP208
LQFP176
TFBGA216
LQFP208
LQFP176
UFBGA176
P2
I/O FT
I/O FT
Notes
-
LQFP144
LQFP100
24
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
TIM2_CH3, TIM5_CH3,
TIM9_CH1, USART2_TX,
SAI2_SCK_B, ETH_MDIO,
MDIOS_MDIO, LCD_R1,
EVENTOUT
ADC1_IN2,
ADC2_IN2,
ADC3_IN2,
WKUP2
-
LPTIM1_IN2,
QUADSPI_BK2_IO0,
SAI2_SCK_B,
ETH_MII_CRS,
FMC_SDCKE0, LCD_R0,
EVENTOUT
-
-
-
-
G4
44
47
J4
K10
44
47
J4
PH3
I/O FT
-
QUADSPI_BK2_IO1,
SAI2_MCLK_B,
ETH_MII_COL,
FMC_SDNE0, LCD_R1,
EVENTOUT
-
-
H4
45
48
H4
N12
45
48
H4
PH4
I/O FT
-
I2C2_SCL, LCD_G5,
OTG_HS_ULPI_NXT,
LCD_G4, EVENTOUT
-
-
-
J4
46
49
J3
N11
46
49
J3
PH5
I/O FT
-
I2C2_SDA, SPI5_NSS,
FMC_SDNWE,
EVENTOUT
-
-
TIM2_CH4, TIM5_CH4,
TIM9_CH2, USART2_RX,
LCD_B2,
OTG_HS_ULPI_D0,
ETH_MII_COL, LCD_B5,
EVENTOUT
ADC1_IN3,
ADC2_IN3,
ADC3_IN3
25
37
R2
47
50
R2
M1
0
47
50
R2
PA3
26
38
-
-
51
K6
J9
-
51
K6
VSS
S
-
-
-
-
-
-
L4
48
-
L5
-(4)
48
-
L5
BYPASS_
REG
I
FT
-
-
-
27
39
K4
49
52
K5
K9
49
52
K5
VDD
S
-
-
-
-
60/129
I/O FT
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
30
31
32
40
41
42
43
44
P4
P3
R3
N5
50
51
52
53
54
53
54
55
56
57
N4
P4
P3
R3
N5
L9
P11
N10
M9
-
50
51
52
53
54
53
54
55
56
57
N4
P4
P3
R3
N5
PA4
PA5
PA6
PA7
PC4
33
45
P5
55
58
P5
-
55
58
P5
PC5
-
-
-
-
59
L7
-
-
59
L7
VDD
I/O
I/O
I/O structure
Pin type
TFBGA216
LQFP208
LQFP176
TFBGA216
LQFP208
LQFP176
UFBGA176
N4
TT
a
TT
a
I/O FT
I/O FT
I/O FT
I/O FT
S
DocID027972 Rev 5
-
Notes
29
LQFP144
LQFP100
28
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
USART2_CK, SPI6_NSS,
OTG_HS_SOF,
DCMI_HSYNC,
LCD_VSYNC, EVENTOUT
ADC1_IN4,
ADC2_IN4,
DAC_OUT1
-
TIM2_CH1/TIM2_ETR,
TIM8_CH1N,
SPI1_SCK/I2S1_CK,
SPI6_SCK,
OTG_HS_ULPI_CK,
LCD_R4, EVENTOUT
ADC1_IN5,
ADC2_IN5,
DAC_OUT2
-
TIM1_BKIN, TIM3_CH1,
TIM8_BKIN, SPI1_MISO,
SPI6_MISO, TIM13_CH1,
MDIOS_MDC,
DCMI_PIXCLK, LCD_G2,
EVENTOUT
ADC1_IN6,
ADC2_IN6
-
TIM1_CH1N, TIM3_CH2,
TIM8_CH1N,
SPI1_MOSI/I2S1_SD,
SPI6_MOSI, TIM14_CH1,
ETH_MII_RX_DV/ETH_RM
II_CRS_DV,
FMC_SDNWE,
EVENTOUT
ADC1_IN7,
ADC2_IN7
-
DFSDM_CKIN2,
I2S1_MCK, SPDIF_RX2,
ETH_MII_RXD0/ETH_RMII
_RXD0, FMC_SDNE0,
EVENTOUT
ADC1_IN14,
ADC2_IN14
-
DFSDM_DATIN2,
SPDIF_RX3,
ETH_MII_RXD1/ETH_RMII
_RXD1, FMC_SDCKE0,
EVENTOUT
ADC1_IN15,
ADC2_IN15
-
-
-
61/129
94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
UFBGA176
LQFP176
LQFP208
TFBGA216
WLCSP180
LQFP176
LQFP208
TFBGA216
-
-
60
L6
-
-
60
L6
34
35
46
47
R5
R4
56
57
61
62
R5
R4
P10
J8
56
57
61
62
R5
R4
Notes
LQFP144
-
I/O structure
LQFP100
-
Pin type
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
VSS
S
-
-
-
PB0
PB1
I/O FT
I/O FT
Additional
functions
-
-
TIM1_CH2N, TIM3_CH3,
TIM8_CH2N,
DFSDM_CKOUT,
UART4_CTS, LCD_R3,
OTG_HS_ULPI_D1,
ETH_MII_RXD2, LCD_G1,
EVENTOUT
ADC1_IN8,
ADC2_IN8
-
TIM1_CH3N, TIM3_CH4,
TIM8_CH3N,
DFSDM_DATIN1, LCD_R6,
OTG_HS_ULPI_D2,
ETH_MII_RXD3, LCD_G0,
EVENTOUT
ADC1_IN9,
ADC2_IN9
-
36
48
M6
58
63
M5
J7
58
63
M5
PB2
I/O FT
-
SAI1_SD_A,
SPI3_MOSI/I2S3_SD,
QUADSPI_CLK,
DFSDM_CKIN1,
EVENTOUT
-
-
-
-
64
G4
-
-
64
G4
PI15
I/O FT
-
LCD_G2, LCD_R0,
EVENTOUT
-
-
-
-
-
65
R6
-
-
65
R6
PJ0
I/O FT
-
LCD_R7, LCD_R1,
EVENTOUT
-
-
-
-
-
66
R7
-
-
66
R7
PJ1
I/O FT
-
LCD_R2, EVENTOUT
-
-
-
-
-
67
P7
-
-
67
P7
PJ2
I/O FT
-
DSI_TE, LCD_R3,
EVENTOUT
-
-
-
-
-
68
N8
-
-
68
N8
PJ3
I/O FT
-
LCD_R4, EVENTOUT
-
-
-
-
-
69
M9
-
-
69
M9
PJ4
I/O FT
-
LCD_R5, EVENTOUT
-
-
49
R6
59
70
P8
N9
59
70
P8
PF11
I/O FT
-
SPI5_MOSI, SAI2_SD_B,
FMC_SDNRAS,
DCMI_D12, EVENTOUT
-
-
50
P6
60
71
M6
K7
60
71
M6
PF12
I/O FT
-
FMC_A6, EVENTOUT
-
-
51
M8
61
72
K7
P9
61
72
K7
VSS
S
-
-
-
-
52
N8
62
73
L8
M8
62
73
L8
VDD
S
-
-
-
62/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
LQFP176
LQFP208
TFBGA216
WLCSP180
LQFP176
LQFP208
TFBGA216
Notes
I/O structure
LQFP144
UFBGA176
Alternate functions
LQFP100
Pin type
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
-
53
N6
63
74
N6
L8
63
74
N6
PF13
I/O FT
-
I2C4_SMBA,
DFSDM_DATIN6,
FMC_A7, EVENTOUT
-
-
54
R7
64
75
P6
K8
64
75
P6
PF14
I/O FT
-
I2C4_SCL,
DFSDM_CKIN6, FMC_A8,
EVENTOUT
-
-
55
P7
65
76
M8
P8
65
76
M8
PF15
I/O FT
-
I2C4_SDA, FMC_A9,
EVENTOUT
-
-
56
N7
66
77
N7
N8
66
77
N7
PG0
I/O FT
-
FMC_A10, EVENTOUT
-
-
57
M7
67
78
M7
L7
67
78
M7
PG1
I/O FT
-
FMC_A11, EVENTOUT
-
-
TIM1_ETR,
DFSDM_DATIN2,
UART7_RX,
QUADSPI_BK2_IO0,
FMC_D4, EVENTOUT
-
-
TIM1_CH1N,
DFSDM_CKIN2,
UART7_TX,
QUADSPI_BK2_IO1,
FMC_D5, EVENTOUT
-
-
TIM1_CH1,
DFSDM_CKOUT,
UART7_RTS,
QUADSPI_BK2_IO2,
FMC_D6, EVENTOUT
-
37
38
58
59
R8
P8
68
69
79
80
R8
N9
M7
N7
68
69
79
80
R8
N9
PE7
PE8
I/O FT
I/O FT
39
60
P9
70
81
P9
P7
70
81
P9
PE9
-
61
M9
71
82
K8
-
71
82
K8
VSS
S
-
-
-
-
-
62
N9
72
83
L9
-
72
83
L9
VDD
S
-
-
-
-
-
TIM1_CH2N,
DFSDM_DATIN4,
UART7_CTS,
QUADSPI_BK2_IO3,
FMC_D7, EVENTOUT
-
40
63
R9
73
84
R9
J6
73
84
R9
PE10
I/O FT
Additional
functions
I/O FT
DocID027972 Rev 5
63/129
94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
85
P10
PE11
I/O FT
-
42
65 R10
75
86
R10
L6
75
86
R10
PE12
I/O FT
-
TIM1_CH3N, SPI4_SCK,
DFSDM_DATIN5,
SAI2_SCK_B, FMC_D9,
LCD_B4, EVENTOUT
-
-
TFBGA216
74
LQFP208
K6
LQFP176
P10
WLCSP180
85
TFBGA216
74
LQFP208
P10
LQFP176
64
UFBGA176
41
TIM1_CH2, SPI4_NSS,
DFSDM_CKIN4,
SAI2_SD_B, FMC_D8,
LCD_G3, EVENTOUT
LQFP144
Alternate functions
LQFP100
Notes
I/O structure
Pin type
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Additional
functions
-
43
66
N11
76
87
R12
P6
76
87
R12
PE13
I/O FT
-
TIM1_CH3, SPI4_MISO,
DFSDM_CKIN5,
SAI2_FS_B, FMC_D10,
LCD_DE, EVENTOUT
44
67
P11
77
88
P11
N6
77
88
P11
PE14
I/O FT
-
TIM1_CH4, SPI4_MOSI,
SAI2_MCLK_B, FMC_D11,
LCD_CLK, EVENTOUT
-
45
68
R11
78
89
R11
M6
78
89
R11
PE15
I/O FT
-
TIM1_BKIN, FMC_D12,
LCD_R7, EVENTOUT
-
-
TIM2_CH3, I2C2_SCL,
SPI2_SCK/I2S2_CK,
DFSDM_DATIN7,
USART3_TX,
QUADSPI_BK1_NCS,
OTG_HS_ULPI_D3,
ETH_MII_RX_ER,
LCD_G4, EVENTOUT
-
-
TIM2_CH4, I2C2_SDA,
DFSDM_CKIN7,
USART3_RX,
OTG_HS_ULPI_D4,
ETH_MII_TX_EN/ETH_RM
II_TX_EN, DSI_TE,
LCD_G5, EVENTOUT
-
46
69 R12
79
90
P12
K5
79
90
P12
PB10
I/O FT
47
70 R13
80
91
R13
L5
80
91
R13
PB11
48
71
M1
0
81
92
L11
P5
81
92
L11
VCAP_1
S
-
-
-
-
49
-
-
-
93
K9
N5
-
93
K9
VSS
S
-
-
-
-
82
94
L10
P4
82
94
L10
VDD
S
-
-
-
-
50
72 N10
64/129
I/O FT
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
UFBGA176
LQFP176
LQFP208
TFBGA216
WLCSP180
LQFP176
LQFP208
TFBGA216
-
-
95
M1
4
-
-
95
M1
4
PJ5
I/O FT
Notes
LQFP144
-
I/O structure
LQFP100
-
Pin type
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
LCD_R6, EVENTOUT
-
-
-
-
M11
83
96
P13
-
83
96
P13
PH6
I/O FT
-
I2C2_SMBA, SPI5_SCK,
TIM12_CH1,
ETH_MII_RXD2,
FMC_SDNE1, DCMI_D8,
EVENTOUT
-
-
N12
84
97
N13
-
84
97
N13
PH7
I/O FT
-
I2C3_SCL, SPI5_MISO,
ETH_MII_RXD3,
FMC_SDCKE1, DCMI_D9,
EVENTOUT
-
-
-
M1
2
85
98
P14
M5
-
98
P14
PH8
I/O FT
-
I2C3_SDA, FMC_D16,
DCMI_HSYNC, LCD_R2,
EVENTOUT
-
-
-
M1
3
86
99
N14
K4
-
99
N14
PH9
I/O FT
-
I2C3_SMBA, TIM12_CH2,
FMC_D17, DCMI_D0,
LCD_R3, EVENTOUT
-
-
-
L13
87
100 P15
L4
-
100 P15
PH10
I/O FT
-
TIM5_CH1, I2C4_SMBA,
FMC_D18, DCMI_D1,
LCD_R4, EVENTOUT
-
-
-
L12
88
101 N15
M4
-
101 N15
PH11
I/O FT
-
TIM5_CH2, I2C4_SCL,
FMC_D19, DCMI_D2,
LCD_R5, EVENTOUT
-
-
-
K12
89
102
M1
5
P3
-
102
M1
5
PH12
I/O FT
-
TIM5_CH3, I2C4_SDA,
FMC_D20, DCMI_D3,
LCD_R6, EVENTOUT
-
-
-
H12
90
-
K10
N4
-
-
K10
VSS
S
-
-
-
-
-
J12
91
-
-
103 K11
VDD
S
-
-
-
103 K11
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94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
53
73
74
P13
75 R14
92
93
94
104 L13
105 K14
106 R14
H8
J5
N3
85
86
87
104 L13
105 K14
106 R14
PB12
PB13
PB14
I/O structure
Pin type
TFBGA216
LQFP208
LQFP176
TFBGA216
LQFP208
LQFP176
UFBGA176
P12
I/O FT
I/O FT
I/O FT
Notes
52
LQFP144
LQFP100
51
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
TIM1_BKIN, I2C2_SMBA,
SPI2_NSS/I2S2_WS,
DFSDM_DATIN1,
USART3_CK, UART5_RX,
CAN2_RX,
OTG_HS_ULPI_D5,
ETH_MII_TXD0/ETH_RMII
_TXD0, OTG_HS_ID,
EVENTOUT
-
-
TIM1_CH1N,
SPI2_SCK/I2S2_CK,
DFSDM_CKIN1,
OTG_HS_VB
USART3_CTS,
US
UART5_TX, CAN2_TX,
OTG_HS_ULPI_D6,
ETH_MII_TXD1/ETH_RMII
_TXD1, EVENTOUT
-
TIM1_CH2N, TIM8_CH2N,
USART1_TX, SPI2_MISO,
DFSDM_DATIN2,
USART3_RTS,
UART4_RTS, TIM12_CH1,
SDMMC2_D0,
OTG_HS_DM, EVENTOUT
-
-
54
76 R15
95
107 R15
N2
88
107 R15
PB15
I/O FT
-
RTC_REFIN, TIM1_CH3N,
TIM8_CH3N, USART1_RX,
SPI2_MOSI/I2S2_SD,
DFSDM_CKIN2,
UART4_CTS, TIM12_CH2,
SDMMC2_D1,
OTG_HS_DP, EVENTOUT
55
77
P15
96
108 L15
M3
89
108 L15
PD8
I/O FT
-
DFSDM_CKIN3,
USART3_TX, SPDIF_RX1,
FMC_D13, EVENTOUT
-
56
78
P14
97
109 L14
L3
90
109 L14
PD9
I/O FT
-
DFSDM_DATIN3,
USART3_RX, FMC_D14,
EVENTOUT
-
66/129
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STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
59
80 N14
99
81 N13 100
111 N10
112
M1
0
110 K15
K3
J4
92
93
111 N10
112
M1
0
PD10
PD11
PD12
I/O structure
91
Pin type
M2
TFBGA216
LQFP208
110 K15
LQFP176
TFBGA216
98
I/O FT
I/O FT
I/O FT
Notes
58
LQFP208
79 N15
LQFP176
LQFP144
UFBGA176
LQFP100
57
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
DFSDM_CKOUT,
USART3_CK, FMC_D15,
LCD_B3, EVENTOUT
-
-
I2C4_SMBA,
USART3_CTS,
QUADSPI_BK1_IO0,
SAI2_SD_A,
FMC_A16/FMC_CLE,
EVENTOUT
-
-
TIM4_CH1, LPTIM1_IN1,
I2C4_SCL, USART3_RTS,
QUADSPI_BK1_IO1,
SAI2_FS_A,
FMC_A17/FMC_ALE,
EVENTOUT
-
-
TIM4_CH2, LPTIM1_OUT,
I2C4_SDA,
QUADSPI_BK1_IO3,
SAI2_SCK_A, FMC_A18,
EVENTOUT
-
60
82
M1
5
101
113 M11
L2
94
113 M11
PD13
-
83
-
102
114
J10
M1
95
114
J10
VSS
S
-
-
-
-
84
J13 103
115
J11
-
96
115
J11
VDD
S
-
-
-
61
85
M1
4
116
L12
L1
97
116 L12
PD14
I/O FT
-
TIM4_CH3, UART8_CTS,
FMC_D0, EVENTOUT
-
62
86
L14 105
117 K13
K2
98
117 K13
PD15
I/O FT
-
TIM4_CH4, UART8_RTS,
FMC_D1, EVENTOUT
-
-
-
-
-
118 K12
-
-
-
-
PJ6
I/O FT
-
LCD_R7, EVENTOUT
-
-
-
-
-
119
J12
-
-
-
-
PJ7
I/O FT
-
LCD_G0, EVENTOUT
-
-
-
-
-
120 H12
-
-
-
-
PJ8
I/O FT
-
LCD_G1, EVENTOUT
-
-
-
-
-
121
J13
-
-
-
-
PJ9
I/O FT
-
LCD_G2, EVENTOUT
-
-
-
-
-
122 H13
-
-
-
-
PJ10
I/O FT
-
LCD_G3, EVENTOUT
-
-
-
-
-
123
G1
2
-
-
-
-
PJ11
I/O FT
-
LCD_G4, EVENTOUT
-
104
I/O FT
DocID027972 Rev 5
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94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
LQFP208
TFBGA216
-
-
H6
100
-
-
J3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LQFP208
-
124 H11
-
-
125 H10
118 H11
-
H10
Notes
LQFP176
-
-
I/O structure
WLCSP180
99
-
TFBGA216
K1
LQFP176
-
UFBGA176
-
LQFP144
-
LQFP100
-
-
Pin type
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
VDD
S
-
-
-
-
VDDDSI
S
-
-
-
-
VSS
S
-
-
-
-
S
-
-
-
-
119 K12 VCAPDSI
Additional
functions
G1
3
VDD12DS
I
S
-
-
-
-
J1
101 120 J12
DSI_D0P
A
-
-
-
-
-
J2
102 121 J13
DSI_D0N
A
-
-
-
-
-
-
H5
103 122
G1
2
VSSDSI
S
-
-
-
-
-
-
-
H4
104 123 H12 DSI_CKP
A
-
-
-
-
-
-
-
-
H3
105 124 H13 DSI_CKN
A
-
-
-
-
-
-
-
-
-
-
VDD12DS
I
S
-
-
-
-
-
-
-
-
H1
107 126 F12
DSI_D1P
A
-
-
-
-
-
-
-
-
-
H2
108 127 F13
DSI_D1N
A
-
-
-
-
-
-
-
-
-
-
109 128
-
VSSDSI
S
-
-
-
-
-
-
-
126
G1
3
-
-
-
-
PK0
I/O FT
-
LCD_G5, EVENTOUT
-
-
-
-
-
127 F12
-
-
-
-
PK1
I/O FT
-
LCD_G6, EVENTOUT
-
-
-
-
-
128 F13
-
-
-
-
PK2
I/O FT
-
LCD_G7, EVENTOUT
-
-
87
L15 106 129
M1
3
H9
110
129
M1
3
PG2
I/O FT
-
FMC_A12, EVENTOUT
-
-
88
K15 107 130
M1
2
G9
111
130
M1
2
PG3
I/O FT
-
FMC_A13, EVENTOUT
-
-
89
K14 108 131 N12
G1
112
131 N12
PG4
I/O FT
-
FMC_A14/FMC_BA0,
EVENTOUT
-
-
90
K13 109 132 N11
G2
113
132 N11
PG5
I/O FT
-
FMC_A15/FMC_BA1,
EVENTOUT
-
68/129
-
106 125
-
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
Pin Number
STM32F768Ax
STM32F769xx
LQFP208
TFBGA216
WLCSP180
LQFP176
LQFP208
Pin name (function after reset)
Pin type
Notes
91
J15
110
133
J15
G3
114
133 J15
PG6
I/O FT
-
FMC_NE3, DCMI_D12,
LCD_R7, EVENTOUT
-
-
92
J14
111
134
J14
G4
115
134 J14
PG7
I/O FT
-
SAI1_MCLK_A,
USART6_CK, FMC_INT,
DCMI_D13, LCD_CLK,
EVENTOUT
-
-
SPI6_NSS, SPDIF_RX2,
USART6_RTS,
ETH_PPS_OUT,
FMC_SDCLK, LCD_G7,
EVENTOUT
-
-
93 H14 112
-
94
-
95 H13 114
63
64
65
G1
2
113
96 H15 115
97
98
G1
5
G1
4
116
117
I/O structure
LQFP176
-
TFBGA216
LQFP144
UFBGA176
Alternate functions
LQFP100
STM32F767xx
135 H14
G5
116
135 H14
PG8
G1
0
F1
117
136
G1
0
VSS
S
-
-
-
137 G11
F2
118
137 G11
VDDUSB
S
-
-
-
-
TIM3_CH1, TIM8_CH1,
I2S2_MCK,
DFSDM_CKIN3,
USART6_TX,
FMC_NWAIT,
SDMMC2_D6,
SDMMC1_D6, DCMI_D0,
LCD_HSYNC, EVENTOUT
-
-
TIM3_CH2, TIM8_CH2,
I2S3_MCK,
DFSDM_DATIN3,
USART6_RX, FMC_NE1,
SDMMC2_D7,
SDMMC1_D7, DCMI_D1,
LCD_G6, EVENTOUT
-
-
TRACED1, TIM3_CH3,
TIM8_CH3, UART5_RTS,
USART6_CK,
FMC_NE2/FMC_NCE,
SDMMC1_D0, DCMI_D2,
EVENTOUT
136
138 H15
139
140
G1
5
G1
4
G6
F3
G8
119
138 H15
120 139
121 140
G1
5
G1
4
PC6
PC7
PC8
I/O FT
Additional
functions
I/O FT
I/O FT
I/O FT
DocID027972 Rev 5
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Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
141 F14
E1
122 141 F14
PC9
I/O structure
Pin type
TFBGA216
LQFP208
LQFP176
TFBGA216
LQFP208
LQFP176
F14 118
I/O FT
Notes
99
UFBGA176
LQFP144
LQFP100
66
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
MCO2, TIM3_CH4,
TIM8_CH4, I2C3_SDA,
I2S_CKIN, UART5_CTS,
QUADSPI_BK1_IO0,
LCD_G3, SDMMC1_D1,
DCMI_D3, LCD_B2,
EVENTOUT
--
-
67
10
0
F15 119
142 F15
E2
123 142 F15
PA8
I/O FT
-
MCO1, TIM1_CH1,
TIM8_BKIN2, I2C3_SCL,
USART1_CK,
OTG_FS_SOF, CAN3_RX,
UART7_RX, LCD_B3,
LCD_R6, EVENTOUT
68
10
1
E15 120 143 E15
F4
124 143 E15
PA9
I/O FT
-
TIM1_CH2, I2C3_SMBA,
SPI2_SCK/I2S2_CK,
USART1_TX, DCMI_D0,
LCD_R5, EVENTOUT
OTG_FS_VB
US
69
10
D15 121 144 D15
2
-
TIM1_CH3, USART1_RX,
LCD_B4, OTG_FS_ID,
MDIOS_MDIO, DCMI_D1,
LCD_B1, EVENTOUT
-
-
TIM1_CH4,
SPI2_NSS/I2S2_WS,
UART4_RX,
USART1_CTS, CAN1_RX,
OTG_FS_DM, LCD_R4,
EVENTOUT
-
-
-
70
10
C15 122 145 C15
3
F5
E3
125 144 D15
126 145 C15
PA10
PA11
I/O FT
I/O FT
71
10
4
B15 123 146 B15
D1
127 146 B15
PA12
I/O FT
-
TIM1_ETR,
SPI2_SCK/I2S2_CK,
UART4_TX,
USART1_RTS,
SAI2_FS_B, CAN1_TX,
OTG_FS_DP, LCD_R5,
EVENTOUT
72
10
5
A15 124 147 A15
D2
128 147 A15
PA13(JT
MSSWDIO)
I/O FT
-
JTMS-SWDIO, EVENTOUT
70/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
Pin Number
STM32F768Ax
STM32F769xx
LQFP176
Pin name (function after reset)
Pin type
I/O structure
Notes
C1
129 148 E11
VCAP_2
S
-
-
-
-
74
10
7
F12 126 149 F10
C2
130 149 F10
VSS
S
-
-
-
-
75
10
8
G1
3
127 150 F11
B2
131 150 F11
VDD
S
-
-
-
-
-
-
E12 128 151 E12
F6
-
151 E12
PH13
I/O FT
-
TIM8_CH1N, UART4_TX,
CAN1_TX, FMC_D21,
LCD_G2, EVENTOUT
-
-
-
E13 129 152 E13
F7
-
152 E13
PH14
I/O FT
-
TIM8_CH2N, UART4_RX,
CAN1_RX, FMC_D22,
DCMI_D4, LCD_G3,
EVENTOUT
-
-
-
D13 130 153 D13
E5
-
153 D13
PH15
I/O FT
-
TIM8_CH3N, FMC_D23,
DCMI_D11, LCD_G4,
EVENTOUT
-
-
TFBGA216
WLCSP180
F13 125 148 E11
LQFP208
TFBGA216
10
6
LQFP208
73
LQFP176
LQFP144
UFBGA176
Alternate functions
LQFP100
STM32F767xx
Additional
functions
-
-
E14 131 154 E14
E4
132 154 E14
PI0
I/O FT
-
TIM5_CH4,
SPI2_NSS/I2S2_WS,
FMC_D24, DCMI_D13,
LCD_G5, EVENTOUT
-
-
D14 132 155 D14
B3
133 155 D14
PI1
I/O FT
-
TIM8_BKIN2,
SPI2_SCK/I2S2_CK,
FMC_D25, DCMI_D8,
LCD_G6, EVENTOUT
-
-
-
C14 133 156 C14
C3
PI2
I/O FT
-
TIM8_CH4, SPI2_MISO,
FMC_D26, DCMI_D9,
LCD_G7, EVENTOUT
-
-
TIM8_ETR,
SPI2_MOSI/I2S2_SD,
FMC_D27, DCMI_D10,
EVENTOUT
-
-
-
C13 134 157 C13
-
-
D9
135
-
-
C9
136 158 E10
-
F9
D3
-
156 C14
134 157 C13
PI3
-
135
F9
VSS
S
-
-
-
-
136 158 E10
VDD
S
-
-
-
-
I/O FT
DocID027972 Rev 5
--
71/129
94
Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
11
0
A13 138 160 A13
78 111 B14 139 161 B14
F8
B4
138 160 A13
139 161 B14
I/O structure
Pin type
TFBGA216
137 159 A14
LQFP208
LQFP176
A3
PA14(JTC
KI/O FT
SWCLK)
PA15(JTD
I/O FT
I)
PC10
I/O FT
Notes
77
TFBGA216
UFBGA176
A14 137 159 A14
LQFP208
LQFP144
10
9
LQFP176
LQFP100
76
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
JTCK-SWCLK,
EVENTOUT
-
-
JTDI,
TIM2_CH1/TIM2_ETR,
HDMI_CEC,
SPI1_NSS/I2S1_WS,
SPI3_NSS/I2S3_WS,
SPI6_NSS, UART4_RTS,
CAN3_TX, UART7_TX,
EVENTOUT
-
-
DFSDM_CKIN5,
SPI3_SCK/I2S3_CK,
USART3_TX, UART4_TX,
QUADSPI_BK1_IO1,
SDMMC1_D2, DCMI_D8,
LCD_R2, EVENTOUT
-
-
DFSDM_DATIN5,
SPI3_MISO, USART3_RX,
UART4_RX,
QUADSPI_BK2_NCS,
SDMMC1_D3, DCMI_D4,
EVENTOUT
-
-
79
11
2
80
11
3
A12 141 163 A12
D4
141 163 A12
PC12
I/O FT
-
TRACED3,
SPI3_MOSI/I2S3_SD,
USART3_CK, UART5_TX,
SDMMC1_CK, DCMI_D9,
EVENTOUT
81
11
4
B12 142 164 B12
A4
142 164 B12
PD0
I/O FT
-
DFSDM_CKIN6,
DFSDM_DATIN7,
UART4_RX, CAN1_RX,
FMC_D2, EVENTOUT
-
82
11
5
-
DFSDM_DATIN6,
DFSDM_CKIN7,
UART4_TX, CAN1_TX,
FMC_D3, EVENTOUT
--
72/129
B13 140 162 B13
C12 143 165 C12
C4
D5
140 162 B13
143 165 C12
PC11
PD1
I/O FT
I/O FT
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
D6
PD2
I/O structure
Pin type
TFBGA216
LQFP208
144 166 D12
I/O FT
Notes
D12 144 166 D12
LQFP176
TFBGA216
LQFP208
LQFP176
LQFP144
UFBGA176
LQFP100
83
11
6
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
TRACED2, TIM3_ETR,
UART5_RX,
SDMMC1_CMD,
DCMI_D11, EVENTOUT
-
-
84
11
7
D11 145 167 C11
B5
145 167 C11
PD3
I/O FT
-
DFSDM_CKOUT,
SPI2_SCK/I2S2_CK,
DFSDM_DATIN0,
USART2_CTS, FMC_CLK,
DCMI_D5, LCD_G7,
EVENTOUT
85
11
8
D10 146 168 D11
A5
146 168 D11
PD4
I/O FT
-
DFSDM_CKIN0,
USART2_RTS, FMC_NOE,
EVENTOUT
-
86
11
9
C11 147 169 C10
C5
147 169 C10
PD5
I/O FT
-
USART2_TX, FMC_NWE,
EVENTOUT
-
-
12
0
D8
148 170
F8
B6
148 170
F8
VSS
S
-
-
-
-
-
12
1
C8
149 171
E9
A6
149 171
E9
VDDSDM
MC
S
-
-
-
-
-
DFSDM_CKIN4,
SPI3_MOSI/I2S3_SD,
SAI1_SD_A, USART2_RX,
DFSDM_DATIN1,
SDMMC2_CK,
FMC_NWAIT, DCMI_D10,
LCD_B2, EVENTOUT
-
-
87
12
2
B11 150 172 B11
E6
150 172 B11
88
12
3
-
-
-
-
174 B10
-
-
-
-
-
-
175
-
-
A11 151 173 A11
B9
E7
PD6
I/O FT
PD7
I/O FT
-
DFSDM_DATIN4,
SPI1_MOSI/I2S1_SD,
DFSDM_CKIN1,
USART2_CK, SPDIF_RX0,
SDMMC2_CMD,
FMC_NE1, EVENTOUT
174 B10
PJ12
I/O FT
-
LCD_G3, LCD_B0,
EVENTOUT
-
175
PJ13
I/O FT
-
LCD_G4, LCD_B1,
EVENTOUT
-
151 173 A11
B9
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Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
LQFP176
LQFP208
TFBGA216
WLCSP180
LQFP176
LQFP208
TFBGA216
Notes
I/O structure
LQFP144
UFBGA176
Alternate functions
LQFP100
Pin type
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
-
-
-
-
176
C9
-
-
176
C9
PJ14
I/O FT
-
LCD_B2, EVENTOUT
-
-
-
-
-
177 D10
-
-
177 D10
PJ15
I/O FT
-
LCD_B3, EVENTOUT
-
-
SPI1_MISO, SPDIF_RX3,
USART6_RX,
QUADSPI_BK2_IO2,
SAI2_FS_B, SDMMC2_D0,
FMC_NE2/FMC_NCE,
DCMI_VSYNC,
EVENTOUT
-
-
SPI1_NSS/I2S1_WS,
LCD_G3, SAI2_SD_B,
SDMMC2_D1, FMC_NE3,
DCMI_D2, LCD_B2,
EVENTOUT
-
-
SPI1_SCK/I2S1_CK,
SPDIF_RX0,
SDMMC2_D2,
ETH_MII_TX_EN/ETH_RM
II_TX_EN, DCMI_D3,
LCD_B3, EVENTOUT
-
-
LPTIM1_IN1, SPI6_MISO,
SPDIF_RX1,
USART6_RTS, LCD_B4,
SDMMC2_D3, FMC_NE4,
LCD_B1, EVENTOUT
-
-
TRACED0, LPTIM1_OUT,
SPI6_SCK, USART6_CTS,
ETH_MII_TXD0/ETH_RMII
_TXD0, FMC_A24,
LCD_R0, EVENTOUT
-
-
TRACED1, LPTIM1_ETR,
SPI6_MOSI, USART6_TX,
QUADSPI_BK2_IO3,
ETH_MII_TXD1/ETH_RMII
_TXD1, FMC_A25,
LCD_B0, EVENTOUT
-
-
-
12
C10 152 178
4
12
5
-
12
6
-
12
7
-
12
8
-
12
9
74/129
B10 153 179
B9
B8
A8
A7
154 180
155 181
156 182
157 183
D9
C8
B8
C7
B3
A4
C6
A7
B7
D7
C7
-
152 178
153 179
154 180
155 181
156 182
157 183
D9
C8
B8
C7
B3
A4
PG9
PG10
PG11
PG12
PG13
PG14
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
I/O FT
DocID027972 Rev 5
Additional
functions
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
Pin Number
STM32F768Ax
STM32F769xx
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
WLCSP180
LQFP176
LQFP208
TFBGA216
Pin name (function after reset)
Pin type
I/O structure
Notes
Alternate functions
LQFP100
STM32F767xx
-
13
0
D7
158 184
F7
A8
158 184
F7
VSS
S
-
-
-
-
-
13
1
C7
159 185
E8
B8
159 185
E8
VDD
S
-
-
-
-
-
-
-
-
186
D8
-
-
186
D8
PK3
I/O FT
-
LCD_B4, EVENTOUT
-
-
-
-
-
187
D7
-
-
187
D7
PK4
I/O FT
-
LCD_B5, EVENTOUT
-
-
-
-
-
188
C6
-
-
188
C6
PK5
I/O FT
-
LCD_B6, EVENTOUT
-
-
-
-
-
189
C5
-
-
189
C5
PK6
I/O FT
-
LCD_B7, EVENTOUT
-
-
-
-
-
190
C4
-
-
190
C4
PK7
I/O FT
-
LCD_DE, EVENTOUT
-
-
13
2
B7
160 191
B7
F9
160 191
B7
PG15
I/O FT
-
USART6_CTS,
FMC_SDNCAS,
DCMI_D13, EVENTOUT
-
-
JTDO/TRACESWO,
TIM2_CH2,
SPI1_SCK/I2S1_CK,
SPI3_SCK/I2S3_CK,
SPI6_SCK, SDMMC2_D2,
CAN3_RX, UART7_RX,
EVENTOUT
-
-
NJTRST, TIM3_CH1,
SPI1_MISO, SPI3_MISO,
SPI2_NSS/I2S2_WS,
SPI6_MISO, SDMMC2_D3,
CAN3_TX, UART7_TX,
EVENTOUT
-
-
UART5_RX, TIM3_CH2,
I2C1_SMBA,
SPI1_MOSI/I2S1_SD,
SPI3_MOSI/I2S3_SD,
SPI6_MOSI, CAN2_RX,
OTG_HS_ULPI_D7,
ETH_PPS_OUT,
FMC_SDCKE1,
DCMI_D10, LCD_G7,
EVENTOUT
-
89
90
91
13
3
13
4
13
5
A10 161 192 A10
A9
A6
162 193
163 194
A9
A8
E8
D8
A9
161 192 A10
162 193
163 194
A9
A8
PB3
(JTDO/
TRACES
WO)
PB4(NJT
RST)
PB5
I/O FT
I/O FT
I/O FT
DocID027972 Rev 5
Additional
functions
75/129
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Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
B6
B6
B9
164 195
B6
PB6
93
13
7
B5
165 196
B5
C8
165 196
B5
PB7
94
13
8
D6
166 197
E6
A10 166 197
E6
BOOT0
95
96
97
13
9
14
0
14
1
76/129
A5
B4
A4
167 198
168 199
169 200
A7
B4
A6
E9
D9
C9
167 198
168 199
169 200
A7
B4
A6
PB8
PB9
PE0
I/O structure
Pin type
TFBGA216
LQFP208
LQFP176
TFBGA216
LQFP208
LQFP176
164 195
I/O FT
I/O FT
I
B
I/O FT
I/O FT
I/O FT
DocID027972 Rev 5
Notes
13
6
UFBGA176
LQFP144
LQFP100
92
WLCSP180
STM32F768Ax
STM32F769xx
STM32F767xx
Pin name (function after reset)
Pin Number
Alternate functions
Additional
functions
-
UART5_TX, TIM4_CH1,
HDMI_CEC, I2C1_SCL,
DFSDM_DATIN5,
USART1_TX, CAN2_TX,
QUADSPI_BK1_NCS,
I2C4_SCL, FMC_SDNE1,
DCMI_D5, EVENTOUT
-
-
TIM4_CH2, I2C1_SDA,
DFSDM_CKIN5,
USART1_RX, I2C4_SDA,
FMC_NL, DCMI_VSYNC,
EVENTOUT
-
-
-
VPP
-
I2C4_SCL, TIM4_CH3,
TIM10_CH1, I2C1_SCL,
DFSDM_CKIN7,
UART5_RX, CAN1_RX,
SDMMC2_D4,
ETH_MII_TXD3,
SDMMC1_D4, DCMI_D6,
LCD_B6, EVENTOUT
-
-
I2C4_SDA, TIM4_CH4,
TIM11_CH1, I2C1_SDA,
SPI2_NSS/I2S2_WS,
DFSDM_DATIN7,
UART5_TX, CAN1_TX,
SDMMC2_D5,
I2C4_SMBA,
SDMMC1_D5, DCMI_D7,
LCD_B7, EVENTOUT
-
-
TIM4_ETR, LPTIM1_ETR,
UART8_RX,
SAI2_MCLK_A,
FMC_NBL0, DCMI_D2,
EVENTOUT
-
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
Pin Number
STM32F768Ax
STM32F769xx
TFBGA216
Pin name (function after reset)
Pin type
202
F6
A11
202
F6
VSS
S
-
-
-
-
C6
171 203
E5
C10 171 203
E5
PDR_ON
S
-
-
-
-
C5
172 204
E7
B11 172 204
E7
VDD
S
-
-
-
-
-
A3
99
-
D5
-
14
3
10
0
14
4
-
-
Notes
LQFP208
I/O FT
14
2
I/O structure
WLCSP180
PE1
98
LQFP176
TFBGA216
A5
LQFP176
B10 170 201
UFBGA176
A5
LQFP144
170 201
LQFP100
LQFP208
STM32F767xx
Alternate functions
Additional
functions
-
LPTIM1_IN2, UART8_TX,
FMC_NBL1, DCMI_D3,
EVENTOUT
-
-
-
D4
173 205
C3
D10 173 205
C3
PI4
I/O FT
-
TIM8_BKIN,
SAI2_MCLK_A,
FMC_NBL2, DCMI_D5,
LCD_B4, EVENTOUT
-
-
C4
174 206
D3
D11 174 206
D3
PI5
I/O FT
-
TIM8_CH1, SAI2_SCK_A,
FMC_NBL3,
DCMI_VSYNC, LCD_B5,
EVENTOUT
-
-
-
C3
175 207
D6
C11 175 207
D6
PI6
I/O FT
-
TIM8_CH2, SAI2_SD_A,
FMC_D28, DCMI_D6,
LCD_B6, EVENTOUT
-
-
-
C2
176 208
D4
B12 176 208
D4
PI7
I/O FT
-
TIM8_CH3, SAI2_FS_A,
FMC_D29, DCMI_D7,
LCD_B7, EVENTOUT
-
-
-
F6
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
F7
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
F8
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
F9
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
F10
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
G6
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
G7
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
G8
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
G9
-
-
-
-
-
-
-
VSS
S
-
-
-
-
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Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 10. STM32F767xx, STM32F768Ax and STM32F769xx pin and ball definitions (continued)
Pin Number
STM32F768Ax
STM32F769xx
LQFP144
UFBGA176
LQFP176
LQFP208
TFBGA216
WLCSP180
LQFP176
LQFP208
TFBGA216
Pin name (function after reset)
Pin type
I/O structure
Notes
Alternate functions
LQFP100
STM32F767xx
-
-
G1
0
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
H6
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
H7
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
H8
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
H9
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
H10
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
J6
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
J7
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
J8
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
J9
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
J10
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
K6
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
K7
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
K8
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
K9
-
-
-
-
-
-
-
VSS
S
-
-
-
-
-
-
K10
-
-
-
-
-
-
-
VSS
S
-
-
-
-
Additional
functions
1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current
(3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: - The speed should not exceed 2 MHz with a
maximum load of 30 pF. - These I/Os must not be used as a current source (e.g. to drive an LED).
2. FT = 5 V tolerant except when in analog mode or oscillator mode (for PC14, PC15, PH0 and PH1).
3. If the device is in regulator OFF/internal reset ON mode (BYPASS_REG pin is set to VDD), then PA0 is used as an internal
reset (active low).
4. Internally connected to VDD or VSS depending on part number.
78/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 11. FMC pin definition
Pin name
NOR/PSRAM/SR
AM
NOR/PSRAM
Mux
NAND16
SDRAM
PF0
A0
-
-
A0
PF1
A1
-
-
A1
PF2
A2
-
-
A2
PF3
A3
-
-
A3
PF4
A4
-
-
A4
PF5
A5
-
-
A5
PF12
A6
-
-
A6
PF13
A7
-
-
A7
PF14
A8
-
-
A8
PF15
A9
-
-
A9
PG0
A10
-
-
A10
PG1
A11
-
-
A11
PG2
A12
-
-
A12
PG3
A13
-
-
-
PG4
A14
-
-
BA0
PG5
A15
-
-
BA1
PD11
A16
A16
CLE
-
PD12
A17
A17
ALE
-
PD13
A18
A18
-
-
PE3
A19
A19
-
-
PE4
A20
A20
-
-
PE5
A21
A21
-
-
PE6
A22
A22
-
-
PE2
A23
A23
-
-
PG13
A24
A24
-
-
PG14
A25
A25
-
-
PD14
D0
DA0
D0
D0
PD15
D1
DA1
D1
D1
PD0
D2
DA2
D2
D2
PD1
D3
DA3
D3
D3
PE7
D4
DA4
D4
D4
PE8
D5
DA5
D5
D5
PE9
D6
DA6
D6
D6
PE10
D7
DA7
D7
D7
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Pinouts and pin description
STM32F767xx STM32F768Ax STM32F769xx
Table 11. FMC pin definition (continued)
80/129
Pin name
NOR/PSRAM/SR
AM
NOR/PSRAM
Mux
NAND16
SDRAM
PE11
D8
DA8
D8
D8
PE12
D9
DA9
D9
D9
PE13
D10
DA10
D10
D10
PE14
D11
DA11
D11
D11
PE15
D12
DA12
D12
D12
PD8
D13
DA13
D13
D13
PD9
D14
DA14
D14
D14
PD10
D15
DA15
D15
D15
PH8
D16
-
-
D16
PH9
D17
-
-
D17
PH10
D18
-
-
D18
PH11
D19
-
-
D19
PH12
D20
-
-
D20
PH13
D21
-
-
D21
PH14
D22
-
-
D22
PH15
D23
-
-
D23
PI0
D24
-
-
D24
PI1
D25
-
-
D25
PI2
D26
-
-
D26
PI3
D27
-
-
D27
PI6
D28
-
-
D28
PI7
D29
-
-
D29
PI9
D30
-
-
D30
PI10
D31
-
-
D31
PD7
NE1
NE1
-
-
PG6
NE3
-
-
-
PG9
NE2
NE2
NCE
-
PG10
NE3
NE3
-
-
PG11
-
-
-
-
PG12
NE4
NE4
-
-
PD3
CLK
CLK
-
-
PD4
NOE
NOE
NOE
-
PD5
NWE
NWE
NWE
-
PD6
NWAIT
NWAIT
NWAIT
-
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Pinouts and pin description
Table 11. FMC pin definition (continued)
Pin name
NOR/PSRAM/SR
AM
NOR/PSRAM
Mux
NAND16
SDRAM
PB7
NADV
NADV
-
-
PF6
-
-
-
-
PF7
-
-
-
-
PF8
-
-
-
-
PF9
-
-
-
-
PF10
-
-
-
-
PG6
-
-
-
-
PG7
-
-
INT
-
PE0
NBL0
NBL0
-
NBL0
PE1
NBL1
NBL1
-
NBL1
PI4
NBL2
-
-
NBL2
PI5
NBL3
-
-
NBL3
PG8
-
-
-
SDCLK
PC0
-
-
-
SDNWE
PF11
-
-
-
SDNRAS
PG15
-
-
-
SDNCAS
PH2
-
-
-
SDCKE0
PH3
-
-
-
SDNE0
PH6
-
-
-
SDNE1
PH7
-
-
-
SDCKE1
PH5
-
-
-
SDNWE
PC2
-
-
-
SDNE0
PC3
-
-
-
SDCKE0
PC6
NWAIT
NWAIT
NWAIT
-
PB5
-
-
-
SDCKE1
PB6
-
-
-
SDNE1
DocID027972 Rev 5
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94
AF0
AF1
AF2
AF3
AF4
I2C4/UA
RT5/TIM
1/2
-
TIM2_C
H1/TIM2
_ETR
TIM5_C
H1
PA1
-
TIM2_C
H2
TIM5_C
H2
-
-
PA2
-
TIM2_C
H3
TIM5_C
H3
TIM9_CH
1
PA3
-
TIM2_C
H4
TIM5_C
H4
PA4
-
-
PA5
-
PA6
AF7
AF8
AF9
AF10
USART2
_CTS
UART4_
TX
-
-
-
USART2
_RTS
UART4_
RX
QUADSP
I_BK1_IO
3
-
-
-
USART2
_TX
SAI2_SC
K_B
-
TIM9_CH
2
-
-
-
USART2
_RX
-
LCD_B2
-
-
-
SPI1_NS SPI3_NS
S/I2S1_ S/I2S3_
WS
WS
USART2
_CK
SPI6_NS
S
-
-
TIM2_C
H1/TIM2
_ETR
-
TIM8_CH
1N
-
SPI1_SC
K/I2S1_
CK
-
-
SPI6_SC
K
-
-
TIM1_B
KIN
TIM3_C
H1
TIM8_BKI
N
-
SPI1_MI
SO
-
-
SPI6_MI
SO
PA7
-
TIM1_C
H1N
TIM3_C
H2
TIM8_CH
1N
-
SPI1_M
OSI/I2S1
_SD
-
-
PA8
MCO1
TIM1_C
H1
-
TIM8_BKI
N2
I2C3_SC
L
-
-
PA9
-
TIM1_C
H2
-
-
I2C3_SM
BA
SPI2_SC
K/I2S2_
CK
PA10
-
TIM1_C
H3
-
-
-
-
DocID027972 Rev 5
Port A
-
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
-
PA0
TIM8_ET
R
I2C1/2/3/
4/USART
1/CEC
AF6
-
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
SAI2_SD_ ETH_MII_
B
CRS
-
-
-
EVEN
TOUT
SAI2_MC
K_B
ETH_MII_
RX_CLK/
ETH_RMI
I_REF_C
LK
-
-
LCD_R2
EVEN
TOUT
-
ETH_MDI
O
MDIOS_
MDIO
-
LCD_R1
EVEN
TOUT
-
-
LCD_B5
EVEN
TOUT
-
OTG_HS
_SOF
DCMI_H
SYNC
LCD_VS
YNC
EVEN
TOUT
OTG_HS_
ULPI_CK
-
-
-
LCD_R4
EVEN
TOUT
TIM13_C
H1
-
-
MDIOS_
MDC
DCMI_PI
XCLK
LCD_G2
EVEN
TOUT
SPI6_MO
SI
TIM14_C
H1
-
-
-
EVEN
TOUT
USART1
_CK
-
-
OTG_FS_
SOF
-
UART7_
RX
LCD_B3
LCD_R6
EVEN
TOUT
-
USART1
_TX
-
-
-
-
-
DCMI_D
0
LCD_R5
EVEN
TOUT
-
USART1
_RX
-
LCD_B4
OTG_FS_
ID
-
MDIOS_
MDIO
DCMI_D
1
LCD_B1
EVEN
TOUT
OTG_HS_ ETH_MII_
ULPI_D0
COL
ETH_MII_
RX_DV/E FMC_SD
TH_RMII_
NWE
CRS_DV
STM32F767xx STM32F768Ax STM32F769xx
SYS
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
Port
AF5
Pinouts and pin description
82/129
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping
AF0
Port
Port A
AF1
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
DocID027972 Rev 5
I2C4/UA
RT5/TIM
1/2
PA11
-
TIM1_C
H4
-
-
-
SPI2_NS
S/I2S2_
WS
UART4_
RX
USART1
_CTS
-
CAN1_R
X
OTG_FS_
DM
-
-
-
LCD_R4
EVEN
TOUT
PA12
-
TIM1_ET
R
-
-
-
SPI2_SC
K/I2S2_
CK
UART4_
TX
USART1
_RTS
SAI2_FS
_B
CAN1_T
X
OTG_FS_
DP
-
-
-
LCD_R5
EVEN
TOUT
PA13
JTMSSWDIO
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PA14
JTCKSWCLK
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PA15
JTDI
TIM2_C
H1/TIM2
_ETR
-
-
HDMICEC
SPI6_NS
S
UART4_
RTS
-
-
CAN3_TX
UART7_
TX
-
-
EVEN
TOUT
PB0
-
TIM1_C
H2N
TIM3_C
H3
TIM8_CH
2N
-
-
DFSDM_
CKOUT
-
UART4_
CTS
LCD_R3
OTG_HS_ ETH_MII_
ULPI_D1
RXD2
-
-
LCD_G1
EVEN
TOUT
PB1
-
TIM1_C
H3N
TIM3_C
H4
TIM8_CH
3N
-
-
DFSDM_
DATIN1
-
-
LCD_R6
OTG_HS_ ETH_MII_
ULPI_D2
RXD3
-
-
LCD_G0
EVEN
TOUT
PB2
-
-
-
-
-
-
SAI1_SD
_A
SPI3_MO
SI/I2S3_
SD
QUADSP
I_CLK
DFSDM_
CKIN1
-
-
-
-
EVEN
TOUT
PB3
JTDO/T
RACES
WO
TIM2_C
H2
-
-
-
SPI1_SC SPI3_SC
K/I2S1_ K/I2S3_
CK
CK
PB4
NJTRST
-
TIM3_C
H1
-
-
SPI1_MI
SO
PB5
-
UART5_
RX
TIM3_C
H2
-
I2C1_SM
BA
PB6
-
UART5_
TX
TIM4_C
H1
HDMICEC
I2C1_SC
L
Port B
I2C1/2/3/
4/USART
1/CEC
SPI1_NS SPI3_NS
S/I2S1_ S/I2S3_
WS
WS
SPI3_MI
SO
SPI1_M SPI3_M
OSI/I2S1 OSI/I2S3
_SD
_SD
-
DFSDM_
DATIN5
83/129
-
SPI6_SC
K
-
SDMMC2
_D2
CAN3_R
X
UART7_
RX
-
-
EVEN
TOUT
SPI2_NS
S/I2S2_
WS
SPI6_MI
SO
-
SDMMC2
_D3
CAN3_TX
UART7_
TX
-
-
EVEN
TOUT
-
SPI6_MO
SI
CAN2_R
X
OTG_HS_ ETH_PPS FMC_SD
ULPI_D7
_OUT
CKE1
DCMI_D
10
LCD_G7
EVEN
TOUT
USART1
_TX
-
CAN2_T
X
QUADSPI
_BK1_NC
S
DCMI_D
5
-
EVEN
TOUT
I2C4_SC
L
FMC_SD
NE1
Pinouts and pin description
SYS
STM32F767xx STM32F768Ax STM32F769xx
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
AF1
AF2
AF3
AF4
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
I2C1/2/3/
4/USART
1/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
I2C4/UA
RT5/TIM
1/2
PB7
-
-
TIM4_C
H2
-
I2C1_SD
A
-
DFSDM_
CKIN5
USART1
_RX
-
-
-
I2S4_SD
A
FMC_NL
DCMI_V
SYNC
-
EVEN
TOUT
PB8
-
I2C4_SC
L
TIM4_C
H3
TIM10_C
H1
I2C1_SC
L
-
DFSDM_
CKIN7
UART5_
RX
-
CAN1_R
X
SDMMC2
_D4
ETH_MII_
TXD3
SDMMC
_D4
DCMI_D
6
LCD_B6
EVEN
TOUT
PB9
-
I2S4_SD
A
TIM4_C
H4
TIM11_CH
1
I2C1_SD
A
SPI2_NS
DFSDM_ UART5_T
S/I2S2_
DATIN7
X
WS
-
CAN1_T
X
SDMMC2
_D5
I2C4_SM
BA
SDMMC
_D5
DCMI_D
7
LCD_B7
EVEN
TOUT
PB10
-
TIM2_C
H3
-
-
I2C2_SC
L
SPI2_SC
DFSDM_
K/I2S2_
DATIN7
CK
USART3
_TX
-
QUADSP
I_BK1_N
CS
OTG_HS_ ETH_MII_
ULPI_D3
RX_ER
-
-
LCD_G4
EVEN
TOUT
PB11
-
TIM2_C
H4
-
-
I2C2_SD
A
DFSDM_
CKIN7
USART3
_RX
-
-
ETH_MII_
OTG_HS_ TX_EN/E
ULPI_D4 TH_RMII_
TX_EN
-
DSI_TE
LCD_G5
EVEN
TOUT
PB12
-
TIM1_B
KIN
-
-
I2C2_SM
BA
SPI2_NS
DFSDM_
S/I2S2_
DATIN1
WS
USART3
_CK
UART5_
RX
CAN2_R
X
ETH_MII_
OTG_HS_ TXD0/ET OTG_HS
ULPI_D5 H_RMII_T
_ID
XD0
-
-
EVEN
TOUT
PB13
-
TIM1_C
H1N
-
-
-
SPI2_SC
DFSDM_
K/I2S2_
CKIN1
CK
USART3
_CTS
UART5_T
X
CAN2_T
X
ETH_MII_
OTG_HS_ TXD1/ET
ULPI_D6 H_RMII_T
XD1
-
-
-
EVEN
TOUT
PB14
-
TIM1_C
H2N
-
TIM8_CH
2N
USART1_
TX
SPI2_MI
SO
USART3
_RTS
UART4_
RTS
TIM12_C
H1
SDMMC2
_D0
-
OTG_HS
_DM
-
-
EVEN
TOUT
PB15
RTC_RE
FIN
TIM1_C
H3N
-
TIM8_CH
3N
SPI2_M
USART1_
DFSDM_
OSI/I2S2
RX
CKIN2
_SD
-
UART4_
CTS
TIM12_C
H2
SDMMC2
_D1
-
OTG_HS
_DP
-
-
EVEN
TOUT
Port B
-
DFSDM_
DATIN2
STM32F767xx STM32F768Ax STM32F769xx
DocID027972 Rev 5
SYS
Pinouts and pin description
84/129
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
AF1
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
DocID027972 Rev 5
SYS
I2C4/UA
RT5/TIM
1/2
PC0
-
-
-
DFSDM_
CKIN0
-
PC1
TRACED
0
-
-
DFSDM_
DATAIN0
PC2
-
-
-
PC3
-
-
PC4
-
PC5
I2C1/2/3/
4/USART
1/CEC
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
-
SAI2_FS
_B
-
OTG_HS_
ULPI_ST
P
-
FMC_SD
NWE
-
LCD_R5
EVEN
TOUT
-
SPI2_M
SAI1_SD
OSI/I2S2
_A
_SD
-
-
-
DFSDM_
CKIN4
ETH_MD
C
MDIOS_
MDC
-
-
EVEN
TOUT
DFSDM_
CKIN1
-
SPI2_MI
SO
DFSDM_
CKOUT
-
-
-
OTG_HS_ ETH_MII_ FMC_SD
ULPI_DIR
TXD2
NE0
-
-
EVEN
TOUT
-
DFSDM_
DATAIN1
-
SPI2_M
OSI/I2S2
_SD
-
-
-
-
OTG_HS_
ETH_MII_ FMC_SD
ULPI_NX
TX_CLK
CKE0
T
-
-
EVEN
TOUT
-
-
DFSDM_
CKIN2
-
I2S1_M
CK
-
-
SPDIF_R
X2
-
-
ETH_MII_
RXD0/ET FMC_SD
H_RMII_
NE0
RXD0
-
-
EVEN
TOUT
-
-
-
DFSDM_
DATAIN2
-
-
-
-
SPDIF_R
X3
-
-
ETH_MII_
RXD1/ET FMC_SD
H_RMII_
CKE0
RXD1
-
-
EVEN
TOUT
PC6
-
-
TIM3_C
H1
TIM8_CH
1
-
I2S2_M
CK
-
DFSDM_
CKIN3
USART6
_TX
FMC_NW
AIT
SDMMC2
_D6
-
SDMMC
_D6
DCMI_D
0
LCD_HS
YNC
EVEN
TOUT
PC7
-
-
TIM3_C
H2
TIM8_
CH2
-
-
I2S3_M
CK
DFSDM_
DATAIN3
USART6
_RX
FMC_NE
1
SDMMC2
_D7
-
SDMMC
_D7
DCMI_D
1
LCD_G6
EVEN
TOUT
PC8
TRACED
1
-
TIM3_C
H3
TIM8_
CH3
-
-
-
UART5_
RTS
USART6
_CK
FMC_NE
2/FMC_N
CE
-
-
SDMMC
_D0
DCMI_D
2
-
EVEN
TOUT
PC9
MCO2
-
TIM3_C
H4
TIM8_
CH4
I2C3_SD
A
I2S_CKI
N
-
UART5_
CTS
-
QUADSP
I_BK1_IO
0
LCD_G3
-
SDMMC
_D1
DCMI_D
3
LCD_B2
EVEN
TOUT
PC10
-
-
-
DFSDM_
CKIN5
-
-
SPI3_SC
K/I2S3_
CK
USART3
_TX
-
-
SDMMC
_D2
DCMI_D
8
LCD_R2
EVEN
TOUT
Port C
QUADSP
UART4_T
I_BK1_IO
X
1
85/129
Pinouts and pin description
DFSDM_
DATIN4
-
STM32F767xx STM32F768Ax STM32F769xx
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
AF1
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
I2C4/UA
RT5/TIM
1/2
PC11
-
-
-
DFSDM_
DATAIN5
-
-
SPI3_MI
SO
USART3
_RX
UART4_
RX
QUADSP
I_BK2_N
CS
-
-
SDMMC
_D3
DCMI_D
4
-
EVEN
TOUT
PC12
TRACED
3
-
-
-
-
-
SPI3_M
OSI/I2S3
_SD
USART3
_CK
UART5_T
X
-
-
-
SDMMC
_CK
DCMI_D
9
-
EVEN
TOUT
PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PC14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PC15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PD0
-
-
-
DFSDM_
CKIN6
-
-
DFSDM_
DATAIN7
-
UART4_
RX
CAN1_R
X
-
-
FMC_D2
-
-
EVEN
TOUT
PD1
-
-
-
DFSDM_
DATAIN6
-
-
DFSDM_
CKIN7
-
UART4_T
X
CAN1_T
X
-
-
FMC_D3
-
-
EVEN
TOUT
PD2
TRACED
2
-
TIM3_ET
R
-
-
-
-
-
UART5_
RX
-
-
-
SDMMC
_CMD
DCMI_D
11
-
EVEN
TOUT
PD3
-
-
-
DFSDM_
CKOUT
-
SPI2_SC
DFSDM_
K/I2S2_
DATAIN0
CK
USART2
_CTS
-
-
-
-
FMC_CL
K
DCMI_D
5
LCD_G7
EVEN
TOUT
PD4
-
-
-
-
-
-
DFSDM_
CKIN0
USART2
_RTS
-
-
-
-
FMC_N
OE
-
-
EVEN
TOUT
PD5
-
-
-
-
-
-
-
USART2
_TX
-
-
-
-
FMC_N
WE
-
-
EVEN
TOUT
PD6
-
-
-
DFSDM_
CKIN4
-
SPI3_M
SAI1_SD
OSI/I2S3
_A
_SD
USART2
_RX
-
-
DFSDM_
DATAIN1
SDMMC2
_CK
FMC_N
WAIT
DCMI_D
10
LCD_B2
EVEN
TOUT
PD7
-
-
-
DFSDM_
DATAIN4
-
SPI1_M
DFSDM_
OSI/I2S1
CKIN1
_SD
USART2
_CK
SPDIF_R
X0
-
-
SDMMC2
_CMD
FMC_NE
1
-
-
EVEN
TOUT
PD8
-
-
-
DFSDM_
CKIN3
-
USART3
_TX
SPDIF_R
X1
-
-
-
FMC_D1
3
-
-
EVEN
TOUT
I2C1/2/3/
4/USART
1/CEC
Port C
DocID027972 Rev 5
Port D
-
-
STM32F767xx STM32F768Ax STM32F769xx
SYS
Pinouts and pin description
86/129
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
DocID027972 Rev 5
Port D
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
87/129
SYS
I2C4/UA
RT5/TIM
1/2
PD9
-
-
-
DFSDM_
DATAIN3
-
-
-
USART3
_RX
-
-
-
-
FMC_D1
4
-
-
EVEN
TOUT
PD10
-
-
-
DFSDM_
CKOUT
-
-
-
USART3
_CK
-
-
-
-
FMC_D1
5
-
LCD_B3
EVEN
TOUT
PD11
-
-
-
-
I2C4_SM
BA
-
-
USART3
_CTS
-
QUADSP
SAI2_SD_
I_BK1_IO
A
0
-
FMC_A1
6/FMC_
CLE
-
-
EVEN
TOUT
PD12
-
-
TIM4_C
H1
LPTIM1_I
N1
I2C4_SC
L
-
-
USART3
_RTS
-
QUADSP
SAI2_FS_
I_BK1_IO
A
1
-
FMC_A1
7/FMC_
ALE
-
-
EVEN
TOUT
PD13
-
-
TIM4_C
H2
LPTIM1_
OUT
I2C4_SD
A
-
-
-
-
QUADSP
I_BK1_IO
3
SAI2_SC
K_A
-
FMC_A1
8
-
-
EVEN
TOUT
PD14
-
-
TIM4_C
H3
-
-
-
-
-
UART8_
CTS
-
-
-
FMC_D0
-
-
EVEN
TOUT
PD15
-
-
TIM4_C
H4
-
-
-
-
-
UART8_
RTS
-
-
-
FMC_D1
-
-
EVEN
TOUT
PE0
-
-
TIM4_ET LPTIM1_E
R
TR
-
-
-
-
UART8_
Rx
-
SAI2_MC
K_A
-
FMC_NB
L0
DCMI_D
2
-
EVEN
TOUT
PE1
-
-
-
LPTIM1_I
N2
-
-
-
-
UART8_T
x
-
-
-
FMC_NB
L1
DCMI_D
3
-
EVEN
TOUT
PE2
TRACEC
LK
-
-
-
-
SPI4_SC
K
SAI1_M
CLK_A
-
-
QUADSP
I_BK1_IO
2
-
ETH_MII_
TXD3
FMC_A2
3
-
-
EVEN
TOUT
PE3
TRACED
0
-
-
-
-
-
SAI1_SD
_B
-
-
-
-
-
FMC_A1
9
-
-
EVEN
TOUT
PE4
TRACED
1
-
-
-
-
SPI4_NS SAI1_FS
S
_A
-
-
-
DFSDM_
DATAIN3
-
FMC_A2
0
DCMI_D
4
LCD_B0
EVEN
TOUT
PE5
TRACED
2
-
-
TIM9_CH
1
-
SPI4_MI
SO
SAI1_SC
K_A
-
-
-
DFSDM_
CKIN3
-
FMC_A2
1
DCMI_D
6
LCD_G0
EVEN
TOUT
PE6
TRACED
3
TIM1_B
KIN2
-
TIM9_CH
2
-
SPI4_M
OSI
SAI1_SD
_A
-
-
-
SAI2_MC
K_B
-
FMC_A2
2
DCMI_D
7
LCD_G1
EVEN
TOUT
I2C1/2/3/
4/USART
1/CEC
Pinouts and pin description
Port E
AF1
STM32F767xx STM32F768Ax STM32F769xx
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
SYS
I2C4/UA
RT5/TIM
1/2
PE7
-
TIM1_ET
R
-
-
-
-
DFSDM_
DATAIN2
-
UART7_
Rx
-
QUADSPI
_BK2_IO0
-
FMC_D4
-
-
EVEN
TOUT
PE8
-
TIM1_C
H1N
-
-
-
-
DFSDM_
CKIN2
-
UART7_T
x
-
QUADSPI
_BK2_IO1
-
FMC_D5
-
-
EVEN
TOUT
PE9
-
TIM1_C
H1
-
-
-
-
DFSDM_
CKOUT
-
UART7_
RTS
-
QUADSPI
_BK2_IO2
-
FMC_D6
-
-
EVEN
TOUT
PE10
-
TIM1_C
H2N
-
-
-
-
DFSDM_
DATAIN4
-
UART7_
CTS
-
QUADSPI
_BK2_IO3
-
FMC_D7
-
-
EVEN
TOUT
PE11
-
TIM1_C
H2
-
-
-
SPI4_NS DFSDM_
S
CKIN4
-
-
-
SAI2_SD_
B
-
FMC_D8
-
LCD_G3
EVEN
TOUT
PE12
-
TIM1_C
H3N
-
-
-
SPI4_SC DFSDM_
K
DATAIN5
-
-
-
SAI2_SC
K_B
-
FMC_D9
-
LCD_B4
EVEN
TOUT
PE13
-
TIM1_C
H3
-
-
-
SPI4_MI
SO
DFSDM_
CKIN5
-
-
-
SAI2_FS_
B
-
FMC_D1
0
-
LCD_DE
EVEN
TOUT
PE14
-
TIM1_C
H4
-
-
-
SPI4_M
OSI
-
-
-
-
SAI2_MC
K_B
-
FMC_D1
1
-
LCD_CL
K
EVEN
TOUT
PE15
-
TIM1_B
KIN
-
-
-
-
-
-
-
-
-
-
FMC_D1
2
-
LCD_R7
EVEN
TOUT
PF0
-
-
-
-
I2C2_SD
A
-
-
-
-
-
-
-
FMC_A0
-
-
EVEN
TOUT
PF1
-
-
-
-
I2C2_SC
L
-
-
-
-
-
-
-
FMC_A1
-
-
EVEN
TOUT
PF2
-
-
-
-
I2C2_SM
BA
-
-
-
-
-
-
-
FMC_A2
-
-
EVEN
TOUT
PF3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A3
-
-
EVEN
TOUT
PF4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A4
-
-
EVEN
TOUT
PF5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A5
-
-
EVEN
TOUT
Port F
I2C1/2/3/
4/USART
1/CEC
STM32F767xx STM32F768Ax STM32F769xx
DocID027972 Rev 5
Port E
AF1
Pinouts and pin description
88/129
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
DocID027972 Rev 5
Port F
AF1
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
I2C4/UA
RT5/TIM
1/2
PF6
-
-
-
TIM10_C
H1
-
SPI5_NS SAI1_SD
S
_B
-
PF7
-
-
-
TIM11_CH
1
-
SPI5_SC
K
SAI1_M
CLK_B
-
PF8
-
-
-
-
-
SPI5_MI
SO
SAI1_SC
K_B
-
UART7_
RTS
PF9
-
-
-
-
-
SPI5_M
OSI
SAI1_FS
_B
-
PF10
-
-
-
-
-
-
-
PF11
-
-
-
-
-
SPI5_M
OSI
PF12
-
-
-
-
-
PF13
-
-
-
-
PF14
-
-
-
PF15
-
-
PG0
-
PG1
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
QUADSP
I_BK1_IO
3
-
-
-
-
-
EVEN
TOUT
QUADSP
UART7_T
I_BK1_IO
x
2
-
-
-
-
-
EVEN
TOUT
TIM13_C
H1
QUADSPI
_BK1_IO0
-
-
-
-
EVEN
TOUT
UART7_
CTS
TIM14_C
H1
QUADSPI
_BK1_IO1
-
-
-
-
EVEN
TOUT
-
-
QUADSP
I_CLK
-
-
-
DCMI_D
11
LCD_DE
EVEN
TOUT
-
-
-
-
SAI2_SD_
B
-
FMC_SD
NRAS
DCMI_D
12
-
EVEN
TOUT
-
-
-
-
-
-
-
FMC_A6
-
-
EVEN
TOUT
I2C4_SM
BA
-
DFSDM_
DATAIN6
-
-
-
-
-
FMC_A7
-
-
EVEN
TOUT
-
I2C4_SC
L
-
DFSDM_
CKIN6
-
-
-
-
-
FMC_A8
-
-
EVEN
TOUT
-
-
I2C4_SD
A
-
-
-
-
-
-
-
FMC_A9
-
-
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
FMC_A1
0
-
-
EVEN
TOUT
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A1
1
-
-
EVEN
TOUT
PG2
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A1
2
-
-
EVEN
TOUT
PG3
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A1
3
-
-
EVEN
TOUT
UART7_
Rx
Port G
89/129
Pinouts and pin description
SYS
I2C1/2/3/
4/USART
1/CEC
AF9
STM32F767xx STM32F768Ax STM32F769xx
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
SYS
I2C4/UA
RT5/TIM
1/2
PG4
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A1
4/FMC_
BA0
-
-
EVEN
TOUT
PG5
-
-
-
-
-
-
-
-
-
-
-
-
FMC_A1
5/FMC_
BA1
-
-
EVEN
TOUT
PG6
-
-
-
-
-
-
-
-
-
-
-
-
FMC_NE
3
DCMI_D
12
LCD_R7
EVEN
TOUT
PG7
-
-
-
-
-
-
SAI1_M
CLK_A
-
USART6
_CK
-
-
-
FMC_IN
T
DCMI_D
13
LCD_CL
K
EVEN
TOUT
PG8
-
-
-
-
-
SPI6_NS
S
-
SPDIF_R
X2
USART6
_RTS
-
-
-
LCD_G7
EVEN
TOUT
PG9
-
-
-
-
-
SPI1_MI
SO
-
SPDIF_R
X3
USART6
_RX
PG10
-
-
-
-
-
SPI1_NS
S/I2S1_
WS
-
-
-
PG11
-
-
-
-
-
SPI1_SC
K/I2S1_
CK
-
SPDIF_R
X0
PG12
-
-
-
LPTIM1_I
N1
-
SPI6_MI
SO
-
PG13
TRACED
0
-
-
LPTIM1_
OUT
-
SPI6_SC
K
PG14
TRACED
1
-
-
LPTIM1_E
TR
-
PG15
-
-
-
-
-
I2C1/2/3/
4/USART
1/CEC
ETH_PPS FMC_SD
_OUT
CLK
QUADSP
SAI2_FS_
I_BK2_IO
B
2
SDMMC2
_D0
FMC_NE
2/FMC_
NCE
DCMI_V
SYNC
-
EVEN
TOUT
LCD_G3
SAI2_SD_
B
SDMMC2
_D1
FMC_NE
3
DCMI_D
2
LCD_B2
EVEN
TOUT
-
-
SDMMC2
_D2
ETH_MII_
TX_EN/E
TH_RMII_
TX_EN
-
DCMI_D
3
LCD_B3
EVEN
TOUT
SPDIF_R
X1
USART6
_RTS
LCD_B4
-
SDMMC2
_D3
FMC_NE
4
-
LCD_B1
EVEN
TOUT
-
-
USART6
_CTS
-
-
ETH_MII_
TXD0/ET FMC_A2
H_RMII_T
4
XD0
-
LCD_R0
EVEN
TOUT
SPI6_M
OSI
-
-
USART6
_TX
QUADSP
I_BK2_IO
3
-
ETH_MII_
TXD1/ET FMC_A2
5
H_RMII_T
XD1
-
LCD_B0
EVEN
TOUT
-
-
-
USART6
_CTS
-
-
DCMI_D
13
-
EVEN
TOUT
-
FMC_SD
NCAS
STM32F767xx STM32F768Ax STM32F769xx
DocID027972 Rev 5
Port G
AF1
Pinouts and pin description
90/129
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
DocID027972 Rev 5
Port H
AF1
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
I2C4/UA
RT5/TIM
1/2
PH0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PH1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PH2
-
-
-
LPTIM1_I
N2
-
-
-
-
-
QUADSP
I_BK2_IO
0
SAI2_SC
K_B
ETH_MII_ FMC_SD
CRS
CKE0
-
LCD_R0
EVEN
TOUT
PH3
-
-
-
-
-
-
-
-
-
QUADSP
I_BK2_IO
1
SAI2_MC
K_B
ETH_MII_ FMC_SD
COL
NE0
-
LCD_R1
EVEN
TOUT
PH4
-
-
-
-
I2C2_SC
L
-
-
-
-
LCD_G5
OTG_HS_
ULPI_NX
T
-
-
-
LCD_G4
EVEN
TOUT
PH5
-
-
-
-
I2C2_SD
A
SPI5_NS
S
-
-
-
-
-
-
FMC_SD
NWE
-
-
EVEN
TOUT
PH6
-
-
-
-
I2C2_SM
BA
SPI5_SC
K
-
-
-
TIM12_C
H1
-
ETH_MII_ FMC_SD
RXD2
NE1
DCMI_D
8
-
EVEN
TOUT
PH7
-
-
-
-
I2C3_SC
L
SPI5_MI
SO
-
-
-
-
-
ETH_MII_ FMC_SD
RXD3
CKE1
DCMI_D
9
-
EVEN
TOUT
PH8
-
-
-
-
I2C3_SD
A
-
-
-
-
-
-
-
FMC_D1
6
DCMI_H
SYNC
LCD_R2
EVEN
TOUT
PH9
-
-
-
-
I2C3_SM
BA
-
-
-
-
TIM12_C
H2
-
-
FMC_D1
7
DCMI_D
0
LCD_R3
EVEN
TOUT
PH10
-
-
TIM5_C
H1
-
I2C4_SM
BA
-
-
-
-
-
-
-
FMC_D1
8
DCMI_D
1
LCD_R4
EVEN
TOUT
PH11
-
-
TIM5_C
H2
-
I2C4_SC
L
-
-
-
-
-
-
-
FMC_D1
9
DCMI_D
2
LCD_R5
EVEN
TOUT
PH12
-
-
TIM5_C
H3
-
I2C4_SD
A
-
-
-
-
-
-
-
FMC_D2
0
DCMI_D
3
LCD_R6
EVEN
TOUT
PH13
-
-
-
TIM8_CH
1N
-
-
-
-
UART4_T
X
CAN1_T
X
-
-
FMC_D2
1
-
LCD_G2
EVEN
TOUT
I2C1/2/3/
4/USART
1/CEC
Pinouts and pin description
91/129
SYS
STM32F767xx STM32F768Ax STM32F769xx
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
AF1
AF2
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
I2C4/UA
RT5/TIM
1/2
PH14
-
-
-
TIM8_CH
2N
-
-
-
-
UART4_
RX
CAN1_R
X
-
-
FMC_D2
2
DCMI_D
4
LCD_G3
EVEN
TOUT
PH15
-
-
-
TIM8_CH
3N
-
-
-
-
-
-
-
-
FMC_D2
3
DCMI_D
11
LCD_G4
EVEN
TOUT
PI0
-
-
TIM5_C
H4
-
-
SPI2_NS
S/I2S2_
WS
-
-
-
-
-
-
FMC_D2
4
DCMI_D
13
LCD_G5
EVEN
TOUT
PI1
-
-
-
TIM8_BKI
N2
-
SPI2_SC
K/I2S2_
CK
-
-
-
-
-
-
FMC_D2
5
DCMI_D
8
LCD_G6
EVEN
TOUT
PI2
-
-
-
TIM8_CH
4
-
SPI2_MI
SO
-
-
-
-
-
-
FMC_D2
6
DCMI_D
9
LCD_G7
EVEN
TOUT
PI3
-
-
-
TIM8_ET
R
-
SPI2_M
OSI/I2S2
_SD
-
-
-
-
-
-
FMC_D2
7
DCMI_D
10
-
EVEN
TOUT
PI4
-
-
-
TIM8_BKI
N
-
-
-
-
-
-
SAI2_MC
K_A
-
FMC_NB
L2
DCMI_D
5
LCD_B4
EVEN
TOUT
PI5
-
-
-
TIM8_CH
1
-
-
-
-
-
-
SAI2_SC
K_A
-
FMC_NB
L3
DCMI_V
SYNC
LCD_B5
EVEN
TOUT
PI6
-
-
-
TIM8_CH
2
-
-
-
-
-
-
SAI2_SD_
A
-
FMC_D2
8
DCMI_D
6
LCD_B6
EVEN
TOUT
PI7
-
-
-
TIM8_CH
3
-
-
-
-
-
-
SAI2_FS_
A
-
FMC_D2
9
DCMI_D
7
LCD_B7
EVEN
TOUT
PI8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
EVEN
TOUT
PI9
-
-
-
-
-
-
-
-
UART4_
RX
CAN1_R
X
-
-
FMC_D3
0
-
LCD_VS
YNC
EVEN
TOUT
PI10
-
-
-
-
-
-
-
-
-
-
-
ETH_MII_
RX_ER
FMC_D3
1
-
LCD_HS
YNC
EVEN
TOUT
PI11
-
-
-
-
-
-
-
-
-
LCD_G6
OTG_HS_
ULPI_DIR
-
-
-
-
EVEN
TOUT
I2C1/2/3/
4/USART
1/CEC
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
SYS
Port H
Port I
AF3
Pinouts and pin description
92/129
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
AF1
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
I2C4/UA
RT5/TIM
1/2
PI12
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_HS
YNC
EVEN
TOUT
PI13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_VS
YNC
EVEN
TOUT
PI14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_CL
K
EVEN
TOUT
PI15
-
-
-
-
-
-
-
-
-
LCD_G2
-
-
-
-
LCD_R0
EVEN
TOUT
PJ0
-
-
-
-
-
-
-
-
-
LCD_R7
-
-
-
-
LCD_R1
EVEN
TOUT
PJ1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R2
EVEN
TOUT
PJ2
-
-
-
-
-
-
-
-
-
-
-
-
-
DSI_TE
LCD_R3
EVEN
TOUT
PJ3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R4
EVEN
TOUT
PJ4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R5
EVEN
TOUT
PJ5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R6
EVEN
TOUT
PJ6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_R7
EVEN
TOUT
PJ7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G0
EVEN
TOUT
PJ8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G1
EVEN
TOUT
PJ9
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G2
EVEN
TOUT
PJ10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G3
EVEN
TOUT
I2C1/2/3/
4/USART
1/CEC
Port I
DocID027972 Rev 5
Port J
93/129
Pinouts and pin description
SYS
STM32F767xx STM32F768Ax STM32F769xx
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
AF0
Port
Port J
AF1
AF2
AF3
TIM8/9/10/
11/LPTIM
TIM3/4/5
1/DFSDM/
CEC
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
SPI2/I2S
SAI2/QU
SPI2/I2S
SPI6/SAI
SPI1/I2S
2/SPI3/I2
CAN1/2/T ADSPI/S
UART7/
2/SPI3/I2
2/USART
1/SPI2/I2
S3/SPI6/
IM12/13/ DMMC2/D I2C4/CAN FMC/SD
S3/SAI1/
6/UART4/
S2/SPI3/
USART1/
14/QUAD FSDM/OT 3/SDMM MMC1/M
I2C4/UA
5/7/8/OT
I2S3/SPI
2/3/UART
SPI/FMC/ G2_HS/O
C2/ETH DIOS/OT
RT4/DF
G_FS/SP
4/5/6
5/DFSDM
LCD
TG1_FS/L
G2_FS
SDM
DIF
/SPDIF
CD
AF13
AF14
AF15
DCMI/L
CD/DSI
LCD
SYS
I2C4/UA
RT5/TIM
1/2
PJ11
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G4
EVEN
TOUT
PJ12
-
-
-
-
-
-
-
-
-
LCD_G3
-
-
-
-
LCD_B0
EVEN
TOUT
PJ13
-
-
-
-
-
-
-
-
-
LCD_G4
-
-
-
-
LCD_B1
EVEN
TOUT
PJ14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B2
EVEN
TOUT
PJ15
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B3
EVEN
TOUT
PK0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G5
EVEN
TOUT
PK1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G6
EVEN
TOUT
PK2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_G7
EVEN
TOUT
PK3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B4
EVEN
TOUT
PK4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B5
EVEN
TOUT
PK5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B6
EVEN
TOUT
PK6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_B7
EVEN
TOUT
PK7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LCD_DE
EVEN
TOUT
I2C1/2/3/
4/USART
1/CEC
Port K
STM32F767xx STM32F768Ax STM32F769xx
DocID027972 Rev 5
SYS
Pinouts and pin description
94/129
Table 12. STM32F767xx, STM32F768Ax and STM32F769xx alternate function mapping (continued)
STM32F767xx STM32F768Ax STM32F769xx
4
Memory mapping
Memory mapping
The memory map is shown in Figure 19.
Figure 19. Memory map
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[([()))))
$+%
[[')))))))
5HVHUYHG
[&[)))))))
[%))
$+%
0E\WH
%ORFN
&RUWH[0
,QWHUQDO
SHULSKHUDOV
5HVHUYHG
[
[[)))))))
[))))
[(
[')))))))
0E\WH
%ORFN
)0&
['
[&)))))))
$+%
0E\WH
%ORFN
)0&
[&
[)))))))
[
[)))))))
0E\WH
%ORFN
4XDG63,DQG
)0&EDQN
[
5HVHUYHG
[&[))))
[%))
0E\WH
%ORFN
)0&EDQNWR
EDQN
[
[)))))))
$3%
0E\WH
%ORFN
3HULSKHUDOV
[
[)))))))
0E\WH
%ORFN
65$0
[
[)))))))
0E\WH
%ORFN
[
5HVHUYHG
[[)))))))
65$0.%
[&[))))
65$0.%
[[%)))
'7&0.%
[[))))
5HVHUYHG
[)))[)))))))
2SWLRQ%\WHV
[)))[))))
5HVHUYHG
[[))())))
5HVHUYHG
[
[[))))
[)))
$3%
)ODVKPHPRU\RQ$;,0LQWHUIDFH [[)))))
5HVHUYHG
[[))))))
)ODVKPHPRU\RQ,7&0LQWHUIDFH [[)))))
5HVHUYHG
[[)))))
6\VWHPPHPRU\
[[('%)
5HVHUYHG
[[)))))
,7&05$0
[[)))
DocID027972 Rev 5
[
06Y9
95/129
99
Memory mapping
STM32F767xx STM32F768Ax STM32F769xx
Table 13. STM32F767xx, STM32F768Ax and STM32F769xx register boundary
addresses
Bus
Cortex-M7
AHB3
AHB2
96/129
Boundary address
Peripheral
0xE00F FFFF - 0xFFFF FFFF
Reserved
0xE000 0000 - 0xE00F FFFF
Cortex-M7 internal peripherals
0xD000 0000 - 0xDFFF FFFF
FMC bank 6
0xC000 0000 - 0xCFFF FFFF
FMC bank 5
0xA000 2000 - 0xBFFF FFFF
Reserved
0xA000 1000 - 0xA000 1FFF
Quad-SPI control register
0xA000 0000- 0xA000 0FFF
FMC control register
0x9000 0000 - 0x9FFF FFFF
Quad-SPI
0x8000 0000 - 0x8FFF FFFF
FMC bank 3
0x7000 0000 - 0x7FFF FFFF
FMC bank 2
0x6000 0000 - 0x6FFF FFFF
FMC bank 1
0x5006 0C00- 0x5FFF FFFF
Reserved
0x5006 0800 - 0x5006 0BFF
RNG
0x5005 2000 - 0x5005 FFFF
Reserved
0x5005 1000 - 0x5005 1FFF
JPEG codec
0x5005 0000 - 0x5005 03FF
DCMI
0x5004 0000- 0x5004 FFFF
Reserved
0x5000 0000 - 0x5003 FFFF
USB OTG FS
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Memory mapping
Table 13. STM32F767xx, STM32F768Ax and STM32F769xx register boundary
addresses (continued)
Bus
Boundary address
Peripheral
0x4008 0000- 0x4FFF FFFF
Reserved
0x4004 0000 - 0x4007 FFFF
USB OTG HS
0x4002 BC00- 0x4003 FFFF
Reserved
0x4002 B000 - 0x4002 BBFF
Chrom-ART (DMA2D)
0x4002 9400 - 0x4002 AFFF
Reserved
0x4002 9000 - 0x4002 93FF
0x4002 8C00 - 0x4002 8FFF
0x4002 8800 - 0x4002 8BFF
ETHERNET MAC
0x4002 8400 - 0x4002 87FF
0x4002 8000 - 0x4002 83FF
AHB1
0x4002 6800 - 0x4002 7FFF
Reserved
0x4002 6400 - 0x4002 67FF
DMA2
0x4002 6000 - 0x4002 63FF
DMA1
0x4002 5000 - 0X4002 5FFF
Reserved
0x4002 4000 - 0x4002 4FFF
BKPSRAM
0x4002 3C00 - 0x4002 3FFF
Flash interface register
0x4002 3800 - 0x4002 3BFF
RCC
0X4002 3400 - 0X4002 37FF
Reserved
0x4002 3000 - 0x4002 33FF
CRC
0x4002 2C00 - 0x4002 2FFF
Reserved
0x4002 2800 - 0x4002 2BFF
GPIOK
0x4002 2400 - 0x4002 27FF
GPIOJ
0x4002 2000 - 0x4002 23FF
GPIOI
0x4002 1C00 - 0x4002 1FFF
GPIOH
0x4002 1800 - 0x4002 1BFF
GPIOG
0x4002 1400 - 0x4002 17FF
GPIOF
0x4002 1000 - 0x4002 13FF
GPIOE
0X4002 0C00 - 0x4002 0FFF
GPIOD
0x4002 0800 - 0x4002 0BFF
GPIOC
0x4002 0400 - 0x4002 07FF
GPIOB
0x4002 0000 - 0x4002 03FF
GPIOA
DocID027972 Rev 5
97/129
99
Memory mapping
STM32F767xx STM32F768Ax STM32F769xx
Table 13. STM32F767xx, STM32F768Ax and STM32F769xx register boundary
addresses (continued)
Bus
APB2
98/129
Boundary address
Peripheral
0x4001 7C00 - 0x4001 FFFF
Reserved
0x4001 7800 - 0x4001 7BFF
MDIOS
0x4001 7400 - 0x4001 77FF
DFSDM
0x4001 6C00 - 0x4001 73FF
DSI Host
0x4001 6800 - 0x4001 6BFF
LCD-TFT
0x4001 6000 - 0x4001 67FF
Reserved
0x4001 5C00 - 0x4001 5FFF
SAI2
0x4001 5800 - 0x4001 5BFF
SAI1
0x4001 5400 - 0x4001 57FF
SPI6
0x4001 5000 - 0x4001 53FF
SPI5
0x4001 4C00 - 0x4001 4FFF
Reserved
0x4001 4800 - 0x4001 4BFF
TIM11
0x4001 4400 - 0x4001 47FF
TIM10
0x4001 4000 - 0x4001 43FF
TIM9
0x4001 3C00 - 0x4001 3FFF
EXTI
0x4001 3800 - 0x4001 3BFF
SYSCFG
0x4001 3400 - 0x4001 37FF
SPI4
0x4001 3000 - 0x4001 33FF
SPI1/I2S1
0x4001 2C00 - 0x4001 2FFF
SDMMC1
0x4001 2400 - 0x4001 2BFF
Reserved
0x4001 2000 - 0x4001 23FF
ADC1 - ADC2 - ADC3
0x4001 1C00 - 0x4001 1FFF
SDMMC2
0x4001 1800 - 0x4001 1BFF
Reserved
0x4001 1400 - 0x4001 17FF
USART6
0x4001 1000 - 0x4001 13FF
USART1
0x4001 0800 - 0x4001 0FFF
Reserved
0x4001 0400 - 0x4001 07FF
TIM8
0x4001 0000 - 0x4001 03FF
TIM1
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Memory mapping
Table 13. STM32F767xx, STM32F768Ax and STM32F769xx register boundary
addresses (continued)
Bus
APB1
Boundary address
Peripheral
0x4000 8000- 0x4000 FFFF
Reserved
0x4000 7C00 - 0x4000 7FFF
UART8
0x4000 7800 - 0x4000 7BFF
UART7
0x4000 7400 - 0x4000 77FF
DAC
0x4000 7000 - 0x4000 73FF
PWR
0x4000 6C00 - 0x4000 6FFF
HDMI-CEC
0x4000 6800 - 0x4000 6BFF
CAN2
0x4000 6400 - 0x4000 67FF
CAN1
0x4000 6000 - 0x4000 63FF
I2C4
0x4000 5C00 - 0x4000 5FFF
I2C3
0x4000 5800 - 0x4000 5BFF
I2C2
0x4000 5400 - 0x4000 57FF
I2C1
0x4000 5000 - 0x4000 53FF
UART5
0x4000 4C00 - 0x4000 4FFF
UART4
0x4000 4800 - 0x4000 4BFF
USART3
0x4000 4400 - 0x4000 47FF
USART2
0x4000 4000 - 0x4000 43FF
SPDIFRX
0x4000 3C00 - 0x4000 3FFF
SPI3 / I2S3
0x4000 3800 - 0x4000 3BFF
SPI2 / I2S2
0x4000 3400 - 0x4000 37FF
CAN3
0x4000 3000 - 0x4000 33FF
IWDG
0x4000 2C00 - 0x4000 2FFF
WWDG
0x4000 2800 - 0x4000 2BFF
RTC & BKP Registers
0x4000 2400 - 0x4000 27FF
LPTIM1
0x4000 2000 - 0x4000 23FF
TIM14
0x4000 1C00 - 0x4000 1FFF
TIM13
0x4000 1800 - 0x4000 1BFF
TIM12
0x4000 1400 - 0x4000 17FF
TIM7
0x4000 1000 - 0x4000 13FF
TIM6
0x4000 0C00 - 0x4000 0FFF
TIM5
0x4000 0800 - 0x4000 0BFF
TIM4
0x4000 0400 - 0x4000 07FF
TIM3
0x4000 0000 - 0x4000 03FF
TIM2
DocID027972 Rev 5
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99
Package information
5
STM32F767xx STM32F768Ax STM32F769xx
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
5.1
LQFP100 14x 14 mm, low-profile quad flat package
information
Figure 20. LQFP100, 14 x 14 mm 100-pin low-profile quad flat package outline
MM
C
!
!
!
3%!4).'0,!.%
#
'!5'%0,!.%
$
,
$
!
+
CCC #
,
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0).
)$%.4)&)#!4)/.
E
1. Drawing is not to scale.
100/129
%
%
%
B
DocID027972 Rev 5
,?-%?6
STM32F767xx STM32F768Ax STM32F769xx
Package information
Table 14. LQPF100, 14 x 14 mm 100-pin low-profile quad flat package mechanical
data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.000
-
-
0.4724
-
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
E3
-
12.000
-
-
0.4724
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID027972 Rev 5
101/129
128
Package information
STM32F767xx STM32F768Ax STM32F769xx
Figure 21. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint
AIC
1. Dimensions are expressed in millimeters.
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 22. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
top view example
3URGXFWLGHQWLILFDWLRQ 45.'
7*5
5HYLVLRQFRGH
3
'DWHFRGH
: 88
3LQLGHQWLILHU
069
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
102/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
LQFP144 20 x 20 mm, low-profile quad flat package
information
Figure 23. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline
C
!
!
3%!4).'
0,!.%
#
!
MM
CCC #
!
'!5'%0,!.%
$
+
,
$
,
$
%
%
%
B
5.2
Package information
0).
)$%.4)&)#!4)/.
E
!?-%?6
1. Drawing is not to scale.
Table 15. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
21.800
22.000
22.200
0.8583
0.8661
0.874
DocID027972 Rev 5
103/129
128
Package information
STM32F767xx STM32F768Ax STM32F769xx
Table 15. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
D1
19.800
20.000
20.200
0.7795
0.7874
0.7953
D3
-
17.500
-
-
0.689
-
E
21.800
22.000
22.200
0.8583
0.8661
0.8740
E1
19.800
20.000
20.200
0.7795
0.7874
0.7953
E3
-
17.500
-
-
0.6890
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 24. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
recommended footprint
DLH
1. Dimensions are expressed in millimeters.
104/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 25. LQFP144, 20 x 20mm, 144-pin low-profile quad flat package
top view example
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
3
45.';*5
: 88
3LQ
LGHQWLILHU
'DWHFRGH
-36
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID027972 Rev 5
105/129
128
Package information
5.3
STM32F767xx STM32F768Ax STM32F769xx
LQFP176 24 x 24 mm, low-profile quad flat package
information
Figure 26. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package outline
C
!
!
!
# 3EATINGPLANE
MM
GAUGEPLANE
K
!
,
($
0).
)$%.4)&)#!4)/.
,
$
:%
%
(%
E
:$
B
4?-%?6
1. Drawing is not to scale.
Table 16. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
106/129
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
-
1.450
0.0531
-
0.0060
b
0.170
-
0.270
0.0067
-
0.0106
C
0.090
-
0.200
0.0035
-
0.0079
D
23.900
-
24.100
0.9409
-
0.9488
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Package information
Table 16. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E
23.900
-
24.100
0.9409
-
0.9488
e
-
0.500
-
-
0.0197
-
HD
25.900
-
26.100
1.0200
-
1.0276
HE
25.900
-
26.100
1.0200
-
1.0276
L
0.450
-
0.750
0.0177
-
0.0295
L1
-
1.000
-
-
0.0394
-
ZD
-
1.250
-
-
0.0492
-
ZE
-
1.250
-
-
0.0492
-
ccc
-
-
0.080
-
-
0.0031
k
0°
-
7°
0°
-
7°
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID027972 Rev 5
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128
Package information
STM32F767xx STM32F768Ax STM32F769xx
Figure 27. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
recommended footprint
4?&0?6
1. Dimensions are expressed in millimeters.
108/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 28. LQFP176, 24 x 24 mm, 176-pin low-profile quad flat package
top view example
3URGXFWLGHQWLILFDWLRQ
45.'**5
5HYLVLRQFRGH
: 88
'DWHFRGH
3
3LQ
LGHQWLILHU
069
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID027972 Rev 5
109/129
128
Package information
5.4
STM32F767xx STM32F768Ax STM32F769xx
WLCSP 180-bump, 5.5 x 6 mm, wafer level chip scale
package information
Figure 29. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package outline
H
'
)
$%$//
/2&$7,21
*
'(7$,/$
H
(
$
25,(17$7,21
5()(5(1&(
H
$
H
7239,(:
$
$
%277209,(:
6,'(9,(:
%803
6($7,1*3/$1(
'(7$,/$
527$7('R
$*B:/&63B0(B9
1. Drawing is not to scale.
110/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Package information
Table 17. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.525
0.555
0.585
0.0207
0.0219
0.230
A1
-
0.175
-
-
0.0069
-
A2
-
0.380
-
-
0.0150
-
A3
-
0.025
-
-
0.0010
-
(2)
0.220
0.250
0.280
0.0087
0.0098
0.0110
D
5.502
5.537
5.572
0.2166
0.2180
0.2194
E
6.060
6.095
6.130
0.2386
0.2400
0.2413
e
-
0.400
-
-
0.0157
-
e1
-
4.800
-
-
0.1890
-
e2
-
5.200
-
-
0.2047
-
F
-
0.368
-
-
0.0145
-
G
-
0.477
-
-
0.0188
-
aaa
-
0.110
-
-
0.0043
-
bbb
-
0.110
-
-
0.0043
-
ccc
-
0.110
-
-
0.0043
-
ddd
-
0.050
-
-
0.0020
-
eee
-
0.050
-
-
0.0020
-
b
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
DocID027972 Rev 5
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128
Package information
STM32F767xx STM32F768Ax STM32F769xx
Figure 30. WLCSP 180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale
package recommended footprint
'SDG
'VP
$*B:/&63B)3B9
1. Dimensions are expressed in millimeters.
Table 18. WLCSP 180-bump, 5.5 x 6 mm, recommended PCB design rules
(0.4 mm pitch)
112/129
Dimension
Recommended values
Pitch
0.4
Dpad
0.225 mm
Dsm
0.290 mm typ. (depends on the soldermask
registration tolerance)
Stencil opening
0.250 mm
Stencil thickness
0.1 mm
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 31. WLCSP180-bump, 5.5 x 6 mm, 0.4 mm pitch wafer level chip scale package
top view example
3URGXFWLGHQWLILFDWLRQ
45.'"*:
5HYLVLRQFRGH
'DWHFRGH
: 88
3
%DOO$
LGHQWLILHU
069
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID027972 Rev 5
113/129
128
Package information
5.5
STM32F767xx STM32F768Ax STM32F769xx
LQFP208 28 x 28 mm low-profile quad flat package
information
Figure 32. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package outline
6($7,1*
3/$1(
F
$
$
$
&
FFF &
PP
$
*$8*(3/$1(
.
/
'
/
'
'
3,1
,'(17,),&$7,21
(
(
(
E
H
6)@.&@7
1. Drawing is not to scale.
Table 19. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data
inches(1)
millimeters
Symbol
114/129
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
--
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Package information
Table 19. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
29.800
30.000
30.200
1.1732
1.1811
1.1890
D1
27.800
28.000
28.200
1.0945
1.1024
1.1102
D3
-
25.500
-
-
1.0039
-
E
29.800
30.000
30.200
1.1732
1.1811
1.1890
E1
27.800
28.000
28.200
1.0945
1.1024
1.1102
E3
-
25.500
-
-
1.0039
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7.0°
0°
3.5°
7.0°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
DocID027972 Rev 5
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128
Package information
STM32F767xx STM32F768Ax STM32F769xx
Figure 33. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
recommended footprint
-36
1. Dimensions are expressed in millimeters.
116/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 34. LQFP208, 28 x 28 mm, 208-pin low-profile quad flat package
top view example
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
5
45.'#*5
3LQ
LGHQWLILHU
'DWHFRGH \HDUZHHN
<::
069
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID027972 Rev 5
117/129
128
Package information
5.6
STM32F767xx STM32F768Ax STM32F769xx
UFBGA176+25, 10 x 10, 0.65 mm ultra thin fine-pitch ball grid
array package information
Figure 35. UFBGA176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
package outline
&
^ĞĂƚŝŶŐƉůĂŶĞ
Ϯ ϰ
ĚĚĚ ϭ
ď
$EDOO
LGHQWLILHU
Ğ
$EDOO
LQGH[
DUHD
$
&
&
Ğ
Z
ϭϱ
ϭ
KddKDs/t
‘EEDOOV
dKWs/t
‘ HHH 0 & $ ‘ III 0 &
ϬϳͺDͺsϲ
1. Drawing is not to scale.
Table 20. UFBGA176+25, 10 × 10 × 0.65 mm ultra thin fine-pitch ball grid array
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.002
0.0031
0.0043
A2
0.400
0.450
0.500
0.0157
0.0177
0.0197
b
0.230
0.280
0.330
0.0091
0.0110
0.0130
D
9.950
10.000
10.050
0.3917
0.3937
0.3957
E
9.950
10.000
10.050
0.3917
0.3937
0.3957
e
-
0.650
-
-
0.0256
-
F
0.400
0.450
0.500
0.0157
0.0177
0.0197
ddd
-
-
0.080
-
-
0.0031
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
118/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
Package information
Figure 36. UFBGA176+25, 10 x 10 mm x 0.65 mm, ultra fine-pitch ball grid array
package recommended footprint
'SDG
'VP
Ϭϳͺ&Wͺsϭ
Table 21. UFBGA176+25 recommended PCB design rules (0.65 mm pitch BGA)
Dimension
Recommended values
Pitch
0.65 mm
Dpad
0.300 mm
Dsm
0.400 mm typ. (depends on the soldermask registration tolerance)
Stencil opening
0.300 mm
Stencil thickness
Between 0.100 mm and 0.125 mm
Pad trace width
0.100 mm
DocID027972 Rev 5
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128
Package information
STM32F767xx STM32F768Ax STM32F769xx
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 37. UFBGA176+25, 10 × 10 × 0.6 mm ultra thin fine-pitch ball grid array
package top view example
5HYLVLRQFRGH
3URGXFWLGHQWLILFDWLRQ
5
670)
,,.
'DWHFRGH
%DOO$
LQGHQWLILHU
< ::
069
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
120/129
DocID027972 Rev 5
STM32F767xx STM32F768Ax STM32F769xx
5.7
Package information
TFBGA216, 13 x 13 x 0.8 mm thin fine-pitch ball grid
array package information
Figure 38. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package outline
= 6HDWLQJSODQH
GGG =
$
$ $
'
H
;
$EDOO
$EDOO
LGHQWLILHU LQGH[DUHD
)
'
$
*
(
(
H
<
5
‘EEDOOV
‘ HHH 0 = < ;
‘ III 0 =
%277209,(:
7239,(:
$/B0(B9
1. Drawing is not to scale.
Table 22. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.100
-
-
0.0433
A1
0.150
-
-
0.0059
-
-
A2
-
0.760
-
-
0.0299
-
b
0.350
0.400
0.450
0.0138
0.0157
0.0177
D
12.850
13.000
13.150
0.5118
0.5118
0.5177
D1
-
11.200
-
-
0.4409
-
E
12.850
13.000
13.150
0.5118
0.5118
0.5177
E1
-
11.200
-
-
0.4409
-
e
-
0.800
-
-
0.0315
-
F
-
0.900
-
-
0.0354
-
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Package information
STM32F767xx STM32F768Ax STM32F769xx
Table 22. TFBGA216, 13 × 13 × 0.8 mm thin fine-pitch ball grid array
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
G
-
0.900
-
-
0.0354
-
ddd
-
-
0.100
-
-
0.0039
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 39. TFBGA216, 13 x 13 mm, 0.8 mm pitch, thin fine-pitch ball grid array
package recommended footprint
'SDG
'VP
$/B)3B9
Table 23. TFBGA216 recommended PCB design rules (0.8 mm pitch BGA)
Dimension
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Recommended values
Pitch
0.8
Dpad
0.400 mm
Dsm
0.470 mm typ. (depends on the soldermask registration tolerance)
Stencil opening
0.400 mm
Stencil thickness
Between 0.100 mm and 0.125 mm
Pad trace width
0.120 mm
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Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 40. TFBGA216, 13 × 13 × 0.8mm thin fine-pitch ball grid array
package top view example
3URGXFWLGHQWLILFDWLRQ
45.'
5HYLVLRQFRGH
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3
%DOO$
LGHQWLILHU
'DWHFRGH
: 88
069
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Package information
5.8
STM32F767xx STM32F768Ax STM32F769xx
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max x ΘJA)
Where:
•
TA max is the maximum ambient temperature in ° C,
•
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 24. Package thermal characteristics
Symbol
ΘJA
Parameter
Value
Thermal resistance junction-ambient
LQFP100 - 14 × 14 mm / 0.5 mm pitch
43
Thermal resistance junction-ambient
WLCSP180 - 0.4 mm pitch
30
Thermal resistance junction-ambient
LQFP144 - 20 × 20 mm / 0.5 mm pitch
40
Thermal resistance junction-ambient
LQFP176 - 24 × 24 mm / 0.5 mm pitch
38
Thermal resistance junction-ambient
LQFP208 - 28 × 28 mm / 0.5 mm pitch
19
Thermal resistance junction-ambient
UFBGA176 - 10× 10 mm / 0.5 mm pitch
39
Thermal resistance junction-ambient
TFBGA216 - 13 × 13 mm / 0.8 mm pitch
29
Unit
°C/W
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
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6
Part numbering
Part numbering
Table 25. Ordering information scheme
Example:
STM32
F
76x
V
G
T
6
xxx
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
F = general-purpose
Device subfamily
767= STM32F767xx, USB OTG FS/HS, camera interface,
Ethernet, LCD-TFT
768 = STM32F768Ax, USB OTG FS/HS, camera interface,
DSI host, WLCSP with internal regulator OFF
769= STM32F769xx, USB OTG FS/HS, camera interface,
Ethernet, DSI host
Pin count
V = 100 pins
Z = 144 pins
I = 176 pins
A = 180 pins
B = 208 pins
N = 216 pins
Flash memory size
G = 1024 Kbytes of Flash memory
I = 2048 Kbytes of Flash memory
Package
T = LQFP
K = UFBGA
H = TFBGA
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C.
7 = Industrial temperature range, –40 to 105 °C.
Options
xxx = programmed parts
TR = tape and reel
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
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Recommendations when using internal reset OFF
Appendix A
STM32F767xx STM32F768Ax STM32F769xx
Recommendations when using internal reset
OFF
When the internal reset is OFF, the following integrated features are no longer supported:
A.1
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled
•
The brownout reset (BOR) circuitry must be disabled
•
The embedded programmable voltage detector (PVD) is disabled
•
VBAT functionality is no more available and VBAT pin should be connected to VDD
•
The over-drive mode is not supported
Operating conditions
Table 26. Limitations depending on the operating power supply range
Operating
power
supply
range
ADC
operation
Maximum
Flash
memory
access
frequency
with no wait
states
(fFlashmax)
VDD =1.7 to
2.1 V(3)
Conversion
time up to
1.2 Msps
20 MHz
Maximum Flash
memory access
frequency with
wait states (1)(2)
168 MHz with 8
wait states and
over-drive OFF
I/O operation
Possible Flash
memory
operations
8-bit erase and
– No I/O
program
compensation
operations only
1. Applicable only when the code is executed from Flash memory. When the code is executed from RAM, no
wait state is required.
2. Thanks to the ART accelerator on ITCM interface and L1-cache on AXI interface, the number of wait states
given here does not impact the execution speed from the Flash memory since the ART accelerator or L1cache allows to achieve a performance equivalent to 0-wait state program execution.
3. VDD/VDDA minimum value of 1.7 V, with the use of an external power supply supervisor (refer to
Section 2.18.1: Internal reset ON).
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Revision history
Revision history
Table 27. Document revision history
Date
Revision
27-Aug-2015
1
Initial release.
2
Added WLCSP180 package:
– Updated Table 10: STM32F767xx, STM32F768Ax and
STM32F769xx pin and ball definitions.
– Updated figure in the cover page.
– Added Figure 13: STM32F769xx/STM32F768Ax WLCSP180 ballout.
– Updated Table 4: Regulator ON/OFF and internal reset ON/OFF
availability.
– Updated Table 2: STM32F767xx, STM32F768Ax and STM32F769xx
features and peripheral counts.
– Updated Table 24: Package thermal characteristics.
– Updated Table 25: Ordering information scheme adding A for 180
pins.
Updated Section 2.24: Inter-integrated circuit interface (I2C) adding
Fast-mode plus.
3
Updated Section 2.25: Universal synchronous/asynchronous receiver
transmitters (USART).
Updated Table 4: Regulator ON/OFF and internal reset ON/OFF
availability adding WLCSP180 information.
Updated Table 2: STM32F767xx, STM32F768Ax and STM32F769xx
features and peripheral counts STM32F76xAx by STM32F769Ax.
Added Section 5.4: WLCSP 180-bump, 5.5 x 6 mm, wafer level chip
scale package information package information.
Updated Table 10: STM32F767xx, STM32F768Ax and STM32F769xx
pin and ball definitions adding note 1.
Updated the whole databrief adding STM32F768Ax devices.
Updated the whole databrief increasing the frequencies from 50 MHz,
100 MHz and 200MHz to 54 MHz, 108 MHz and 216 MHz respectively.
05-Oct-2015
05-Jan-2016
Changes
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Revision history
STM32F767xx STM32F768Ax STM32F769xx
Table 27. Document revision history (continued)
Date
Revision
07-Jan-2016
4
Updated cover page replacing 12.5 Mbit/s by 27 Mbit/s.
5
Updated Table 24: Package thermal characteristics adding WLCSP180
RTH.
updated Table 25: Ordering information scheme.
Added marking example for all packages.
Updated Table 2: STM32F767xx, STM32F768Ax and STM32F769xx
features and peripheral counts ethernet feature not available for
WLCSP180 package.
Updated Section 2.17: Power supply schemes replacing VDDMMC by
VDDSDMMC.
Updated Table 10: STM32F767xx, STM32F768Ax and STM32F769xx
pin and ball definitions WKUP and WLCSP180 Qx pins.
Updated Figure 13: STM32F769xx/STM32F768Ax WLCSP180 ballout
replacing “Q” by “P” row.
Updated Figure 2: STM32F767xx, STM32F768Ax and STM32F769xx
block diagram.
Added Figure 12: STM32F769xx LQFP176 pinout with DSI.
Updated Table 26: Limitations depending on the operating power
supply range changing note 3 and removing note 4.
Updated Section 2.33: Controller area network (bxCAN) with SRAM
allocation for CAN1, CAN2 and CAN3.
03-Mar-2016
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
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