LM2700 600kHz/1.25MHz, 2.5A, Step-up PWM DC/DC Converter LM2700 FEATURES DESCRIPTION


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LM2700 600kHz/1.25MHz, 2.5A, Step-up PWM DC/DC Converter LM2700 FEATURES DESCRIPTION | Manualzz

LM2700 www.ti.com

SNVS152C – MAY 2001 – REVISED MARCH 2013

LM2700 600kHz/1.25MHz, 2.5A, Step-up PWM DC/DC Converter

Check for Samples: LM2700

1

FEATURES

2

• 3.6A, 0.08

Ω , Internal Switch

• Operating Input Voltage Range of 2.2V to 12V

• Input Undervoltage Protection

• Adjustable Output Voltage up to 17.5V

• 600kHz/1.25MHz Pin Selectable Frequency

Operation

• Over Temperature Protection

• Small 14-Lead TSSOP or WSON Package

APPLICATIONS

• LCD Bias Supplies

• Handheld Devices

• Portable Applications

• GSM/CDMA Phones

• Digital Cameras

DESCRIPTION

The LM2700 is a step-up DC/DC converter with a

3.6A, 80m Ω internal switch and pin selectable operating frequency. With the ability to produce

500mA at 8V from a single Lithium Ion battery, the

LM2700 is an ideal part for biasing LCD displays. The

LM2700 can be operated at switching frequencies of

600kHz and 1.25MHz allowing for easy filtering and low noise. An external compensation pin gives the user flexibility in setting frequency compensation, which makes possible the use of small, low ESR ceramic capacitors at the output. The LM2700 features continuous switching at light loads and operates with a switching quiescent current of 2.0mA

at 600kHz and 3.0mA at 1.25MHz. The LM2700 is available in a low profile 14-lead TSSOP package or a 14-lead WSON package.

Typical Application Circuit

Figure 1. 600 kHz Operation

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2001–2013, Texas Instruments Incorporated

LM2700

SNVS152C – MAY 2001 – REVISED MARCH 2013

Connection Diagram

5

6

7

8

9

Pin

1

2

3

4

10

11

12

13

14

Name

V

C

FB

SHDN

AGND

PGND

PGND

PGND

SW

SW

SW

NC

V

IN

FSLCT

NC

Figure 2. Top View

14-Lead TSSOP or WSON

PIN DESCRIPTION

Function

Compensation network connection. Connected to the output of the voltage error amplifier.

Output voltage feedback input.

Shutdown control input, active low.

Analog ground.

Power ground. PGND pins must be connected together directly at the part.

Power ground. PGND pins must be connected together directly at the part.

Power ground. PGND pins must be connected together directly at the part.

Power switch input. Switch connected between SW pins and PGND pins.

Power switch input. Switch connected between SW pins and PGND pins.

Power switch input. Switch connected between SW pins and PGND pins.

Pin not connected internally.

Analog power input.

Switching frequency select input. V

IN

= 1.25MHz. Ground = 600kHz.

Connect to ground.

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Block Diagram

LM2700

SNVS152C – MAY 2001 – REVISED MARCH 2013

Detailed Description

The LM2700 utilizes a PWM control scheme to regulate the output voltage over all load conditions. The operation can best be understood referring to the block diagram and

Figure 17

of the

Operation

section. At the start of each cycle, the oscillator sets the driver logic and turns on the NMOS power device conducting current through the inductor, cycle 1 of

Figure 17 (a). During this cycle, the voltage at the V

C pin controls the peak inductor current. The V

C voltage will increase with larger loads and decrease with smaller. This voltage is compared with the summation of the SW voltage and the ramp compensation. The ramp compensation is used in PWM architectures to eliminate the sub-harmonic oscillations that occur during duty cycles greater than 50%. Once the summation of the ramp compensation and switch voltage equals the V

C voltage, the PWM comparator resets the driver logic turning off the NMOS power device. The inductor current then flows through the schottky diode to the load and output capacitor, cycle 2 of

Figure 17 (b). The NMOS power device is then set by the oscillator at the

end of the period and current flows through the inductor once again.

The LM2700 has dedicated protection circuitry running during normal operation to protect the IC. The Thermal

Shutdown circuitry turns off the NMOS power device when the die temperature reaches excessive levels. The

UVP comparator protects the NMOS power device during supply power startup and shutdown to prevent operation at voltages less than the minimum input voltage. The OVP comparator is used to prevent the output voltage from rising at no loads allowing full PWM operation over all load conditions. The LM2700 also features a shutdown mode decreasing the supply current to 5µA.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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SNVS152C – MAY 2001 – REVISED MARCH 2013

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Absolute Maximum Ratings

(1) (2)

V

IN

SW Voltage

FB Voltage

V

C

Voltage

SHDN Voltage

(3)

FSLCT

(3)

Maximum Junction Temperature

Power Dissipation

(4)

Lead Temperature

Vapor Phase (60 sec.)

Infrared (15 sec.)

ESD Susceptibility

(5)

Human Body Model

Machine Model

12V

18V

7V

0.965V

≤ V

C

≤ 1.565V

7V

12V

150°C

Internally Limited

300°C

215°C

220°C

2kV

200V

(1) Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test conditions, see the Electrical Characteristics.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.

(3) This voltage should never exceed V

IN

.

(4) The maximum allowable power dissipation is a function of the maximum junction temperature, T

J

(MAX), the junction-to-ambient thermal resistance, θ

JA

, and the ambient temperature, T

A

. See the Electrical Characteristics table for the thermal resistance. The maximum allowable power dissipation at any ambient temperature is calculated using: P

D

(MAX) = (T

J(MAX)

− T

A

)/ θ

JA

. Exceeding the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.

(5) The human body model is a 100 pF capacitor discharged through a 1.5k

Ω resistor into each pin. The machine model is a 200pF capacitor discharged directly into each pin.

Operating Conditions

Operating Junction Temperature Range

(1)

Storage Temperature

Supply Voltage

SW Voltage

− 40°C to +125°C

− 65°C to +150°C

2.2V to 12V

17.5V

(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are

100% tested or ensured through statistical analysis. All limits at temperature extremes are ensured via correlation using standard

Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).

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Electrical Characteristics

Specifications in standard type face are for T

J

Temperature Range (T

J

= −

= 25°C and those with boldface type apply over the full Operating

40°C to +125°C) Unless otherwise specified. V

IN

=2.2V and I

L

= 0A, unless otherwise specified.

Symbol Parameter Conditions

Min

(1)

Typ

(2)

Max

(1)

Units

I

Q

1.2

2

mA

V

FB

I

CL

(3)

%V

FB

/ Δ V

IN

I

B

V

IN g m

A

V

D

MAX

D

MIN f

S

I

SHDN

I

L

R

DSON

Th

SHDN

UVP

θ

JA

Quiescent Current FB = 2.2V (Not Switching)

FSLCT = 0V

FB = 2.2V (Not Switching)

FSLCT = V

IN

V

SHDN

= 0V

Feedback Voltage

Switch Current Limit

Feedback Voltage Line

Regulation

FB Pin Bias Current

(5)

V

IN

= 2.7V

2.2V

≤ V

IN

(4)

≤ 12.0V

Input Voltage Range

Error Amp Transconductance Δ I = 5µA

Error Amp Voltage Gain

Maximum Duty Cycle

Minimum Duty Cycle

FSLCT = Ground

FSLCT = Ground

Switching Frequency

Shutdown Pin Current

Switch Leakage Current

Switch R

DSON

(6)

SHDN Threshold

FSLCT = V

IN

FSLCT = Ground

FSLCT = V

IN

V

SHDN

= V

IN

V

SHDN

= 0V

V

SW

= 18V

V

IN

= 2.7V, I

SW

= 2A

Output High

Output Low

On Threshold

Off Threshold

Thermal Resistance

(7)

TSSOP, package only

WSON, package only

1.2285

2.55

2.2

40

78

480

1

0.9

1.95

1.85

1.3

5

1.26

3.6

0.02

0.5

600

1.25

0.008

− 0.5

0.02

155

135

85

15

30

80

0.6

0.6

2.05

1.95

150

45

2

20

1.2915

4.3

0.07

40

12

290

720

1.5

1

− 1

20

150

0.3

2.2

2.1

mA

µA m Ω

V

V

V

V

µA

V

A

%/V nA

V

µmho

V/V

%

% kHz

MHz

µA

°C/W

(1) All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are

100% tested or ensured through statistical analysis. All limits at temperature extremes are ensured via correlation using standard

Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) Typical numbers are at 25°C and represent the most likely norm.

(3) Duty cycle affects current limit due to ramp generator.

(4) Current limit at 0% duty cycle. See

Typical Performance Characteristics

section for Switch Current Limit vs. V

IN

(5) Bias current flows into FB pin.

(6) Does not include the bond wires. Measured directly at the die.

(7) Refer to Texas Instrument's packaging website for more detailed thermal information and mounting techniques for the WSON and

TSSOP packages.

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SNVS152C – MAY 2001 – REVISED MARCH 2013

Typical Performance Characteristics

Efficiency vs. Load Current

(V

OUT

= 8V, f

S

= 600 kHz)

Efficiency vs. Load Current

(V

OUT

= 8V, f

S

= 1.25 MHz) www.ti.com

Figure 3.

Efficiency vs. Load Current

(V

OUT

= 5V, f

S

= 600 kHz)

Figure 4.

Efficiency vs. Load Current

(V

OUT

= 12V, f

S

= 600 kHz)

Figure 5.

Switch Current Limit vs. Temperature

Figure 6.

Switch Current Limit vs. V

IN

Figure 7.

Figure 8.

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LM2700

SNVS152C – MAY 2001 – REVISED MARCH 2013

Typical Performance Characteristics (continued)

R

DSON

(I

SW vs. V

= 2A)

IN

I

Q vs. V

IN

(600 kHz, not switching)

Figure 9.

I

Q vs. V

IN

(600 kHz, switching)

Figure 11.

I

Q vs. V

IN

(1.25 MHz, switching)

Figure 10.

I

Q vs. V

IN

(1.25 MHz, not switching)

Figure 12.

I

Q vs. V

IN

(In shutdown)

Figure 13.

Figure 14.

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SNVS152C – MAY 2001 – REVISED MARCH 2013

Typical Performance Characteristics (continued)

Frequency vs. V

IN

(600 kHz)

Frequency vs. V

IN

(1.25 MHz) www.ti.com

Figure 15.

Figure 16.

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Operation

LM2700

SNVS152C – MAY 2001 – REVISED MARCH 2013

Figure 17. Simplified Boost Converter Diagram

(a) First Cycle of Operation (b) Second Cycle Of Operation

CONTINUOUS CONDUCTION MODE

The LM2700 is a current-mode, PWM boost regulator. A boost regulator steps the input voltage up to a higher output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady state), the boost regulator operates in two cycles.

In the first cycle of operation, shown in

Figure 17 (a), the transistor is closed and the diode is reverse biased.

Energy is collected in the inductor and the load current is supplied by C

OUT

.

The second cycle is shown in

Figure 17 (b). During this cycle, the transistor is open and the diode is forward

biased. The energy stored in the inductor is transferred to the load and output capacitor.

The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as:

V

OUT

=

V

IN

1-D

V

IN

, D' = (1-D) =

V

OUT

(1) where D is the duty cycle of the switch, D and D ′ will be required for design calculations.

SETTING THE OUTPUT VOLTAGE

The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in

Figure 19

. The feedback pin voltage is 1.26V, so the ratio of the feedback resistors sets the output voltage according to the following equation:

R

FB1

= R

FB2 x

V

OUT

- 1.26

1.26

:

(2)

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SNVS152C – MAY 2001 – REVISED MARCH 2013

INTRODUCTION TO COMPENSATION

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Figure 18. (a) Inductor current. (b) Diode current.

The LM2700 is a current mode PWM boost converter. The signal flow of this control scheme has two feedback loops, one that senses switch current and one that senses output voltage.

To keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet certain criteria. The inductor, along with input and output voltage, will determine the slope of the current through the inductor (see

Figure 18 (a)). If the slope of the inductor current is too great, the circuit will be unstable above

duty cycles of 50%. A 4.7µH inductor is recommended for most 600 kHz applications, while a 2.2µH inductor may be used for most 1.25 MHz applications. If the duty cycle is approaching the maximum of 85%, it may be necessary to increase the inductance by as much as 2X. See Inductor and Diode Selection for more detailed inductor sizing.

The LM2700 provides a compensation pin (V

C

) to customize the voltage loop feedback. It is recommended that a series combination of R

C and C

C be used for the compensation network, as shown in application, there exists a unique combination of R

C and C

C

Figure 19

. For any given that will optimize the performance of the LM2700 circuit in terms of its transient response. The series combination of R

C according to the following equations: and C

C introduces a pole-zero pair

1 f

ZC

=

2

S

R

C

C

C

Hz

(3) f

PC

=

1

2

S

(R

C

+ R

O

)C

C

Hz

(4)

10

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SNVS152C – MAY 2001 – REVISED MARCH 2013 where R

O is the output impedance of the error amplifier, approximately 850k performance can be optimized by choosing values within the range 5k Ω ≤ R

C

≤ 20k Ω

Ω . For most applications,

(R

C can be up to 200k Ω if

C

C2 is used, see High Output Capacitor ESR Compensation) and 680pF ≤ C

C

≤ 4.7nF. Refer to the

Application

Information

section for recommended values for specific circuits and conditions. Refer to the

COMPENSATION

section for other design requirement.

COMPENSATION

This section will present a general design procedure to help insure a stable and operational circuit. The designs in this datasheet are optimized for particular requirements. If different conversions are required, some of the components may need to be changed to ensure stability. Below is a set of general guidelines in designing a stable circuit for continuous conduction operation (loads greater than approximately 100mA), in most all cases this will provide for stability during discontinuous operation as well. The power components and their effects will be determined first, then the compensation components will be chosen to produce stability.

INDUCTOR AND DIODE SELECTION

Although the inductor sizes mentioned earlier are fine for most applications, a more exact value can be calculated. To ensure stability at duty cycles above 50%, the inductor must have some minimum value determined by the minimum input voltage and the maximum output voltage. This equation is:

L >

V

IN

R

DSON

0.144 fs

(

D

D'

)

2

-1

(

D

D'

)

+1

(in H)

(5) where fs is the switching frequency, D is the duty cycle, and R

DSON taken from the graph "R

DSON vs. V

IN

" in the is the ON resistance of the internal switch

Typical Performance Characteristics

section. This equation is only good for duty cycles greater than 50% (D>0.5), for duty cycles less than 50% the recommended values may be used. The corresponding inductor current ripple as shown in

Figure 18

(a) is given by:

' i

L

=

V

IN

D

2Lfs

(in Amps)

(6)

The inductor ripple current is important for a few reasons. One reason is because the peak switch current will be the average inductor current (input current or I

LOAD

/D') plus Δ i

L

. As a side note, discontinuous operation occurs when the inductor current falls to zero during a switching cycle, or

Δ i

L current. Therefore, continuous conduction mode occurs when Δ i

L is greater than the average inductor is less than the average inductor current. Care must be taken to make sure that the switch will not reach its current limit during normal operation. The inductor must also be sized accordingly. It should have a saturation current rating higher than the peak inductor current expected. The output voltage ripple is also affected by the total ripple current.

The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output current. The typical current waveform for the diode in continuous conduction mode is shown in

Figure 18 (b). The

diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current rating must be greater than the maximum load current expected, and the peak current rating must be greater than the peak inductor current. During short circuit testing, or if short circuit conditions are possible in the application, the diode current rating must exceed the switch current limit. Using Schottky diodes with lower forward voltage drop will decrease power dissipation and increase efficiency.

DC GAIN AND OPEN-LOOP GAIN

Since the control stage of the converter forms a complete feedback loop with the power components, it forms a closed-loop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover frequency and the phase margin. A high phase margin (greater than 45°) is desired for the best stability and transient response. For the purpose of stabilizing the LM2700, choosing a crossover point well below where the right half plane zero is located will ensure sufficient phase margin. A discussion of the right half plane zero and checking the crossover using the DC gain will follow.

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INPUT AND OUTPUT CAPACITOR SELECTION

The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is required to reduce the input ripple and noise for proper operation of the regulator. The size used is dependant on the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of the regulator is very close to the source output. The size will generally need to be larger for applications where the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value of 10µF should be used for the less stressful condtions while a 33µF or 47µF capacitor may be required for higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very low ripple on the input source voltage.

The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted R

ESR

) capacitors be used such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require more compensation which will be explained later on in the section. The ESR is also important because it determines the peak to peak output voltage ripple according to the approximate equation:

Δ V

OUT

≊ 2 Δ i

L

R

ESR

(in Volts) (7)

A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output capacitor you can determine a pole-zero pair introduced into the control loop by the following equations:

1 f

P1

=

2

S

(R

ESR

+ R

L

)C

OUT

(in Hz)

(8) f

Z1

=

1

2

S

R

ESR

C

OUT

(in Hz)

(9)

Where R

L is the minimum load resistance corresponding to the maximum load current. The zero created by the

ESR of the output capacitor is generally very high frequency if the ESR is small. If low ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the

HIGH OUTPUT CAPACITOR ESR

COMPENSATION

section.

RIGHT HALF PLANE ZERO

A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be designed to have a bandwidth of less than ½ the frequency of the RHP zero. This zero occurs at a frequency of:

RHPzero =

V

OUT

(D')

2

2

S,

LOAD

L

(in Hz)

(10) where I

LOAD is the maximum load current.

SELECTING THE COMPENSATION COMPONENTS

The first step in selecting the compensation components R

C the control loop. Simply choose values for R

C and C

C and C

C is to set a dominant low frequency pole in within the ranges given in the

INTRODUCTION TO

COMPENSATION

section to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is determined by the equation:

1 f

PC

=

2

S

(R

C

+ R

O

)C

C

(in Hz)

(11) where R

O than R

O is the output impedance of the error amplifier, approximately 850k Ω . Since R

C is generally much less

, it does not have much effect on the above equation and can be neglected until a value is chosen to set the zero f

ZC

. f

ZC is created to cancel out the pole created by the output capacitor, f

P1

. The output capacitor pole will shift with different load currents as shown by the equation, so setting the zero is not exact. Determine the range of f

P1 over the expected loads and then set the zero f frequency of this zero is determined by:

ZC to a point approximately in the middle. The f

ZC

=

1

2

S

C

C

R

C

(in Hz)

(12)

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Now R

C can be chosen with the selected value for C

C

. Check to make sure that the pole f

PC is still in the 10Hz to

500Hz range, change each value slightly if needed to ensure both component values are in the recommended range. After checking the design at the end of this section, these values can be changed a little more to optimize performance if desired. This is best done in the lab on a bench, checking the load step response with different values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should produce a stable, high performance circuit. For improved transient response, higher values of R

C should be chosen. This will improve the overall bandwidth which makes the regulator respond more quickly to transients. If more detail is required, or the most optimal performance is desired, refer to a more in depth discussion of compensating current mode DC/DC switching regulators.

HIGH OUTPUT CAPACITOR ESR COMPENSATION

When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding another capacitor, C

C2

, directly from the compensation pin V

C

R

C and C

C to ground, in parallel with the series combination of

. The pole should be placed at the same frequency as f

Z1

, the ESR zero. The equation for this pole follows:

1 f

PC2

=

2

S

C

C2

(R

C

//R

O

)

(in Hz)

(13)

To ensure this equation is valid, and that C

C2 f

PC2 must be greater than 10f

ZC

.

can be used without negatively impacting the effects of R

C and C

C

,

CHECKING THE DESIGN

The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP zero. This is done by calculating the open-loop DC gain, A

DC

. After this value is known, you can calculate the crossover visually by placing a

20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also be improved by adding C

C2 as discussed earlier in the section. The equation for A equations required for the calculation:

DC is given below with additional

A

DC(DB)

= 20log

10

R

FB2

(

R

FB1

+ R

FB2

) g m

R

O

D'

{[(

Z cLeff)// R

L

R

DSON

]//R

L

}

(in dB)

(14)

Z c #

2fs nD'

(in rad/s)

(15)

Leff =

L

(D')

2

(16) n = 1+

2mc m1

(no unit)

(17)

(18) mc ≊ 0.072fs (in V/s) m1

#

V

IN

R

DSON

L

(in V/s)

(19) where R

L

"R

DSON is the minimum load resistance, V

IN vs. V

IN is the minimum input voltage, g transconductance found in the Electrical Characteristics table, and R

DSON

" in the

Typical Performance Characteristics

section.

m is the error amplifier is the value chosen from the graph

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LAYOUT CONSIDERATIONS

The LM2700 uses two separate ground connections, PGND for the driver and NMOS power device and AGND for the sensitive analog control circuitry. The AGND and PGND pins should be tied directly together at the package. The feedback and compensation networks should be connected directly to a dedicated analog ground plane and this ground plane must connect to the AGND pin. If no analog ground plane is available then the ground connections of the feedback and compensation networks must tie directly to the AGND pin. Connecting these networks to the PGND can inject noise into the system and effect performance.

The input bypass capacitor C

IN

, as shown in

Figure 19

, must be placed close to the IC. This will reduce copper trace resistance which effects input voltage ripple of the IC. For additional input voltage filtering, a 100nF bypass capacitor can be placed in parallel with C

IN

, close to the V

IN pin, to shunt any high frequency noise to ground.

The output capacitor, C

OUT

, should also be placed close to the IC. Any copper trace connections for the C

OUT capacitor can increase the series resistance, which directly effects output voltage ripple. The feedback network, resistors R

FB1 and R

FB2

, should be kept close to the FB pin, and away from the inductor, to minimize copper trace connections that can inject noise into the system. Trace connections made to the inductor and schottky diode should be minimized to reduce power dissipation and increase overall efficiency. For more detail on switching power supply layout considerations see Application Note AN-1149: Layout Guidelines for Switching

Power Supplies (literature number SNVA021 ).

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APPLICATION INFORMATION

LM2700

SNVS152C – MAY 2001 – REVISED MARCH 2013

Figure 19. 600 kHz operation, 8V output

Figure 20. 1.25 MHz operation, 8V output

Figure 21. 600 kHz operation, 5V output

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LM2700

SNVS152C – MAY 2001 – REVISED MARCH 2013

www.ti.com

V

IN

= 3.3V, I

OUT

CH1: I

OUT

= 200mA ⇝ 700mA

0.5A/div DC Coupled

⇝ 200mA

CH2: V

OUT

500mV/div AC Coupled

CH3: Inductor Current 1A/div DC Coupled

20µs/div

Figure 22. Load Transient for

Figure 21

Figure 23. 600 kHz operation, 12V output

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V

IN

= 3.3V, I

OUT

CH1: I

OUT

= 50mA ⇝ 350mA

0.5A/div DC Coupled

⇝ 50mA

CH2: V

OUT

500mV/div AC Coupled

CH3: Inductor Current 1A/div DC Coupled

50µs/div

Figure 24. Load Transient for

Figure 23

LM2700

SNVS152C – MAY 2001 – REVISED MARCH 2013

Figure 25. Triple Output TFT Bias (600 kHz operation)

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LM2700

SNVS152C – MAY 2001 – REVISED MARCH 2013

www.ti.com

V

IN

= 3.3V, I

OUT

CH1: V

IN

= 500mA

2V/div DC Coupled

CH2: V

OUT

5V/div DC Coupled

CH3: Inductor Current 500mA/div DC Coupled

1ms/div

Figure 26. Start Up Waveform for

Figure 25

V

IN

= 3.3V, I

OUT

CH1: I

OUT

= 50mA ⇝ 375mA

0.2A/div DC Coupled

⇝ 50mA

CH2: V

OUT

2V/div AC Coupled

CH3: Inductor Current 1A/div DC Coupled

500µs/div

Figure 27. Load Transient for

Figure 25 , 8V Output

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SNVS152C – MAY 2001 – REVISED MARCH 2013

REVISION HISTORY

Changes from Revision B (March 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ..........................................................................................................

18

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PACKAGE OPTION ADDENDUM

www.ti.com

1-Nov-2013

PACKAGING INFORMATION

Orderable Device

LM2700LD-ADJ/NOPB

LM2700LDX-ADJ/NOPB

Status

(1)

ACTIVE

ACTIVE

Package Type Package

Drawing

WSON

WSON

NHE

NHE

Pins Package

14

14

Qty

Eco Plan

(2)

1000 Green (RoHS

& no Sb/Br)

4500 Green (RoHS

& no Sb/Br)

Lead/Ball Finish

(6)

CU SN

CU SN

MSL Peak Temp

(3)

Op Temp (°C)

Level-3-260C-168 HR -40 to 125

Level-3-260C-168 HR -40 to 125

Device Marking

(4/5)

S00001B

S00001B

LM2700MT-ADJ

LM2700MT-ADJ/NOPB

NRND

ACTIVE

TSSOP

TSSOP

PW

PW

14

14

94

94

TBD

Green (RoHS

& no Sb/Br)

Call TI

CU SN

Call TI

Level-1-260C-UNLIM

-40 to 125

-40 to 125

2700MT

-ADJ

2700MT

-ADJ

LM2700MTX-ADJ/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS

& no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

CU SN Level-1-260C-UNLIM

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

-40 to 125 2700MT

-ADJ

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

www.ti.com

1-Nov-2013

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

6-Nov-2015

*All dimensions are nominal

Device

LM2700LD-ADJ/NOPB

Package

Type

Package

Drawing

WSON

LM2700LDX-ADJ/NOPB WSON

LM2700MTX-ADJ/NOPB TSSOP

NHE

NHE

PW

Pins

14

14

14

SPQ

1000

4500

2500

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

178.0

12.4

330.0

330.0

12.4

12.4

A0

(mm)

4.3

4.3

6.95

B0

(mm)

4.3

4.3

5.6

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

1.3

1.3

1.6

8.0

12.0

8.0

12.0

8.0

12.0

Q1

Q1

Q1

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

6-Nov-2015

*All dimensions are nominal

Device

LM2700LD-ADJ/NOPB

LM2700LDX-ADJ/NOPB

LM2700MTX-ADJ/NOPB

Package Type Package Drawing Pins

WSON

WSON

TSSOP

NHE

NHE

PW

14

14

14

SPQ

1000

4500

2500

Length (mm) Width (mm) Height (mm)

213.0

367.0

367.0

191.0

367.0

367.0

55.0

35.0

35.0

Pack Materials-Page 2

NHE0014A

MECHANICAL DATA

www.ti.com

LDA14A (REV A)

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards.

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