PR533 1. General description USB NFC integrated reader solution

PR533

USB NFC integrated reader solution

Rev. 3.6 — 27 October 2014

206436

Product short data sheet

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The PR5331C3HN is a highly integrated transceiver module for contactless reader/writer communication at 13.56 MHz.

A dedicated ROM code is implemented to handle different RF protocols by an integrated microcontroller. The system host controller communicates with the PR5331C3HN by using the USB or the HSU link.

The protocol between the host controller and the PR5331C3HN, on top of this physical link is the CCID protocol.

1.1 RF protocols

PR5331C3HN supports the PCD mode for FeliCa (212 kbps and 424 kbps),

ISO/IEC14443 Type A and B (from 106 kbps to 848 kbps), MIFARE (106 kbps), B' cards

(106 kbps), picoPass tag (106 kbps) and Innovision Jewel cards (106 kbps)

The Initiator passive mode (from 106 kbps to 424 kbps) can be supported through the

PC/SC transparent mode.

1.2 Interfaces

The PR5331C3HN supports a USB 2.0 full speed interface (bus powered or host powered mode).

Alternatively to the USB interface, a High Speed UART (from 9600b up to 1.2 Mb) can be used to connect the PR533 to a host.

The PR5331C3HN has also a master I

2

C-bus interface that allows to connect one of the following peripherals:

•

An external EEPROM: in this case the PR5331C3HN is configured as master and is able to communicate with external EEPROM (address A0h) which can store configuration data like PID, UID and RF parameters. When a USB host interface is used, these parameters are retrieved from the EEPROM at startup of the device

•

A TDA8029 contact smart card reader

1.3 Standards compliancy

PR5331C3HN offers commands in order for applications to be compliant with “EMV

Contactless Communication Protocol Specification V2.0.1”.

PR5331C3HN supports RF protocols ISO/IEC 14443A and B such as compliancy with

Smart eID standard can be achieved at application level.

NXP Semiconductors

PR533


Support of USB 2.0 full speed, interoperable with USB 3.0 hubs.

The PR533C3HN in PCD mode is compliant with EMV contactless specification V2.0.1.

1.4 Supported operating systems

•

Microsoft Windows 2000

•

Microsoft Windows XP (32 and 64 bits)

•

Microsoft Windows 2003 Server (32 and 64 bits)

•

Microsoft Windows 2008 Server (32 and 64 bits)

•

Microsoft Windows Vista (32 and 64 bits)

•

Microsoft Windows 7 (32 and 64 bits)

The PR533 is supported by the following OS through the PCSC-Lite driver:

•

GNU/Linux using libusb 1.0.x and later

•

Mac OS Leopard (1.5.6 and newer)

•

Mac OS Snow Leopard (1.6.X)

•

Solaris

•

FreeBSD

2. Features and benefits



USB 2.0 full speed host interface and CCID protocol support



Integrated microcontroller implements high-level RF protocols



Buffered output drivers to connect an antenna with minimum number of external components



Integrated RF level detector



Integrated data mode detector



Supports ISO/IEC 14443A Reader/Writer mode up to 848 kbit/s



Supports ISO/IEC 14443B Reader/Writer mode up to 848 kbit/s



Supports contactless communication according to the FeliCa protocol at 212 kbit/s and

424 kbit/s



Supports MIFARE encryption



Typical operating distance in Read/Write mode for communication to

ISO/IEC 14443A/MIFARE, ISO/IEC 14443B or FeliCa cards up to 50 mm depending on antenna size and tuning



I

2

C-bus master interface allows to connect an external I

2

C EEPROM for configuration data storage or to control a TDA8029 contact smart card reader



Low-power modes



Hard power-down mode



Soft power-down mode



Only one external oscillator required (27.12 MHz Crystal oscillator)



Power modes



USB bus power mode



2.5 V to 3.6 V power supply operating range in non-USB bus power mode

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

Dedicated I/O ports for external device control

3. Quick reference data

Table 1.

Quick reference data

I

I

I

I

I

Symbol

V

V

V

V

V

V

BUS

DDA

DDD

DD(TVDD)

DD(PVDD)

DD(SVDD)

BUS pd

CCSL

DDD

DD(SVDD)

I

DDA

I

DD(TVDD)

Parameter

bus supply voltage analog supply voltage digital supply voltage

TVDD supply voltage

PVDD supply voltage

SVDD supply voltage bus supply current power-down current suspended low-power device supply current digital supply current

SVDD supply current analog supply current

TVDD supply current

Conditions

P tot

T amb total power dissipation ambient temperature

[1] V

DDD

, V

DDA

and V

DD(TVDD) must always be at the same supply voltage.

Min

4.02

2.5

Typ

5

3.3

Max

5.25

3.6

(non-USB mode);

V

BUS

= V

DDD;

V

SSD

= 0 V

V

DDA

V

= V

DDD

V

DD(PVDD)

SS(PVSS)

; V

SSA

= V

= V

= V

DD(TVDD)

SSD

=

SS(TVSS)

=

= 0 V

[1]

2.5

[1]

2.5

[1]

2.5

3.3

3.3

3.3

1.6

-

V

DDD

 0.1 -

3.6

3.6

3.6

3.6

V

DDD

V

SSA

= V

SSD

= V

SS(PVSS)

=

V

SS(TVSS)

= 0 V; reserved for future use maximum load current (USB mode); measured on V

BUS maximum inrush current limitation; at power-up

(curlimoff = 0)

150

100

V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

= 3 V; not powered from USB hard power-down;

RF level detector off

10

30 soft power-down; RF level detector on

RF level detector on, (without resistor on DP/DM)

250

[1]

15 RF level detector on,

V

DD(SVDD)

switch off

V

DDS

= 3 V

RF level detector on during RF transmission;

V

DD(TVDD)

= 3 V

T amb

=

30 to +85 C

-

-

-

-

30

-

-

-

6

60

-

30

100

0.55

+85 mA mA

V

V

V

V

V

Unit

V

V mA mA mA

W

C

A

A

A mA

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Table 2.

Ordering information

Type number Package

Name

PR5331C3HN/C360

[1][2][3]

PR5331C3HN/C370

[1][2][3]

HVQFN40

Description

plastic thermal enhanced very thin quad flat package; no leads;

40 terminals; body 6

 6  0.85 mm

Version

SOT618-1

[1] 60 or 70 refers to the ROM code version described in the User Manual. For differences of romcode versions refer to the release note of the product.

[2]

Refer to Section 14.4 “Licenses”

.

[3] MSL 2 (Moisture Sensitivity Level).

The following block diagram describes hardware blocks controlled by PR5331C3HN firmware or which can be accessible for data transaction by a host baseband.

RSTPD_N RSTOUT_N DVDD P70_IRQ AVSS

VBUS

DVSS

OSCIN

OSCOUT

DELATT

I0

I1

MATX

SDA

P50_SCL

PVDD

SUPPLY

SUPERVISOR

REGULATOR

3.3 V

27 MHz OSC

AND

FRAC N

PLL

48 MHz

USB

DEVICE

PCR

80C51 CPU

44 k ROM

1.2 k BYTES RAM

SVDD

SWITCH

NFC

ANALOG

FRONT END

AND

CLUART

SVDD

SIGIN

SIGOUT

P34

TVDD

AVDD

RX

VMID

TX1

TVSS

TX2

I

2

C

MASTER

P30 P31 P32_INT0

GPIOs

P33_INT0 P35

aaa-000043

Fig 1.

Block diagram

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6.1 Pinning

terminal 1 index area

DVSS

LOADMOD

TVSS1

TX1

TVDD

TX2

TVSS2

AVDD

VMID

RX

3

4

5

6

1

2

7

8

9

10

PR533

30

29

28

27

26

25

24

23

22

21

P32_INT0

P31

P30

DELATT

PVDD

DP

DM

DVSS

RSTOUT_N

P70_IRQ

aaa-000044

Transparent top view

Fig 2.

Pin configuration for HVQFN 40 (SOT618-1)

6.2 Pin description

Table 3.

PR533 pin description

Symbol Pin Type Pad ref voltage

DVSS

LOADMOD

1

2

G

O DVDD

TVSS1

TX1

TVDD

TX2

TVSS2

AVDD

VMID

RX

AVSS

AUX1

AUX2

DVSS

3

4

5

8

9

6

7

10 I

P

P

O

G

G

O

P

11 G

12 O

13 O

14 G

TVDD

TVDD

AVDD

AVDD

DVDD

DVDD

Description

digital ground load modulation output provides digital signal for FeliCa and MIFARE card operating mode transmitter ground: supplies the output stage of TX1 transmitter 1: transmits modulated 13.56 MHz energy carrier transmitter power supply: supplies the output stage of TX1 and TX2 transmitter 2: delivers the modulated 13.56 MHz energy carrier transmitter ground: supplies the output stage of TX2 analog power supply internal reference voltage: This pin delivers the internal reference voltage.

receiver input: Input pin for the reception signal, which is the load modulated

13.56 MHz energy carrier from the antenna circuit analog ground auxiliary output 1: This pin delivers analog and digital test signals auxiliary output 2: This pin delivers analog and digital test signals digital ground

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Table 3.


…continued


Description

OSCIN

OSCOUT

15 I

16 O

AVDD

AVDD crystal oscillator input: input to the inverting amplifier of the oscillator. This pin is also the input for an externally generated clock (f clk

= 27.12 MHz).

crystal oscillator output: output of the inverting amplifier of the oscillator.

I0

I1

TESTEN

17

18

19 I

I

I

DVDD

DVDD

DVDD interface mode lines: selects the used host interface; in test mode I0 is used as test signals.

P35

P70_IRQ

RSTOUT_N

20 I/O

21 I/O

22 O

DVDD

PVDD

PVDD test enable pin: when set to 1 enable the test mode. when set to 0 reset the TCB and disable the access to the test mode.

general purpose I/O signal interrupt request: output to signal an interrupt event to the host (Port 7 bit 0) output reset signal; when LOW it indicates that the circuit is in reset state.

DVSS

DM

23 G

24 I/O PVDD

DP

PVDD

DELATT

P30

P31

P32_INT0

P33_INT1

P50_SCL

SDA

P34

SIGOUT

SIGIN

SVDD

25

26

29

30

31

32

33

34

35

36

37

I

I/O

P

27 O

28 I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

P

PVDD

PVDD

PVDD

PVDD

PVDD

PVDD

DVDD

DVDD

SVDD

SVDD

SVDD digital ground

USB D

 data line in USB mode or TX in HSU mode; in test mode this signal is used as input and output test signal

USB D+ data line in USB mode or RX in HSU mode; in test mode this signal is used as input and output test signal.

I/O pad power supply optional output for an external 1.5 k

 resistor connection on D+.

general purpose I/O signal. Can be configured to act either as RX line of the second serial interface UART or general purpose I/O.

In test mode this signal is used as input and output test signal.

general purpose I/O signal. Can be configured to act either as TX line of the second serial interface UART or general purpose I/O.


general purpose I/O signal. Can also be used as an interrupt source


general purpose I/O signal. Can be used to generate an HZ state on the output of the selected interface for the Host communication and to enter into power-down mode without resetting the internal state of PR533.


I

2

C-bus clock line - open-drain in output mode

I

2

C-bus data line - open-drain in output mode general purpose I/O signal or clock signal for the SAM contactless communication interface output: delivers a serial data stream according to NFCIP-1 and output signal for the SAM.

In test mode this signal is used as test signal output.

contactless communication interface input: accepts a digital, serial data stream according to NFCIP-1 and input signal from the SAM.

In test mode this signal is used as test signal input.

output power for SAM power supply. Switched on by Firmware with an overload detection. Used as a reference voltage for SAM communication.

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Table 3.


…continued


Description

RSTPD_N 38 I PVDD reset and power-down: When LOW, internal current sources are switched off, the oscillator is inhibited, and the input pads are disconnected from the outside world.

With a negative edge on this pin the internal reset phase starts.

DVDD

VBUS

39 P

40 P digital power supply

USB power supply.

[1] Pin types: I= Input, O = Output, I/O = Input/Output, P = Power and G = Ground.

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions

V

DDA

V

DDD

V

DD(TVDD)

V

DD(PVDD)

V

DD(SVDD)

V

BUS

P tot

I

DD(SVDD) analog supply voltage digital supply voltage

TVDD supply voltage

PVDD supply voltage

SVDD supply voltage bus supply voltage total power dissipation

SVDD supply current

V i

V

ESD input voltage electrostatic discharge voltage maximum current in V

DDS switch

TX1, TX2, RX pins

HBM

MM

CDM

T stg

T j

V i(dyn)(RX) storage temperature junction temperature dynamic input voltage on pin RX input signal at 13.56 MHz

V i(dyn)(TX1) dynamic input voltage on pin TX1 input signal at 13.56 MHz

I

V i(dyn)(TX2) dynamic input voltage on pin TX2 input signal at 13.56 MHz

TX1 current on pin TX1 output signal at 13.56 MHz

I

TX2 current on pin TX2 output signal at 13.56 MHz

[1] 1500

, 100 pF; EIA/JESD22-A114-A

[2] 0.75 mH, 200 pF; EIA/JESD22-A115-A

[3] Field induced model; EIA/JESC22-C101-C

0.5

[1]

[2]

-

[3]

-

55

40

0.7

1.2

1.2

300

300

-

-

Min

0.5

0.5

0.5

0.5

0.5

0.5

+4

+4

+4

Max

+4

+4

+5.5

500

30

+4

2.0

200

1

+150

+125

V kV

V

DD(AVDD)

+ 1.0

V

V

DD(TVDD)

+ 1.3

V

V

DD(TVDD)

+ 1.3

V

+300 mA

V kV

C

C

+300 mA

V

V

V

Unit

V

V

V mW mA

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8. Recommended operating conditions

Table 5.

Operating conditions


V

V

V

V

DD(TVDD)

TVDD supply voltage

V

BUS

DDA

DDD

DD(PVDD) bus supply voltage V

SSA

= V

SSD = VSS(PVSS)

= V

SS(TVSS)

= 0 V analog supply voltage digital supply voltage supply voltage (non-USB mode); V

BUS

= V

DDD

;

V

SSA

= V

SSD = VSS(PVSS)

= V

SS(TVSS)

= 0 V

V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

;

V

SSA

= V

SSD = VSS(PVSS)

= V

SS(TVSS)

= 0 V

V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

;

V

SSA

= V

SSD = VSS(PVSS)

= V

SS(TVSS)

= 0 V

PVDD supply voltage

V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

;

V

SSA

= V

SSD = VSS(PVSS)

= V

SS(TVSS)

= 0 V supply pad for host interface;

V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

;

V

SSA

= V

SSD = VSS(PVSS)

= V

SS(TVSS)

= 0 V

T amb ambient temperature

Min

4.02

2.5

[1][2]

2.5

[1][2]

2.5

[1][2]

2.5

[2]

1.6

30

[1] V

SSA

, V

DDD

and V

DD(TVDD)

shall always be on the same voltage level.

[2] Supply voltages below 3 V reduces the performance (e.g. the achievable operating distance).

Typ

5

3.3

3.3

+25

3.3

3.6

3.3

3.6

1.8 to 3.3 3.6

+85

Max

5.25

3.6

3.6

Unit

V

V

V

C

V

V

V

Table 6.

Thermal characteristics

Symbol Parameter

R th(j-a) thermal resistance from junction to ambient

Conditions

in free air with exposed pad soldered on a 4 layer Jedec

PCB-0.5

-

Min Typ Max Unit

37 41.1 K/W

10. Characteristics

Unless otherwise specified, the limits are given for the full operating conditions. The typical value is given for 25

C, V

DDD

= 3.4 V and V

DD(PVDD)

= 3 V in non-USB bus power mode, V

BUS

= 5 V in USB power mode.

Timings are only given from characterization results.

10.1 Power management characteristics

10.1.1 Current consumption characteristics

Typical value using a complementary driver configuration and an antenna matched to

40

 between TX1 and TX2 at 13.56 MHz.

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Table 7.

Current consumption characteristics

I

I

I

Symbol

pd

CCSL

DDD

Parameter

power-down current suspended low-power device supply current digital supply current

Conditions Min Typ Max Unit

V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

= 3 V; not powered from USB hard power-down current; not powered from USB; RF level detector off

[1]

1.3

10 soft power-down current; not powered from USB; RF level detector on

[1]

9 30

[1]

120 250 V

BUS

= 5 V; V

DDA

= V

DDD

= V

DD(TVDD)

=

V

DD(PVDD)

= 3 V; V

DDS

= 0 V; RF level detector on (without resistor on pin DP

(D+))

12 -

A

A

A mA

I

I

I

I

DDA

DD(PVDD)

DD(SVDD)

DD(TVDD) analog supply current

PVDD supply current

SVDD supply current

TVDD supply current

V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

= 3 V; RF level detector on

V

DDA

= V

DDD

= V

DD(TVDD)

= V

DD(PVDD)

= 3 V

RF level detector on

RF level detector off sam_switch_en set to 1 continuous wave; V

DD(TVDD)

= 3 V

[2]

-

[3]

-

[4][5]

-

-

-

-

-

-

3

1.5

60

6

5

30

30

100 mA mA mA mA mA

[1] I pd

is the total currents over all supplies.

[2] I

DD(PVDD)

depends on the overall load at the digital pins.

[3] I

DD(SVDD)

depends on the overall load on V

DD(SVDD)

pad.

[4] I

DD(TVDD)

depends on V

DD(TVDD)

and the external circuitry connected to TX1 and TX2.

[5] During operation with a typical circuitry the overall current is below 100 mA.

10.1.2 Voltage regulator characteristics

Table 8.

Voltage regulator characteristics

[1]

I

I

Symbol

V

BUS

V

DDD

BUS inrush(lim)

V

V th(rst)reg th(rst)reg(hys)

Parameter

bus supply voltage digital supply voltage

Conditions

USB mode; V

SS

= 0 V after inrush current limitation (USB mode); from I

VDDD

= 0 mA to

I

VDDD

= 150 mA

USB mode; measure on V

BUS at power-up (curlimofff = 0) bus supply current inrush current limit regulator reset threshold voltage regulator reset regulator reset threshold voltage hysteresis

V

DDD

decoupling capacitor

[1] The internal regulator is only enabled when the USB interface is selected by I0 and I1.


4.02 5 5.25 V

2.95 3.3

3.6

V

-

-

-

150 mA

100 mA

1.90 2.15 2.40 V

35 60 85 mV

8 10 -

F

10.2 Antenna presence self test thresholds

The values in

Table 9 are guaranteed by design. Only functional is done in production for

cases andet_ithl[1:0] = 10b and for andet_ithh[2:0] = 011b.

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Table 9.

Antenna presence detection

Parameter Conditions Min

I

VDDD

lower current threshold for antenna presence detection

andet_ithl[1:0] 00b -

01b

10b -

-

11b -

I

VDDD

upper current threshold for antenna presence detection

andet_ithh[2:0] 000b -

001b -

010b

011b

100b

101b

110b

111b

-

-

-

-

-

-

Typ

5

15

25

35

105

120

135

150

45

60

75

90

-

-

-

-

-

-

-

-

-

-

-

-

Max Unit

mA mA mA mA mA mA mA mA mA mA mA mA

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10.3 Typical 27.12 MHz Crystal requirements

Table 10.

Crystal requirements

f


xtal

ESR crystal frequency equivalent series resistance

C

L

P xtal load capacitance crystal power dissipation

Conditions

-

-

Min Typ

27.107

27.12

100

-

-

10

Max Unit

-

-

27.133

MHz

100

 pF

W

10.4 Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT)

Table 11.

Pin characteristics for 27.12 MHz XTAL Oscillator (OSCIN, OSCOUT)

Symbol

I

LI

V

IH

V

IL

V

OH

V

OL f clk



 n(th) f

n(th)

Parameter

input leakage current

HIGH-level input voltage

LOW-level input voltage

HIGH-level output voltage

LOW-level output voltage clock frequency duty cycle phase noise threshold phase noise threshold frequency

Conditions

RSTPD_N = 0 V

 n(th)

=

140dBc/Hz;

20dB/decade slope

[1]

-

[1]

-

-

Min

1

0.7

 V

DDA

0

-

0.05 %

40

OSCIN

V i

C i input voltage input capacitance

DC

V

DDA

= 2.8 V; V i

V i

(AC) = 1 V p-p

(DC) = 0.65 V;

-

-

OSCOUT

C i input capacitance -

-

-

-

Typ Max

+1

-

-

V

DDA

0.3

 V

DDA

1.1

0.2

-

-

27.12

+0.05 %

50 60

140

50

0.65

2

2

-

-

-

V pF pF

[1]

 n(th)

and f

n(th)

define the mask for maximum acceptable phase noise of the clock signal at the OSCIN, OSCOUT inputs. See Figure 3

“27.12 MHz input clock phase noise spectrum mask” .

V

V

Unit

mA

V

V

MHz

% dBc/Hz kHz phase noise

(dBc/Hz)

-20 dB/decade acceptable phase noise area

φ n(th) f

φn(th) frequency (Hz)

001aao393

Fig 3.

27.12 MHz input clock phase noise spectrum mask

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10.5 RSTPD_N input pin characteristics

Table 12.

RSTPD_N input pin characteristics


V

IH

V

IL



Conditions

I

I

IH

IL

C i

HIGH-level input current

V

I

= V

DD(PVDD)

LOW-level input current V

I

= 0 V input capacitance

0

1

-

1

Min Typ Max

V

DD(PVDD)

0.4 -

V

DD(PVDD)

Unit

V

0.4

-

-

2.5

-

1

1

V

A

A pF

10.6 Input pin characteristics for I0, I1 and TESTEN

Table 13.

Input pin characteristics for I0, I1 and TESTEN

I


V

V

IL

I

IH

IL

C i

IH



Conditions

HIGH-level input current I0 and I1;

V

I

= V

DDD


I

= 0 V input capacitance

[1]

Min

0.7

 V

DDD

[2]

[3]

0

1

-

1

-

-

-

Typ Max

2.5

-

V

0.3

 V

DDD

1

1

DDD

Unit

V

V

A

A pF

[1] To minimize power consumption when in soft power-down mode, the limit is V

DDD

 0.4 V.

[2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V.

[3] TESTEN should never be set to high level in the application. It is used for production test purpose only. It is recommended to connect TESTEN to ground although there is a pull-down included.

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10.7 RSTOUT_N output pin characteristics

Table 14.

RSTOUT_N output pin characteristics

I

I


V

V

OH

OL

OH

OL


LOW-level output voltage

HIGH-level output current

LOW-level output current

Conditions

V

DD(PVDD)

= 3 V; I

OH

=

4 mA

V

DD(PVDD)

= 1.8 V; I

OH

=

2 mA

V

DD(PVDD)

= 3 V; I

OL

= 4 mA

V

DD(PVDD)

= 1.8 V; I

OL

= 2 mA

V

DD(PVDD)

= 3 V; V

OH

0.8

 V

DD(PVDD)

=

V

DD(PVDD)

= 1.8 V; V

OH

0.7

 V

DD(PVDD)

=

V

DD(PVDD)

= 3 V; V

OL

0.2

 V

DD(PVDD)

=

V

DD(PVDD)

= 1.8 V; V

OL

0.3

 V

DD(PVDD)

=

C

L t r load capacitance rise time t f fall time

V

DD(PVDD)

= 3 V;

V

OH

= 0.8

 V

DD(PVDD)

; C

L

= 30 pF

V

DDP

= 1.8 V;

V

OH

= 0.7

 V

DD(PVDD)

; C

L

= 30 pF

V

DD(PVDD)

= 3 V;

V

OL

= 0.2

 V

DD(PVDD)

; C

L

= 30 pF

V

DD(PVDD)

= 1.8 V;

V

OL

= 0.3

 V

DD(PVDD)

; C

L

= 30 pF

[1]

Min

0.7

 V

DD(PVDD)

0.7

 V

DD(PVDD)

0

[1]

[2]

0

4

-

-

-

-

-

Typ Max

-

V

DD(PVDD)

V

DD(PVDD)

0.3

 V

DD(PVDD)

0.3

 V

DD(PVDD)

V

V

Unit

V

V mA

[2]

4

-

-

-

-

2

2

-

-

-

-

-

-

-

-

-

-

-

30

13.5

10.8

13.5

10.8

mA mA mA pF ns ns ns ns

[1] Data at V

DD(PVDD)

= 1.8V are only given from characterization results.

[2] I

OH

and I

OL

give the output drive capability from which the rise and fall times may be calculated as a function of the load capacitance.

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10.8 Input/output characteristics for pin P70_IRQ

Table 15.

Input/output pin characteristics for pin P70_IRQ

t

I

LI

C i

C

L t r

I

I

I

I


V

IH


V

IL

V

OH


V

OL

IH

IL

OH

OL

Conditions

HIGH-level output voltage push-pull mode;

V

DD(PVDD)

= 3 V; I

OH

=

4 mA push-pull mode;

V

DD(PVDD)

= 1.8 V; I

OH

= -2 mA

LOW-level output voltage push-pull mode;

V

DD(PVDD)

= 3 V; I

OL

= 4 mA push-pull mode;

V

DD(PVDD)

= 1.8 V; I

OL

= 2 mA

HIGH-level input current input mode; V

I

= V

DDD

LOW-level input current input mode; V

I

= 0 V


V

DD(PVDD)

V

OH

= 3 V;

= 0.8

 V

DD(PVDD)

LOW-level output current input leakage current

V

V

DD(PVDD)

OL

= 3 V;

= 0.2

 V

DD(PVDD)

RSTPD_N = 0.4 V input capacitance f load capacitance rise time fall time

V

DD(PVDD)

= 3 V;

V

OH

= 0.8

 V

DD(PVDD)

;

C

L

= 30 pF

V

DD(PVDD)

= 1.8 V;

V

OH

= 0.7

 V

DD(PVDD)

;

C

L

= 30 pF

V

DD(PVDD)

= 3 V;

V

OL

= 0.2

 V

DD(PVDD)

;

C

L

= 30 pF

V

DD(PVDD)

= 1.8 V;

V

OL

= 0.3

 V

DD(PVDD)

;

C

L

= 30 pF

[1]

[2]

[3]

[3]

[5]

[5]

-

-

-

-

-

-

Min

0.7

 V

DD(PVDD)

0

0.7

 V

DD(PVDD)

0.7

 V

DD(PVDD)

0

0

1

1

4

4

1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Typ

2.5

-

-

Max

V

DD(PVDD)

0.3

V

V

0.3

0.3

1

1

1

30

13.5

10.8

13.5

10.8

 V

 V

 V

DD(PVDD)

DD(PVDD)

DD(PVDD)

DD(PVDD)

DD(PVDD)

Unit

V

V

V

V

V

V

A

A mA mA

A pF pF ns ns ns ns


DD(PVDD)

 0.4 V.


[3] Data at V

DD(PVDD)

= 1.8 V are only given from characterization results.

[4] The I

OH

and I

OL

give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance.

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10.9 Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX,

P32_INT0, P33_INT1

Table 16.

Input/output pin characteristics for P30 / UART_RX, P31 / UART_TX, P32_INT0, P33_INT1

I

I

I

I t


V

V

IL

V

OH

V

I

LI

C i

C

L t r f

IH

IL

IH

OL

OH

OL



HIGH-level output voltage push-pull mode;

I

V

DD(PVDD)

OH

= 3 V;

=

4 mA

I

V

DD(PVDD)

= 1.8 V;

OH

=

2 mA

LOW-level output voltage push-pull mode;

V

DD(PVDD)

I

OL

= 4 mA

= 3 V;

V

DD(PVDD)

I

OL

= 2 mA

= 1.8 V;

HIGH-level input current input mode;

V

I

= V

DD(PVDD)


I

= 0 V


V

DD(PVDD)

V

OH

= 3 V;

= 0.8

 V

DD(PVDD)

LOW-level output current V

DD(PVDD)

= 3 V;

V

OL

= 0.2

 V

DD(PVDD) input leakage current RSTPD_N = 0.4 V input capacitance load capacitance rise time fall time

Conditions

V

DD(PVDD)

= 3 V;

V

OH

= 0.8

 V

DD(PVDD)

;

C

L

= 30 pF

V

DD(PVDD)

= 1.8 V;

V

OH

= 0.7

 V

DD(PVDD)

;

C

L

= 30 pF

V

DD(PVDD)

= 3 V;

V

OL

= 0.2

 V

DD(PVDD)

;

C

L

= 30 pF

V

DD(PVDD)

= 1.8 V;

V

OL

= 0.3

 V

DD(PVDD)

;

C

L

= 30 pF

[1]

Min

0.7

 V

DD(PVDD)

[2]

0

V

DD(PVDD)

0.4

[3]

[3]

[4]

[4]

-

-

-

-

-

-

V

DD(PVDD)

0.4

0

0

1

1

4

4

1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Typ

2.5

-

-

-

Max

V

DD(PVDD)

0.3

 V

DD(PVDD)

V

DD(PVDD)

V

0.4

0.4

1

1

1

DD(PVDD)

30

13.5

10.8

13.5

10.8

Unit

V

V

V

V

V

V

A

A mA mA



DD(PVDD)

 0.4 V.

[2] To minimize power consumption when in soft power-down mode, the limit is 0.4 V

[3] Data at V

DD(PVDD)

= 1.8 V are only given from characterization results.

[4] The I

OH

and I

OL


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10.10 Input/output pin characteristics for P35

Table 17.

Input/output pin characteristics for P35

t

I

LI

C i

C

L t r

I

V

OL

I

IH

I

IL

I

OH


V

IH

V

IL

V

OH




OL


Conditions

V

LOW-level output voltage V

V


I

I

DDD

DDD

= V

= 3 V; I

DDD

= 0 V

OH

= 3 V; I

OL

=

4 mA

= 4 mA

HIGH-level output current V

DDD

= 3 V;

V

OH

= 0.8

 V

DD(PVDD)


DDD

V

OL

= 3 V;

= 0.2

 V

DD(PVDD) input leakage current input capacitance

RSTPD_N = 0.4 V f load capacitance rise time fall time

V

DDD

= 3 V; V

C

L

= 30 pF

OH

= 0.8

 V

DDD

;

V

DDD

C

L

= 1.8 V; V

= 30 pF

OH

= 0.7

 V

DDD

;

V

DDD

= 3 V; V

C

L

= 30 pF

OL

= 0.2

 V

DDD

;

V

DDD

= 1.8 V; V

C

L

= 30 pF

OL

= 0.3

 V

DDD

;

[1]

[2]

[3]

[3]

-

-

-

-

-

-

Min

0.7

 V

DDD

0

V

DDD

 0.4

0

1

1

4

4

1

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Typ Max

2.5

-

-

-

V

1

1

1

DDD

0.3

 V

DDD

V

DDD

0.4

30

13.5

10.8

13.5

10.8

Unit

V

V

V

V

A

A mA mA



DDD

 0.4 V.


[3] The I

OH

and I

OL


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10.11 Input/output pin characteristics for DP and DM

Table 18.

Input/output pin characteristics for DP and DM for USB interface

I

I


V

IH

V

IL

V

OH




V

OL

OH

OL

I

IH

I

IL

I

LI

C i

Z

INP





LOW-level input current input leakage current input capacitance input impedance exclusive of pull-up/pull-down (for low-/full speed)

Conditions

V

DD(PVDD)

= 3.3 V

V

DD(PVDD)

= 3.3 V;

R

PD

= 1.5

 to V

SS

V

DD(PVDD)

R

PD

= 3.3 V;

= 1.5

 to V

DD(PVDD)

V

DD(PVDD)

= 3.3 V;

V

OH

= 0.8

 V

DD(PVDD)

V

DD(PVDD)

= 1.8 V;

V

OH

= 0.7

 V

DD(PVDD)

V

DD(PVDD)

V

OL

= 3.3 V;

= 0.2

 V

DD(PVDD)

V

DD(PVDD)

= 1.8 V;

V

OL

= 0.3

 V

DD(PVDD)

V

I

= V

DD(PVDD)

V

I

= 0 V

RSTPD_N = 0 V

[1]

[2]

[2]

-

Min

2

0

2.8

0

4

2

4

2

-

1

-

300

28 Z

DRV driver output impedance for driver which is not high-speed capable t

FDRATE full-speed data rate for devices which are not high-speed capable t

DJ1 source jitter total (including frequency tolerance) to next transition t t

DJ2

FDEOP source jitter total (including frequency tolerance) for paired transitions source jitter for differential transition to SE0 transition t

JR1 t

JR2 receiver jitter to next transition receiver jitter for paired transitions t

FEOPT source SE0 interval of EOP t

FEOPR receiver SE0 interval of EOP t

FST width of SE0 interval during differential transition

-

11.97

3.5

4

2

18.5

9

160

82

-

-

-

-

-

-

-

-

-

-

-

-

-

Typ

-

-

-

-

2.5

-

-

-

-

-

-

-

-

-

Max

3.6

0.8

V

DD(PVDD)

V

V

Unit

V

0.3

1

1

+1

-

3.5

44

12.03

+3.5

+4

+5

+18.5

+9

175

-

14

V mA mA mA mA ns ns ns ns ns

A

A

A pF k





Mb/s ns ns ns

[1] The value does not guarantee the power-down consumptions. To reach the specified power-down consumptions, the limit is 0.4 V.

[2] The I

OH

and I

OL


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Table 19.

USB DP/DM differential receiver input levels


V

DI

-

V

CM differential input sensitivity voltage differential common mode voltage range

-

Min

0.2

0.8

Table 20.

USB DP/DM driver characteristics

t t t


r rise time f

FRFM fall time differential rise and fall time matching

Conditions

C

L

= 50 pF;

10 % to 90 % of (V

OH

- V

OL

)

C

L

= 50 pF;

10 % to 90 % of (V

OH

- V

OL

)

(t

FR

/t

FF

); excluding the first transition from Idle state

V

CRS output signal crossover voltage excluding the first transition from Idle state

Min

4

4

90

1.3

level 1

-

-

-

-

-

Typ

-

Typ

-

Max

2.5

Max

20

20

111.1

2.0

+400 mV differential

Unit

V

V

Unit

ns ns

%

V point 3 point 4 point 1 point 2

0 V differential point 5 level 2

0 % unit interval

Fig 4.

Transmit waveform at DP/DM

point 6

100 %

001aan914

-400 mV differential

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Table 21.

Input Pin characteristics for DP for HSU interface


[1]

V

IH

V

IL

I

IH

I

IL

I

LI

C i




LOW-level input current input leakage current input capacitance

V i

V i

= V

DD(PVDD)

= 0 V

RSTPD_N = 0 V

[2]

-

-

-

1

Min

0.7

 V

DD(PVDD)

0

2.5

-

-

-

-

Typ Max

V

DD(PVDD)

0.3

 V

DD(PVDD)

1

1

1

3.5

Unit

V

V mA mA mA pF

[1] The value does not guarantee the power-down consumptions. To reach the specified power-down consumptions, the limit is

V

DD(PVDD)

 0.4 V.

[2] The value does not guarantee the power-down consumptions. To reach the specified power-down consumptions, the limit is 0.4 V.

Table 22.

Output Pin characteristics for DM for HSU interface

t

I

LI

C

L t r

I

I

Symbol

V

V

OH

OL

OH

Parameter




Conditions

V

DD(PVDD)

= 3 V; I

OH

=

4 mA

V

DD(PVDD)

= 1.8 V; I

OH

=

2 mA

V

DD(PVDD)

= 3 V; I

OL

=

4 mA

V

DD(PVDD)

= 1.8 V; I

OL

=

2 mA

V

DD(PVDD)

V

OH

= 3 V;

= 0.8

 V

DD(PVDD)

OL


V

DD(PVDD)

= 1.8 V;

V

OH

= 0.7

 V

DD(PVDD)

V

DD(PVDD)

= 3.3 V;

V

OL

= 0.2

 V

DD(PVDD)

V

DD(PVDD)

= 1.8 V;

V

OL

= 0.3

 V

DD(PVDD) input leakage current RSTPD_N = 0 V load capacitance rise time f fall time

V

DDP

= 3 V;

V

OH

= 0.8

 V

DD(PVDD)

;

C

L

= 30 pF

V

DD(PVDD)

= 1.8 V;

V

OH

= 0.7

 V

DD(PVDD)

;

C

L

= 30 pF

V

DD(PVDD)

= 3 V;

V

OL

= 0.2

 V

DD(PVDD)

;

C

L

= 30 pF

V

DDP

= 1.8 V;

V

OL

= 0.3

 V

DD(PVDD)

;

C

L

= 30 pF

-

-

-

2

[1]

4

2

[1]

Min Typ

V

DD(PVDD)

 0.4 -

V

DD(PVDD)

 0.4 -

0 -

0

4

-

-

-

-

1

-

-

-

-

-

-

-

-

-

-

-

-

-

Max

V

DD(PVDD)

V

DD(PVDD)

0.4

0.4

1

30

13.5

10.8

13.5

10.8

Unit

V

V

V

V mA mA mA mA mA pF ns ns ns ns

[1] The I

OH

and I

OL

give the output driving capability and allow to calculate directly the rise and fall time as function of the load capacitance

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10.12 Input pin characteristics for SCL

Table 23.

Input/output drain output pin characteristics for SCL I

2

C interface


V

IH

V

IL

V

OL

C

L t r t f

I

IH

I

IL

I

LI

C i





LOW-level input current input leakage current input capacitance load capacitance rise time of both SDA and SCL signals fall time of both SDA and SCL signals

Conditions

V

DDD

= 3 V;

I

OL

=

4 mA

V

I

= V

DDD

V

I

= 0 V

RSTPD_N = 0.4 V

[1]

[2]

[3]

[3]

-

-

Min

0.7

 V

DD(PVDD)

0

0

1

1

1

20

20 -

-

-

-

-

-

-

-

-

Typ Max

V

DDD

0.3

 V

DDD

0.3

2.5

1

1

1

30

300

300

A

A

A pF pF ns ns

V

V

Unit

V


DDD

 0.4 V.


[3] The PR533 has a slope control according to the I

2

C-bus specification for the Fast mode. The slope control is always present and not dependent of the I

2

C-bus speed.

10.13 Input/output pin characteristics for SDA

Table 24.

Input/output drain output pin characteristics for SDA I

2

C interface


V

V

IH

IL

V

OL t r t f

I

IH

I

IL

I

LI

C i

C

L





LOW-level input current input leakage current input capacitance load capacitance rise time of both SDA and SCL signals fall time of both SDA and SCL signals

Conditions

I

V

DDD

= 3 V;

OL

=

4 mA

V

I

= V

DDD

V

I

= 0 V

RSTPD_N = 0.4 V

[1]

[2]

[3]

[3]

-

-

Min

0.7

 V

DD(PVDD)

0

0

1

1

1

20

20

-

-

-

-

-

-

-

-

-

Typ Max

V

DDD

0.3

 V

DDD

0.3

2.5

1

1

1

30

300

300

A

A

A pF pF ns ns

Unit

V

V

V


DDD

 0.4 V.



2


2

C-bus speed.

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10.14 Output pin characteristics for DELATT

Table 25.

Output pin characteristics for DELATT


V

V

IL

I

IH

I

IL

I

LI

C i

OH





Conditions

input mode; V

I

= V

DD(SVDD) input mode; V

I

= 0 V

RSTPD_N = 0.4 V

[1]

-

Min

0.7

 V

DD(SVDD)

0

1

1

1


DD(PVDD)

 0.4 V.

-

-

-

Typ

-

-

2.5

10.15 Input pin characteristics for SIGIN

Table 26.

Input/output pin characteristics for SIGIN


V

V

IL

I

IH

I

IL

I

LI

C i

IH





Conditions

V

V

I

I

= V

DD(SVDD)

= 0 V

RSTPD_N = 0.4 V

[1]

[2]

-

Min

0.7

 V

DD(SVDD)

0

1

1

1


DD(SVDD)

 0.4 V.


-

-

-

Typ

-

-

2.5

-

1

1

Max

V

DD(SVDD)

0.3

 V

DD(PVDD)

1

Unit

V

V

A

A

A pF

-

+1

+1

Max

V

DD(SVDD)

0.3

 V

DD(SVDD)

+1

Unit

V

V

A

A

A pF

10.16 Output pin characteristics for SIGOUT

Table 27.

Output pin characteristics for SIGOUT

t

I

I

I


V

V

OH

OL

OH

OL

Conditions

HIGH-level output voltage V

DDD

 0.1 < V

I

OH

=

4 mA

DD(SVDD)

< V

DDD


DDD

 0.1 < V

I

OL

= +4 mA

DD(SVDD)

< V

DDD


DDD

 0.1 < V

I

OH

=

4 mA

DD(SVDD)

< V

DDD


DDD

 0.1 < V

I

OL

= +4 mA

DD(SVDD)

< V

DDD

LI

C i input leakage current input capacitance

RSTPD_N = 0.4 V

C

L t r load capacitance rise time f fall time

V

DD(SVDD)

= 3 V;

V

OH

= 0.8

 V

DD(SVDD)

; C out

= 30 pF

V

DD(SVDD)

= 3 V;

V

OL

= 0.2

 V

DD(SVDD)

; C out

= 30 pF

-

Min

V

DD(SVDD)

 0.4 -

Typ Max

V

DD(SVDD)

Unit

V

0

0.4

4

-

-

-

1

-

-

-

-

-

2.5

-

-

-

-

0.4

+1

30

9

9

V mA mA

A pF pF ns ns

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10.17 Input/output pin characteristics for P34

Table 28.

Input/output pin characteristics for P34

t

I

LI

C i

C

L t r

I

I


V

IH

V

IL

V

OH



V

OL

IH

IL

V

V

OH

OL

Conditions


LOW-level output voltage push-pull;

I

V

DDD

 0.1 < V

DD(SVDD)

OH

=

4 mA

< V

DDD push-pull;

V

DDD

 0.1 < V

DD(SVDD)

I

OH

= +4 mA

< V

DDD

HIGH-level input current input mode; V

I

= V

DD(SVDD)


I

= 0 V

HIGH-level output voltage I

V

DDD

OH

 0.1 < V

=

4 mA

DD(SVDD)

< V

DDD


V

DDD

 0.1 < V

I

OL

= +4 mA

DD(SVDD)

< V

DDD input leakage current RSTPD_N = 0.4 V input capacitance load capacitance rise time f fall time

V

DDD

= 0.1 < V

DDD

V

OH

= 0.8

 V

DD(SVDD)

;

C out

= 30 pF

V

DDD

= 0.1 < V

DDD

V

OL

= 0.2

 V

DD(SVDD)

;

C out

= 30 pF

[1]

Min

0.7

 V

DD(SVDD)

[2]

[3]

[3]

-

-

-

-

0

V

DD(SVDD)

 0.4 -

0

1

1

0.4

4

1

-

-

-

-

-

-

-

-

Typ

2.5

13.5

-

-

-

Max

V

DD(SVDD)

0.3

 V

DD(SVDD)

V

DD(SVDD)

0.4

+1

+1

+1

13.5

-

30

Unit

V

V

V

V

A

A

V

V

A pF pF ns ns


DD(SVDD)

 0.4 V.


[3] I

OH

and I

OL

specify the output drive capability from which the rise and fall times may be calculated as a function of the load capacitance.

10.18 Output pin characteristics for LOADMOD

Table 29.

Output pin characteristics for LOADMOD


V

OH t t

V

C r f

OL

L


DDD

= 3 V;

I

OH

=

4 mA


DDD

= 3 V;

I

OL

= 4 mA load capacitance rise time fall time

V

DDD

= 3 V;

V

OH

= 0.8

 V

DDD

;

C out

= 10 pF

V

DDD

= 3 V;

V

OL

 = 0.2  V

DDD

;

C out

= 10 pF

-

-

-


V

DDD

 0.4 -

V

DDD

V

0

-

-

-

0.4

10

4.5

4.5

V pF ns ns

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10.19 Input pin characteristics for RX

V in, RX

AVDD +1 V

Miller coded signals

V

RX, IV, mil

- V mod m

RXmil

=

V

RX, IV, mil

+ V mod

V

RX, IV, mil

V mod

VMID

13.56 MHz carrier

0 V

V in, RX

AVDD +1 V

Manchester coded signals

V

RXMod, Man

V

RX, IV, Man

V mod

VMID

13.56 MHz carrier

0 V

Fig 5.

RX input parameters

Table 30.

Input pin characteristics for RX

Symbol

V i

Parameter

input voltage

Conditions

dynamic; signal frequency at

13.56 MHz

C i

R s input capacitance series resistance RX input;

V

DDA

= 3 V; receiver active;

V

RX(p-p)

= 1 V;

1.5 V DC offset

Minimum dynamic input voltage

6

315

aaa-002342

Min

0.7

Typ Max Unit

V

DDA

+1 V

10 14

350 385 pF



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Table 30.

Input pin characteristics for RX

…continued


V

RX(p-p) peak-to-peak receiver voltage

Miller coded;

106 kbit/s

Manchester coded; 212 kbit/s and 424 kbit/s

Maximum dynamic input voltage

V

RX(p-p) peak-to-peak receiver voltage

Miller coded;

106 kbit/s

Manchester coded;

212 and 424 kbit/s

Minimum modulation voltage

V mod modulation voltage RxGain = 6 and 7

[1]

-

RxGain = 4 and 5

[1]

-

RxGain = 0 to 3

[1]

-

-

-

Min

V

DDA

V

DDA

Minimum modulation index

m modulation index

-

Miller coded;

106 kbit/s

V

RX(p-p)

= 1.5 V;

SensMiller = 3

-

-

-

-

-

Typ Max

150 500

100 200

33 -

-

-

6

18

120

[1] The minimum modulation voltage is valid for all modulation schemes except Miller coded signals.

Unit

mV mV

V

V mV mV mV

%

10.20 Output pin characteristics for AUX1/AUX2

Table 31.

Output pin characteristics for AUX1/AUX2


V

OH

I

I

I

V

OL

OH

OL

LI

C i

C

L


DDD

= 3 V;

I

OH

=

4 mA


DDD

= 3 V;

I

OL

= 4 mA


DDD

= 3 V; V

OH

=

V

DDD

0.3


DDD

= 3 V; V

OL

=

V

DDD

-0.3

input leakage current RSTPD_N = 0 V input capacitance load capacitance

Min Typ Max

V

DDD

 0.4 -

V

DDD

V

SSD

4

4

-

-

1

-

-

-

-

-

-

-

2.5

-

+1

15

Unit

V

V

SSD

+0.4

V mA mA

A pF pF

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10.21 Output pin characteristics for TX1/TX2

Table 32.

Output pin characteristics for TX1/TX2


V

OH

V

OL


Conditions

V

DD(TVDD)

= 3 V;

I

O

= 32 mA; CWGsN = Fh

V

DD(TVDD)

= 3 V;

I

O

= 80 mA; CWGsN = Fh


DD(TVDD)

= 2.5 V;

I

O

= 32 mA; CWGsN = Fh

V

DD(TVDD)

= 2.5 V;

I

O

= 80 mA; CWGsN = Fh

Table 33.

Output resistance for TX1/TX2


R

OH

HIGH-level output resistance

Conditions1

V

DD(TVDD)

V

DD(TVDD)

= 3 V; V

O

 100 mV

=

R

OL

LOW-level output resistance

10h

20h

40h

80h

F0h

08h

10h

20h

3Fh

CWGsP

01h

02h

04h

-

-

-

-


150 mV

-

-

400 mV

240 mV

640 mV


133 180 251



67

34

17

8.5

90

46

23

12

125



62



31



15.5



4.7

2.3

34

17

8.5

4.7

2.3

6

3

46

23

12

6

3

7.8

4.4

62

31

15.5



7.8



4.4











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10.22 System reset timing

V th(rst)reg +

V th(rst)reg(hys)

V

DD(PVDD)

PR533


V th(rst)reg(hys)

RSTPD_N t rst t

POR t w(rst)

RSTOUT_N

001aao394

Fig 6.

System reset overview

Table 34.

Reset duration time


t

POR t rst t w(rst) power-on reset time reset time reset pulse width

Conditions

hard power-down time; user dependent reset time when RSTPD_N is released

[1] Dependent on the 27.12 MHz crystal oscillator startup time.

[2] If the t rst

pulse is shorter than 20 ns, the device may be only partially reset.

Min

[1]

0.1

[2]

20

[1]

0.1

Typ

-

0.4

0.4

Max

-

2

2

Unit

ms ns ms

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10.23 Timing for the I

2

C-bus interface

SDA t f t

LOW t

SU;DAT t f t

HD;STA t

SP t r t

BUF

SCL t r t

HD;STA t

HD;DAT t

HIGH t

SU;STO

S Sr t

SU;STA

P S

001aaj635

Fig 7.

I

2

C-bus parameters

Table 35.

I

2

C-bus timing specification

t t f


SCL t

HD;STA

SCL clock frequency hold time (repeated) START condition

Conditions

after this period, the first clock pulse is generated t

SU;STA set-up time for a repeated START condition set-up time for STOP condition t

SU;STO t

LOW t

HIGH t

HD;DAT t

SU;DAT t r

LOW period of the SCL clock

HIGH period of the SCL clock data hold time data set-up time rise time of both SDA and SCL signals

P50_SCL

P50_SCL

P50_SCL t f

BUF stretch fall time of both SDA and SCL signals bus free time between a STOP and START condition stretch time

P50_SCL

[1]

[2]

-

Min

0

600

600

600

1300 -

600 -

0

100 -

-

[1]

20 -

20

1.3

-

-

-

-

-

-

-

Typ

-

-

-

-

-

-

Max

400

900

-

300

300

1

Unit

kHz ns ns ns ns ns ns ns ns ns ms ms t h hold time stretching time on

P50_SCL when woken-up on its own address internal for SDA internal for SDA in

SPD mode

[3]

330 -

-

590

270 ns ns


2


2

C-bus speed.

[2] 27.12 MHz quartz starts in less than 800

s. For example, quartz like TAS-3225A, TAS-7 or KSS2F with appropriate layout.

[3] The PR533 has an internal hold time of around 270 ns for the SDA signal to bridge the undefined region of the falling edge of P50_SCL.

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10.24 Temperature sensor

Table 36.

Temperature sensor characteristics

Symbol

T th(act)otp

Parameter

overtemperature protection activation threshold temperature

Conditions

CIU

[1]


100 125 140

C

[1] The temperature sensor embedded in the PR533 is not intended to monitor the temperature. Its purpose is to prevent destruction of the IC due to excessive heat. The external application should include circuitry to ensure that the ambient temperature does not exceed 85

C as specified in

Table 5 “Operating conditions” .

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11. Application information

interface supply l

2

C

MEMORY

RSDA RSCL

SDA

P50_SCL

SVDD

SIGOUT

SIGIN

P34

SECURE

CORE supply

VBUS

DVDD

PVDD

RTSPD_N host interface

P70_IRQ

DVSS

PR533

OSCIN

RX

R1

CRX

R2

VMID

TX1

L0

TVSS1

TVSS2

CVMID

C0

C1

C0

C1

TX2

L0

TVDD

AVDD

AVSS

OSCOUT

C2

RQ

C2

RQ antenna

27.12 MHz

aaa-000042

Fig 8.

Application diagram of PR533

12. Abbreviations

Table 37.

Abbreviations

Acronym

CDM

Description

Charge device Body Model

CRC

EEPROM

HBM

HPD

Cyclic Redundancy Check

Electrically Erasable Programmable Read-Only Memory

Human Body Model

Hard Power Down

MM

NFC

SPD

Machine Model

Near Field Communication

Soft Power Down mode

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13. Revision history

Table 38.

Revision history

Document ID Release date Data sheet status

PR533_SDS v.3.6

Modifications:

PR533_SDS v.3.5

[1]

Modifications:

20141027 Product short data sheet

•

Section 1.2 “Interfaces” : updated


•

Template updated.

•

Descriptive title updated.

•

Alternative descriptive title updated.

PR533_SDS v.3.3

Modifications:

PR533_SDS v.3.2

Modifications:


•

Section 14.4 “Licenses”

: updated


•

Section 4 “Ordering information” : updated

•

General update to comply full data sheet

PR5331C3HN_SDS v.3.0 20110803 Product short data sheet

[1] Revision 3.4 is not available.

-

-

-

-

-

Change notice

-

Supersedes

PR533_SDS v.3.5

PR533_SDS v.3.4

PR533_SDS v.3.2

PR5331C3HN_SDS v.3.0

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14. Legal information

Document status

[1][2]

Objective [short] data sheet

Product status

[3]

Development

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

Definition

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

.

14.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the

Product data sheet.

14.3 Disclaimers

Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

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Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.



Rev. 3.6 — 27 October 2014

206436 31 of 36


PR533


Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities.

Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.

14.4 Licenses

Purchase of NXP ICs with ISO/IEC 14443 type B functionality

This NXP Semiconductors IC is ISO/IEC 14443 Type B software enabled and is licensed under Innovatron’s

Contactless Card patents license for ISO/IEC 14443 B.

The license includes the right to use the IC in systems and/or end-user equipment.

RATP/Innovatron

Technology

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that complies with one of the Near

Field Communication (NFC) standards ISO/IEC 18092 and ISO/IEC 21481 does not convey an implied license under any patent right infringed by implementation of any of those standards.

14.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

MIFARE — is a trademark of NXP Semiconductors N.V.

I

2

C-bus — logo is a trademark of NXP Semiconductors N.V.

15. Contact information

For more information, please visit:

http://www.nxp.com

For sales office addresses, please send an email to:

[email protected]

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Notes

PR533


PR533_SDS


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Rev. 3.6 — 27 October 2014

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16. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .3

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .4

Table 3. PR533 pin description . . . . . . . . . . . . . . . . . . . .5

Table 4. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 5. Operating conditions . . . . . . . . . . . . . . . . . . . . .8

Table 6. Thermal characteristics . . . . . . . . . . . . . . . . . . .8

Table 7. Current consumption characteristics . . . . . . . . .9

Table 8. Voltage regulator characteristics

[1]

. . . . . . . . . . .9

Table 9. Antenna presence detection . . . . . . . . . . . . . . .10

Table 10. Crystal requirements. . . . . . . . . . . . . . . . . . . . . 11

Table 11. Pin characteristics for 27.12 MHz XTAL

Oscillator (OSCIN, OSCOUT). . . . . . . . . . . . . . 11

Table 12. RSTPD_N input pin characteristics . . . . . . . . .12

Table 13. Input pin characteristics for I0, I1 and

TESTEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 14. RSTOUT_N output pin characteristics . . . . . . .13

Table 15. Input/output pin characteristics for pin P70_IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Table 16. Input/output pin characteristics for P30 /

UART_RX, P31 / UART_TX, P32_INT0,

P33_INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 17. Input/output pin characteristics for P35 . . . . . .16

Table 18. Input/output pin characteristics for DP and DM for USB interface. . . . . . . . . . . . . . . . .17

Table 19. USB DP/DM differential receiver input levels . .18

Table 20. USB DP/DM driver characteristics . . . . . . . . . .18

Table 21. Input Pin characteristics for DP for HSU interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 22. Output Pin characteristics for DM for HSU interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Table 23. Input/output drain output pin characteristics for SCL I

2

C interface. . . . . . . . . . . . . . . . . . . . .20

Table 24. Input/output drain output pin characteristics for SDA I

2

C interface . . . . . . . . . . . . . . . . . . . .20

Table 25. Output pin characteristics for DELATT . . . . . . .21

Table 26. Input/output pin characteristics for SIGIN . . . . .21

Table 27. Output pin characteristics for SIGOUT . . . . . . .21

Table 28. Input/output pin characteristics for P34 . . . . . .22

Table 29. Output pin characteristics for LOADMOD . . . .22

Table 30. Input pin characteristics for RX . . . . . . . . . . . .23

Table 31. Output pin characteristics for AUX1/AUX2 . . .24

Table 32. Output pin characteristics for TX1/TX2. . . . . . .25

Table 33. Output resistance for TX1/TX2 . . . . . . . . . . . . .25

Table 34. Reset duration time . . . . . . . . . . . . . . . . . . . . .26

Table 35. I

2

C-bus timing specification . . . . . . . . . . . . . . .27

Table 36. Temperature sensor characteristics . . . . . . . . .28

Table 37. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .29

Table 38. Revision history . . . . . . . . . . . . . . . . . . . . . . . .30

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Rev. 3.6 — 27 October 2014

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17. Figures

Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

Fig 2. Pin configuration for HVQFN 40 (SOT618-1) . . . .5

Fig 3. 27.12 MHz input clock phase noise spectrum mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Fig 4. Transmit waveform at DP/DM . . . . . . . . . . . . . . .18

Fig 5. RX input parameters . . . . . . . . . . . . . . . . . . . . . .23

Fig 6. System reset overview. . . . . . . . . . . . . . . . . . . . .26

Fig 7. I

2

C-bus parameters . . . . . . . . . . . . . . . . . . . . . . .27

Fig 8. Application diagram of PR533 . . . . . . . . . . . . . . .29

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Rev. 3.6 — 27 October 2014

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PR533


18. Contents

3

4

5

6

6.1

6.2

7

1

1.1

1.2

1.3

1.4

2

General description . . . . . . . . . . . . . . . . . . . . . . 1

RF protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Standards compliancy. . . . . . . . . . . . . . . . . . . . 1

Supported operating systems . . . . . . . . . . . . . . 2

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 3

Ordering information . . . . . . . . . . . . . . . . . . . . . 4

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Pinning information . . . . . . . . . . . . . . . . . . . . . . 5

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7

8

9

Recommended operating conditions. . . . . . . . 8

Thermal characteristics . . . . . . . . . . . . . . . . . . 8

10 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8

10.1 Power management characteristics . . . . . . . . . 8

10.1.1 Current consumption characteristics . . . . . . . . 8

10.1.2 Voltage regulator characteristics. . . . . . . . . . . . 9

10.2 Antenna presence self test thresholds . . . . . . . 9

10.3

10.4

10.5

10.6

Typical 27.12 MHz Crystal requirements . . . . 11

Pin characteristics for 27.12 MHz XTAL

Oscillator (OSCIN, OSCOUT). . . . . . . . . . . . . 11

RSTPD_N input pin characteristics . . . . . . . . 12

10.7

10.8

10.9

Input pin characteristics for I0, I1 and

TESTEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

RSTOUT_N output pin characteristics . . . . . . 13

Input/output characteristics for pin P70_IRQ . 14

Input/output pin characteristics for P30 /

UART_RX, P31 / UART_TX, P32_INT0,

P33_INT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Input/output pin characteristics for P35 . . . . . 16 10.10

10.11

10.12

10.13

10.14

10.15

10.16

10.17

10.18

10.19

10.20

Input/output pin characteristics for DP and DM 17

Input pin characteristics for SCL. . . . . . . . . . . 20

Input/output pin characteristics for SDA . . . . . 20

Output pin characteristics for DELATT . . . . . . 21

Input pin characteristics for SIGIN . . . . . . . . . 21

Output pin characteristics for SIGOUT . . . . . . 21

Input/output pin characteristics for P34 . . . . . 22

Output pin characteristics for LOADMOD. . . . 22

10.21

10.22

10.23

10.24

Input pin characteristics for RX. . . . . . . . . . . . 23

Output pin characteristics for AUX1/AUX2 . . . 24

Output pin characteristics for TX1/TX2. . . . . . 25

System reset timing . . . . . . . . . . . . . . . . . . . . 26

Timing for the I

2

C-bus interface . . . . . . . . . . . 27

Temperature sensor . . . . . . . . . . . . . . . . . . . . 28

11

12

13

14

14.1

14.2

14.3

14.4

14.5

15

16

17

18

Application information . . . . . . . . . . . . . . . . . 29

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . 30

Legal information . . . . . . . . . . . . . . . . . . . . . . 31

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 31

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Contact information . . . . . . . . . . . . . . . . . . . . 32

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP Semiconductors N.V. 2014.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 27 October 2014

206436

PR533 1. General description USB NFC integrated reader solution

USB NFC integrated reader solution

2. Features and benefits

3. Quick reference data

8. Recommended operating conditions

10. Characteristics

11. Application information

12. Abbreviations

13. Revision history

14. Legal information

15. Contact information

Notes

16. Tables

17. Figures

18. Contents

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