LM6211 Low Noise, RRO Operational Amplifier with CMOS Input and... LM6211 FEATURES
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SNOSAH2C – FEBRUARY 2006 – REVISED MARCH 2013
LM6211 Low Noise, RRO Operational Amplifier with CMOS Input and 24V Operation
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1
FEATURES
2
(Typical 24V Supply Unless Otherwise Noted)
• Supply Voltage Range 5V to 24V
• Input Referred Voltage Noise 5.5 nV/
√
Hz
• Unity Gain Bandwidth 20 MHz
• 1/f Corner Frequency 400 Hz
• Slew Rate 5.6 V/ μ s
• Supply Current 1.05 mA
• Low Input Capacitance 5.5 pF
• Temperature Range -40°C to 125°C
• Total Harmonic Distortion 0.01% @ 1 kHz,
600 Ω
• Output Short Circuit Current 25 mA
APPLICATIONS
• PLL Loop Filters
• Low Noise Active Filters
• Strain Gauge Amplifiers
• Low Noise Microphone Amplifiers
DESCRIPTION
The LM6211 is a wide bandwidth, low noise op amp with a wide supply voltage range and a low input bias current. The LM6211 operates with a single supply voltage of 5V to 24V, is unity gain stable, has a groundsensing CMOS input stage, and offers rail-to-rail output swing.
The LM6211 is designed to provide optimal performance in high voltage, low noise systems. The LM6211 has a unity gain bandwidth of 20 MHz and an input referred voltage noise density of 5.5 nV/ √ Hz at 10 kHz. The
LM6211 achieves these specifications with a low supply current of only 1 mA. The LM6211 has a low input bias current of 2.3 pA, an output short circuit current of 25 mA and a slew rate of 5.6 V/us. The LM6211 also features a low common-mode input capacitance of 5.5 pF which makes it ideal for use in wide bandwidth and high gain circuits. The LM6211 is well suited for low noise applications that require an op amp with very low input bias currents and a large output voltage swing, like active loop-filters for wide-band PLLs. A low total harmonic distortion, 0.01% at 1 kHz with loads as high as 600 Ω , also makes the LM6211 ideal for high fidelity audio and microphone amplifiers.
The LM6211 is available in the small SOT-23 package, allowing the user to implement ultra-small and cost effective board layouts.
Typical Application
1000
V
S
= 5V, 24V
CHARGE
PUMP
OUTPUT
-
+
V
S_PLL
2
VCO
INPUT
100
10
1
1 10 100 1k
FREQUENCY (Hz)
10k 100k
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LM6211
SNOSAH2C – FEBRUARY 2006 – REVISED MARCH 2013
www.ti.com
Absolute Maximum Ratings
(1) (2)
ESD Tolerance
(3)
V
IN
Differential
Supply Voltage (V
S
= V
+
– V
−
)
Voltage at Input/Output pins
Storage Temperature Range
Junction Temperature
(4)
Soldering Information
Human Body Model
Machine Model
2000V
200V
±0.3V
25V
V
+
+0.3V, V
−
− 0.3V
− 65°C to +150°C
+150°C
235°C
260°C
Infrared or Convection (20 sec)
Wave Soldering Lead Temp. (10 sec)
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
(3) Human Body Model is 1.5 k Ω in series with 100 pF. Machine Model is 0 Ω in series with 200 pF.
(4) The maximum power dissipation is a function of T
J(MAX)
, θ
JA
, and T
A
. The maximum allowable power dissipation at any ambient temperature is P
D
= (T
J(MAX)
- T
A
)/ θ
JA
. All numbers apply for packages soldered directly onto a PC board.
Operating Ratings
(1)
Temperature Range
Supply Voltage (V
S
= V
+
– V
−
)
Package Thermal Resistance ( θ
JA
(2)
) 5-Pin SOT-23
− 40°C to +125°C
5V to 24V
178°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics Tables.
(2) The maximum power dissipation is a function of T
J(MAX)
, θ
JA
, and T
A
. The maximum allowable power dissipation at any ambient temperature is P
D
= (T
J(MAX)
- T
A
)/ θ
JA
. All numbers apply for packages soldered directly onto a PC board.
5V Electrical Characteristics
(1)
Unless otherwise specified, all limits are ensured for T
A the temperature extremes.
= 25°C, V
+
= 5V, V
−
= 0V, V
CM
= V
O
= V
+
/2. Boldface limits apply at
Symbol Parameter Conditions Min
(2)
Typ
(3)
Max
(2)
Units
V
OS
Input Offset Voltage V
CM
= 0.5V
0.1
±2.5
±2.8
mV
TC V
OS
I
B
I
OS
CMRR
PSRR
CMVR
Input Offset Average Drift
Input Bias Current
Input Offset Current
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Input Common-Mode Voltage
Range
V
CM
= 0.5V
(4)
V
CM
= 0.5V
(5) (6)
V
CM
= 0.5V
0 V ≤ V
CM
≤
0.4 V ≤ V
CM
3V
≤ 2.3 V
V
+
= 5V to 24V, V
CM
= 0.5V
V
+
= 4.5V to 25V, V
CM
= 0.5V
CMRR ≥ 65 dB
CMRR ≥ 60 dB
83
70
85
78
80
0
0
2
0.5
0.1
98
98
95
5
10
3.3
2.4
μ
V/C pA
nA
pA dB dB
V
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm at the time of characterization.
(4) Offset voltage average drift is determined by dividing the change in V
OS
(5) Positive current corresponds to current flowing into the device.
(6) Input bias current is ensured by design.
at the temperature extremes into the total temperature change.
2
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5V Electrical Characteristics
(continued)
Unless otherwise specified, all limits are ensured for T
A the temperature extremes.
= 25°C, V
+
= 5V, V
−
= 0V, V
CM
= V
O
= V
+
/2. Boldface limits apply at
Symbol
A
VOL
Parameter
Large Signal Voltage Gain
Conditions
V
O
= 0.35V to 4.65, R
L
= 2 k Ω to V
+
/2
Min
(2)
82
80
Typ
(3)
110
Max
(2)
Units
dB
V
O
= 0.25V to 4.75, R
L
= 10 k Ω to V
+
/2 85
82
110
V
O
Output Swing High R
L
= 2 k Ω to V
+
/2 50 150
165
Output Swing Low
R
L
= 10 k Ω to V
+
/2
R
L
= 2 k Ω to V
+
/2
20
39
85
90
150
170
mV from rail
R
L
= 10 k Ω to V
+
/2 13 85
90
I
OUT
Output Short Circuit Current Sourcing to V
+
V
ID
= 100 mV
/2
(7)
Sinking to V
+
/2
V
ID
= − 100 mV
(7)
13
10
20
10
16
30 mA
I
S
Supply Current 0.96
1.10
1.25
mA
SR Slew Rate A
V
= +1, 10% to 90%
(8)
5.5
V/
μ s
GBW Gain Bandwidth Product 17 MHz e n
Input-Referred Voltage Noise i n
THD
Input-Referred Current Noise
Total Harmonic Distortion f = 10 kHz f = 1 kHz f = 1 kHz
A
V
= 2, R
L
= 600
Ω to V
+
/2
5.5
6.0
0.01
0.01
nV/ √ Hz pA/ √ Hz
%
(7) The device is short circuit protected and can source or sink its limit currents continuously. However, care should be taken such that when the output is driving short circuit currents, the inputs do not see more than ±0.3V differential voltage.
(8) Slew rate is the average of the rising and falling slew rates.
24V Electrical Characteristics
(1)
Unless otherwise specified, all limits are ensured for T
A the temperature extremes.
= 25°C, V
+
= 24V, V
−
= 0V, V
CM
= V
O
= V
+
/2. Boldface limits apply at
Symbol Parameter Conditions Min
(2)
Typ
(3)
Max
(2)
Units
V
OS
Input Offset Voltage V
CM
= 0.5V
0.25
±2.7
±3.0
mV
TC V
OS
I
B
I
OS
CMRR
PSRR
CMVR
Input Offset Average Drift
Input Bias Current
Input Offset Current
Common Mode Rejection Ratio
Power Supply Rejection Ratio
Input Common-Mode Voltage
Range
V
CM
= 0.5V
(4)
V
CM
= 0.5V
(5) (6)
V
CM
= 0.5V
0 ≤ V
CM
≤
0.4
≤ V
CM
21V
≤ 20V
V
+
= 5V to 24V, V
CM
= 0.5V
V
+
= 4.5V to 25V, V
CM
= 0.5V
CMRR
≥
65 dB
CMRR ≥ 60 dB
80
0
0
85
70
85
78
±2
2
0.1
105
98
98
25
10
21.5
20.5
μ V/C pA
nA
pA dB dB
V
(1) Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
(3) Typical values represent the most likely parametric norm at the time of characterization.
(4) Offset voltage average drift is determined by dividing the change in V
(5) Positive current corresponds to current flowing into the device.
OS at the temperature extremes into the total temperature change.
(6) Input bias current is ensured by design.
Copyright © 2006–2013, Texas Instruments Incorporated
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24V Electrical Characteristics
(continued)
Unless otherwise specified, all limits are ensured for T
A the temperature extremes.
= 25°C, V
+
= 24V, V
−
= 0V, V
CM
= V
O
= V
+
/2. Boldface limits apply at
Symbol
A
VOL
Parameter
Large Signal Voltage Gain
Conditions
V
O
= 1.5V to 22.5V, R
L
= 2 k Ω to V
+
/2
Min
(2)
82
77
Typ
(3)
120
Max
(2)
Units
dB
V
O
= 1V to 23V, R
L
= 10 k Ω to V
+
/2 85
82
120
V
O
Output Swing High R
L
= 2 k Ω to V
+
/2 212 400
520
Output Swing Low
R
L
= 10 k Ω to V
+
/2
R
L
= 2 k Ω to V
+
/2
48
150
150
165
350
420
mV from rail
R
L
= 10 k Ω to V
+
/2 38 150
170
I
OUT
Output Short Circuit Current Sourcing to V
+
V
ID
= 100 mV
/2
(7)
Sinking to V
+
/2
V
ID
= − 100 mV
(7)
20
15
30
20
25
38 mA
I
S
Supply Current 1.05
1.25
1.40
mA
SR Slew Rate A
V
= +1, V
O
10% to 90%
= 18 V
PP
(8)
5.6
V/
μ s
GBW e n i n
THD
Gain Bandwidth Product
Input-Referred Voltage Noise
Input-Referred Current Noise
Total Harmonic Distortion f = 10 kHz f = 1 kHz f = 1 kHz
A
V
= 2, R
L
= 2 k Ω to V
+
/2
20
5.5
6.0
0.01
0.01
MHz nV/
√
Hz pA/ √ Hz
%
(7) The device is short circuit protected and can source or sink its limit currents continuously. However, care should be taken such that when the output is driving short circuit currents, the inputs do not see more than ±0.3V differential voltage.
(8) Slew rate is the average of the rising and falling slew rates.
Connection Diagram
V
OUT
1 5
V
+
V
-
2
+
-
IN+
3 4
IN-
Figure 1. 5-Pin SOT-23 - Top View
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Typical Performance Characteristics
Unless otherwise specified, T
A
= 25°C, V
S
= 24V, V
+
= V
S
, V
−
= 0 V, V
CM
= V
S
/2.
Supply Current vs.
Supply Voltage
V
OS vs.
Supply Voltage
0.8
1.4
1.3
1.2
1.1
1
0.9
0.8
125°C
25°C
-40°C
0.7
0.6
0.5
5 7 9 11 13 15 17 19 21 23
25
V
S
(V)
Figure 2.
0.6
0.4
0.2
0
-0.2
-0.4
125°C
25°C
-40°C
-0.6
5 7 9 11 13 15 17 19 21 23
25
V
S
(V)
Figure 3.
V
OS vs.
V
CM
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
0
V
S
= 5V
25°C
0.5
125°C
-40°C
1 1.5
2
V
CM
(V)
Figure 4.
2.5
3 3.5
1
V
S
= 5V
Input Bias Current vs.
V
CM
0.5
-40°C
0
-0.5
-1
-1.5
25°C
-2
0 0.5
1 1.5
2 2.5
3 3.5
4
V
CM
(V)
Figure 6.
V
OS vs.
V
CM
0.4
0.2
0
-0.2
1
0.8
0.6
125°C
25°C
-40°C
-0.4
V
S
= 24V
-0.6
0 2 4 6 8 10 12 14 16 18 20 22
V
CM
(V)
Figure 5.
Input Bias Current vs.
V
CM
2.5
2
1.5
1
0.5
0
-0.5
-1
V
S
= 5V
-1.5
125°C
-2
-2.5
0 0.5
1 1.5
2 2.5
3 3.5
4
V
CM
(V)
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified, T
A
= 25°C, V
S
Input Bias Current vs.
V
CM
= 24V, V
+
4
V
S
= 24V
= V
S
, V
−
= 0 V, V
CM
= V
S
/2.
2
Input Bias Current vs.
V
CM
V
S
= 24V
2
-40°C
0
0
125°C
-2 -2
25°C
-4
-4
-6
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-8
0 2 4 6 8 10 12 14 16 18 20 22
V
CM
(V)
Figure 8.
30
25
Sourcing Current vs.
Supply Voltage
25°C
-40°C
20
125°C
15
10
5
0
4 6 8 10 12 14 16 18 20 22 24
V
S
(V)
Figure 10.
Positive Output Swing vs.
Supply Voltage
70
R
L
= 10 k :
60
125°C
50
25°C
40
30
-40°C
20
10
0
4 6 8 10 12 14 16 18 20 22 24
V
S
(V)
Figure 12.
30
20
-6
0 2 4 6 8 10 12 14 16 18 20 22
V
CM
(V)
Figure 9.
Sinking Current vs.
Supply Voltage
50
45
40
35
30
25
20
15
-40°C
25°C
125°C
10
5
0
4 6 8 10 12 14 16 18 20 22 24
V
S
(V)
Figure 11.
Negative Output Swing vs.
Supply Voltage
60
R
L
= 10 k :
50
125°C
25°C
40
10
-40°C
0
4 6 8 10 12 14 16 18 20 22 24
V
S
(V)
Figure 13.
6
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Typical Performance Characteristics (continued)
Unless otherwise specified, T
A
= 25°C, V
S
= 24V, V
Positive Output Swing vs.
Supply Voltage
+
350
R
L
= 2 k :
= V
S
, V
−
= 0 V, V
CM
= V
S
/2.
250
300
200
250
125°C
25°C
200
150
Negative Output Swing vs.
Supply Voltage
R
L
= 2 k
:
125°C
25°C
150
100
100
50
-40°C
0
4 6 8 10 12 14 16 18 20 22 24
V
S
(V)
Figure 14.
50
-40°C
0
4 6 8 10 12 14 16 18 20 22 24
V
S
(V)
Figure 15.
20
18
16
14
12
10
8
6
4
2
0
0
V
S
= 5V
1
Sourcing Current vs.
Output Voltage
-40°C
25°C
2 3
V
OUT
(V)
Figure 16.
4
125°C
5
30
V
S
= 24V
Sourcing Current vs.
Output Voltage
-40°C
25
25°C
20
15
10
5
0
0 4
125°C
8 12
V
OUT
(V)
16
Figure 18.
20 24
25
20
15
10
5
0
0
40
35
V
S
= 5V
Sinking Current vs.
Output Voltage
-40°C
30
1
25°C
2 3
V
OUT
(V)
Figure 17.
4
125°C
5
Sinking Current vs.
Output Voltage
50
45
40
35
30
25
20
15
10
5
0
0
V
S
= 24V
4
-40°C
25°C
8 12
V
OUT
(V)
16
Figure 19.
125°C
20 24
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Typical Performance Characteristics (continued)
Unless otherwise specified, T
A
= 25°C, V
S
= 24V, V
+
= V
Open Loop Gain and Phase with Resistive Load
S
, V
−
180 180
= 0 V, V
CM
= V
S
/2.
Open Loop Gain and Phase with Capacitive Load
180 180
160
140
120
100
PHASE
R
L
= 2k : , 10 k : , 10M :
80
60
40
20
GAIN
0
-20
-40
100 1k
R
L
= 2k
:
, 10 k
:
, 10M
:
10k 100k
1M
FREQUENCY (Hz)
Figure 20.
10M
0
-20
-40
100M
80
60
40
20
160
140
120
100
160
140
PHASE
120
100
80
60
40
20
0
-20
-40
100
GAIN
C
1k
L
C
L
= 50 pF
C
L
= 20 pF
CL = 100 pF
= 20 pF, 50 pF, 100 pF
10M
0
-20
-40
100M
160
140
120
100
80
60
40
20
10k 100k
1M
FREQUENCY (Hz)
Figure 21.
1000
Input Referred Voltage Noise vs.
Frequency
V
S
= 5V, 24V
0.1
THD+N vs.
Frequency
100
10
1
1 10 100 1k
FREQUENCY (Hz)
10k
Figure 22.
100k
1
V
S
= 5V
THD+N vs.
Output Amplitude
0.1
0.01
R
L
= 600
:
0.001
0.0001
0.001
R
L
= 100 k :
0.01
0.1
1
OUTPUT AMPLITUDE (V)
Figure 24.
10
0.01
R
L
= 600
:
, V
S
= 5V
R
L
= 600
:
, V
S
= 24V
R
L
= 100 k
:
, V
S
= 5V
0.001
R
L
= 100 k
:
, V
S
= 24V
0.0001
10 100 1k 10k
FREQUENCY (Hz)
Figure 23.
1
V s
= 24V
THD+N vs.
Output Amplitude
0.1
100k
0.01
R
L
= 600
:
0.001
R
L
= 100 k :
0.0001
0.001
0.01
0.1
1 10
OUTPUT AMPLITUDE (V)
Figure 25.
100
8
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Typical Performance Characteristics (continued)
Unless otherwise specified, T
A
= 25°C, V
S
Slew Rate vs.
Supply Voltage
6
= 24V, V
+
= V
S
, V
−
= 0 V, V
CM
= V
S
/2.
70
Overshoot and Undershoot vs.
Capacitive Load
OVERSHOOT %
5.8
60 5.6
5.4
5.2
5
4.8
4.6
FALLING EDGE
RISING EDGE
4.4
5 7 9 11 13 15 17 19 21 23 25
V
S
(V)
Figure 26.
50
40
30
15
UNDERSHOOT %
25 35 45
CAPACITIVE LOAD (pF)
Figure 27.
55
0.015
Small Signal Transient Response
V
S
= 24V
0.01
C
L
= 10 pF
6
Large Signal Transient Response
4
0.005
0
-0.005
-0.01
-0.015
0 1 2 3 4 5 6 7 8 9 10
TIME (
P s)
Figure 28.
60
Phase Margin vs.
Capacitive Load (Stability)
V
S
= 5V
50
40
R
L
= 2 k :
R
L
= 10 k
:
30
R
L
= 10 M
:
20
10
0
10
1000 100
CAPACITIVE LOAD (pF)
Figure 30.
2
0
-2
-4
V
S
= 24V
C
L
= 10 pF
-6
0 1 2 3 4 5 6 7 8 9 10
TIME (
P s)
Figure 29.
60
Phase Margin vs.
Capacitive Load (Stability)
V
S
= 24V
50
R
L
= 2 k :
40
R
L
= 10 k :
30
20
R
L
= 10 M :
10
0
10
1000 100
CAPACITIVE LOAD (pF)
Figure 31.
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Typical Performance Characteristics (continued)
Unless otherwise specified, T
A
= 25°C, V
S
= 24V, V
Closed Loop Output Impedance vs.
Frequency
+
100
= V
S
, V
−
= 0 V, V
CM
= V
S
/2.
0
PSRR vs.
Frequency
-20
10
V
S
= 5V, -PSRR
-40
1
V
S
= 24V, -PSRR
0.1
V
S
= 5V
-60
-80
0.01
V
S
= 24V
0.001
10 100 1k
10k
100k
FREQUENCY (Hz)
Figure 32.
1M
10M
-100
-120
10
V
S
= 5V, +PSRR
100
V
S
= 24V, +PSRR
10M 1k 10k 100k
FREQUENCY (Hz)
Figure 33.
1M
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CMRR vs.
Frequency
0
-20
-40
-60
-80
-100
V
S
= 5V
-120
10
V
S
= 24V
100 1k
10k
FREQUENCY (Hz)
Figure 34.
100k 1M
10
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APPLICATION NOTES
ADVANTAGES OF THE LM6211
High Supply Voltage, Low Power Operation
The LM6211 has performance ensured at supply voltages of 5V and 24V. The LM6211 is ensured to be operational at all supply voltages between 5V and 24V. In this large range of operation, the LM6211 draws a fairly constant supply current of 1 mA, while providing a wide bandwidth of 20 MHz. The wide operating range makes the LM6211 a versatile choice for a variety of applications ranging from portable instrumentation to industrial control systems.
Low Input Referred Noise
The LM6211 has very low flatband input referred voltage noise, 5.5 nV/ √ Hz. The 1/f corner frequency, also very low, is about 400 Hz. The CMOS input stage allows for an extremely low input current (2 pA) and a very low input referred current noise (0.01 pA/ √ Hz). This allows the LM6211 to maintain signal fidelity and makes it ideal for audio, wireless or sensor based applications.
Low Input Bias Current and High Input Impedance
The LM6211 has a CMOS input stage, which allows it to have very high input impedance, very small input bias currents (2 pA) and extremely low input referred current noise (0.01 pA/ √ Hz). This level of performance is essential for op amps used in sensor applications, which deal with extremely low currents of the order of a few nanoamperes. In this case, the op amp is being driven by a sensor, which typically has a source impedance of tens of M Ω . This makes it essential for the op amp to have a much higher impedance.
Low Input Capacitance
The LM6211 has a comparatively small input capacitance for a high voltage CMOS design. Low input capacitance is very beneficial in terms of driving large feedback resistors, required for higher closed loop gain.
Usually, high voltage CMOS input stages have a large input capacitance, which when used in a typical gain configuration, interacts with the feedback resistance to create an extra pole. The extra pole causes gain-peaking and can compromise the stability of the op amp. The LM6211 can, however, be used with larger resistors due to its smaller input capacitance, and hence provide more gain without compromising stability. This also makes the
LM6211 ideal for wideband transimpedance amplifiers, which require a wide bandwidth, low input referred noise and low input capacitance.
RRO, Ground Sensing and Current Limiting
The LM6211 has a rail-to-rail output stage, which provides the maximum possible output dynamic range. This is especially important for applications requiring a large output swing, like wideband PLL synthesizers which need an active loop filter to drive a wide frequency range VCO. The input common mode range includes the negative supply rail which allows direct sensing at ground in a single supply operation. The LM6211 also has a short circuit protection circuit which limits the output current to about 25 mA sourcing and 38 mA sinking, and allows the LM6211 to drive short circuit loads indefinitely. However, while driving short circuit loads care should be taken to prevent the inputs from seeing more than ±0.3V differential voltage, which is the absolute maximum differential input voltage.
Small Size
The small footprint of the LM6211 package saves space on printed circuit boards, and enables the design of smaller and more compact electronic products. Long traces between the signal source and the op amp make the signal path susceptible to noise. By using a physically smaller package, the LM6211 can be placed closer to the signal source, reducing noise pickup and enhancing signal integrity
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STABILITY OF OP AMP CIRCUITS
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Stability and Capacitive Loading
The LM6211 is designed to be unity gain stable for moderate capacitive loads, around 100 pF. That is, if connected in a unity gain buffer configuration, the LM6211 will resist oscillation unless the capacitive load is higher than about 100 pF. For higher capacitive loads, the phase margin of the op amp reduces significantly and it tends to oscillate. This is because an op amp cannot be designed to be stable for high capacitive loads without either sacrificing bandwidth or supplying higher current. Hence, for driving higher capacitive loads, the LM6211 needs to be externally compensated.
UNSTABLE
ROC = 40 dB/decade
STABLE
ROC
±
20 dB/decade
0
FREQUENCY (Hz)
Figure 35. Gain vs. Frequency for an Op Amp
An op amp, ideally, has a dominant pole close to DC, which causes its gain to decay at the rate of 20 dB/decade with respect to frequency. If this rate of decay, also known as the rate of closure (ROC), remains at 20 dB/decade at the unity gain bandwidth of the op amp, the op amp is stable. If, however, a large capacitance is added to the output of the op amp, it combines with the output impedance of the op amp to create another pole in its frequency response before its unity gain frequency (
Figure 35 ). This increases the ROC to 40 dB/decade
and causes instability.
In such a case a number of techniques can be used to restore stability to the circuit. The idea behind all these schemes is to modify the frequency response such that it can be restored to a ROC of 20 dB/decade, which ensures stability.
In the Loop Compensation
illustrates a compensation technique, known as ‘in the loop’ compensation, that employs an RC feedback circuit within the feedback loop to stabilize a non-inverting amplifier configuration. A small series resistance, R
S
, is used to isolate the amplifier output from the load capacitance, C
L is inserted across the feedback resistor to bypass C
L at higher frequencies.
, and a small capacitance, C
F
,
V
IN
+
R
OUT
-
C
F
R
S
C
L
R
L
R
IN
R
F
Figure 36. In the Loop Compensation
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The values for R
S and C pole attributed to C
L
F are decided by ensuring that the zero attributed to C
F lies at the same frequency as the
. This ensures that the effect of the second pole on the transfer function is compensated for by the presence of the zero, and that the ROC is maintained at 20 dB/decade. For the circuit shown in
the values of R
S and C
F are given by
shows different values of R
S and C
F that need to be used for maintaining stability with different values of C
L are assumed to be 10 k Ω , R
L is taken as 2 k Ω , while R
, as well as the phase margins to be expected. R
F
OUT is taken to be 60 Ω .
and R
IN
R
S
= R
OUT
R
IN
R
F
©
C
F
=
§
¨
©
R
F
+ 2R
IN
RF
2
¨
¨
§
C
L
R
OUT
(1)
Table 1.
C
L
(pF)
250
300
500
R
S
( Ω )
60
60
60
C
F
(pF)
4.5
5.4
9
Phase Margin (°)
39.8
49.5
53.1
Although this methodology provides circuit stability for any load capacitance, it does so at the price of bandwidth.
The closed loop bandwidth of the circuit is now limited by R
S and C
F
.
Compensation by External Resistor
In some applications it is essential to drive a capacitive load without sacrificing bandwidth. In such a case, in the loop compensation is not viable. A simpler scheme for compensation is shown in
. A resistor, R
ISO
, is placed in series between the load capacitance and the output. T110his introduces a zero in the circuit transfer function, which counteracts the effect of the pole formed by the load capacitance, and ensures stability.
Figure 37. Compensation By Isolation Resistor
The value of R
ISO to be used should be decided depending on the size of C
L and the level of performance desired. Values ranging from 5 Ω to 50 Ω are usually sufficient to ensure stability. A larger value of R
ISO will result in a system with lesser ringing and overshoot, but will also limit the output swing and the short circuit current of the circuit.
Stability and Input Capacitance
In certain applications, for example I-V conversion, transimpedance photodiode amplification and buffering the output of current-output DAC, capacitive loading at the input of the op amp can endanger stability. The capacitance of the source driving the op amp, the op amp input capacitance and the parasitic/wiring capacitance contribute to the loading of the input. This capacitance, C
IN
, interacts with the feedback network to introduce a peaking in the closed loop gain of the circuit, and hence causes instability.
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+
V
IN
-
R
1
C
IN
-
+
C
F
R
2
+
-
V
OUT
Figure 38. Compensating for Input Capacitance
This peaking can be eliminated by adding a feedback capacitance, C
F
, as shown in
zero in the feedback network, and hence a pole in the closed loop response, and thus maintains stability. An optimal value of C
F is given by
Equation 2 . A simpler approach is to select C
margin. This approach, however, limits the bandwidth excessively.
F
= (R
1
/R
2
)C
IN for a 90° phase
Typical Applications
ACTIVE LOOP FILTER FOR PLLs
A typical phase locked loop, or PLL, functions by creating a negative feedback loop in terms of the phase of a signal. A simple PLL consists of three main components: a phase detector, a loop filter and a voltage controlled oscillator (VCO). The phase detector compares the phase of the output of the PLL with that of a reference signal, and feeds the error signal into the loop filter, thus performing negative feedback. The loop filter performs the important function of averaging (or low-pass filtering) the error and providing the VCO with a DC voltage, which allows the VCO to modify its frequency such that the error is minimized. The performance of the loop filter affects a number of specifications of the PLL, like its frequency range, locking time and phase noise.
Since a loop filter is a very noise sensitive application, it is usually suggested that only passive components be used in its design. Any active devices, like discrete transistors or op amps, would add significantly to the noise of the circuit and would hence worsen the in-band phase noise of the PLL. But newer and faster PLLs, like TI’s
LMX2430, have a power supply voltage of less than 3V, which limits the phase-detector output of the PLL. If a passive loop filter is used with such circuits, then the DC voltage that can be provided to the VCO is limited to couple of volts. This limits the range of frequencies for which the VCO, and hence the PLL, is functional. In certain applications requiring a wider operating range of frequencies for the PLL, like set-top boxes or base stations, this level of performance is not adequate and requires active amplification, hence the need for active loop filters.
An active loop filter typically consists of an op amp, which provides the gain, accompanied by a three or four pole
RC filter. The non-inverting input of the op amp is biased to a fixed value, usually the mid-supply of the PLL, while a feedback network provides the gain as well as one, or two, poles for low pass filtering.
illustrates a typical active loop filter.
CHARGE
PUMP
OUTPUT
-
+
V
S_PLL
2
VCO
INPUT
Figure 39. A Typical Active Loop Filter
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Certain performance characteristics are essential for an op amp if it is to be used in a PLL loop filter. Low input referred voltage and current noise are essential, as they directly affect the noise of the filter and hence the phase noise of the PLL. Low input bias current is also important, as bias current affects the level of ‘reference spurs’, artifacts in the frequency spectrum of the PLL caused by mismatch or leakage at the output of the phase detector. A large input and output swing is beneficial in terms of increasing the flexibility in biasing the op amp.
The op amp can then be biased such that the output range of the PLL is mapped efficiently onto the input range of the VCO.
With a CMOS input, ultra low input bias currents (2 pA) and low input referred voltage noise (5.5 nV/ √ Hz), the
LM6211 is an ideal op amp for using in a PLL active loop filter. The LM6211 has a ground sensing input stage, a rail-to-rail output stage, and an operating supply range of 5V - 24V, which makes it a versatile choice for the design of a wide variety of active loop filters.
shows the LM6211 used with the LMX2430 to create an RF frequency synthesizer. The LMX2430 detects the PLL output, compares it with its internal reference clock and outputs the phase error in terms of current spikes. The LM6211 is used to create a loop filter which averages the error and provides a DC voltage to the VCO. The VCO generates a sine wave at a frequency determined by the DC voltage at its input. This circuit can provide output signal frequencies as high as 2 GHz, much higher than a comparative passive loop filter.
Compared to a similar passive loop filter, the LM6211 doesn’t add significantly to the phase noise of the PLL, except at the edge of the loop bandwidth, as shown in
. A peaking of loop gain is expected, since the loop filter is deliberately designed to have a wide bandwidth and a low phase margin so as to minimize locking time.
4.0
3.0
ACTIVE LOOP FILTER
WITH LM6211
2.0
1.0
0.0
-1.0
1k
PASSIVE LOOP FILTER
10k 100k
OFFSET FREQUENCY (Hz)
1M
Figure 40. Effect of LM6211 on Phase Noise of PLL
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V
S
_PLL
RF_PLL PROGRAMMING INPUTS
R
5
18
:
C
26
0.01
P
F
C
27
100 pF
C
39
V
S
_PLL
R
47
C
38
IF_PLL I/O's
1
2
3
4
5
6
7
GND
F
IN
_IF
CE
D
0
_IF
OSC_EN
OSC_OUT/FL
0
_IF
OSC_IN
LE
V
S
F
IN
B_RF
F
IN
_RF
GND
D
0
_RF
GND
13
12
11
17
16
15
14
C
10
0.01 P F
C
5
100 pF
C
11
100 pF
C
6
100 pF
V
S
_PLL
LMX2430
V
S
_OP AMP
C
41
0.1
P
F
R
50
10
:
C
1
C
2
C
4
R
2
-
+
V
S
_PLL
R
46
100 k
:
R
45
100 k
:
R
3
LM6211
C
3
C
13
0.01
P
F
C
14
100 pF
C
37
0.1 P F
7
6
5
4
R
41
R
7
18
:
C
36
C
7
100 pF
RF_OUT
R
6
18
:
C
40
100 pF
V
CC
12
13
14
15
C8
0.01 P F
V
S
_RF
L2
C9
100 pF
V586ME04
Figure 41. LM6211 in the Active Loop Filter for LMX2430
ADC INPUT DRIVER
A typical application for a high performance op amp is as an ADC driver, which delivers the analog signal obtained from sensors and actuators to ADCs for conversion to the digital domain and further processing.
Important requirements in this application are a slew rate high enough to drive the ADC input and low input referred voltage and current noise. If an op amp is used with an ADC, it is critical that the op amp noise does not affect the dynamic range of the ADC. The LM6211, with low input referred voltage and current noise, provides a great solution for this application. For example, the LM6211 can be used to drive an ADS121021, a 12-bit ADC from TI. If it provides a gain of 10 to a maximum input signal amplitude of 100 mV, for a bandwidth as wide as
100 kHz, the average noise seen at the input of the ADC is only 44.6 µVrms. Hence the dynamic range of the
ADC, measured in Effective Number of Bits or ENOB, is only reduced by 0.3 bits, despite amplifying the input signal by a gain of 10. Low input bias currents and high input impedance also help as they prevent the loading of the sensor and allow the measurement system to function over a large range.
shows a circuit for monitoring fluid pressure in a hydraulic system, in which the LM6211 is used to sense the error voltage from the pressure sensor. Two LM6211 amplifiers are used to make a difference amplifier which senses the error signal, amplifies it by a gain of 100, and delivers it to the ADC input. The ADC converts the error voltage into a pressure reading to be displayed and drives the DAC, which changes the voltage driving the resistance bridge sensor. This is used to control the gain of the pressure measurement circuit, such that the range of the sensor can be modified to obtain the best resolution possible.
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V
OUT
1
4.096V
C1
3
6 SYNC
5 SCLK
4 DOUT
2
120 pF
+5V
4
5
1,2
B1
7,8
6
0.1 P F
3
4
+
+5V
A2
5
-
2
1
100 k
:
180 :
0.2
P
F
1 P F
A
V
= 100 2.02 k :
470 pF
2
3
2.048V
V
REF
1
+5V
+IN
C2
-IN
8
4
7 SCLK
6 DOUT
5 CS
3
-
+5V
A1
4
+
5
2
100 k :
1
0.2
P
F
470 pF
180 :
PRESSURE SENSOR
0.2 mV/Volt/PSI
A1, A2 = LM6211
B1 = LM4140ACM-2.0
C1 = DAC081S101
C2 = ADC121S625
Figure 42. Hydraulic Pressure Monitoring System
DAC OUTPUT AMPLIFIER
Op amps are often used to improve a DAC's output driving capability. High performance op amps are required as
I-V converters at the outputs of high resolution current output DACs. Since most DACs operate with a single supply of 5V, a rail-to-rail output swing is essential for this application. A low offset voltage is also necessary to prevent offset errors in the waveform generated. Also, the output impedance of DACs is quite high, more than a few k Ω in some cases, so it is also advisable for the op amp to have a low input bias current. An op amp with a high input impedance also prevents the loading of the DAC, and hence, avoids gain errors. The op amp should also have a slew rate which is fast enough to not affect the settling time of the DAC output.
The LM6211, with a CMOS input stage, ultra low input bias current, a wide bandwidth (20 MHz) and a rail-to-rail output swing for a supply voltage of 24V is an ideal op amp for such an application.
shows a typical circuit for this application. The op amp is usually expected to add another time constant to the system, which worsens the settling time, but the wide bandwidth of the LM6211 (20 MHz) allows the system performance to improve without any significant degradation of the settling time.
V
S
10
P
F
V
S
3
0.1 P F
SYNC 6
SCLK 5
DOUT 4
DAC081S101
2
1
-
LM6211
+
Figure 43. DAC Driver Circuit
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AUDIO PREAMPLIFIER
With low input referred voltage noise, low supply voltage and low supply current, and low harmonic distortion, the
LM6211 is ideal for audio applications. Its wide unity gain bandwidth allows it to provide large gain over a wide frequency range and it can be used to design a preamplifier to drive a load of as low as 600 Ω with less than
0.001% distortion. Two amplifier circuits are shown in
and
.
is an inverting amplifier, with a 10 k Ω feedback resistor, R
2
, and a 1 k Ω input resistor, R
1 is a non-inverting amplifier, using the same values for R
1 and R
2
, and hence provides a gain of − 10.
, and provides a gain of 11. In either of these circuits, the coupling capacitor C
C1 while the feedback capacitor C
F decides the lower frequency at which the circuit starts providing gain, decides the frequency at which the gain starts dropping off.
shows the frequency response of the circuit in
with different values of C
F
.
C
F
+
V
IN
-
C
C1
R
1
1 k :
R
B1
V
+
-
+
R
2
10 k :
C
C2
+
-
V
OUT
R
B2
A
V
= -
R
2
R
1
= -10
Figure 44. Inverting Audio Amplifier
V
+
+
V
IN
-
C
C2
R
B1
R
B2
+
-
R
2
10 k :
+
V
OUT
-
R
1
1 k :
C
C1
C
F
A
V
= 1 +
R
2
R
1
= 11
Figure 45. Non-Inverting Audio Preamplifier
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25
20
15
10
5
0
-5
-10
-15
-20
1
C
F
= 10 pF
C
F
= 1 nF
C
F
= 100 pF
10
100 1k 10k
FREQUENCY (Hz)
100k 1M
Figure 46. Frequency Response of the Non-Inverting Preamplifier
TRANSIMPEDANCE AMPLIFIER
A transimpedance amplifier converts a small input current into a voltage. This current is usually generated by a photodiode. The transimpedance gain, measured as the ratio of the output voltage to the input current, is expected to be large and wide-band. Since the circuit deals with currents in the range of a few nA, low noise performance is essential. The LM6211, being a CMOS input op amp, provides a wide bandwidth and low noise performance while drawing very low input bias current, and is hence ideal for transimpedance applications.
A transimpedance amplifier is designed on the basis of the current source driving the input. A photodiode is a very common capacitive current source, which requires transimpedance gain for transforming its miniscule current into easily detectable voltages. The photodiode and amplifier’s gain are selected with respect to the speed and accuracy required of the circuit. A faster circuit would require a photodiode with lesser capacitance and a faster amplifier. A more sensitive circuit would require a sensitive photodiode and a high gain. A typical transimpedance amplifier is shown in
Figure 47 . The output voltage of the amplifier is given by the equation
V
OUT
= − I values of I
IN
IN
R
F
. Since the output swing of the amplifier is limited, R can be detected.
F should be selected such that all possible
The LM6211 has a large gain-bandwidth product (20 MHz), which enables high gains at wide bandwidths. A railto-rail output swing at 24V supply allows detection and amplification of a wide range of input currents. A CMOS input stage with negligible input current noise and low input voltage noise allows the LM6211 to provide high fidelity amplification for wide bandwidths. These properties make the LM6211 ideal for systems requiring wideband transimpedance amplification.
C
F
R
F
I
IN
C
CM
C
D
-
+
+
V
OUT
-
V
B C
IN
= C
D
+ C
CM
V
OUT
=
- R
F
I
IN
Figure 47. Photodiode Transimpedance Amplifier
The following parameters are used to design a transimpedance amplifier: the amplifier gain-bandwidth product,
A
0
; the amplifier input capacitance, C
CM
; the photodiode capacitance, C
D
; the transimpedance gain required, R
F
; and the amplifier output swing. Once a feasible R
F is selected using the amplifier output swing, these numbers can be used to design an amplifier with the desired transimpedance gain and a maximally flat frequency response. The input common-mode capacitance with respect to V
CM for the LM6211 is give in
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20
15
V
S
= 5V
10
V
S
= 24V
5
0
0 2 4 6 8 10 12 14 16 18 20 22 24
V
CM
(V)
Figure 48. Input Common-Mode Capacitance vs. V
CM
An essential component for obtaining a maximally flat response is the feedback capacitor, C
F seen at the input of the amplifier, C
IN
, combined with the feedback resistor, R
F causes gain-peaking and can destabilize the circuit. C
IN capacitor C
F creates a pole, f
P in the noise gain of the circuit, which neutralizes the zero in the noise gain, f created by the combination of R
F and C
IN is usually just the sum of C
D and C
. The capacitance
, generates a phase lag which
CM
. The feedback
. If properly positioned, the noise gain pole created by C
F
Z can ensure that the slope of the gain remains at 20 dB/decade till the unity gain frequency of the amplifier is reached, thus
, ensuring stability. As shown in
P is positioned such that it coincides with the point where the noise gain intersects the op amp’s open loop gain. In this case, f transimpedance amplifier. The value of C
F
P is also the overall 3 dB frequency of the needed to make it so is given by
Equation 2 . A larger value of C
F causes excessive reduction of bandwidth, while a smaller value fails to prevent gain peaking and maintain stability.
C
F
=
1 + 1 + 4
S
R
F
C
IN
A
0
2
S
R
F
A
0
(2)
Calculating C
F from
can sometimes return unreasonably small values (<1 pF), especially for high speed applications. In these cases, it is often more practical to use the circuit shown in
in order to allow more reasonable values. In this circuit, the capacitance C
F capacitance, C
F
' is (1+ R
B
/R
A
) times the effective feedback
. A larger capacitor can now be used in this circuit to obtain a smaller effective capacitance.
R
A
R
B
C
F c
R
F
-
+
IF R
A
< < R
F
©
C
F c
=
¨
§
1 +
R
B
R
A
¨
§
C
F
Figure 49. Modifying C
F
For example, if a C
F such that R
B
<< R
F
/R
A of 0.5 pF is needed, while only a 5 pF capacitor is available, R
= 9. This would convert a C
F
' of 5 pF into a C
F
B and R
A can be selected of 0.5 pF. This relationship holds as long as R
A
20
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Copyright © 2006–2013, Texas Instruments Incorporated
LM6211
SNOSAH2C – FEBRUARY 2006 – REVISED MARCH 2013
www.ti.com
OP AMP
OPEN LOOP
GAIN f
Z
=
1
2
S R
F
C
IN f
P
=
A
0
2
S
R
F
(C
IN
+C
F
)
NOISE GAIN WITH NO C
F
NOISE GAIN WITH C
F f
Z f
P
FREQUENCY
Figure 50. Method for C
F
selection
A
0
SENSOR INTERFACES
The low input bias current and low input referred noise of the LM6211 make it ideal for sensor interfaces. These circuits are required to sense voltages of the order of a few μ V, and currents amounting to less than a nA, and hence the op amp needs to have low voltage noise and low input bias current. Typical applications include infrared (IR) thermometry, thermocouple amplifiers and pH electrode buffers.
is an example of a typical circuit used for measuring IR radiation intensity, often used for estimating the temperature of an object from a distance. The IR sensor generates a voltage proportional to I, which is the intensity of the IR radiation falling on it. As shown in
Figure 51 , K is the constant of proportionality relating the voltage across the IR sensor (V
IN radiation intensity, I. The resistances R
A
C
F and R
B is added to filter out the high frequency noise.
) to the are selected to provide a high gain to amplify this voltage, while
IR SENSOR
+
V
IN
= KI
-
+
-
R
B
+
V
OUT
-
IR RADIATION
INTENSITY, I
R
A
C
F
V
OUT
R
A
I =
K(R
A
+ R
B
)
Figure 51. IR Radiation Sensor
Copyright © 2006–2013, Texas Instruments Incorporated
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LM6211
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21
LM6211
SNOSAH2C – FEBRUARY 2006 – REVISED MARCH 2013
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REVISION HISTORY
Changes from Revision B (March 2013) to Revision C Page
• Changed layout of National Data Sheet to TI format ..........................................................................................................
22
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PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
PACKAGING INFORMATION
Orderable Device
LM6211MF
LM6211MF/NOPB
Status
(1)
NRND
ACTIVE
Package Type Package
Drawing
SOT-23
SOT-23
DBV
DBV
Pins Package
5
5
Qty
Eco Plan
(2)
1000 TBD
1000 Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
Call TI
CU SN
MSL Peak Temp
(3)
Call TI
Level-1-260C-UNLIM
Op Temp (°C)
-40 to 125
-40 to 125
AT1A
AT1A
Device Marking
(4/5)
LM6211MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 125 AT1A
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
www.ti.com
TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
23-Sep-2013
*All dimensions are nominal
Device
LM6211MF
LM6211MF/NOPB
LM6211MFX/NOPB
Package
Type
Package
Drawing
SOT-23 DBV
SOT-23 DBV
SOT-23 DBV
Pins
5
5
5
SPQ
1000
1000
3000
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
178.0
8.4
178.0
178.0
8.4
8.4
A0
(mm)
3.2
3.2
3.2
B0
(mm)
3.2
3.2
3.2
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
1.4
1.4
1.4
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
23-Sep-2013
*All dimensions are nominal
Device
LM6211MF
LM6211MF/NOPB
LM6211MFX/NOPB
Package Type Package Drawing Pins
SOT-23
SOT-23
SOT-23
DBV
DBV
DBV
5
5
5
SPQ
1000
1000
3000
Length (mm) Width (mm) Height (mm)
210.0
210.0
210.0
185.0
185.0
185.0
35.0
35.0
35.0
Pack Materials-Page 2
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