DAC104S085/DAC104S085-Q1 10-Bit Micro Power QUAD Digital-to-Analog Converter with Rail-to-Rail Output DAC104S085 FEATURES
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SNAS362F – MAY 2006 – REVISED MARCH 2013
DAC104S085/DAC104S085-Q1 10-Bit Micro Power QUAD Digital-to-Analog Converter with
Rail-to-Rail Output
Check for Samples: DAC104S085
1
FEATURES
2
• Ensured Monotonicity
• Low Power Operation
• Rail-to-Rail Voltage Output
• Power-on Reset to 0V
• Simultaneous Output Updating
• Wide power supply range (+2.7V to +5.5V)
• Industry's Smallest Package
• Power Down Modes
• AEC-Q100 Grade 1 Qualified
APPLICATIONS
• Battery-Powered Instruments
• Digital Gain and Offset Adjustment
• Programmable Voltage & Current Sources
• Programmable Attenuators
• Automotive
KEY SPECIFICATIONS
• Resolution 10 bits
• INL ±2 LSB (max)
• DNL +0.35 / − 0.25 LSB (max)
• Settling Time 6 μ s (max)
• Zero Code Error +15 mV (max)
• Full-Scale Error − 0.75 %FS (max)
• Supply Power
– Normal
– 1.1 mW (3V)
– 2.5 mW (5V) typ
– Power Down
– 0.3
μ W (3V)
– 0.8
μ W (5V) typ
DESCRIPTION
The DAC104S085 is a full-featured, general purpose
QUAD 10-bit voltage-output digital-to-analog converter (DAC) that can operate from a single +2.7V
to 5.5V supply and consumes 1.1 mW at 3V and 2.5
mW at 5V. The DAC104S085 is packaged in 10-lead
SON and VSSOP packages. The 10-lead SON package makes the DAC104S085 the smallest QUAD
DAC in its class. The on-chip output amplifier allows rail-to-rail output swing and the three wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range. Competitive devices are limited to 25 MHz clock rates at supply voltages in the 2.7V to 3.6V range. The serial interface is compatible with standard SPI, QSPI, MICROWIRE and DSP interfaces.
The reference for the DAC104S085 serves all four channels and can vary in voltage between 1V and V
A
, providing the widest possible output dynamic range.
The DAC104S085 has a 16-bit input shift register that controls the outputs to be updated, the mode of operation, the powerdown condition, and the binary input data.
All four outputs can be updated simultaneously or individually depending on the setting of the two mode of operation bits.
A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three different termination options.
The low power consumption and small packages of the DAC104S085 make it an excellent choice for use in battery operated equipment.
The DAC104S085 is one of a family of pin compatible
DACs, including the 8-bit DAC084S085 and the 12-bit
DAC124S085. The DAC104S085 operates over the extended industrial temperature range of − 40°C to
+125°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
DAC104S085
SNAS362F – MAY 2006 – REVISED MARCH 2013
Pin Configuration
V
A
V
OUTA
V
OUTB
V
OUTC
V
OUTD
1
2
3
4
5
SON
10
9
8
7
6
SCLK
SYNC
D
IN
V
REFIN
GND
V
A
V
OUTA
V
OUTB
V
OUTC
V
OUTD
3
4
1
2
5
VSSOP
10
9
8
7
6
SCLK
SYNC
D
IN
V
REFIN
GND
Block Diagram
POWER-ON
RESET
DAC
REGISTER
10
INPUT
CONTROL
LOGIC
10
10
10
10
V
REFIN
REF
10 BIT DAC
REF
10 BIT DAC
REF
10 BIT DAC
REF
10 BIT DAC
POWER-DOWN
CONTROL
LOGIC
BUFFER
DAC104S085
BUFFER
V
OUTA
2.5k
100k
V
OUTB
2.5k
100k
BUFFER V
OUTC
2.5k
100k
BUFFER V
OUTD
2.5k
100k
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SYNC
SCLK D
IN
2
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SON
VSSOP
Pin No.
1
2
3
4
5
6
7
8
9
10
11
Symbol
V
A
V
OUTA
V
OUTB
V
OUTC
V
OUTD
GND
V
REFIN
D
IN
SYNC
SCLK
PAD
(SON only)
SNAS362F – MAY 2006 – REVISED MARCH 2013
Type
Supply
Analog Output
Analog Output
Analog Output
Analog Output
Ground
Analog Input
Digital Input
Ground
PIN DESCRIPTIONS
Digital Input
Digital Input
Description
Power supply input. Must be decoupled to GND.
Channel A Analog Output Voltage.
Channel B Analog Output Voltage.
Channel C Analog Output Voltage.
Channel D Analog Output Voltage.
Ground reference for all on-chip circuitry.
Unbuffered reference voltage shared by all channels. Must be decoupled to GND.
Serial Data Input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the fall of SYNC.
Frame synchronization input for the data input. When this pin goes low, it enables the input shift register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the DAC.
Serial Clock Input. Data is clocked into the input shift register on the falling edges of this pin.
Exposed die attach pad can be connected to ground or left floating.
Soldering the pad to the PCB offers optimal thermal performance and enhances package self-alignment during reflow.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2) (3)
Supply Voltage, V
A
Voltage on any Input Pin
Input Current at Any Pin
(4)
Package Input Current
(4)
Power Consumption at T
A
= 25°C
ESD Susceptibility
(6)
Human Body Model
Machine Model
6.5V
− 0.3V to 6.5V
10 mA
20 mA
See
(5)
2500V
250V
+150°C
− 65°C to +150°C
Junction Temperature
Storage Temperature
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(4) When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
(5) The absolute maximum junction temperature (T
J max) for this device is 150°C. The maximum allowable power dissipation is dictated by
T
J max, the junction-to-ambient thermal resistance ( θ
JA
), and the ambient temperature (T
A
), and can be calculated using the formula
P
D
MAX = (T
J max − T
A
) / θ
JA
. The values for maximum power dissipation will be reached only when the device is operated in a severe fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
(6) Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through ZERO
Ohms.
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Operating Ratings
(1) (2)
Operating Temperature Range
Supply Voltage, V
A
Reference Voltage, V
REFIN
Digital Input Voltage
(3)
Output Load
SCLK Frequency
− 40°C ≤ T
A
≤ +125°C
+2.7V to 5.5V
+1.0V to V
A
0.0V to 5.5V
0 to 1500 pF
Up to 40 MHz
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
(3) The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of V
A
, will not cause errors in the conversion result. For example, if V
A is 3V, the digital input pins can be driven with a 5V logic device.
I/O
TO INTERNAL
CIRCUITRY
GND
Package Thermal Resistances
(1)
Package
10-Lead VSSOP
10-Lead SON
θ
JA
240°C/W
250°C/W
Soldering process must comply with Reflow Temperature Profile specifications. Refer to
http://www.ti.com/lit/SNOA549 .
(1) Reflow temperature profiles are different for lead-free packages.
Electrical Characteristics
The following specifications apply for V
A
= +2.7V to +5.5V, V range 12 to 1011. Boldface limits apply for T specified.
MIN
≤ T
A
≤ T
REFIN
MAX
= V
A
, C
L
= 200 pF to GND, f
SCLK and all other limits are at T
A
= 30 MHz, input code
= 25°C, unless otherwise
Symbol Parameter Conditions Typical
(1)
Limits
(1)
Units
(Limits)
STATIC PERFORMANCE
Resolution
INL
Monotonicity
Integral Non-Linearity
DNL
ZE
FSE
GE
ZCED
TC GE
Differential Non-Linearity
Zero Code Error
Full-Scale Error
Gain Error
Zero Code Error Drift
Gain Error Tempco
V
A
= 2.7V to 5.5V
I
OUT
= 0
I
OUT
= 0
All ones Loaded to DAC register
V
A
= 3V
V
A
= 5V
±0.7
+0.08
−
0.03
+5
− 0.1
− 0.2
− 20
−
0.7
− 1.0
10
10
±2
+0.35
−
0.25
+15
− 0.75
− 1.0
Bits (min)
Bits (min)
LSB (max)
LSB (max)
LSB (min) mV (max)
%FSR (max)
%FSR
µV/°C ppm/°C ppm/°C
(1) Typical figures are at T
J
Quality Level).
= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
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Electrical Characteristics (continued)
The following specifications apply for V
A
= +2.7V to +5.5V, V range 12 to 1011. Boldface limits apply for T
MIN
≤ T
A
≤ T
REFIN
MAX
= V
A
, C
L
= 200 pF to GND, f
SCLK and all other limits are at T
A
= 30 MHz, input code
= 25°C, unless otherwise specified.
Symbol Parameter Conditions Typical
(1)
Limits
(1)
Units
(Limits)
OUTPUT CHARACTERISTICS
Output Voltage Range See
(2)
0
V
REFIN
V (min)
V (max)
I
OZ
High-Impedance Output
Leakage Current
(2)
±1
µA (max)
ZCO
FSO
I
OS
I
OS
Zero Code Output
Full Scale Output
Output Short Circuit Current
(source)
Output Short Circuit Current (sink)
V
A
= 3V, I
OUT
= 200 µA
V
A
= 3V, I
OUT
= 1 mA
V
A
= 5V, I
OUT
= 200 µA
V
A
= 5V, I
OUT
= 1 mA
V
A
= 3V, I
OUT
= 200 µA
V
A
= 3V, I
OUT
= 1 mA
V
A
= 5V, I
OUT
= 200 µA
V
A
= 5V, I
OUT
= 1 mA
V
A
= 3V, V
OUT
= 0V,
Input Code = 3FFh
V
A
= 5V, V
OUT
= 0V,
Input Code = 3FFh
V
A
= 3V, V
OUT
= 3V,
Input Code = 000h
V
A
= 5V, V
OUT
= 5V,
Input Code = 000h
1.3
6.0
7.0
10.0
2.984
2.934
4.989
4.958
-56
-69
52
75 mV mV mV mV
V
V
V
V mA mA mA mA
I
O
Continuous Output
Current
(2)
Available on each DAC output
11
mA (max)
C
L
Maximum Load Capacitance
R
L
= ∞
R
L
= 2k Ω
1500
1500
7.5
pF pF
Ω Z
OUT
DC Output Impedance
REFERENCE INPUT CHARACTERISTICS
Input Range Minimum
VREFIN Input Range Maximum
Input Impedance
LOGIC INPUT CHARACTERISTICS
I
IN
Input Current
(2)
0.2
30
1.0
V
A
V (min)
V (max) k Ω
V
IL
V
IH
Input Low Voltage
(2)
Input High Voltage
(2)
V
A
= 3V
V
A
= 5V
V
A
= 3V
V
A
= 5V
0.9
1.5
1.4
2.1
±1
0.6
0.8
2.1
2.4
3
µA (max)
V (max)
V (max)
V (min)
V (min) pF (max) C
IN
Input Capacitance
POWER REQUIREMENTS
(2)
V
A
(3)
Supply Voltage Minimum
Supply Voltage Maximum
2.7
5.5
V (min)
V (max)
(2) This parameter is ensured by design and/or characterization and is not tested in production.
(3) To ensure accuracy, it is required that V
A and V
REFIN be well bypassed.
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Electrical Characteristics (continued)
The following specifications apply for V
A
= +2.7V to +5.5V, V range 12 to 1011. Boldface limits apply for T
MIN
≤ T
A
≤ T
REFIN
MAX
= V
A
, C
L
= 200 pF to GND, f
SCLK and all other limits are at T
A
= 30 MHz, input code
= 25°C, unless otherwise specified.
Symbol Parameter Conditions Typical
(1)
Limits
(1)
Units
(Limits)
I
N
I
PD
P
N
P
PD
Normal Supply Current (output unloaded)
Power Down Supply Current
(output unloaded, SYNC = DIN =
0V after PD mode loaded)
Normal Supply Power (output unloaded) f
SCLK
= 30 MHz f
SCLK
= 0
All PD Modes,
(2) f
SCLK
= 30 MHz f
SCLK
= 0
Power Down Supply Power (output unloaded, SYNC = DIN = 0V after All PD Modes,
(2)
PD mode loaded)
V
A
= 2.7V
to 3.6V
V
A
= 4.5V
to 5.5V
V
A
= 2.7V
to 3.6V
V
A
= 4.5V
to 5.5V
V
A
= 2.7V
to 3.6V
V
A
= 4.5V
to 5.5V
V
A
= 2.7V
to 3.6V
V
A
= 4.5V
to 5.5V
V
A
= 2.7V
to 3.6V
V
A
= 4.5V
to 5.5V
V
A
= 2.7V
to 3.6V
V
A
= 4.5V
to 5.5V
350
500
330
460
0.10
0.15
1.1
2.5
1.0
2.3
0.3
0.8
485
650
1.0
1.0
1.7
3.6
3.6
5.5
µA (max)
µA (max)
µA
µA
µA (max)
µA (max) mW (max) mW (max) mW mW
µW (max)
µW (max)
A.C. and Timing Characteristics
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for V
A
= +2.7V to +5.5V, V range 12 to 1011. Boldface limits apply for T
MIN
≤ T
A
≤ T
REFIN
MAX
= V
A
, C
L
= 200 pF to GND, f
SCLK and all other limits are at T
A
= 30 MHz, input code
= 25°C, unless otherwise specified.
Symbol
f
SCLK
Parameter
SCLK Frequency
Conductions Typical
(1)
40
Limits
(1)
30
Units
(Limits)
MHz (max) t s
Output Voltage Settling Time
(2)
100h to 300h code change
R
L
= 2 k Ω , C
L
= 200 pF
4.5
6
µs (max)
SR Output Slew Rate
Glitch Impulse
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Code change from 200h to 1FFh
1
12
0.5
1
3
160
V/µs nV-sec nV-sec nV-sec nV-sec kHz t
WU
1/f
SCLK t
CH
Total Harmonic Distortion
Wake-Up Time
SCLK Cycle Time
SCLK High time
V
REFIN
= 2.5V ± 0.1Vpp
V
REFIN
= 2.5V ± 0.1Vpp
input frequency = 10kHz
V
A
= 3V
V
A
= 5V
70
6
39
25
7
33
10
dB
µsec
µsec ns (min) ns (min)
(1) Typical figures are at T
J
Quality Level).
= 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average Outgoing
(2) This parameter is ensured by design and/or characterization and is not tested in production.
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A.C. and Timing Characteristics (continued)
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for V
A
= +2.7V to +5.5V, V range 12 to 1011. Boldface limits apply for T specified.
MIN
≤ T
A
≤ T
REFIN
MAX
= V
A
, C
L
= 200 pF to GND, f
SCLK and all other limits are at T
A
= 30 MHz, input code
= 25°C, unless otherwise
Symbol
t
CL
Parameter Conductions Typical
(1)
7
Limits
(1)
10
Units
(Limits)
ns (min) t
SS t
DS t
DH t
CFSR t
SYNC
SCLK Low Time
SYNC Set-up Time prior to SCLK
Falling Edge
Data Set-Up Time prior to SCLK Falling
Edge
Data Hold Time after SCLK Falling
Edge
SCLK fall prior to rise of SYNC
SYNC High Time
4
1.5
1.5
0
6
10
3.5
3.5
3
10
ns (min) ns (min) ns (min) ns (min) ns (min)
Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is V
REF
/ 1024 = V
A
/ 1024.
DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change in the output of another DAC.
DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale change in the input register of another DAC.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh) loaded into the DAC and the value of V
A x 1023 / 1024.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line through the input to output transfer function. The deviation of any given code from this straight line is measured from the center of that code value. The end point method is used. INL for this product is specified over a limited range, per the
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = V
REF
/ 2 n where
• where V
REF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 10 for the DAC104S085.
(1)
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of V
A
.
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave
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on V
REFIN with a full-scale code loaded into the DAC.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from the power supply. The difference between the supply and output currents is the power consumed by the device without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is updated.
TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs with an ideal sine wave applied to V
REFIN
. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This is the time from the falling edge of the
16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been entered.
Transfer Characteristic
FSE
1023 x V
REFIN
1024
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
DIGITAL INPUT CODE
Figure 1. Input / Output Transfer Characteristic
1024
Timing Diagrams
SCLK t
SYNC
1 2 t
SS t
CL
13
1 / f
SCLK
14 t
CH
15 16 t
CFSR
SYNC
D
IN
8
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t
DH
DB15 t
DS
Figure 2. Serial Timing Diagram
DB0
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Typical Performance Characteristics
V
REF
= V
A
, f
SCLK
= 30 MHz, T
A
= 25C, Input Code Range 12 to 1011, unless otherwise stated
INL at V
A
= 3.0V
INL at V
A
= 5.0V
Figure 3.
DNL at V
A
= 3.0V
Figure 5.
V
INL/DNL
REFIN vs at V
A
= 3.0V
V
Figure 4.
DNL at V
A
= 5.0V
Figure 6.
INL/DNL
REFIN vs at V
A
= 5.0V
Figure 7.
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Typical Performance Characteristics (continued)
V
REF
= V
A
, f
SCLK
= 30 MHz, T
A
= 25C, Input Code Range 12 to 1011, unless otherwise stated
f
SCLK
INL/DNL vs at V
A
= 2.7V
INL/DNL vs
V
A www.ti.com
Figure 9.
INL/DNL vs
Clock Duty Cycle at V
A
= 3.0V
Figure 10.
INL/DNL vs
Clock Duty Cycle at V
A
= 5.0V
Figure 11.
INL/DNL vs
Temperature at V
A
= 3.0V
Figure 12.
INL/DNL vs
Temperature at V
A
= 5.0V
Figure 13.
10
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Typical Performance Characteristics (continued)
V
REF
= V
A
, f
SCLK
= 30 MHz, T
A
= 25C, Input Code Range 12 to 1011, unless otherwise stated
Zero Code Error vs.
V
A
Zero Code Error vs.
V
REFIN
Figure 15.
Zero Code Error vs.
f
SCLK
Figure 17.
Zero Code Error vs.
Temperature
Figure 16.
Zero Code Error vs.
Clock Duty Cycle
Figure 18.
Full-Scale Error vs.
V
A
Figure 19.
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Typical Performance Characteristics (continued)
V
REF
= V
A
, f
SCLK
= 30 MHz, T
A
= 25C, Input Code Range 12 to 1011, unless otherwise stated
Full-Scale Error vs.
V
REFIN
Full-Scale Error vs.
f
SCLK www.ti.com
Figure 21.
Full-Scale Error vs.
Clock Duty Cycle
Figure 22.
Full-Scale Error vs.
Temperature
Figure 23.
Supply Current vs.
V
A
Figure 24.
Supply Current vs.
Temperature
Figure 25.
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Figure 26.
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Typical Performance Characteristics (continued)
V
REF
= V
A
, f
SCLK
= 30 MHz, T
A
= 25C, Input Code Range 12 to 1011, unless otherwise stated
5V Glitch Response Power-On Reset
Figure 27.
Figure 28.
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FUNCTIONAL DESCRIPTION
DAC SECTION
The DAC104S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor strings that are followed by an output buffer. The reference voltage is externally applied at V by all four DACs.
REFIN and is shared
For simplicity, a single resistor string is shown in
Figure 29 . This string consists of 1024 equal valued resistors
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight binary with an ideal output voltage of:
V
OUTA,B,C,D
= V
REFIN x (D / 1024) (2) where D is the decimal equivalent of the binary code that is loaded into the DAC register. D can take on any value between 0 and 1023. This configuration ensures that the DAC is monotonic.
V
A
R
R
R
To Output Amplifier
R
R
Figure 29. DAC Resistor String
OUTPUT AMPLIFIERS
The output amplifiers are rail-to-rail, providing an output voltage range of 0V to V
A when the reference is V
A
. All amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and V
A in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the
, reference is less than V
A
, there is only a loss in linearity in the lowest codes. The output capabilities of the amplifier are described in the
Tables.
The output amplifiers are capable of driving a load of 2 k Ω in parallel with 1500 pF to ground or to V
A code and full-scale outputs for given load currents are available in the
Table.
. The zero-
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REFERENCE VOLTAGE
The DAC104S085 uses a single external reference that is shared by all four channels. The reference pin, V
REFIN
, is not buffered and has an input impedance of 30 k Ω . It is recommended that V
REFIN source with low output impedance. The reference voltage range is 1.0V to V
A be driven by a voltage
, providing the widest possible output dynamic range.
SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs and operates at clock rates up to 40 MHz. See the
for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the D
IN line is clocked into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register, it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Serial Timing Diagram,
). On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel address, mode of operation and/or register contents) is executed. At this point the SYNC line may be kept low or brought high. Any data and clock pusles after the 16th falling clock edge will be ignored. In either case, SYNC must be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of SYNC.
Since the SYNC and D
IN buffers draw more current when they are high, they should be idled low between write sequences to minimize power consumption.
INPUT SHIFT REGISTER
The input shift register,
Figure 30 , has sixteen bits. The first two bits are address bits. They determine whether
the register data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that determine the mode of operation (writing to a DAC register without updating the outputs of all four DACs, writing to a DAC register and updating the outputs of all four DACs, writing to the register of all four DACs and updating their outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The data format is straight binary (MSB first, LSB last), with all 0's corresponding to an output of 0V and all 1's corresponding to a full-scale output of V
REFIN
- 1 LSB. The contents of the serial input register are transferred to the DAC register on the sixteenth falling edge of SCLK. See Timing Diagram,
MSB LSB
A1 A0 OP1 OP0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D
DATA BITS
0 0 Write to specified register but do not update outputs.
0 1 Write to specified register and update outputs.
1 0 Write to all registers and update outputs.
1 1 Power-down outputs.
Figure 30. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and there is no change in the mode of operation or in the DAC output voltages.
POWER-ON RESET
The power-on reset circuit controls the output voltages of the four DACs during power-up. Upon application of power, the DAC registers are filled with zeros and the output voltages are 0V. The outputs remain at 0V until a valid write sequence is made to the DAC.
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POWER-DOWN MODES
The DAC104S085 has four power-down modes, two of which are identical. In power-down mode, the supply current drops to 20 µA at 3V and 30 µA at 5V. The DAC104S085 is set in power-down mode by setting OP1 and
OP0 to 11. Since this mode powers down all four DACs, the address bits, A1 and A0, are used to select different output terminations for the DAC outputs. Setting A1 and A0 to 00 or 11 causes the outputs to be tri-stated (a high impedance state). While setting A1 and A0 to 01 or 10 causes the outputs to be terminated by 2.5 k Ω or 100 k Ω to ground respectively (see
A1
0
0
1
1
A0
0
1
0
1
Table 1. Power-Down Modes
OP1
1
1
1
1
OP0
1
1
1
1
Operating Mode
High-Z outputs
2.5 k Ω to GND
100 k Ω to GND
High-Z outputs
The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the power-down modes. However, the contents of the DAC registers are unaffected when in power-down. Each DAC register maintains its value prior to the DAC104S085 being powered down unless it is changed during the write sequence which instructed it to recover from power down. Minimum power consumption is achieved in the power-down mode with SYNC and D
IN
Time) is typically t
WU idled low and SCLK disabled. The time to exit power-down (Wake-Up
µsec as stated in the
A.C. and Timing Characteristics
table.
Applications Information
USING REFERENCES AS POWER SUPPLIES
While the simplicity of the DAC104S085 implies ease of use, it is important to recognize that the path from the reference input (V
REFIN
) to the VOUTs will have essentially zero Power Supply Rejection Ratio (PSRR).
Therefore, it is necessary to provide a noise-free supply voltage to V
REFIN range of the DAC104S085, the supply pin (V
A
) and V
REFIN
. In order to utilize the full dynamic can be connected together and share the same supply voltage. Since the DAC104S085 consumes very little power, a reference source may be used as the reference input and/or the supply voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some low noise regulators can also be used. Listed below are a few reference and power supply options for the DAC104S085.
LM4130
The LM4130, with its 0.05% accuracy over temperature, is a good choice as a reference source for the
DAC104S085. The 4.096V version is useful if a 0 to 4.095V output range is desirable or acceptable. Bypassing the LM4130 VIN pin with a 0.1µF capacitor and the VOUT pin with a 2.2µF capacitor will improve stability and reduce output noise. The LM4130 comes in a space-saving 5-pin SOT23.
Input
Voltage
C1
0.1
P
F
LM4132-4.1
C2
2.2
P
F
C3
0.1
P
F
V
A
V
REFIN
DAC104S085
V
OUT
= 0V to 4.092V
SYNC
DIN
SCLK
Figure 31. The LM4130 as a power supply
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LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the
DAC104S085. It is available in 4.096V and 5V versions and comes in a space-saving 3-pin SOT23.
Input
Voltage
R
V
Z
I
Z
LM4050-4.1 or
LM4050-5.0
I
DAC
0.47
P
F
V
A
V
REFIN
DAC104S085
SYNC
DIN
SCLK
0.1
P
F
V
OUT
= 0V to 5V
Figure 32. The LM4050 as a power supply
The minimum resistor value in the circuit of
must be chosen such that the maximum current through the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at its maximum, the LM4050 voltage at its minimum, and the DAC104S085 drawing zero current. The maximum resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum
DAC104S085 current in full operation. The conditions for minimum current include the input voltage at its minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the
DAC104S085 draws its maximum current. These conditions can be summarized as
R(min) = ( V
IN
(max) − V
Z
(min) ) /I
Z
(max) (3) and
R(max) = ( V
IN
(min) − V
Z
(max) ) / ( (I
DAC
(max) + I
Z
(min) ) where
• V
Z
(min) and V temperature
Z
(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
• I
Z
(max) is the maximum allowable current through the LM4050
• I
Z
(min) is the minimum current required by the LM4050 for proper regulation
• I
DAC
(max) is the maximum DAC104S085 supply current.
(4)
LP3985
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good choice for applications that do not require a precision reference for the DAC104S085. It comes in 3.0V, 3.3V and
5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Since low frequency noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
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Input
Voltage
1
P
F
LP3985
0.01
P
F
0.1
P
F
V
A
V
REFIN
DAC104S085
SYNC
DIN
V
OUT
= 0V to 5V
SCLK
0.1
P
F
Figure 33. Using the LP3985 regulator
An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF ceramic capacitor with an ESR requirement of 5m
Ω to 500m
Ω is required at the output. Careful interpretation and understanding of the capacitor specification is required to ensure correct device operation.
LP2980
The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon grade. It is available in 3.0V, 3.3V and 5V versions, among others.
Input
Voltage
V
IN
LP2980
V
OUT
ON /OFF
1
P
F
0.1
P
F
V
A
V
REFIN
DAC104S085
SYNC
DIN
SCLK
V
OUT
= 0V to 5V
Figure 34. Using the LP2980 regulator
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The
ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors are typically not a good choice due to their large size and have ESR values that may be too high at low temperatures.
BIPOLAR OPERATION
The DAC104S085 is designed for single supply operation and thus has a unipolar output. However, a bipolar output may be obtained with the circuit in
. This circuit will provide an output voltage range of ±5 Volts.
A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.
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+5V
10
P
F
+
0.1
P
F
R
1
10 pF
R
2
-
+
+5V
-5V
DAC104S085
SYNC
DIN
V
OUT
SCLK
Figure 35. Bipolar Operation
The output voltage of this circuit for any code is found to be
V
O
= (V
A x (D / 1024) x ((R1 + R2) / R1) - V
A x R2 / R1) where
• D is the input code in decimal form
• With V
A
= 5V and R1 = R2
V
O
= (10 x D / 1024) - 5V
A list of rail-to-rail amplifiers suitable for this application are indicated in
.
±5V
(5)
(6)
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AMP
Table 2. Some Rail-to-Rail Amplifiers
LMC7111
LM7301
LM8261
PKGS
DIP-8
SOT23-5
SO-8
SOT23-5
SOT23-5
Typ V
OS
0.9 mV
0.03 mV
0.7 mV
Typ I
SUPPLY
25 µA
620 µA
1 mA
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DSP/MICROPROCESSOR INTERFACING
Interfacing the DAC104S085 to microprocessors and DSPs is quite simple. The following guidelines are offered to hasten the design process.
ADSP-2101/ADSP2103 Interfacing
shows a serial interface between the DAC104S085 and the ADSP-2101/ADSP2103. The DSP should be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
ADSP-2101/
ADSP2103
TFS
DT
SCLK
DAC104S085
SYNC
DIN
SCLK
Figure 36. ADSP-2101/2103 Interface
80C51/80L51 Interface
A serial interface between the DAC104S085 and the 80C51/80L51 microcontroller is shown in
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is transmitted to the DAC104S085. Since the 80C51/80L51 transmits 8-bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the
80C51/80L51 transmits data with the LSB first while the DAC104S085 requires data with the MSB first.
80C51/80L51
P3.3
TXD
RXD
DAC104S085
SYNC
SCLK
DIN
Figure 37. 80C51/80L51 Interface
68HC11 Interface
A serial interface between the DAC104S085 and the 68HC11 microcontroller is shown in
. The SYNC line of the DAC104S085 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.
The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the second byte of data to the DAC, after which PC7 should be raised to end the write sequence.
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68HC11
PC7
SCK
MOSI
DAC104S085
SYNC
SCLK
DIN
Figure 38. 68HC11 Interface
Microwire Interface
shows an interface between a Microwire compatible device and the DAC104S085. Data is clocked out on the rising edges of the SK signal. As a result, the SK of the Microwire device needs to be inverted before driving the SCLK of the DAC104S085.
MICROWIRE
DEVICE
CS
SK
SO
DAC104S085
SYNC
SCLK
DIN
Figure 39. Microwire Interface
LAYOUT, GROUNDING, AND BYPASSING
For best accuracy and minimum noise, the printed circuit board containing the DAC104S085 should have separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located in the same board layer. There should be a single ground plane. A single ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate ground planes must be connected in one place, preferably near the DAC104S085. Special care is required to ensure that digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous return path below their traces.
The DAC104S085 power supply should be bypassed with a 10µF and a 0.1µF capacitor as close as possible to the device with the 0.1µF right at the device supply pin. The 10µF capacitor should be a tantalum type and the
0.1µF capacitor should be a low ESL, low ESR type. The power supply for the DAC104S085 should only be used for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the board. The clock and data lines should have controlled impedances.
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REVISION HISTORY
Changes from Revision E (March 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
DAC104S085CIMM/NOPB
DAC104S085CIMMX/NOPB
Status
(1)
ACTIVE
ACTIVE
Package Type Package
Drawing
VSSOP
VSSOP
DGS
DGS
Pins Package
10
10
Qty
Eco Plan
(2)
1000 Green (RoHS
& no Sb/Br)
3500 Green (RoHS
& no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
CU SN Level-1-260C-UNLIM
CU SN Level-1-260C-UNLIM
Op Temp (°C)
-40 to 105
-40 to 105
X68C
X68C
Device Marking
(4/5)
DAC104S085CISD/NOPB
DAC104S085CISDX/NOPB
DAC104S085QIMM/NOPB
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
VSSOP
DSC
DSC
DGS
10
10
10
1000 Green (RoHS
& no Sb/Br)
4500 Green (RoHS
& no Sb/Br)
1000 Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 105
-40 to 105
-40 to 125
X69C
X69C
X68Q
DAC104S085QIMMX/NOPB ACTIVE VSSOP DGS 10 3500 Green (RoHS
& no Sb/Br)
CU SN Level-1-260C-UNLIM -40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
X68Q
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC104S085, DAC104S085-Q1 :
•
Catalog: DAC104S085
•
Automotive: DAC104S085-Q1
NOTE: Qualified Version Definitions:
•
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
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TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
23-Sep-2013
*All dimensions are nominal
Device Package
Type
Package
Drawing
DAC104S085CIMM/NOPB VSSOP DGS
DAC104S085CIMMX/NOP
B
VSSOP
DAC104S085CISD/NOPB WSON
DGS
DSC
DAC104S085CISDX/NOP
B
DAC104S085QIMM/NOP
B
DAC104S085QIMMX/NO
PB
WSON
VSSOP
DSC
DGS
VSSOP DGS
Pins
10
10
10
10
10
10
SPQ
1000
3500
1000
4500
1000
3500
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
178.0
12.4
330.0
12.4
A0
(mm)
5.3
5.3
B0
(mm)
3.4
3.4
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
1.4
1.4
8.0
8.0
12.0
12.0
Q1
Q1
178.0
330.0
178.0
330.0
12.4
12.4
12.4
12.4
3.3
3.3
5.3
5.3
3.3
3.3
3.4
3.4
1.0
1.0
1.4
1.4
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
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PACKAGE MATERIALS INFORMATION
23-Sep-2013
*All dimensions are nominal
Device
DAC104S085CIMM/NOPB
DAC104S085CIMMX/NOP
B
DAC104S085CISD/NOPB
DAC104S085CISDX/NOP
B
DAC104S085QIMM/NOPB
DAC104S085QIMMX/NOP
B
Package Type Package Drawing Pins
VSSOP
VSSOP
DGS
DGS
10
10
WSON
WSON
VSSOP
VSSOP
DSC
DSC
DGS
DGS
10
10
10
10
SPQ
1000
3500
1000
4500
1000
3500
Length (mm) Width (mm) Height (mm)
210.0
367.0
185.0
367.0
35.0
35.0
210.0
367.0
210.0
367.0
185.0
367.0
185.0
367.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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