MAX7325 I C Port Expander with 8 Push-Pull and 8 Open-Drain I/Os

MAX7325 I C Port Expander with 8 Push-Pull and 8 Open-Drain I/Os
EVALUATION KIT AVAILABLE
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
General Description
The MAX7325 2-wire serial-interfaced peripheral features
16 I/O ports. Ports are divided into eight push-pull outputs and eight I/Os with selectable internal pullups and
transition detection. Eight ports are push-pull outputs
and eight I/Os may be used as a logic input or an opendrain output. Ports are overvoltage protected to +6V.
All I/O ports configured as inputs are continuously monitored for state changes (transition detection). State
changes are indicated by the INT output. The interrupt
is latched, allowing detection of transient changes.
When the MAX7325 is subsequently accessed through
the serial interface, any pending interrupt is cleared.
The open-drain outputs are rated to sink 20mA, and are
capable of driving LEDs. The RST input clears the serial
interface, terminating any I2C communication to or from
the MAX7325.
The MAX7325 uses two address inputs with four-level
logic to allow 16 I 2 C slave addresses. The slave
address also determines the power-up logic state for
the I/O ports, and enables or disables internal 40kΩ
pullups in groups of four ports.
The MAX7325 is one device in a family of pin-compatible
port expanders with a choice of input ports, open-drain
I/O ports, and push-pull output ports (see Table 1).
The MAX7325 is available in 24-pin QSOP and TQFN
packages and is specified over the -40°C to +125°C
automotive temperature range.
Applications
Cell Phones
SAN/NAS
Servers
o
o
o
o
o
o
o
o
o
o
o
400kHz
Serial Interface
+1.71V to +5.5V Operation
8 Push-Pull Outputs
8 Open-Drain I/O Ports, Rated to 20mA Sink
Current
I/O Ports are Overvoltage Protected to +6V
Selectable I/O Port Power-Up Default Logic States
Transient Changes are Latched, Allowing
Detection Between Read Operations
INT Output Alerts Change on Inputs
AD0 and AD2 Inputs Select from 16 Slave
Addresses
Low 0.6µA (typ) Standby Current
-40°C to +125°C Temperature Range
Ordering Information
PART
TEMP RANGE
AD0
O15
O14
O13
O12
O11
18
17
16
15
14
13
SCL 19
12 O10
SDA 20
11 O9
V+ 21
PIN-PACKAGE
MAX7325AEG+
-40°C to +125°C
24 QSOP
MAX7325AEG/V+
-40°C to +125°C
24 QSOP
MAX7325ATG+
-40°C to +125°C
24 TQFN-EP*
(4mm x 4mm)
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed paddle.
/V Denotes an automotive qualified part.
Notebooks
Satellite Radio
Automotive
Pin Configurations
TOP VIEW
Features
I2C
Selector Guide
OPENPUSH-PULL
DRAIN
OUTPUTS
OUTPUTS
PART
INPUTS
INTERRUPT
MASK
MAX7324
8
Yes
—
MAX7325
Up to 8
—
Up to 8
8
MAX7326
4
Yes
—
12
MAX7327
Up to 4
—
Up to 4
12
8
10 O8
MAX7325
INT 22
RST 23
1
2
3
4
5
6
P0
P1
P2
P3
P4
P5
AD2 24 +
EXPOSED PADDLE
9
GND
8
P7
7
P6
Typical Application Circuit and Functional Diagram appear
at end of data sheet.
TQFN (4mm x 4mm)
Pin Configurations continued at end of data sheet.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-3807; Rev 1; 9/12
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND.)
Supply Voltage V+....................................................-0.3V to +6V
SCL, SDA, AD0, AD2, RST, INT, P0–P7 ...................-0.3V to +6V
O8–O15 ........................................................-0.3V to (V+ + 0.3V)
O8–O15 Output Current ...................................................±25mA
P0–P7 Sink Current ......................................................................25mA
SDA Sink Current ........................................................................ 10mA
INT Sink Current..................................................................10mA
Total V+ Current..................................................................50mA
Total GND Current ...........................................................100mA
Continuous Power Dissipation (TA = +70°C)
24-Pin QSOP (derate 9.5mW/°C over +70°C)...........761.9mW
24-Pin TQFN (derate 20.8mW/°C over+70°C) ........1666.7mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
TYP
UNITS
5.50
V
1.6
V
V+
Power-On-Reset Voltage
VPOR
V+ falling
Standby Current
(Interface Idle)
ISTB
SCL and SDA and other TA = -40°C to
digital inputs at V+
+125°C
0.6
1.9
µA
fSCL = 400kHz; other
digital inputs at V+
23
55
µA
I+
Input High-Voltage
SDA, SCL, AD0, AD2, RST, P0–P7
VIH
Input Low-Voltage
SDA, SCL, AD0, AD2, RST, P0–P7
VIL
Input Leakage Current
SDA, SCL, AD0, AD2, RST, P0–P7
IIH, IIL
1.71
MAX
Operating Supply Voltage
Supply Current
(Interface Running)
TA = -40°C to +125°C
MIN
TA = -40°C to
+125°C
V+ < 1.8V
0.8 x V+
V+ ≥ 1.8V
0.7 x V+
V+ < 1.8V
0.2 x V+
V+ ≥ 1.8V
0.3 x V+
SDA, SCL, AD0, AD2, RST, P0–P7 at V+ or
GND, internal pullup disabled
-0.2
Input Capacitance
SDA, SCL, AD0, AD2, RST, P0–P7
Output Low Voltage
O8–O15, P0–P7
Output High Voltage
O8–O15
+0.2
10
VOL
VOH
90
V+ = +1.71V, ISINK = 5mA (TQFN)
90
230
V+ = +2.5V, ISINK = 10mA (QSOP)
110
210
V+ = +2.5V, ISINK = 10mA (TQFN)
110
260
V+ = +3.3V, ISINK = 15mA (QSOP)
130
230
V+ = +3.3V, ISINK = 15mA (TQFN)
130
280
V+ = +5V, ISINK = 20mA (QSOP)
140
250
V+ = +5V, ISINK = 20mA (TQFN)
140
300
V+ = +1.71V, ISOURCE = 2mA
V+ - 250 V+ - 30
V+ = +2.5V, ISOURCE = 5mA
V+ - 360 V+ - 70
V+ = +3.3V, ISOURCE = 5mA
V+ - 260 V+ - 100
V+ = +5V, ISOURCE = 10mA
V+ - 360 V+ - 120
VOLSDA
ISINK = 6mA
Output Low-Voltage INT
VOLINT
ISINK = 5mA
Port Input Pullup Resistor
RPU
25
V
µA
pF
V+ = +1.71V, ISINK = 5mA (QSOP)
Output Low-Voltage SDA
2
V
180
mV
mV
250
mV
130
250
mV
40
55
kΩ
Maxim Integrated
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
PORT AND INTERRUPT INT TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Port Output Data Valid
tPPV
CL ≤ 100pF
Port Input Setup Time
tPSU
CL ≤ 100pF
0
Port Input Hold Time
tPH
CL ≤ 100pF
4
INT Input Data Valid Time
tIV
CL ≤ 100pF
4
µs
INT Reset Delay Time from STOP
tIP
CL ≤ 100pF
4
µs
INT Reset Delay Time from
Acknowledge
tIR
CL ≤ 100pF
4
µs
4
µs
µs
µs
TIMING CHARACTERISTICS
(V+ = +1.71V to +5.5V, TA = -40°C to +125°C, unless otherwise noted. Typical values are at V+ = +3.3V, TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
Serial-Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
µs
Hold Time (Repeated) START
Condition
tHD, STA
0.6
µs
Repeated START Condition
Setup Time
tSU, STA
0.6
µs
STOP Condition Setup Time
tSU, STO
0.6
µs
Data Hold Time
tHD, DAT
Data Setup Time
tSU, DAT
100
ns
tLOW
tHIGH
1.3
0.7
µs
µs
SCL Clock Low Period
SCL Clock High Period
(Note 2)
0.9
µs
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Notes 3, 4)
20 +
0.1Cb
300
ns
Fall Time of Both SDA and SCL
Signals, Receiving
tF
(Notes 3, 4)
20 +
0.1Cb
300
ns
tF,TX
(Notes 3, 4)
20 +
0.1Cb
250
ns
Fall Time of SDA Transmitting
Pulse Width of Spike Suppressed
tSP
(Note 5)
Capacitive Load for Each Bus
Line
Cb
(Note 3)
RST Pulse Width
tW
500
ns
tRST
1
µs
RST Rising to START Condition
Setup Time
50
ns
400
pF
Note 1: All parameters are tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 3: Guaranteed by design.
Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 x V+ and 0.7 x V+.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Maxim Integrated
3
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
1.4
1.2
V+ = +5.0V
1.0
V+ = +3.3V
V+ = +2.5V
0.8
fSCL = 400kHz
50
0.6
0.4
40
30
V+ = +3.3V
20
V+ = +2.5V
V+ = +1.71V
10
V+ = +1.71V
0.2
0
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
OUTPUT VOLTAGE LOW
vs. TEMPERATURE
OUTPUT VOLTAGE HIGH
vs. TEMPERATURE
0.20
V+ = +3.3V
ISINK = 15mA
0.15
0.10
V+ = +2.5V
ISINK = 10mA
0.05
V+ = +1.71V
ISINK = 5mA
V+ = +5.0V
ISOURCE = 10mA
5
OUTPUT VOLTAGE HIGH (V)
V+ = +5.0V
ISINK = 20mA
6
MAX7325 toc03
0.25
OUTPUT VOLTAGE LOW (V)
V+ = +5.0V
4
MAX7325 toc04
STANDBY CURRENT (µA)
1.6
60
SUPPLY CURRENT (µA)
fSCL = 0kHz
1.8
MAX7325 toc01
2.0
MAX7325 toc02
SUPPLY CURRENT
vs. TEMPERATURE
STANDBY CURRENT
vs. TEMPERATURE
V+ = +3.3V
ISOURCE = 5mA
3
V+ = +2.5V ISOURCE = 5mA
V+ = +1.71V ISOURCE = 2mA
2
1
0
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
Pin Description
PIN
4
NAME
FUNCTION
QSOP
TQFN
1
22
INT
Interrupt Output, Active Low. INT is an open-drain output.
2
23
RST
Reset Input, Active Low. Drive RST low to clear the 2-wire interface.
3, 21
24, 18
AD2, AD0
4–11
1–8
P0–P7
12
9
GND
13–20
10–17
O8–O15
22
19
SCL
I2C-Compatible Serial-Clock Input
23
20
SDA
I2C-Compatible Serial-Data I/O
24
21
V+
Positive Supply Voltage. Bypass V+ to GND with a ceramic capacitor of at least 0.047µF.
—
—
EP
Exposed Paddle (TQFN Only). Connect exposed pad to GND.
Address Inputs. Select device slave address with AD0 and AD2. Connect AD0 and AD2
to either GND, V+, SCL, or SDA to give four logic combinations (see Tables 2 and 3).
Open-Drain I/O Ports
Ground
Output Ports. O8–O15 are push-pull outputs rated at 20mA.
Maxim Integrated
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Detailed Description
MAX7319–MAX7329 Family Comparison
The MAX7324–MAX7327 family consists of four pincompatible, 16-port expanders that integrate the functions of the MAX7320 and one of either MAX7319,
MAX7321, MAX7322, or MAX7323.
Functional Overview
The MAX7325 is a general-purpose port expander operating from a +1.71V to +5.5V supply with eight push-pull
outputs and eight open-drain I/O ports. Each open-drain
output is rated to sink 20mA, and the entire device is
rated to sink 100mA into all ports combined. The outputs
drive loads connected to supplies up to +5.5V.
The MAX7325 is set to two of 32 I2C slave addresses
(see Tables 2 and 3) using the address select inputs
AD0 and AD2, and is accessed over an I2C serial interface up to 400kHz. The eight outputs and eight I/Os
have different slave addresses. The eight push-pull outputs have the 101xxxx addresses and the eight inputs
have addresses with 110xxxx. The RST input clears the
serial interface in case of a bus lockup, terminating any
serial transaction to or from the MAX7325.
Configure any port as a logic input by setting the port
output logic-high (logic-high for an open-drain output is
high impedance). When the MAX7325 is read through
the serial interface, the actual logic levels at the ports
are read back.
Table 1. MAX7319–MAX7329 Family Comparison
PART
INPUT
I2C
SLAVE
INPUTS INTERRUPT
ADDRESS
MASK
OPENDRAIN
OUTPUTS
PUSHPULL
OUTPUTS
CONFIGURATION
16-PORT EXPANDERS
8 input and 8 push-pull output versions:
8 input ports with programmable latching transition
detection interrupt and selectable pullups.
8
MAX7324
Yes
—
8
8 push-pull outputs with selectable default logic
levels.
Offers maximum versatility for automatic input
monitoring. An interrupt mask selects which inputs
cause an interrupt on transitions, and transition flags
identify which inputs have changed (even if only
for a transient) since the ports were last read.
8 I/O and 8 push-pull output versions:
8 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
101xxxx
and
110xxxx
8 push-pull outputs with selectable default logic
levels.
MAX7325
Maxim Integrated
Up to 8
—
Up to 8
8
Open-drain outputs can level shift the logic-high
state to a higher or lower voltage than V+ using
external pullup resistors, but pullups draw current
when output is low. Any open-drain port can be used
as an input by setting the open-drain output to logichigh. Transition flags identify which open-drain port
inputs have changed (even if only for a transient)
since the ports were last read.
5
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Table 1. MAX7319–MAX7329 Family Comparison (continued)
PART
INPUT
I2C
SLAVE
INPUTS INTERRUPT
ADDRESS
MASK
OPENDRAIN
OUTPUTS
PUSHPULL
OUTPUTS
CONFIGURATION
4 input-only, 12 push-pull output versions:
4 input ports with programmable latching transition
detection interrupt and selectable pullups.
4
MAX7326
Yes
—
12
12 push-pull outputs with selectable default logic
levels.
Offers maximum versatility for automatic input
monitoring. An interrupt mask selects which inputs
cause an interrupt on transitions, and transition flags
identify which inputs have changed (even if only
for a transient) since the ports were last read.
4 I/O, 12 push-pull output versions:
4 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
101xxxx
and
110xxxx
12 push-pull outputs with selectable default logic
levels.
MAX7327
Up to 4
—
Up to 4
12
Open-drain outputs can level shift the logic-high
state to a higher or lower voltage than V+ using
external pullup resistors, but pullups draw current
when output is low. Any open-drain port can be used
as an input by setting the open-drain output to logichigh. Transition flags identify which open-drain port
inputs have changed (even if only for a transient)
since the ports were last read.
8-PORT EXPANDERS
MAX7319
110xxxx
8
Yes
—
—
Input-only versions:
8 input ports with programmable latching transition
detection interrupt and selectable pullups.
MAX7320
101xxxx
—
—
—
8
Output-only versions:
8 push-pull outputs with selectable power-up default
levels.
MAX7321
110xxxx
Up to 8
—
Up to 8
—
I/O versions:
8 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
4
4 input-only, 4 output-only versions:
4 input ports with programmable latching transition
detection interrupt and selectable pullups.
4 push-pull outputs with selectable power-up default
levels.
MAX7322
6
110xxxx
4
Yes
—
Maxim Integrated
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Table 1. MAX7319–MAX7329 Family Comparison (continued)
PART
INPUT
I2C
SLAVE
INPUTS INTERRUPT
ADDRESS
MASK
OPENDRAIN
OUTPUTS
PUSHPULL
OUTPUTS
CONFIGURATION
MAX7323
110xxxx
Up to 4
—
Up to 4
4
4 I/O, 4 output-only versions:
4 open-drain I/O ports with latching transition
detection interrupt and selectable pullups.
4 push-pull outputs with selectable power-up default
levels.
MAX7328
MAX7329
0100xxx
0111xxx
Up to 8
—
Up to 8
—
8 open-drain I/O ports with nonlatching transition
detection interrupt and pullups on all ports.
The open-drain ports offer latching transition detection
when used as inputs. All input ports are continuously
monitored for changes. An input change sets one of 8
flag bits that identify changed input(s). All flags are
cleared upon a subsequent read or write transaction to
the MAX7325.
A latching interrupt output, INT, is programmed to flag
logic changes on ports used as inputs. Data changes
on any input port forces INT to a logic-low. Changing
the I/O port level through the serial interface does not
cause an interrupt. The interrupt output INT is deasserted when the MAX7325 is next accessed through the
serial interface.
Internal pullup resistors to V+ are selected by the
address select inputs, AD0 and AD2. Pullups are
enabled on the input ports in groups of four (see Table 2).
Use the slave address selection to ensure that I/O ports
used as inputs are logic-high on power-up. I/O ports
with internal pullups enabled default to a logic-high output state. I/O ports with internal pullups disabled
default to a logic-low output state.
Output port power-up logic levels are selected by the
address select inputs, AD0 and AD2. Ports default to
logic-high or logic-low on power-up in groups of four
(see Tables 2 and 3).
Initial Power-Up
On power-up, the transition detection logic is reset, and
INT is deasserted. The transition flags are cleared to indicate no data changes. The power-up default states of the
16 I/O ports are set according to the I2C slave address
selection inputs, AD0 and AD2 (Tables 2 and 3). For I/O
ports used as inputs, ensure that the default states are
logic-high so that the I/O ports power up in the highimpedance state. All I/O ports configured with pullups
enabled also have a logic-high power-up state.
Maxim Integrated
Power-On Reset
The MAX7325 contains an integral power-on-reset
(POR) circuit that ensures all registers are reset to a
known state on power-up. When V+ rises above VPOR
(1.6V max), the POR circuit releases the registers and
2-wire interface for normal operation. When V+ drops to
less than VPOR, the MAX7325 resets all register contents to the POR defaults (Tables 2 and 3).
RST Input
The active-low RST input voids any I 2C transaction
involving the MAX7325, forcing the MAX7325 into the
I2C STOP condition. A reset does not affect the interrupt output (INT).
Standby Mode
When the serial interface is idle, the MAX7325 automatically enters standby mode, drawing minimal supply current.
Slave Address, Power-Up Default Logic
Levels, and Input Pullup Selection
Address inputs AD0 and AD2 determine the MAX7325
slave address, set the power-up I/O state for the ports,
and select which inputs have pullup resistors. Internal
pullups and power-up default states are set in groups
of four (see Table 2).
The MAX7325 slave address is determined on each I2C
transmission, regardless of whether the transmission is
actually addressing the MAX7325. The MAX7325 distinguishes whether address inputs AD0 and AD2 are connected to SDA or SCL instead of fixed logic levels V+
or GND during this transmission. The MAX7325 slave
address can be configured dynamically in the application without cycling the device supply.
On initial power-up, the MAX7325 cannot decode the
address inputs AD0 and AD2 fully until the first I2C
transmission. AD0 and AD2 initially appear to be
7
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
There are circumstances where the assumption that
SDA = SCL = V+ on power-up is not true—for example,
in applications in which there is legitimate bus activity
during power-up. If SDA and SCL are terminated with
pullup resistors to a different supply voltage than the
MAX7325’s supply voltage, and if that pullup supply
rises later than the MAX7325’s supply, then SDA or
SCL may appear at power-up to be connected to GND.
In such applications, use the four address combinations that are selected by connecting address inputs
AD0 and AD2 to V+ or GND (shown in bold in Tables 2
and 3). These selections are guaranteed to be correct
at power-up, independent of SDA and SCL behavior. If
one of the other 12 address combinations is used, an
unexpected combination of pullups might be asserted
until the first I2C transmission (to any device, not necessarily the MAX7325) is put on the bus, and an unexpected combination of ports can initialize as logic-low
outputs instead of inputs or logic-high outputs.
connected to V+ or GND. This is important because the
address selection is used to determine the power-up
logic state and whether pullups are enabled. At powerup, the I2C SDA and SCL bus interface lines are high
impedance at the inputs of every device (master or
slave) connected to the bus, including the MAX7325.
This is guaranteed as part of the I 2C specification.
Therefore, when address inputs AD0 and AD2 are connected to SDA or SCL during power-up, they appear to
be connected to V+.
The power-up logic uses AD0 to select the power-up
state and whether pullups are enabled for ports P0–P3,
and AD2 for ports P4–P7. The rule is that a logic-high,
SDA, or SCL connection selects the pullups and sets
the default logic state to high. A logic-low deselects the
pullups and sets the default logic state to low (Table 2).
The port configuration is correct on power-up for a
standard I 2 C configuration, where SDA or SCL are
pulled up to V+ by the external I2C pullup resistors.
Table 2. MAX7325 Address Map for Ports P0–P7
PIN
CONNECTION
8
DEVICE ADDRESS
PORT POWER-UP DEFAULT
A6 A5 A4 A3 A2 A1 A0
40kΩ INPUT PULLUPS ENABLED
AD2
AD0
P7
P6
P5
P4
P3
P2
P1
P0
P4 P3 P2 P1
P0
SCL
GND
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
P7 P6 P5
Y
Y
Y
Y
—
—
—
—
SCL
V+
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
SCL
SCL
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
SCL
SDA
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
SDA
GND
1
1
0
0
1
0
0
1
1
1
1
0
0
0
0
Y
Y
Y
Y
—
—
—
—
SDA
V+
1
1
0
0
1
0
1
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
Y
SDA
SCL
1
1
0
0
1
1
0
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
SDA
SDA
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
GND
GND
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
—
—
—
—
—
—
—
—
GND
V+
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
—
—
—
—
Y
Y
Y
Y
GND
SCL
1
1
0
1
0
1
0
0
0
0
0
1
1
1
1
—
—
—
—
Y
Y
Y
Y
GND
SDA
1
1
0
1
0
1
1
0
0
0
0
1
1
1
1
—
—
—
—
Y
Y
Y
Y
V+
GND
1
1
0
1
1
0
0
1
1
1
1
0
0
0
0
Y
Y
Y
Y
—
—
—
—
V+
V+
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
V+
SCL
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
V+
SDA
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
Y
Y
Y
Y
Y
Y
Y
Y
Maxim Integrated
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Table 3. MAX7325 Address Map for Outputs O8–O15
PIN
CONNECTION
DEVICE ADDRESS
OUTPUTS POWER-UP DEFAULT
AD2
AD0
A6
A5
A4
A3
A2
A1
A0
O15
O14
O13
O12
O11
O10
O9
O8
SCL
GND
1
0
1
0
0
0
0
1
1
1
1
0
0
0
0
SCL
V+
1
0
1
0
0
0
1
1
1
1
1
1
1
1
1
SCL
SCL
1
0
1
0
0
1
0
1
1
1
1
1
1
1
1
SCL
SDA
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
SDA
GND
1
0
1
0
1
0
0
1
1
1
1
0
0
0
0
SDA
V+
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
SDA
SCL
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
SDA
SDA
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
GND
GND
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
GND
V+
1
0
1
1
0
0
1
0
0
0
0
1
1
1
1
GND
SCL
1
0
1
1
0
1
0
0
0
0
0
1
1
1
1
GND
SDA
1
0
1
1
0
1
1
0
0
0
0
1
1
1
1
V+
GND
1
0
1
1
1
0
0
1
1
1
1
0
0
0
0
V+
V+
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
V+
SCL
1
0
1
1
1
1
0
1
1
1
1
1
1
1
1
V+
SDA
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
Port Inputs
I/O port inputs switch at the CMOS-logic levels as
determined by the expander’s supply voltage, and are
overvoltage tolerant to +6V, independent of the
expander’s supply voltage.
I/O Port Input Transition Detection
All I/O ports configured as inputs are monitored for
changes since the expander was last accessed through
the serial interface. The state of the ports is stored in an
Maxim Integrated
internal “snapshot” register for transition monitoring. The
snapshot is continuously compared with the actual input
conditions, and if a change is detected for any port input,
INT is asserted to signal a state change. The input ports
are sampled (internally latched into the snapshot register)
and the old transition flags cleared during the I2C acknowledge of every MAX7325 read and write access. The previous port transition flags are read through the serial
interface as the second byte of a 2-byte read sequence.
9
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Serial Interface
Serial Addressing
The MAX7325 operates as a slave that sends and
receives data through an I2C interface. The interface
uses a serial-data line (SDA) and a serial-clock line (SCL)
to achieve bidirectional communication between master(s) and slave(s). The master initiates all data transfers
to and from the MAX7325 and generates the SCL clock
that synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain output. A pullup resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a single-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7325’s 7-bit slave
addresses plus R/W bits, 1 or more data bytes, and
finally a STOP condition (Figure 2).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
SDA
tLOW
tBUF
tSU,STA
tSU,DAT
tHD,STA
tSU,STO
tHD,DAT
tHIGH
SCL
tHD,STA
tR
tF
START CONDITION
REPEATED START CONDITION
STOP
CONDITION
START
CONDITION
Figure 1. 2-Wire Serial Interface Timing Details
SDA
SDA
SCL
S
P
START
CONDITION
STOP
CONDITION
Figure 2. START and STOP Conditions
10
SCL
DATA LINE STABLE; CHANGE OF DATA
DATA VALID
ALLOWED
Figure 3. Bit Transfer
Maxim Integrated
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Acknowledge
The acknowledge bit is a clocked 9th bit the recipient
uses to acknowledge receipt of each byte of data
(Figure 4). Each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge
clock pulse, such that the SDA line is stable low during
the high period of the clock pulse. When the master is
transmitting to the MAX7325, the device generates the
acknowledge bit because the MAX7325 is the recipient. When the MAX7325 is transmitting to the master,
the master generates the acknowledge bit because the
master is the recipient.
address are always 1, 1, and 0 (P0–P7) or 1, 0, and 1
(O8 to O15). Connect AD0 and AD2 to GND, V+, SDA,
or SCL to select the slave address bits A3, A2, A1, and
A0. The MAX7325 has 16 possible pairs of slave
addresses (Tables 2 and 3), allowing up to 16
MAX7325 devices on an I2C bus.
Accessing the MAX7325
The MAX7325 is accessed though an I2C interface. The
MAX7325 has two different 7-bit slave addresses for
either the eight open-drain I/O ports (P0–P7) or the
eight push-pull ports (O8–O15). See Tables 2 and 3.
A single-byte read from the I/O ports (P0–P7) of the
MAX7325 returns the status of the eight I/O ports and
clears both the internal transition flags and the INT output when the master acknowledges the slave address
byte. A single-byte read from the eight push-pull ports
(O8–O15) returns the status of the eight output ports,
read back as inputs.
A 2-byte read from the I/O ports (P0–P7) of the
MAX7325 returns the status of the eight I/O ports (as for
a single-byte read), followed by the transition flags.
Again, the internal transition flags and the INT output
are cleared when the master acknowledges the slave
address byte, yet the previous transition flag data is
sent as the second byte. A 2-byte read from the pushpull ports of the MAX7325 repeatedly returns the status
of the eight output ports, read back as inputs.
A multibyte read (more than 2 bytes before the I2C
STOP bit) from the I/O ports (P0–P7) of the MAX7325
repeatedly returns the port data, followed by the transition flags. As the port data is resampled for each transmission, and the transition flags are reset each time, a
multibyte read continuously returns the current data
and identifies any changing input ports.
Slave Address
Each MAX7325 has two different 7-bit slave addresses
(Tables 2 and 3). The addresses are different to communicate to either the eight push-pull outputs or the eight I/Os.
The 8th bit of the slave address following the 7-bit slave
address is the R/W bit. It is low for a write command, and
high for a read command (Figure 5). The first (A6), second (A5), and third (A4) bits of the MAX7325 slave
CLOCK PULSE
FOR ACKNOWLEDGEMENT
START
CONDITION
SCL
1
2
8
9
SDA BY
TRANSMITTER
SDA BY
RECEIVER
S
Figure 4. Acknowledge
SDA
A5
MSB
A4
A3
A2
A1
A0
R/W
ACK
LSB
SCL
Figure 5. Slave Address
Maxim Integrated
11
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Reading the MAX7325
A read from the open-drain I/O ports of the MAX7325
starts with the master transmitting the port group’s
slave address with the R/W bit set to high. The
MAX7325 acknowledges the slave address, and samples the ports during the acknowledge bit. INT
deasserts during the slave address acknowledge.
Typically, the master reads 1 or 2 bytes from the
MAX7325, each byte being acknowledged by the master upon reception with the exception of the last byte.
When the master reads one byte from the open-drain
ports of the MAX7325 and subsequently issues a STOP
condition (Figure 6), the MAX7325 transmits the current
port data, clears the change flags, and resets the transition detection. INT deasserts during the slave
If a port input data change occurs during the read
sequence, then INT is reasserted during the I2C STOP
bit. The MAX7325 does not generate another interrupt
during a single-byte or multibyte read.
Input port data is sampled during the preceding I2C
acknowledge bit (the acknowledge bit for the I2C slave
address in the case of a single-byte or two-byte read).
A multibyte read from the push-pull ports of the
MAX7325 repeatedly returns the status of the eight output ports, read back as inputs.
A single-byte write to either port groups of the
MAX7325 sets the logic state of all eight ports.
A multibyte write to either port group of the MAX7325
repeatedly sets the logic state of all eight ports.
PORT I/O
ACKNOWLEDGE
FROM MAX7325
S
1
1
0
MAX7325 SLAVE ADDRESS
1
P7
A
R/W
D7
P6
P5
D6
P4
D5
D4
P3
P2
D3
PORT SNAPSHOT
D2
P1
ACKNOWLEDGE
FROM MASTER
P0
D1
D0
N
P
PORT SNAPSHOT
SCL
tPH
PORT
tIV
tPSU
tIR
INT OUTPUT
tIP
INT REMAINS HIGH UNTIL STOP CONDITION
S = START CONDITION
P = STOP CONDITION
SHADED = SLAVE TRANSMISSION
N = NOT ACKNOWLEDGE
Figure 6. Reading Open-Drain Ports of the MAX7325 (1 Data Byte)
12
Maxim Integrated
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
acknowledge. The new snapshot data is the current
port data transmitted to the master, and therefore, port
changes occuring during the transmission are detected. INT remains high until the STOP condition.
The master can read 2 bytes from the open-drain ports
of the MAX7325 and subsequently issues a STOP condition (Figure 7). In this case, the MAX7325 transmits
the current port data, followed by the change flags. The
change flags are then cleared, and transition detection
is reset. INT goes high (high impedance if an external
pullup resistor is not fitted) during the slave acknowledge. The new snapshot data is the current port data
transmitted to the master, and therefore, port changes
occuring during the transmission are detected. INT
remains high until the STOP condition.
A read from the push-pull ports of the MAX7325 starts
with the master transmitting the group’s slave address
with the R/W bit set high. The MAX7325 acknowledges
the slave address, and samples the logic state of the
output ports during the acknowledge bit. The master can
read one or more bytes from the push-pull ports of the
MAX7325 and then issues a STOP condition (Figure 8).
The MAX7325 transmits the current port data, read
back from the actual port outputs (not the port output
latches) during the acknowledge. If a port is forced to a
logic state other than its programmed state, the readback reflects this. If driving a capacitive load, the readback port level verification algorithms may need to take
the RC rise/fall time into account.
PORT INPUTS
ACKNOWLEDGE
FROM MAX7325
S
1
1
0 MAX7325 SLAVE ADDRESS 1
I6
I7
A
D7
R/W
D6
I5
D5
I4
I3
D4
INTERRUPT FLAGS
I1
I2
D3
D2
I0
D1
D0
F7
A
D7
F6
F5
D6
F4
D5
D4
F3
D3
D2
D1
F0
D0
ACKNOWLEDGE
FROM MASTER
N
P
PORT SNAPSHOT
PORT SNAPSHOT
PORT SNAPSHOT
F1
F2
SCL
tPH
PORTS
tPSU
tIV
tIR
INT OUTPUT
tIP
INT REMAINS HIGH UNTIL STOP CONDITION
S = START CONDITION
P = STOP CONDITION
SHADED = SLAVE TRANSMISSION
N = NOT ACKNOWLEDGE
Figure 7. Reading Open-Drain Ports of the MAX7325 (2 Data Bytes)
P7
PORT SNAPSHOT DATA
P6
P5
P4
P3
DATA 1
P2
P1
P0
ACKNOWLEDGE FROM MAX7325
S
MAX7325 SLAVE ADDRESS
1
R/W
A
D7
D6
D5
D4
PORT SNAPSHOT TAKEN
D3
D2
D1
D0
PORT SNAPSHOT TAKEN
A
P
ACKNOWLEDGE
FROM MASTER
SCL
Figure 8. Reading Push-Pull Ports of MAX7325
Maxim Integrated
13
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Typically, the master reads one byte from the push-pull
ports of the MAX7325, then issues a STOP condition
(Figure 8). However, the master can read two or more
bytes from the group B ports of the MAX7325, then
issues a STOP condition. In this case, the MAX7325
resamples the port outputs during each acknowledge
and transmits the new data each time.
Writing the MAX7325
A write to either output port groups of the MAX7325
starts with the master transmitting the group’s slave
address with the R/W bit set low. The MAX7325
acknowledges the slave address and samples the
ports during the acknowledge bit. INT goes high (high
impedance if an external pullup resistor is not fitted)
during the slave acknowledge only when it writes to the
open-drain ports. The master can now transmit one or
more bytes of data. The MAX7325 acknowledges these
subsequent bytes of data and updates the corresponding group’s ports with each new byte until the master
issues a STOP condition (Figure 9).
Applications Information
Port Input and I2C Interface Level
Translation from Higher or
Lower Logic Voltages
The MAX7325’s SDA, SCL, AD0, AD2, RST, INT, O8–O15,
and P0–P7 are overvoltage protected to +6V. This
allows the MAX7325 to operate from a lower supply
voltage, such as +3.3V, while the I2C interface and/or
any of the eight I/O ports are driven as inputs from a
higher logic level, such as +5V.
1
SCL
2
3
4
5
6
7
S
START CONDITION
Port Output Signal-Level Translation
The open-drain output architecture allows for level translation to higher or lower voltages than the MAX7325’s
supply. Use an external pullup resistor on any output to
convert the high-impedance logic-high condition to a
positive voltage level. The resistor can be connected to
any voltage up to +6V, and the resistor value chosen to
ensure no more than 20mA is sunk in the logic-low condition. For interfacing CMOS inputs, a pullup resistor value
of 220kΩ is a good starting point. Use a lower resistance
to improve noise immunity, in applications where power
consumption is less critical, or where a faster rise time is
needed for a given capacitive load.
Each of the push-pull output ports has protection
diodes to V+ and GND. When a port output is driven to
a voltage higher than V+ or lower than GND, the appropriate protection diode clamps the output to a diode
drop above V+ or below GND. When the MAX7325 is
powered down (V+ = 0V), every output port’s protection
8
DATA TO INTERRUPT MASK
SLAVE ADDRESS
SDA
The MAX7325 can operate from a higher supply voltage, such as +3V, while the I2C interface and/or some
of the I/O ports P0–P7 are driven from a lower logic
level, such as +2.5V. For V+ < 1.8V, apply a minimum
voltage of 0.8 x V+ to assert a logic-high on any input.
For a V+ ≥ 1.8V, apply a voltage of 0.7 x V+ to assert a
logic-high. For example, a MAX7325 operating from a
+5V supply may not recognize a +3.3V nominal logichigh. One solution for input-level translation is to drive
MAX7325 I/Os from open-drain outputs. Use a pullup
resistor to V+ or a higher supply to ensure a high logic
voltage greater than 0.7 x V+.
0
A
DATA TO INTERRUPT MASK
A
DATA 1
R/W ACKNOWLEDGE
FROM SLAVE
A
DATA 2
ACKNOWLEDGE
FROM SLAVE
ACKNOWLEDGE
FROM SLAVE
INTERNAL WRITE
TO PORT
DATA OUT
FROM PORT
DATA 1 VALID
tPV
DATA 2 VALID
tPV
Figure 9. Writing to the MAX7325
14
Maxim Integrated
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
diodes to V+ and GND continue to appear as a diode
clamp from each output to GND (Figure 10).
Each of the I/O ports P0–P7 has a protection diode to
GND (Figure 11). When a port is driven to a voltage
lower than GND, the protection diode clamps the port
to a diode drop below GND.
Each of the I/O ports P0–P7 also has a 40kΩ (typ)
pullup resistor that can be enabled or disabled. When a
port input is driven to a voltage higher than V+, the
body diode of the pullup enable switch conducts and
the 40kΩ pullup resistor is enabled. When the
MAX7325 is powered down (V+ = 0V), each I/O port
appears as a 40kΩ resistor in series with a diode connected to 0V. Input ports are protected to +6V under
any of these circumstances (Figure 11).
Driving LED Loads
When driving LEDs from one of the outputs, a resistor
must be fitted in series with the LED to limit the LED
current to no more than 20mA. Connect the LED cathode to the MAX7325 port, and the LED anode to V+
through the series current-limiting resistor, RLED. Set
the port output low to illuminate the LED. Choose the
resistor value according to the following formula:
RLED = (VSUPPLY - VLED - VOL) / ILED
where:
RLED is the resistance of the resistor in series with the
LED (Ω).
VSUPPLY is the supply voltage used to drive the LED
(V).
V+
VLED is the forward voltage of the LED (V).
VOL is the output low voltage of the MAX7325 when
sinking ILED (V).
ILED is the desired operating current of the LED (A).
For example, to operate a 2.2V red LED at 10mA from a
+5V supply:
RLED = (5 - 2.2 - 0.1) / 0.01 = 270Ω
Driving Load Currents Higher than 20mA
The MAX7325 can be used to drive loads, such as relays
that draw more than 20mA, by paralleling outputs. Use at
least one output per 20mA of load current; for example, a
5V 330mW relay draws 66mA, and therefore, requires
four paralleled outputs. Any combination of outputs can
be used as part of a load-sharing design because any
combination of ports can be set or cleared at the same
time by writing to the MAX7325. Do not exceed a total
sink current of 100mA for the device.
The MAX7325 must be protected from the negativevoltage transient generated when switching off inductive loads (such as relays), by connecting a
reverse-biased diode across the inductive load.
Choose the peak current for the diode to be greater
than the inductive load’s operating current.
Power-Supply Considerations
The MAX7325 operates with a supply voltage of +1.71V
to +5.5V. Bypass the supply to GND with a ceramic
capacitor of at least 0.047µF as close as possible to the
device. For the TQFN version, additionally connect the
exposed pad to GND.
V+
V+
MAX7325
PULLUP
ENABLE
V+
MAX7325
40kΩ
O8–O15
P0–P7
INPUT
OUTPUT
OUTPUT
GND
GND
Figure 10. MAX7325 Push-Pull Output Port Structure
Maxim Integrated
Figure 11. MAX7325 Open-Drain I/O Port Structure
15
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Functional Diagram
Typical Application Circuit
3.3V
V+
µC
AD0
AD2
SCL
INPUT
SDA
FILTER
I2C
CONTROL
I/O
PORTS
SCL
SCL
SDA
RST
SDA
RST
INT
INT
MAX7325
O15
O14
O13
O12
O11
O10
O9
O8
INT
POWERON RESET
RST
O15
O14
O13
O12
O11
O10
O9
O8
P7
P6
P5
P4
P3
P2
P1
P0
AD0
AD2
MAX7325
GND
P7
P6
P5
P4
P3
P2
P1
P0
OUTPUT
OUTPUT
OUTPUT
OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT/OUTPUT
Chip Information
Pin Configurations (continued)
PROCESS: BiCMOS
TOP VIEW
INT 1
+
24 V+
RST 2
23 SDA
AD2 3
22 SCL
Package Information
21 AD0
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
P0 4
MAX7325
P1 5
20 O15
P2 6
19 O14
P3 7
18 O13
P4 8
17 O12
P5 9
16 O11
P6 10
15 O10
P7 11
14 O9
GND 12
13 O8
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
24 QSOP
E24+1
21-0055
90-0172
24 TQFN-EP
T2444+4
21-0139
90-0022
PACKAGE
TYPE
QSOP
16
Maxim Integrated
MAX7325
I2C Port Expander with 8 Push-Pull
and 8 Open-Drain I/Os
Revision History
REVISION
NUMBER
REVISION
DATE
0
9/06
Initial release
—
1
9/12
Added the MAX7325AEG/V+ to the Ordering Information
1
DESCRIPTION
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Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ________________________________ 17
© 2012 Maxim Integrated Products, Inc.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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