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TMS320VC5416
Fixed-Point Digital Signal Processor
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Literature Number: SPRS095P
March 1999 – Revised October 2008
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
www.ti.com
This data sheet revision history highlights the technical changes made to the SPRS095O device-specific data sheet to make it an SPRS095P revision.
Scope: This document has been reviewed for technical accuracy; the technical content is up-to-date as of the specified release date with the following corrections.
ADDITIONS/CHANGES/DELETIONS
, Signal Descriptions:
•
Updated DESCRIPTION of TRST
•
Added footnote about TRST
2
Revision History Submit Documentation Feedback
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TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
Contents
Revision History
1
...........................................................................................................................
TMS320VC5416 Features
.......................................................................................................
2
3
Introduction
.......................................................................................................................
2.1
2.2
Description
..................................................................................................................
Pin Assignments
............................................................................................................
2.2.1
Terminal Assignments for the GGU Package
...............................................................
2.2.2
Pin Assignments for the PGE Package
2.2.3
Signal Descriptions
......................................................................
..............................................................................................
Functional Overview
...........................................................................................................
3.1
Memory
......................................................................................................................
3.2
3.3
3.1.1
Data Memory
.....................................................................................................
3.1.2
Program Memory
................................................................................................
3.1.3
Extended Program Memory
...................................................................................
On-Chip ROM With Bootloader
...........................................................................................
On-Chip RAM
...............................................................................................................
3.4
3.5
3.6
3.7
3.8
3.9
On-Chip Memory Security
.................................................................................................
Memory Map
................................................................................................................
3.5.1
Relocatable Interrupt Vector Table
............................................................................
On-Chip Peripherals
.......................................................................................................
3.6.1
Software-Programmable Wait-State Generator
.............................................................
3.6.2
Programmable Bank-Switching
................................................................................
3.6.3
Bus Holders
......................................................................................................
Parallel I/O Ports
...........................................................................................................
3.7.1
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)
..........................................................
3.7.2
HPI Nonmultiplexed Mode
......................................................................................
Multichannel Buffered Serial Ports (McBSPs)
..........................................................................
Hardware Timer
............................................................................................................
3.10
Clock Generator
............................................................................................................
3.11
Enhanced External Parallel Interface (XIO2)
...........................................................................
3.12
DMA Controller
.............................................................................................................
3.12.1
Features
..........................................................................................................
3.12.2
DMA External Access
...........................................................................................
3.12.3
DMA Memory Maps
.............................................................................................
3.12.4
DMA Priority Level
...............................................................................................
3.12.5
DMA Source/Destination Address Modification
.............................................................
3.12.6
DMA in Autoinitialization Mode
................................................................................
3.12.7
DMA Transfer Counting
.........................................................................................
3.12.8
DMA Transfer in Doubleword Mode
..........................................................................
3.12.9
DMA Channel Index Registers
.................................................................................
3.12.10
DMA Interrupts
..................................................................................................
3.12.11
DMA Controller Synchronization Events
.....................................................................
3.13
General-Purpose I/O Pins
.................................................................................................
3.13.1
McBSP Pins as General-Purpose I/O
.........................................................................
3.13.2
HPI Data Pins as General-Purpose I/O
......................................................................
3.14
Device ID Register
.........................................................................................................
3.15
Memory-Mapped Registers
...............................................................................................
3.16
McBSP Control Registers and Subaddresses
..........................................................................
3.17
DMA Subbank Addressed Registers
3.18
Interrupts
....................................................................................
....................................................................................................................
4 Support
.............................................................................................................................
Contents
3
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
5
6
www.ti.com
4.1
4.2
Documentation Support
...................................................................................................
Device and Development-Support Tool Nomenclature
................................................................
Electrical Specifications
......................................................................................................
5.1
Absolute Maximum Ratings
...............................................................................................
5.2
5.3
Recommended Operating Conditions
Electrical Characteristics
...................................................................................
.................................................................................................
5.3.1
Test Loading
.....................................................................................................
5.3.2
Timing Parameter Symbology
............................................................................................
5.3.3
Internal Oscillator With External Crystal
.................................................................................
5.4
5.5
Clock Options
...............................................................................................................
5.4.1
Divide-By-Two and Divide-By-Four Clock Options
..........................................................
5.4.2
Multiply-By-N Clock Option (PLL Enabled)
...................................................................
Memory and Parallel I/O Interface Timing
..............................................................................
5.5.1
Memory Read
....................................................................................................
5.5.2
Memory Write
5.5.3
I/O Read
....................................................................................................
..........................................................................................................
5.5.4
I/O Write
..........................................................................................................
5.5.5
Ready Timing for Externally Generated Wait States
..................................................................
5.5.6
HOLD and HOLDA Timings
...............................................................................................
5.5.7
Reset, BIO, Interrupt, and MP/MC Timings
.............................................................................
5.5.8
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
..........................................
5.5.9
External Flag (XF) and TOUT Timings
..................................................................................
5.5.10
Multichannel Buffered Serial Port (McBSP) Timing
...................................................................
5.5.10.1
McBSP Transmit and Receive Timings
....................................................................
5.5.10.2
McBSP General-Purpose I/O Timing
.......................................................................
5.5.10.3
McBSP as SPI Master or Slave Timing
....................................................................
5.5.11
Host-Port Interface Timing
5.5.11.1
HPI8 Mode
...............................................................................................
.....................................................................................................
5.5.11.2
HPI16 Mode
....................................................................................................
Mechanical Data
.................................................................................................................
6.1
Package Thermal Resistance Characteristics
..........................................................................
4
Contents Submit Documentation Feedback
5-4
5-5
5-6
5-7
3-23
5-1
5-2
5-3
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
5-8
5-9
5-10
5-11
5-12
5-13
5-14
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-3
3-4
3-5
3-6
2-1
2-2
3-1
3-2 www.ti.com
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
List of Figures
144-Ball GGU MicroStar BGA™ (Bottom View)
.............................................................................
144-Pin PGE Low-Profile Quad Flatpack (Top View)
.......................................................................
TMS320VC5416 Functional Block Diagram
..................................................................................
Program and Data Memory Map
................................................................................................
Extended Program Memory Map
...............................................................................................
Process Mode Status Register
..................................................................................................
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
.........................
Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]
.........................
Bank-Switching Control Register BSCR)[MMR Address 0029h]
...........................................................
Host-Port Interface — Nonmulltiplexed Mode
.................................................................................
HPI Memory Map
.................................................................................................................
Multichannel Control Register (MCR1)
.........................................................................................
Multichannel Control Register (MCR2)
.........................................................................................
Pin Control Register (PCR)
......................................................................................................
Nonconsecutive Memory Read and I/O Read Bus Sequence
.............................................................
Consecutive Memory Read Bus Sequence (n = 3 reads)
..................................................................
Memory Write and I/O Write Bus Sequence
.................................................................................
DMA Transfer Mode Control Register (DMMCRn)
...........................................................................
On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
.........................................
On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
....................................
DMPREC Register
................................................................................................................
General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
................................................
General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
.................................................
Device ID Register (CSIDR) [MMR Address 003Eh]
.........................................................................
IFR and IMR Registers
...........................................................................................................
Tester Pin Electronics
............................................................................................................
Internal Divide-By-Two Clock Option With External Crystal
...............................................................
External Divide-By-Two Clock Timing
.........................................................................................
Multiply-By-One Clock Timing
..................................................................................................
Nonconsecutive Mode Memory Reads
.......................................................................................
Consecutive Mode Memory Reads
............................................................................................
Memory Write (MSTRB = 0)
....................................................................................................
Parallel I/O Port Read (IOSTRB = 0)
.........................................................................................
Parallel I/O Port Write (IOSTRB = 0)
..........................................................................................
Memory Read With Externally Generated Wait States
.....................................................................
Memory Write With Externally Generated Wait States
.....................................................................
I/O Read With Externally Generated Wait States
...........................................................................
I/O Write With Externally Generated Wait States
...........................................................................
HOLD and HOLDA Timings (HM = 1)
.........................................................................................
List of Figures
5
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-31
5-32
5-33
5-34
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 www.ti.com
Reset and BIO Timings
.........................................................................................................
Interrupt Timing
..................................................................................................................
MP/MC Timing
...................................................................................................................
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
................................................
External Flag (XF) Timing
......................................................................................................
TOUT Timing
.....................................................................................................................
McBSP Receive Timings
.......................................................................................................
McBSP Transmit Timings
.......................................................................................................
McBSP General-Purpose I/O Timings
........................................................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
....................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
....................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
....................................................
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
....................................................
Using HDS to Control Accesses (HCS Always Low)
........................................................................
Using HCS to Control Accesses
...............................................................................................
HINT Timing
......................................................................................................................
GPIOx Timings
...................................................................................................................
Nonmultiplexed Read Timings
.................................................................................................
Nonmultiplexed Write Timings
.................................................................................................
HRDY Relative to CLKOUT
....................................................................................................
6
List of Figures Submit Documentation Feedback
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
3-15
3-16
3-17
3-18
3-19
5-1
5-2
5-3
5-12
5-13
5-14
5-15
5-16
5-17
5-18
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-3
3-4
3-5
3-6
2-1
2-2
3-1
3-2 www.ti.com
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
List of Tables
Terminal Assignments for the TMS320VC5416GGU (144-Pin BGA Package)
.........................................
Signal Descriptions
...............................................................................................................
Standard On-Chip ROM Layout
...............................................................................................
Processor Mode Status (PMST) Register Bit Fields
........................................................................
Software Wait-State Register (SWWSR) Bit Fields
.........................................................................
Software Wait-State Control Register (SWCR) Bit Fields
..................................................................
Bank-Switching Control Register (BSCR) Fields
..............................................................................
Bus Holder Control Bits
..........................................................................................................
Sample Rate Input Clock Selection
...........................................................................................
Clock Mode Settings at Reset
.................................................................................................
DMD Section of the DMMCRn Register
......................................................................................
DMA Reload Register Selection
...............................................................................................
DMA Interrupts
...................................................................................................................
DMA Synchronization Events
..................................................................................................
DMA Channel Interrupt Selection
..............................................................................................
Device ID Register (CSIDR) Bits
................................................................................................
CPU Memory-Mapped Registers
................................................................................................
Peripheral Memory-Mapped Registers for Each DSP Subsystem
........................................................
McBSP Control Registers and Subaddresses
.................................................................................
DMA Subbank Addressed Registers
...........................................................................................
Interrupt Locations and Priorities
................................................................................................
Input Clock Frequency Characteristics
.........................................................................................
Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options
.......................................
Divide-By-2 and Divide-By-4 Clock Options Timing Requirements
.......................................................
Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics
...................................................
Multiply-By-N Clock Option Timing Requirements
..........................................................................
Multiply-By-N Clock Option Switching Characteristics
......................................................................
Memory Read Timing Requirements
..........................................................................................
Memory Read Switching Characteristics
.....................................................................................
Memory Write Switching Characteristics
.....................................................................................
I/O Read Timing Requirements
................................................................................................
I/O Read Switching Characteristics
...........................................................................................
I/O Write Switching Characteristics
............................................................................................
Ready Timing Requirements for Externally Generated Wait States
......................................................
Ready Switching Characteristics for Externally Generated Wait States
..................................................
HOLD and HOLDA Timing Requirements
....................................................................................
HOLD and HOLDA Switching Characteristics
...............................................................................
Reset, BIO, Interrupt, and MP/MC Timing Requirements
..................................................................
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
...........................
List of Tables
7
5-27
5-28
5-29
5-30
5-31
5-32
5-33
5-34
5-35
6-1
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 www.ti.com
External Flag (XF) and TOUT Switching Characteristics
...................................................................
McBSP Transmit and Receive Timing Requirements
.......................................................................
McBSP Transmit and Receive Switching Characteristics
..................................................................
McBSP General-Purpose I/O Timing Requirements
........................................................................
McBSP General-Purpose I/O Switching Characteristics
...................................................................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
.................................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
.............................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
.................................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
.............................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
.................................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
.............................
McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
.................................
McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
.............................
HPI8 Mode Timing Requirements
.............................................................................................
HPI8 Mode Switching Characteristics
..........................................................................................
HPI16 Mode Timing Requirements
............................................................................................
HPI16 Mode Switching Characteristics
.......................................................................................
Thermal Resistance Characteristics
............................................................................................
8
List of Tables Submit Documentation Feedback
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 www.ti.com
1 TMS320VC5416 Features
•
Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and One
Program Memory Bus
•
40-Bit Arithmetic Logic Unit (ALU) Including a
40-Bit Barrel Shifter and Two Independent
40-Bit Accumulators
•
17-
×
17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
•
Compare, Select, and Store Unit (CSSU) for the
Add/Compare Selection of the Viterbi Operator
•
Exponent Encoder to Compute an Exponent
Value of a 40-Bit Accumulator Value in a
Single Cycle
•
Two Address Generators With Eight Auxiliary
Registers and Two Auxiliary Register
Arithmetic Units (ARAUs)
•
Data Bus With a Bus Holder Feature
•
Extended Addressing Mode for 8M
×
16-Bit
Maximum Addressable External Program
Space
•
128K
×
16-Bit On-Chip RAM Composed of:
– Eight Blocks of 8K
×
16-Bit On-Chip
Dual-Access Program/Data RAM
– Eight Blocks of 8K
×
16-Bit On-Chip
Single-Access Program RAM
•
16K
×
16-Bit On-Chip ROM Configured for
Program Memory
•
Enhanced External Parallel Interface (XIO2)
•
Single-Instruction-Repeat and Block-Repeat
Operations for Program Code
•
Block-Memory-Move Instructions for Better
Program and Data Management
•
Instructions With a 32-Bit Long Word Operand
•
Instructions With Two- or Three-Operand
Reads
•
Arithmetic Instructions With Parallel Store and
Parallel Load
•
Conditional Store Instructions
•
Fast Return From Interrupt
•
On-Chip Peripherals
– Software-Programmable Wait-State
Generator and Programmable
Bank-Switching
– On-Chip Programmable Phase-Locked
Loop (PLL) Clock Generator With External
Clock Source
– One 16-Bit Timer
– Six-Channel Direct Memory Access (DMA)
Controller
– Three Multichannel Buffered Serial Ports
(McBSPs)
– 8/16-Bit Enhanced Parallel Host-Port
Interface (HPI8/16)
•
Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes
•
CLKOUT Off Control to Disable CLKOUT
•
On-Chip Scan-Based Emulation Logic, IEEE
Std 1149.1 (JTAG) Boundary Scan Logic
(1)
•
144-Pin Ball Grid Array (BGA)(GGU Suffix)
•
144-Pin Low-Profile Quad Flatpack
(LQFP)(PGE Suffix)
•
6.25-ns Single-Cycle Fixed-Point Instruction
Execution Time (160 MIPS)
•
8.33-ns Single-Cycle Fixed-Point Instruction
Execution Time (120 MIPS)
•
3.3-V I/O Supply Voltage (160 and 120 MIPS)
•
1.6-V Core Supply Voltage (160 MIPS)
•
1.5-V Core Supply Voltage (120 MIPS)
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and
Boundary Scan Architecture
TMS320C54x, TMS320 are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1999–2008, Texas Instruments Incorporated
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 www.ti.com
2 Introduction
This section describes the main features of the TMS320VC5416, lists the pin assignments, and describes the function of each pin. This data manual also provides a detailed description section, electrical specifications, parameter measurement information, and mechanical data about the available packaging.
NOTE
This data manual is designed to be used in conjunction with the TMS320C54x™ DSP
Functional Overview (literature number SPRU307).
2.1
Description
The TMS320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the device unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.
Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture.
In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The device also includes the control mechanisms to manage interrupts, repeated operations, and function calls.
2.2
Pin Assignments
illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction with
to locate signal names and ball grid numbers.
provides the pin assignments for the 144-pin low-profile quad flatpack (LQFP) package.
2.2.1
Terminal Assignments for the GGU Package
13 12 11 10 9 8 7 6 5 4 3 2 1
L
M
N
H
J
K
E
F
G
C
D
A
B
10
Introduction
Figure 2-1. 144-Ball GGU MicroStar BGA™ (Bottom View)
Submit Documentation Feedback
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 www.ti.com
lists each signal name and BGA ball number for the 144-pin TMS320VC5416GGU package.
lists each terminal name, terminal function, and operating modes for the TMS320VC5416. In
DD is the power supply for the I/O pins while CV
DD is the power supply for the core CPU.
Table 2-1. Terminal Assignments for the TMS320VC5416GGU (144-Pin BGA Package)
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DV
DD
CV
SS
BDR1
BFSR1
SIGNAL
QUADRANT 1
CV
SS
A22
CV
SS
DV
DD
A10
HD7
A11
A12
A13
A14
A15
CV
DD
HAS
DV
SS
CV
SS
CV
DD
HCS
HR/W
READY
BGA BALL #
X2/CLKIN
RS
D0
D1
D2
D3
D4
D5
A16
DV
SS
A17
A18
TRST
TCK
TMS
CV
SS
CV
DD
HPIENA
DV
SS
CLKOUT
HD3
X1
SIGNAL
QUADRANT 2
BFSX1
BDX1
DV
DD
DV
SS
CLKMD1
CLKMD2
CLKMD3
HPI16
HD2
TOUT
EMU0
EMU1/OFF
TDO
TDI
J1
J2
J3
J4
K1
G4
H1
H2
H3
H4
K2
K3
L1
L2
L3
M1
M2
F2
F1
G2
G1
G3
E3
E2
E1
F4
F3
D4
D3
D2
D1
E4
A1
B1
C2
C1
BGA BALL #
E13
E12
E11
E10
D13
G10
F13
F12
F11
F10
D12
D11
C13
C12
C11
B13
B12
H12
H13
G12
G13
G11
J11
J12
J13
H10
H11
N13
M13
L12
L13
K10
K11
K12
K13
J10
A5
B5
C5
D5
A4
D7
A6
B6
C6
D6
B3
C3
A2
B2
B4
C4
A3
B8
A8
B7
A7
C7
C9
B9
A9
D8
C8
A13
A12
B11
A11
D10
C10
B10
A10
D9
N9
M9
L9
K9
N10
K7
N8
M8
L8
K8
M10
L10
N11
M11
L11
N12
M12
M6
N6
M7
N7
L7
L5
M5
N5
K6
L6
K4
L4
M4
N4
K5
N1
N2
M3
N3
INT2
INT3
CV
DD
HD1
CV
SS
BCLKX1
DV
SS
BDX0
BDX2
IACK
HBIL
NMI
INT0
INT1
SIGNAL
QUADRANT 3
CV
SS
BCLKR1
HCNTL0
DV
SS
BCLKR0
BCLKR2
BFSR0
BFSR2
BDR0
HCNTL1
BDR2
BCLKX0
BCLKX2
CV
SS
HINT
CV
DD
BFSX0
BFSX2
HRDY
DV
DD
DV
SS
HD0
BGA BALL #
D15
HD5
CV
DD
CV
SS
HDS1
DV
SS
HDS2
DV
DD
A0
A1
A2
A3
HD6
A4
A5
A6
A7
A8
A9
CV
DD
A21
DV
SS
SIGNAL
QUADRANT 4
A19
A20
CV
SS
DV
DD
D6
D7
D8
D9
D10
D11
D12
HD4
D13
D14
BGA BALL #
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2.2.2
Pin Assignments for the PGE Package
The TMS320VC5416PGE 144-pin low-profile quad flatpack (LQFP) pin assignments are shown in
V
SS
DD is the power supply for the I/O pins while CV is the ground for both the I/O pins and the core CPU.
DD is the power supply for the core CPU.
25
26
27
28
21
22
23
24
17
18
19
20
14
15
16
33
34
35
29
30
31
32
36
10
11
12
13
7
8
9
5
6
3
4
1
2
CV
SS
A22
CV
SS
DV
DD
A10
HD7
A11
A12
A13
A14
A15
CV
DD
HAS
DV
SS
CV
SS
CV
DD
HCS
HR/W
READY
PS
DS
IS
R/W
MSTRB
IOSTRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DV
DD
CV
SS
BDR1
BFSR1
84
83
82
81
88
87
86
85
92
91
90
89
95
94
93
76
75
74
80
79
78
77
73
102
101
100
99
98
97
96
108
107
106
105
104
103
A18
A17
DV
SS
A16
D5
D4
D3
D2
D1
D0
RS
X2/CLKIN
X1
HD3
CLKOUT
DV
SS
HPIENA
CV
DD
CV
SS
TMS
TCK
TRST
TDI
TDO
EMU1/OFF
EMU0
TOUT
HD2
HPI16
CLKMD3
CLKMD2
CLKMD1
DV
SS
DV
DD
BDX1
BFSX1
Figure 2-2. 144-Pin PGE Low-Profile Quad Flatpack (Top View)
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2.2.3
Signal Descriptions
lists each signal, function, and operating mode(s) grouped by function.
Table 2-2. Signal Descriptions
TERMINAL
NAME
IACK
I/O
(1)
O/Z
DESCRIPTION
A22 (MSB), I/O/Z
(2) (3)
A21, A20,
A19, A18,
A17, A16,
A15, A14,
A13, A12,
A11, A10, A9,
A8, A7, A6,
A5, A4, A3,
A2, A1,
A0 (LSB)
D15 (MSB), I/O/Z
(2) (3)
D14, D13,
D12, D11,
D10, D9, D8,
D7, D6, D5,
D4, D3, D2,
D1, D0 (LSB)
DATA SIGNALS
Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16 to A22, address external program space memory. A22-A0 is placed in the high-impedance state in the hold mode. A22-A0 also goes into the high-impedance state when OFF is low.A17-A0 are inputs in HPI16 mode.
These pins can be used to address internal memory via the host-port interface (HPI) when the HPI16 pin is high.
These pins also have Schmitt trigger inputs.The address bus has a bus holder feature that eliminates passive components and the power dissipation associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into a high-impedance state.
Parallel data bus D15 (MSB) through D0 (LSB). D15-D0 is multiplexed to transfer data between the core CPU and external data/program memory or I/O devices or HPI in HPI16 mode (when HPI16 pin is high). D15-D0 is placed in the high-impedance state when not outputting data or when RS or HOLD is asserted. D15-D0 also goes into the high-impedance state when OFF is low. These pins also have Schmitt trigger inputs.The data bus has a bus holder feature that eliminates passive components and the power dissipation associated with them.
The bus holder keeps the data bus at the previous logic level when the bus goes into the high-impedance state.
The bus holders on the data bus can be enabled/disabled under software control.
INITIALIZATION, INTERRUPT AND RESET OPERATIONS
Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15-A0. IACK also goes into the high-impedance state when OFF is low.
INT0
(2)
INT1
(2)
INT2
(2)
INT3
(2)
I
External user interrupt inputs. INT0-INT3 are maskable and are prioritized by the interrupt mask register (IMR) and the interrupt mode bit. INT0 -INT3 can be polled and reset by way of the interrupt flag register (IFR).
NMI
RS
MP/MC
BIO
XF
DS
PS
IS
(2)
(2)
(2)
MSTRB
I
I
I
I
O/Z
O/Z
O/Z
Nonmaskable interrupt. NMI is an external interrupt that cannot be masked by way of the INTM or the IMR.
When NMI is activated, the processor traps to the appropriate vector location.
Reset. RS causes the digital signal processor (DSP) to terminate execution and forces the program counter to
0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects various registers and status bits.
Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is selected, and the internal program ROM is mapped into the upper 16K words of program memory space. If the pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed from program space. This pin is only sampled at reset, and the MP/MC bit of the processor mode status (PMST) register can override the mode that is selected at reset.
MULTIPROCESSING SIGNALS
Branch control. A branch can be conditionally executed when BIO is active. If low, the processor executes the conditional instruction. The BIO condition is sampled during the decode phase of the pipeline for the XC instruction, and all other instructions sample BIO during the read phase of the pipeline.
External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is low, and is set high at reset.
MEMORY CONTROL SIGNALS
Data, program, and I/O space select signals. DS, PS, and IS are always high unless driven low for communicating to a particular external space. Active period corresponds to valid address information. DS, PS, and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance state when OFF is low.
Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low.
(1) I = Input, O = Output, Z = High-impedance, S = Supply
(2) These pins have Schmitt trigger inputs.
(3) This pin has an internal bus holder controlled by way of the BSCR register.
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Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
I/O
(1)
DESCRIPTION
READY
R/W
IOSTRB
HOLD
HOLDA
MSC
IAQ
I
O/Z
O/Z
I
O/Z
O/Z
O/Z
Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the processor performs ready detection if at least two software wait states are programmed. The READY signal is not sampled until the completion of the software wait states.
Read/write signal. R/W indicates transfer direction during communication to an external device. R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in the high-impedance state in the hold mode; and it also goes into the high-impedance state when OFF is low.
I/O strobe signal. IOSTRB is always high unless low-level asserted to indicate an external bus access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance state when OFF is low.
Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by the device, these lines go into the high-impedance state.
Hold acknowledge. HOLDA indicates to the external circuitry that the processor is in a hold state and that the address, data, and control lines are in the high-impedance state, allowing them to be available to the external circuitry. HOLDA also goes into the high-impedance state when OFF is low.
This pin is driven high during reset.
Microstate complete. MSC indicates completion of all software wait states. When two or more software wait states are enabled, the MSC pin goes active at the beginning of the first software wait state and goes inactive high at the beginning of the last software wait state. If connected to the READY input, MSC forces one external wait state after the last internal wait state is completed. MSC also goes into the high-impedance state when OFF is low.
Instruction acquisition signal. IAQ is asserted (active low) when there is an instruction address on the address bus and goes into the high-impedance state when OFF is low.
TIMER SIGNALS
CLKOUT
CLKMD1
CLKMD2
CLKMD3
X2/CLKIN
X1
TOUT
(2)
(2)
(2)
(2)
O/Z
I
I
O
O/Z
Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the machine-cycle rate divided by 4.
Clock mode select signals. CLKMD1-CLKMD3 allow the selection and configuration of different clock modes such as crystal, external clock, and PLL mode. The external CLKMD1-CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software.
Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input. (This is revision-dependent, see
for additional information.)
Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left unconnected. X1 does not go into the high-impedance state when OFF is low. (This is revision-dependent, see
for additional information.)
Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low.
MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1), AND
MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
BCLKR0
(2)
BCLKR1
(2)
BCLKR2
(2)
I/O/Z
Receive clock input. BCLKR can be configured as an input or an output; it is configured as an input following reset. BCLKR serves as the serial shift clock for the buffered serial port receiver.
BDR0, BDR1,
BDR2
BFSR0,
BFSR1,
BFSR2
BCLKX0
(2)
BCLKX1
(2)
BCLKX2
(2)
BDX0, BDX1,
BDX2
BFSX0,
BFSX1,
BFSX2
I
I/O/Z
O/Z
Serial data receive input
Frame synchronization pulse for receive input. BFSR can be configured as an input or an output; it is configured as an input following reset. The BFSR pulse initiates the receive data process over BDR.
Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
I/O/Z an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when OFF goes low.
Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is asserted, or when OFF is low.
Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
I/O/Z BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes into the high-impedance state when OFF is low.
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TERMINAL
NAME
HD0-
HD7
(2) (3)
HCNTL0
(4)
HCNTL1
(4)
HBIL
(4)
HCS
(2) (4)
HDS1
(2) (4)
HDS2
(2) (4)
HAS
(2) (4)
HR/W
(4)
HRDY
HINT
HPIENA
(5)
HPI16
(5)
CV
SS
CV
DD
DV
SS
DV
DD
TCK
(2) (4)
TDI
(4)
TDO
TMS
(4)
TRST
(5) (6)
S
S
S
S
I/O
(1)
I/O/Z
O/Z
O/Z
I
I
I
I
I
I
I
I
I
I
I
I
O/Z
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Fixed-Point Digital Signal Processor
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Table 2-2. Signal Descriptions (continued)
DESCRIPTION
HOST-PORT INTERFACE SIGNALS
Parallel bidirectional data bus. The HPI data bus is used by a host device bus to exchange information with the
HPI registers. These pins can also be used as general-purpose I/O pins. HD0-HD7 is placed in the high-impedance state when not outputting data or when OFF is low. The HPI data bus includes bus holders to reduce the static power dissipation caused by floating, unused pins. When the HPI data bus is not being driven by the device, the bus holders keep the pins at the previous logic level. The HPI data bus holders are disabled at reset and can be enabled/disabled via the HBH bit of the BSCR. These pins also have Schmitt trigger inputs.
Control inputs. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control inputs have internal pullups that are only enabled when HPIENA = 0. These pins are not used when HPI16 = 1.
Byte identification. HBIL identifies the first or second byte of transfer. The HPIL input has an internal pullup resistor that is only enabled when HPIENA = 0. This pin is not used when HPI16 = 1.
Chip select. HCS is the select input for the HPI and must be driven low during accesses. The chip select input has an internal pullup resistor that is only enabled when HPIENA = 0.
Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control the transfer. The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0.
Address strobe. Host with multiplexed address and data pins requires HAS to latch the address in the HPIA register. HAS input has an internal pullup resistor that is only enabled when HPIENA = 0.
Read/write. HR/W controls the direction of the HPI transfer. HR/W has an internal pullup resistor that is only enabled when HPIENA = 0.
Ready output. HRDY goes into the high-impedance state when OFF is low. The ready output informs the host when the HPI is ready for the next transfer. This pin is driven high during reset.
Interrupt output. This output is used to interrupt the host. When the DSP is in reset, HINT is driven high. HINT goes into the high-impedance state when OFF is low. This pin is not used when HPI16 = 1.
HPI module select. HPIENA must be tied to DV
DD to have HPI selected. If HPIENA is left open or connected to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data bus has holders set. HPIENA is provided with an internal pulldown resistor that is always active. HPIENA is sampled when RS goes high and is ignored until RS goes low again. This pin should never be changed while reset is high.
HPI16 mode selection. This pin must be tied to DVDD to enable HPI16 mode. The pin has an internal pulldown resistor which is always active. If HPI16 is left open or driven low, the HPI16 mode is disabled.
SUPPLY PINS
Ground. Dedicated ground for the core CPU
+V
DD
. Dedicated power supply for the core CPU
Ground. Dedicated ground for I/O pins
+V
DD
. Dedicated power supply for I/O pins
TEST PINS
IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the falling edge of TCK.
IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.
IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low.
IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into the TAP controller on the rising edge of TCK.
IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the operations of the device. If TRST is driven low, the device operates in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.
(4) This pin has an internal pullup resistor.
(5) This pin has an internal pulldown resistor.
(6) Although this pin includes an internal pulldown resistor, a 470-
Ω external pulldown is required. If the TRST pin is connected to multiple
DSPs, a buffer is recommended to ensure the V
IL and V
IH specifications are met.
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Table 2-2. Signal Descriptions (continued)
TERMINAL
NAME
I/O
(1)
DESCRIPTION
EMU0
(7)
EMU1/OFF
(7)
Emulator 0 pin. When TRST is driven low, EMU0 must be high for activation of the OFF condition. When TRST
I/O/Z is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1 scan system.
I/O/Z
Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1/OFF is used as an interrupt to or from the emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore, for the OFF condition, the following apply:
TRST = low,
EMU0 = high
EMU1/OFF = low
(7) This pin must be pulled up with a 4.7-k Ω resistor to ensure the device is operable in functional mode or emulation mode.
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3 Functional Overview
The following functional overview is based on the block diagram in
P, C, D, E Buses and Control Signals
XIO
54X cLEAD
TI BUS
64K RAM
Single Access
Program
64K RAM
Dual Access
Program/Data
MBus
RHEA
Bridge
RHEA Bus
Enhanced XIO
16K Program
ROM
GPIO
McBSP1
McBSP2
McBSP3
16HPI
16 HPI xDMA logic
RHEAbus
Clocks
TIMER
APLL
JTAG
Figure 3-1. TMS320VC5416 Functional Block Diagram
3.1
Memory
The device provides both on-chip ROM and RAM memories to aid in system performance and integration.
3.1.1
Data Memory
The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access.
The advantages of operating from on-chip memory are as follows:
•
Higher performance because no wait states are required
•
Higher performance because of better flow within the pipeline of the central arithmetic logic unit
(CALU)
•
Lower cost than external memory
•
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
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3.1.2
Program Memory
Software can configure their memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows:
•
Higher performance because no wait states are required
•
Lower cost than external memory
•
Lower power than external memory
The advantage of operating from off-chip memory is the ability to access a larger address space.
3.1.3
Extended Program Memory
The device uses a paged extended memory scheme in program space to allow access of up to 8192K of program memory. In order to implement this scheme, the device includes several features which are also present on C548/549/5410:
•
Twenty-three address lines, instead of sixteen
•
An extra memory-mapped register, the XPC
•
Six extra instructions for addressing extended program space
Program memory in the device is organized into 128 pages that are each 64K in length.
The value of the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.
3.2
On-Chip ROM With Bootloader
The device features a 16K-word
×
16-bit on-chip maskable ROM that can only be mapped into program memory space.
Customers can arrange to have the ROM of the device programmed with contents unique to any particular application.
A bootloader is available in the standard on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip
ROM. This location contains a branch instruction to the start of the bootloader program.
The standard devices provide different ways to download the code to accommodate various system requirements:
•
Parallel from 8-bit or 16-bit-wide EPROM
•
Parallel from I/O space, 8-bit or 16-bit mode
•
Serial boot from serial ports, 8-bit or 16-bit mode
•
Host-port interface boot
•
Warm boot
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The standard on-chip ROM layout is shown in
Table 3-1. Standard On-Chip ROM Layout
ADDRESS RANGE
C000h-D4FFh
D500h-F7FFh
F800h-FBFFh
FC00h-FCFFh
FD00h-FDFFh
FE00h-FEFFh
FF00h-FF7Fh
FF80h-FFFFh
ROM tables for the GSM EFR speech codec
DESCRIPTION
Reserved
Bootloader
µ
-Law expansion table
A-Law expansion table
Sine look-up table
Reserved
(1)
Interrupt vector table
(1) In the ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h-FF7Fh in program space.
3.3
On-Chip RAM
The device contains 64K-word
×
16-bit of on-chip dual-access RAM (DARAM) and 64K-word
×
16-bit of on-chip single-access RAM (SARAM).
The DARAM is composed of eight blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. Four blocks of DARAM are located in the address range 0080h-7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one. The other four blocks of DARAM are located in the address range 18000h-1FFFFh in program space. The DARAM located in the address range 18000h-1FFFFh in program space can be mapped into data space by setting the DROM bit to one.
The SARAM is composed of eight blocks of 8K words each. Each of these eight blocks is a single-access memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a data word is written to another SARAM block. The SARAM is located in the address range
28000h-2FFFFh, and 38000h-3FFFFh in program space.
3.4
On-Chip Memory Security
The device has a maskable option to protect the contents of on-chip memories.
When the RAM/ROM security option is selected, the following restrictions apply:
•
Only the on-chip ROM originating instructions can read the contents of the on-chip ROM; on-chip RAM and external RAM originating instruction can not read data from ROM: instead 0FFFFh is read. Code can still branch to ROM from on-chip RAM or external program memory.
•
The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external memory. To protect the internal RAM, the user must never branch to external memory.
•
The security feature completely disables the scan-based emulation capability of the 54x to prevent the use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG boundary scan test capability.
•
The device is internally forced into microcomputer mode at reset (MP/MC bit forced to zero), preventing the ROM from being disabled by the external MP/MC pin. The status of the MP/MC bit in the PMST register can be changed after reset by the user application.
•
HPI writes have no restriction, but HPI reads are restricted to the 4000h - 5FFFh address range.
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If the ROM-only security option is selected the following restrictions apply:
•
Only the on-chip ROM originating instructions can read the contents of the on-chip ROM; on-chip RAM and external RAM originating instruction cannot read data from ROM: instead 0FFFFh is read. Code can still branch to ROM from on-chip RAM or external program memory.
•
The contents of on-chip RAM can be read by all instructions, even by instructions fetched from external memory. To protect the internal RAM the user must never branch to external memory.
•
The security feature completely disables the scan-based emulation capability of the 54x to prevent the use of a debugger utility. This only affects emulation and does not prevent the use of the JTAG boundary scan test capability.
•
The device can be started in either microcomputer mode or microprocessor mode at reset (depends on the MP/MC pin).
•
HPI read and writes have no restriction.
3.5
Memory Map
The program and data memory map is shown in
Figure 3-2 . Address ranges for on-chip DARAM in data
memory are:
•
DARAM0: 0080h-1FFFh
•
DARAM1: 2000h-3FFFh
•
DARAM2: 4000h-5FFFh
•
DARAM3: 6000h-7FFFh
•
DARAM4: 8000h-9FFFh
•
DARAM5: A000h-BFFFh
•
DARAM6: C000h-DFFFh
•
DARAM7: E000h-FFFFh
Hex
0000
007F
0080
7FFF
8000
Page 0 Program
Reserved
(OVLY = 1)
External
(OVLY = 0)
On-Chip
DARAM0−3
(OVLY = 1)
External
(OVLY = 0)
External
FF7F
FF80 Interrupts
(External)
FFFF
MP/MC= 1
(Microprocessor Mode)
Hex
0000
Page 0 Program
Reserved
(OVLY = 1)
External
(OVLY = 0)
007F
0080 On-Chip
DARAM0−3
(OVLY = 1)
External
(OVLY = 0)
7FFF
8000
BFFF
C000
External
FEFF
FF00
FF7F
FF80
FFFF
On-Chip ROM
(4K x 16-bit)
Reserved
Interrupts
(On-Chip)
MP/MC= 0
(Microcomputer Mode)
Figure 3-2. Program and Data Memory Map
Hex
0000
005F
Data
Memory-Mapped
Registers
0060
007F
0080
Scratch-Pad
RAM
On-Chip
DARAM0−3
(32K x 16-bit)
7FFF
8000
On-Chip
DARAM4−7
(DROM=1) or
External
(DROM=0)
FFFF
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The extended program memory map is shown in
. Address ranges for on-chip DARAM in data memory are:
•
DARAM4: 018000h-019FFFh
•
DARAM5: 01A000h-01BFFFh
•
DARAM6: 01C000h-01DFFFh
•
DARAM7: 01E000h-01FFFFh
Address ranges for on-chip SARAM in program memory are:
•
SARAM0: 028000h-029FFFh
•
SARAM1: 02A000h-02BFFFh
•
SARAM2: 02C000h-02DFFFh
•
SARAM3: 02E000h-02FFFFh
•
SARAM4: 038000h-039FFFh
•
SARAM5: 03A000h-03BFFFh
•
SARAM6: 03C000h-03DFFFh
•
SARAM7: 03E000h-03FFFFh
Hex
010000
017FFF
Program
On-Chip
DARAM0−3
(OVLY=1)
External
(OVLY=0)
018000
01FFFF
On-Chip
DARAM4−7
(MP/MC=0)
External
(MP/MC=1)
Page 1
XPC=1
Hex
Program
020000
On-Chip
DARAM0−3
027FFF
(OVLY=1)
External
(OVLY=0)
028000
On-Chip
SARAM0−3
02FFFF
(MP/MC=0)
External
(MP/MC=1)
Page 2
XPC=2
Hex
030000
037FFF
Program
On-Chip
DARAM0−3
(OVLY=1)
External
(OVLY=0)
038000
On-Chip
SARAM4−7
03FFFF
(MP/MC=0)
External
(MP/MC=1)
Page 3
XPC=3
Hex
040000
047FFF
On-Chip
DARAM0−3
(OVLY=1)
External
(OVLY=0)
048000
04FFFF
Program
External
Page 4
XPC=4
Figure 3-3. Extended Program Memory Map
......
Hex
7F0000
7F7FFF
Program
On-Chip
DARAM0−3
(OVLY=1)
External
(OVLY=0)
7F8000
External
7FFFFF
Page 127
XPC=7Fh
3.5.1
Relocatable Interrupt Vector Table
The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft — meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate interrupt service routine without the overhead.
At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space.
However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page.
NOTE
The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.
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15
IPTR
R/W-1FF
7 6 5 4
IPTR MP/MC OVLY AVIS
MP/MC pin R/W-0 R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
3
DROM
R/W-0
2
CLKOFF
R/W-0
Figure 3-4. Process Mode Status Register
1
SMUL
R/W-0 www.ti.com
8
0
SST
R/W-0
2
1
0
NO.
BIT
NAME
15-7 IPTR
6
5
4
3
MP/MC
OVLY
AVIS
DROM
CLKOFF
SMUL
SST
Table 3-2. Processor Mode Status (PMST) Register Bit Fields
RESET
VALUE
FUNCTION
1FFh
Interrupt vector pointer. The 9-bit IPTR field points to the 128-word program page where the interrupt vectors reside. The interrupt vectors can be remapped to RAM for boot-loaded operations. At reset, these bits are all set to 1; the reset vector always resides at address FF80h in program memory space.
The RESET instruction does not affect this field.
Microprocessor/microcomputer mode. MP/MC enables/disables the on-chip ROM to be addressable in program memory space.
•
MP/MC = 0: The on-chip ROM is enabled and addressable.
•
MP/MC = 1: The on-chip ROM is not available.
MP/MC pin
0
0
0
0
MP/MC is set to the value corresponding to the logic level on the MP/MC pin when sampled at reset.
This pin is not sampled again until the next reset. The RESET instruction does not affect this bit. This bit can also be set or cleared by software.
RAM overlay. OVLY enables on-chip dual-access data RAM blocks to be mapped into program space.
The values for the OVLY bit are:
•
OVLY = 0: The on-chip RAM is addressable in data space but not in program space.
•
OVLY = 1: The on-chip RAM is mapped into program space and data space. Data page 0
(addresses 0h to 7Fh), however, is not mapped into program space.
Address visibility mode. AVIS enables/disables the internal program address to be visible at the address pins.
•
AVIS = 0: The external address lines do not change with the internal program address. Control and data lines are not affected and the address bus is driven with the last address on the bus.
•
AVIS = 1: This mode allows the internal program address to appear at the pins of the device so that the internal program address can be traced. Also, it allows the interrupt vector to be decoded in conjunction with IACK when the interrupt vectors reside on on-chip memory.
DROM enables on-chip DARAM4-7 to be mapped into data space. The DROM bit values are:
•
DROM = 0: The on-chip DARAM4-7 is not mapped into data space.
•
DROM = 1: The on-chip DARAM4-7 is mapped into data space.
CLOCKOUT off. When the CLKOFF bit is 1, the output of CLKOUT is disabled and remains at a high level.
Saturation on multiplication. When SMUL = 1, saturation of a multiplication result occurs before
N/A performing the accumulation in a MAC of MAS instruction. The SMUL bit applies only when OVM = 1 and FRCT = 1.
N/A
Saturation on store. When SST = 1, saturation of the data from the accumulator is enabled before storing in memory. The saturation is performed after the shift operation.
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3.6
On-Chip Peripherals
The device has the following peripherals:
•
Software-programmable wait-state generator
•
Programmable bank-switching
•
A host-port interface (HPI8/16)
•
Three multichannel buffered serial ports (McBSPs)
•
A hardware timer
•
A clock generator with a multiple phase-locked loop (PLL)
•
Enhanced external parallel interface (XIO2)
•
A DMA controller (DMA)
3.6.1
Software-Programmable Wait-State Generator
The software wait-state generator of the device can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption.
The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the software wait-state control register (SWCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The
SWWSR bit fields are shown in
and described in
15
XPA
R/W-0
14
I/O
R/W-111
12 11
DATA
R/W-111
9 8
DATA
7 6 5
DATA PROGRAM
R/W-111 R/W-111
LEGEND: R = Read, W = Write, n = value present after reset
3 2
PROGRAM
R/W-111
0
Figure 3-5. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address
0028h]
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NO.
15
14-12
11-9
8-6
5-3
2-0
BIT
NAME
XPA
I/O
Data
Data
Program
Program www.ti.com
Table 3-3. Software Wait-State Register (SWWSR) Bit Fields
RESET
VALUE
FUNCTION
0
Extended program address control bit. XPA is used in conjunction with the program space fields
(bits 0 through 5) to select the address range for program space wait states.
I/O space. The field value (0-7) corresponds to the base number of wait states for I/O space accesses
111 within addresses 0000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Upper data space. The field value (0-7) corresponds to the base number of wait states for external
111 data space accesses within addresses 8000-FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Lower data space. The field value (0-7) corresponds to the base number of wait states for external
111 data space accesses within addresses 0000-7FFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
111
Upper program space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within the following addresses:
•
XPA = 0: xx8000 - xxFFFFh
•
XPA = 1: 400000h - 7FFFFFh
111
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
Program space. The field value (0-7) corresponds to the base number of wait states for external program space accesses within the following addresses:
•
XPA = 0: xx0000 - xx7FFFh
•
XPA = 1: 000000 - 3FFFFFh.
The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait states.
The software wait-state multiplier bit of the software wait-state control register (SWCR) is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in
and described in
15 8
Reserved
R/W-0
7
Reserved
R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
1 0
SWSM
R/W-0
Figure 3-6. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address
0028h]
NO.
15-1
0
PIN
NAME
Reserved
SWSM
Table 3-4. Software Wait-State Control Register (SWCR) Bit Fields
RESET
VALUE
0
0
FUNCTION
These bits are reserved and are unaffected by writes.
Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor of 1 or 2.
•
SWSM = 0: wait-state base values are unchanged (multiplied by 1)
•
SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states
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3.6.2
Programmable Bank-Switching
Programmable bank-switching logic allows the device to switch between external memory banks without requiring external wait states for memories that need additional time to turn off. The bank-switching logic automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or data space.
Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped ataddress 0029h. The bit fields of the BSCR are shown in
and are described in
14 13 11 8 15
CONSEC
R/W-1
DIVFCT
R/W-11
12
IACKOFF
R/W-1
Reserved
R
7
Reserved
R
LEGEND: R = Read, W = Write, n = value present after reset
3 2
HBH
R/W-0
1
BH
R/W-0
Figure 3-7. Bank-Switching Control Register BSCR)[MMR Address 0029h]
0
Reserved
R
Table 3-5. Bank-Switching Control Register (BSCR) Fields
BIT NAME
RESET
VALUE
FUNCTION
15
14-13
12
11-3
2
1
0
CONSEC
(1)
DIVFCT
IACKOFF
Rsvd
HBH
BH
Rsvd
1
11
11
0
0
Consecutive bank-switching. Specifies the bank-switching mode.
•
CONSEC = 0: Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for continuous memory reads (i.e., no starting and trailing cycles between read cycles).
•
CONSEC = 1: Consecutive bank switches on external memory reads. Each read cycle consists of
3 cycles: starting cycle, read cycle, and trailing cycle.
CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency equal to 1/(DIVFCT+1) of the DSP clock.
•
DIVFCT = 00: CLKOUT is not divided.
•
DIVFCT = 01: CLKOUT is divided by 2 from the DSP clock.
•
DIVFCT = 10: CLKOUT is divided by 3 from the DSP clock.
•
DIVFCT = 11: CLKOUT is divided by 4 from the DSP clock (default value following reset).
IACK signal output off. Controls the output of the IACK signal. IACKOFF is set to 1 at reset.
•
IACKOFF = 0: The IACK signal output off function is disabled.
•
IACKOFF = 1: The IACK signal output off function is enabled.
Reserved
HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.
•
HBH = 0: The bus holder is disabled except when HPI16 = 1.
•
HBH = 1: The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous logic level.
Bus holder. Controls the bus holder. BH is cleared to 0 at reset.
•
BH = 0: The bus holder is disabled.
•
BH = 1: The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic level.
Reserved
(1) For additional information, see
of this document.
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The device has an internal register that holds the MSB of the last address used for a read or write operation in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address used for the current read does not match that contained in this internal register, the MSTRB
(memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new address. The contents of the internal register are replaced with the MSB for the read of the current address. If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs.
In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts are avoided by inserting an extra cycle. For more information, see
of this document.
The bank-switching mechanism automatically inserts one extra cycle in the following cases:
•
A memory read followed by another memory read from a different memory bank.
•
A program-memory read followed by a data-memory read.
•
A data-memory read followed by a program-memory read.
•
A program-memory read followed by another program-memory read from a different page.
3.6.3
Bus Holders
The device has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of the address bus (A[17-0]), data bus (D[15-0]), and the HPI data bus (HD[7-0]). Bus keeper enabling/disabling is described in
.
HPI16 PIN
0
0
0
0
1
1
1
1
BH
0
0
1
1
0
0
1
1
Table 3-6. Bus Holder Control Bits
HBH
0
1
0
1
0
1
0
1
D[15-0]
OFF
OFF
ON
ON
OFF
OFF
ON
ON
A[17-0]
OFF
OFF
OFF
OFF
OFF
ON
OFF
ON
HD[7-0]
OFF
ON
OFF
ON
ON
ON
ON
ON
3.7
Parallel I/O Ports
The device has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the
PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The device can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.
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3.7.1
Enhanced 8-/16-Bit Host-Port Interface (HPI8/16)
The host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI found on earlier TMS320C54x™ DSPs (542, 545, 548, and 549). The HPI can be used to interface to an
8-bit or 16-bit host. When the address and data buses for external I/O is not used (to interface to external devices in program/data/IO spaces), the HPI can be configured as an HPI16 to interface to a 16-bit host.
This configuration can be accomplished by connecting the HPI16 pin to logic "1”.
When the HPI16 pin is connected to a logic "0", the HPI is configured as an HPI8. The HPI8 is an 8-bit parallel port for interprocessor communication. The features of the HPI8 include:
Standard features:
•
Sequential transfers (with autoincrement) or random-access transfers
•
Host interrupt and C54x™ interrupt capability
•
Multiple data strobes and control pins for interface flexibility
The HPI8 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8 through three dedicated registers — the HPI address register (HPIA), the
HPI data register (HPID), and the HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the device.
Enhanced features:
•
Access to entire on-chip RAM through DMA bus
•
Capability to continue transferring during emulation stop
The HPI16 is an enhanced 16-bit version of the TMS320C54x™ DSP 8-bit host-port interface (HPI8). The
HPI16 is designed to allow a 16-bit host to access the DSP on-chip memory, with the host acting as the master of the interface. Some of the features of the HPI16 include:
•
16-bit bidirectional data bus
•
Multiple data strobes and control signals to allow glueless interfacing to a variety of hosts
•
Only nonmultiplexed address/data modes are supported
•
18-bit address bus used in nonmultiplexed mode to allow access to all internal memory (including internal extended address pages)
•
HRDY signal to hold off host accesses due to DMA latency
•
The HPI16 acts as a slave to a 16-bit host processor and allows access to the on-chip memory of the
DSP.
NOTE
Only the nonmultiplexed mode is supported when the HPI is configured as a HPI16.
The HPI functions as a slave and enables the host processor to access the on-chip memory. A major enhancement to the HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one cycle. Note that since host accesses are always synchronized to the device clock, an active input clock (CLKIN) is required for HPI accesses during
IDLE states, and host accesses are not allowed while the device reset pin is asserted.
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3.7.2
HPI Nonmultiplexed Mode
In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register
(HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 18-bit HA address bus. The host initiates the access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the
HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access.
shows a block diagram of the HPI16 in
nonmultiplexed mode.
shows the HPI memory map.
HOST
DATA[15:0]
PPD[15:0]
HPI16
HPID[15:0]
HINT
DMA
Address[17:0]
R/W
Data Strobes
READY
V
CC
HRDY
HCNTL0
HCNTL1
HBIL
HAS
HR/W
HDS1, HDS2, HCS
54xx
CPU
Figure 3-8. Host-Port Interface — Nonmulltiplexed Mode
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Address (Hex)
000 0000
Reserved
000 005F
000 0060
000 007F
000 0080
Scratch-Pad
RAM
DARAM0 −
DARAM3
000 7FFF
000 8000
Reserved
001 7FFF
001 8000
DARAM4 −
DARAM7
001 FFFF
002 0000
Reserved
002 7FFF
002 8000
002 FFFF
003 0000
SARAM0 −
SARAM3
Reserved
003 7FFF
003 8000
SARAM4 −
SARAM7
003 FFFF
004 0000
Reserved
07F FFFF
Figure 3-9. HPI Memory Map
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Fixed-Point Digital Signal Processor
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3.8
Multichannel Buffered Serial Ports (McBSPs)
The device provides three high-speed, full-duplex, multichannel buffered serial ports that allow direct interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial-port interface found on other 54x devices. Like their predecessors, the McBSPs provide:
•
Full-duplex communication
•
Double-buffer data registers, which allow a continuous data stream
•
Independent framing and clocking for receive and transmit
In addition, the McBSPs have the following capabilities:
•
Direct interface to:
– T1/E1 framers
– MVIP switching compatible and ST-BUS compliant devices
– IOM-2 compliant devices
– AC97-compliant devices
– IIS-compliant devices
– Serial peripheral interface
•
Multichannel transmit and receive of up to 128 channels
•
A wide selection of data sizes, including 8, 12, 16, 20, 24, or 32 bits
• µ
-law and A-law companding
•
Programmable polarity for both frame synchronization and data clocks
•
Programmable internal clock and frame generation
The McBSP consists of a data path and control path. The six pins, BDX, BDR, BFSX, BFSR, BCLKX, and
BCLKR, connect the control and data paths to external devices. The implemented pins can be programmed as general-purpose I/O pins if they are not used for serial communication.
The data is communicated to devices interfacing to the McBSP by way of the data transmit (BDX) pin for transmit and the data receive (BDR) pin for receive. The CPU or DMA reads the received data from the data receive register (DRR) and writes the data to be transmitted to the data transmit register (DXR). Data written to the DXR is shifted out to BDX by way of the transmit shift register (XSR). Similarly, receive data on the BDR pin is shifted into the receive shift register (RSR) and copied into the receive buffer register
(RBR). RBR is then copied to DRR, which can be read by the CPU or DMA. This allows internal data movement and external data communications simultaneously.
Control information in the form of clocking and frame synchronization is communicated by way of BCLKX,
BCLKR, BFSX, and BFSR. The device communicates to the McBSP by way of 16-bit-wide control registers accessible via the internal peripheral bus.
The control block consists of internal clock generation, frame synchronization signal generation, and their control, and multichannel selection. This control block sends notification of important events to the CPU and DMA by way of two interrupt signals, XINT and RINT, and two event signals, XEVT and REVT.
The on-chip companding hardware allows compression and expansion of data in either
µ
-law or A-law format. When companding is used, transmitted data is encoded according to the specified companding law and received data is decoded to 2s complement format.
The sample rate generator provides the McBSP with several means of selecting clocking and framing for both the receiver and transmitter. Both the receiver and transmitter can select clocking and framing independently.
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The McBSP allows the multiple channels to be independently selected for the transmitter and receiver.
When multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using time-division multiplexed data streams, the CPU may only need to process a few of them.
Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. All 128 channels in a bit stream consisting of a maximum of 128 channels can be enabled.
15 10
Reserved
R
9
XMCME
R/W
8
XPBBLK
R/W
7 6 5 4
XPBBLK XPABLK
R/W R/W
LEGEND: R = Read, W = Write, n = value present after reset
XCBLK
R
2
Figure 3-10. Multichannel Control Register (MCR1)
1
Reserved
R
15
Reserved
R
10 9
RMCME
R/W
0
XMCM
R/W
8
RPBBLK
R/W
7 6 5 4
RPBBLK RPABLK
R/W R/W
LEGEND: R = Read, W = Write, n = value present after reset
RCBLK
R
2
Figure 3-11. Multichannel Control Register (MCR2)
1
Reserved
R
0
RMCM
R/W
The McBSP has two working modes:
•
In the first mode, when (R/X)MCME = 0, it is comparable with the McBSPs used in the 5410 where the normal 32-channel selection is enabled (default).
•
In the second mode, when (R/X)MCME = 1, it has 128-channel selection capability. Multichannel control register Bit 9, (R/X)MCME, is used as the 128-channel selection enable bit. Once (R/X)MCME
= 1, twelve new registers ((R/X)CERC - (R/X)CERH) are used to enable the 128-channel selection.
The clock stop mode (CLKSTP) in the McBSP provides compatibility with the serial port interface protocol.
Clock stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.
Although the BCLKS pin is not available on the device PGE and GGU packages, the device is capable of synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the
PCR to accommodate this option.
15 14
Reserved
R/W
13
XIOEN
R/W
12
RIOEN
R/W
11
FSXM
R/W
10
FSRM
R/W
9
CLKXM
R/W
8
CLKRM
R/W
7 6 5 4
SCLKME CLKS STAT DX STAT DR STAT
R/W R/W R/W R/W
LEGEND: R = Read, W = Write, n = value present after reset
3
FSXP
R/W
2
FSRP
R/W
Figure 3-12. Pin Control Register (PCR)
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CLKXP
R/W
0
CLKRP
R/W
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The selection of sample rate input clock is made by the combination of the CLKSM (bit 13 in SRGR2) bit value and the SCLKME bit value as shown in
.
SCLKME
0
0
1
1
Table 3-7. Sample Rate Input Clock Selection
CLKSM
0
1
0
1
SAMPLE RATE CLOCK MODE
Reserved (CLKS pin unavailable)
CPU clock
BCLKR
BCLKX
When the SCLKME bit is cleared to 0, the CLKSM bit is used, as before, to select either the CPU clock or the CLKS pin (not bonded out on the device package) as the sample rate input clock. Setting the
SCLKME bit to 1 enables the CLKSM bit to select between the BCLKR pin or BCLKX pin for the sample rate input clock.
When either the BCLKR or CLKX is configured this way, the output buffer for the selected pin is automatically disabled. For example, with SCLKME = 1 and CLKSM = 0, the BCLKR pin is configured as the input of the sample rate generator. Both the transmitter and receiver circuits can be synchronized to the sample rate generator output by setting the CLKXM and CLKRM bits of the pin configuration register
(PCR) to 1. Note that the sample rate generator output will only be driven on the BCLKX pin since the
BCLKR output buffer is automatically disabled.
The McBSP is fully static and operates at arbitrary low clock frequencies. For maximum operating frequency, see
.
3.9
Hardware Timer
The device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits.
3.10 Clock Generator
The clock generator provides clocks to the device, and consists of a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided from an external clock source.
The reference clock input is then divided by two (DIV mode) to generate clocks for the device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU. The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the device.
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This clock generator allows system designers to select the clock source. The sources that drive the clock generator are:
•
A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of the device to enable the internal oscillator.
•
An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left unconnected.
NOTE
The crystal oscillator function is not supported by all die revisions of the device. See the
TMS320VC5416 Digital Signal Processor Silicon Errata (literature number SPRZ172) to verify which die revisions support this functionality.
The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved.
Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:
•
PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.
•
DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation.
The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 - CLKMD3 pins. For more programming information, see the TMS320C54x
DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131). The CLKMD pin configured clock options are shown in
CLKMD1
0
0
0
1
1
1
1
0
CLKMD2
0
0
1
0
1
1
0
1
CLKMD3
0
1
0
0
0
1
1
1
Table 3-8. Clock Mode Settings at Reset
CLKMD RESET VALUE CLOCK MODE
(1)
0000h
9007h
1/2 (PLL disabled)
PLL x 10
4007h
1007h
PLL x 5
PLL x 2
F007h
0000h
F000h
—
PLL x 1
1/2 (PLL disabled)
1/4 (PLL disabled)
Reserved (Bypass mode)
(1) The external CLKMD1-CLKMD3 pins are sampled to determine the desired clock generation mode while RS is low. Following reset, the clock generation mode can be reconfigured by writing to the internal clock mode register in software.
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3.11 Enhanced External Parallel Interface (XIO2)
The device external interface has been redesigned to include several improvements, including: simplification of the bus sequence, more immunity to bus contention when transitioning between read and write operations, the ability for external memory access to the DMA controller, and optimization of the power-down modes.
The bus sequence on the device still maintains all of the same interface signals as on previous 54x devices, but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide additional immunity against bus contention when switching between read operations and write operations. To maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous 54x devices is available.
shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode, or single memory reads in consecutive mode. The accesses shown in
always require 3
CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
MSTRB or IOSTRB
READ
PS/DS/IS
Leading
Cycle
Read
Cycle
Trailing
Cycle
Figure 3-13. Nonconsecutive Memory Read and I/O Read Bus Sequence
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shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown in
require (2 + n) CLKOUT cycles to complete, where n is the number of consecutive reads performed.
CLKOUT
A[22:0]
D[15:0]
R/W
MSTRB
PS/DS
READ READ READ
Leading
Cycle
Read
Cycle
Read
Cycle
Read
Cycle
Trailing
Cycle
Figure 3-14. Consecutive Memory Read Bus Sequence (n = 3 reads)
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shows the bus sequence for all memory writes and I/O writes. The accesses shown in
always require 3 CLKOUT cycles to complete.
CLKOUT
A[22:0]
D[15:0]
R/W
MSTRB or IOSTRB
WRITE
PS/DS/IS
Leading
Cycle
Write
Cycle
Trailing
Cycle
Figure 3-15. Memory Write and I/O Write Bus Sequence
The enhanced interface also provides the ability for DMA transfers to extend to external memory. For more information on DMA capability, see the DMA sections that follow.
The enhanced interface improves the low-power performance already present on the TMS320C5000™
DSP platform by switching off the internal clocks to the interface when it is not being used. This power-saving feature is automatic, requires no software setup, and causes no latency in the operation of the interface.
Additional features integrated in the enhanced interface are the ability to automatically insert bank-switching cycles when crossing 32K memory boundaries (see
), the ability to program up to 14 wait states through software (see
), and the ability to divide down CLKOUT by a factor of 1, 2, 3, or 4. Dividing down CLKOUT provides an alternative to wait states when interfacing to slower external memory or peripheral devices. While inserting wait states extends the bus sequence during read or write accesses, it does not slow down the bus signal sequences at the beginning and the end of the access. Dividing down CLKOUT provides a method of slowing the entire bus sequence when necessary. The CLKOUT divide-down factor is controlled through the DIVFCT field in the bank-switching control register (BSCR) (see
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3.12 DMA Controller
The device direct memory access (DMA) controller transfers data between points in the memory map without intervention by the CPU. The DMA allows movements of data to and from internal program/data memory, internal peripherals (such as the McBSPs), or external memory devices to occur in the background of CPU operation. The DMA has six independent programmable channels, allowing six different contexts for DMA operation.
3.12.1
Features
The DMA has the following features:
•
The DMA operates independently of the CPU.
•
The DMA has six channels. The DMA can keep track of the contexts of six independent block transfers.
•
The DMA has higher priority than the CPU for both internal and external accesses.
•
Each channel has independently programmable priorities.
•
Each channel's source and destination address registers can have configurable indexes through memory on each read and write transfer, respectively. The address may remain constant, be post-incremented, be post-decremented, or be adjusted by a programmable value.
•
Each read or write internal transfer may be initialized by selected events.
•
On completion of a half- or entire-block transfer, each DMA channel may send an interrupt to the CPU.
•
The DMA can perform double-word internal transfers (a 32-bit transfer of two 16-bit words).
3.12.2 DMA External Access
The DMA supports external accesses to data, I/O, and extended program memory. These overlay pages are only visible to the DMA controller. A maximum of two DMA channels can be used for external memory accesses. The DMA external accesses require a minimum of 8 cycles for external writes and a minimum of 11 cycles for external reads assuming the XIO02 is in consecutive mode (CONSEC = 1), wait state is set to two, and CLKOUT is not divided (DIVFCT = 00).
The control of the bus is arbitrated between the CPU and the DMA. While the DMA or CPU is in control of the external bus, the other will be held-off via wait states until the current transfer is complete. The DMA takes precedence over XIO requests.
•
Only two channels are available for external accesses. (One for external reads and one for external writes.)
•
Single-word (16-bit) transfers are supported for external accesses.
•
The DMA does not support transfers from the peripherals to external memory.
•
The DMA does not support transfers from external memory to the peripherals.
•
The DMA does not support external-to-external accesses.
•
The DMA does not support synchronized external accesses.
15
AUTOINIT
14
DINM
13
IMOD
12
CTMOD
11
SLAXS
10
SIND
8
7
DMS
6 5
DLAXS
4
LEGEND: R = Read, W = Write, n = value present after reset
DIND
2 1
Figure 3-16. DMA Transfer Mode Control Register (DMMCRn)
DMD
0
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These new bit fields were created to allow the user to define the space-select for the DMA
(internal/external).
The functions of the DLAXS and SLAXS bits are as follows:
•
DLAXS(DMMCRn[5]) Destination
– 0 = No external access (default internal)
– 1 = External access
•
SLAXS(DMMCRn[11]) Source
– 0 = No external access (default internal)
– 1 = External access
lists the DMD bit values and their corresponding destination space.
DMD
00
01
10
11
Table 3-9. DMD Section of the DMMCRn Register
Destination Space
PS
DS
I/O
Reserved
For the CPU external access, software can configure the memory cells to reside inside or outside the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the address generation logic generates an address outside its bounds, the device automatically generates an external access.
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3.12.3 DMA Memory Maps
The DMA memory maps, shown in
and
Figure 3-18 , allows the DMA transfer to be unaffected
by the status of the MP/MC, DROM, and OVLY bits.
Program
Hex
010000
Program
Hex
0x0000
Program
Program
Hex
0000
005F
0060
Hex xx0000
DLAXS = 0
SLAXS = 0
Reserved
On-Chip
DARAM0
8K Words
1FFF
2000
On-Chip
DARAM1
8K Words
3FFF
4000
Reserved
Reserved
On-Chip
DARAM2
8K Words
5FFF
6000
7FFF
8000
FFFF
On-Chip
DARAM3
8K Words
Reserved
017FFF
018000
019FFF
01A000
01BFFF
01C000
01DFFF
01E000
01FFFF
On-Chip
DARAM 4
8K Words
On-Chip
DARAM 5
8K Words
On-Chip
DARAM 6
8K Words
On-Chip
DARAM 7
8K Words
0x7FFF
0x8000
0x9FFF
0xA000
On-Chip
SARAM 0/4
8K Words
On-Chip
SARAM 1/5
8K Words
0xBFFF
0xC000
On-Chip
SARAM 2/6
8K Words
0xDFFF
0xE000
On-Chip
SARAM 3/7
8K Words
0xFFFF
Page 2 − 3 xxFFFF
Reserved
Page 0
Page 1
Page 4 − 127
Figure 3-17. On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)
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Data Space (0000 - 005F)
Hex
0000
001F
Reserved
0020
DRR20
0021
DRR10
0022 DXR20
0023
0024
002F
DXR10
Reserved
0030
0031
DRR22
DRR12
0032
0033
DXR22
DXR12
0034
0035
0036
0037
Reserved
RCERA2
XCERA2
0038
0039
003A
Reserved
RECRA0
003B
003C
003F
XECRA0
Reserved
0040
0041
0042
0043
DRR21
DRR11
DXR21
DXR11
0044
0049
004A
Reserved
RCERA1
004B
XCERA1
004C
005F
Reserved
0000
005F
0060
007F
0080
1FFF
2000
3FFF
4000
5FFF
6000
7FFF
8000
9FFF
A000
Data Space
Data Space
(See Breakout)
Scratch-Pad
RAM
On-Chip
DARAM0
8K Words
On-Chip
DARAM1
8K Words
On-Chip
DARAM2
8K Words
On-Chip
DARAM3
8K Words
On-Chip
DARAM4
8K Words
On-Chip
DARAM5
8K Words
Hex
0000
I/O Space
Reserved
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BFFF
C000
DFFF
E000
On-Chip
DARAM6
8K Words
On-Chip
DARAM7
8K Words
FFFF
FFFF
Figure 3-18. On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)
3.12.4
DMA Priority Level
Each DMA channel can be independently assigned high- or low-priority relative to each other. Multiple
DMA channels that are assigned to the same priority level are handled in a round-robin manner.
3.12.5 DMA Source/Destination Address Modification
The DMA provides flexible address-indexing modes for easy implementation of data management schemes such as autobuffering and circular buffers. Source and destination addresses can be indexed separately and can be post-incremented, post-decremented, or post-incremented with a specified index offset.
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3.12.6 DMA in Autoinitialization Mode
The DMA can automatically reinitialize itself after completion of a block transfer. Some of the DMA registers can be preloaded for the next block transfer through the DMA reload registers (DMGSA,
DMGDA, DMGCR, and DMGFR). Autoinitialization allows:
•
Continuous operation: Normally, the CPU would have to reinitialize the DMA immediately after the completion of the current block transfers, but with the reload registers, it can reinitialize these values for the next block transfer any time after the current block transfer begins.
•
Repetitive operation:The CPU does not preload the reload register with new values for each block transfer but only loads them on the first block transfer.
The DMA has been enhanced to expand the DMA reload register sets. Each DMA channel now has its own DMA reload register set. For example, the DMA reload register set for channel 0 has DMGSA0,
DMGDA0, DMGCR0, and DMGFR0 while DMA channel 1 has DMGSA1, DMGDA1, DMGCR1, and
DMGFR1, etc.
To utilize the additional DMA reload registers, the AUTOIX bit is added to the DMPREC register as shown in
.
15
FREE
14
AUTOIX
13
DPRC[5:0]
8
7 6 5
IOSEL
LEGEND: R = Read, W = Write, n = value present after reset
DE[5:0]
Figure 3-19. DMPREC Register
0
AUTOIX
0 (default)
1
Table 3-10. DMA Reload Register Selection
DMA RELOAD REGISTER USAGE IN AUTO INIT MODE
All DMA channels use DMGSA0, DMGDA0, DMGCR0 and DMGFR0
Each DMA channel uses its own set of reload registers
3.12.7 DMA Transfer Counting
The DMA channel element count register (DMCTRx) and the frame count register (DMFRCx) contain bit fields that represent the number of frames and the number of elements per frame to be transferred.
•
Frame count. This 8-bit value defines the total number of frames in the block transfer. The maximum number of frames per block transfer is 128 (FRAME COUNT= 0FFh). The counter is decremented upon the last read transfer in a frame transfer. Once the last frame is transferred, the selected 8-bit counter is reloaded with the DMA global frame reload register (DMGFR) if the AUTOINIT bit is set to 1.
A frame count of 0 (default value) means the block transfer contains a single frame.
•
Element count. This 16-bit value defines the number of elements per frame. This counter is decremented after the read transfer of each element. The maximum number of elements per frame is
65536 (DMCTRn = 0FFFFh). In autoinitialization mode, once the last frame is transferred, the counter is reloaded with the DMA global count reload register (DMGCR).
3.12.8 DMA Transfer in Doubleword Mode
Doubleword mode allows the DMA to transfer 32-bit words in any index mode. In doubleword mode, two consecutive 16-bit transfers are initiated and the source and destination addresses are automatically updated following each transfer. In this mode, each 32-bit word is considered to be one element.
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3.12.9 DMA Channel Index Registers
The particular DMA channel index register is selected by way of the SIND and DIND fields in the DMA transfer mode control register (DMMCRn). Unlike basic address adjustment, in conjunction with the frame index DMFRI0 and DMFRI1, the DMA allows different adjustment amounts depending on whether or not the element transfer is the last in the current frame. The normal adjustment value (element index) is contained in the element index registers DMIDX0 and DMIDX1. The adjustment value (frame index) for the end of the frame, is determined by the selected DMA frame index register, either DMFRI0 or DMFRI1.
The element index and the frame index affect address adjustment as follows:
•
Element index: For all except the last transfer in the frame, the element index determines the amount to be added to the DMA channel for the source/destination address register (DMSRCx/DMDSTx) as selected by the SIND/DIND bits.
•
Frame index: If the transfer is the last in a frame, frame index is used for address adjustment as selected by the SIND/DIND bits. This occurs in both single-frame and multiframe transfers.
3.12.10 DMA Interrupts
The ability of the DMA to interrupt the CPU based on the status of the data transfer is configurable and is determined by the IMOD and DINM bits in the DMA transfer mode control register (DMMCRn). The available modes are shown in
.
MODE
ABU (non-decrement)
ABU (non-decrement)
Multiframe
Multiframe
Either
Either
DINM
1
1
1
1
0
0
Table 3-11. DMA Interrupts
IMOD
0
1
0
1
X
X
INTERRUPT
At full buffer only
At half buffer and full buffer
At block transfer complete (DMCTRn = DMSEFCn[7:0] = 0)
At end of frame and end of block (DMCTRn = 0)
No interrupt generated
No interrupt generated
3.12.11 DMA Controller Synchronization Events
The transfers associated with each DMA channel can be synchronized to one of several events. The
DSYN bit field of the DMSEFCn register selects the synchronization event for a channel. The list of possible events and the DSYN values are shown in
.
DSYN VALUE
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
Table 3-12. DMA Synchronization Events
DMA SYNCHRONIZATION EVENT
No synchronization used
McBSP0 receive event
McBSP0 transmit event
McBSP2 receive event
McBSP2 transmit event
McBSP1 receive event
McBSP1 transmit event
McBSP0 receive event - ABIS mode
McBSP0 transmit event - ABIS mode
McBSP2 receive event - ABIS mode
McBSP2 transmit event - ABIS mode
McBSP1 receive event - ABIS mode
McBSP1 transmit event - ABIS mode
Timer interrupt event
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Table 3-12. DMA Synchronization Events (continued)
DMA SYNCHRONIZATION EVENT DSYN VALUE
1110b
1111b
INT3 goes active
Reserved
The DMA controller can generate a CPU interrupt for each of the six channels. However, due to a limit on the number of internal CPU interrupt inputs, channels 0, 1, 2, and 3 are multiplexed with other interrupt sources. DMA channels 0, 1, 2, and 3 share an interrupt line with the receive and transmit portions of the
McBSP. When the device is reset, the interrupts from these three DMA channels are deselected. The
INTSEL bit field in the DMPREC register can be used to select these interrupts, as shown in
.
INTSEL Value
00b (reset)
01b
10b
11b
IMR/IFR[6]
BRINT2
BRINT2
DMAC0
Reserved
Table 3-13. DMA Channel Interrupt Selection
IMR/IFR[7]
BXINT2
BXINT2
DMAC1
IMR/IFR[10]
BRINT1
DMAC2
DMAC2
IMR/IFR[11]
BXINT1
DMAC3
DMAC3
3.13 General-Purpose I/O Pins
In addition to the standard BIO and XF pins, the device has pins that can be configured for general-purpose I/O. These pins are:
•
18 McBSP pins
– BCLKX0/1/2,
– BCLKR0/1/2
– BDR0/1/2
– BFSX0/1/2
– BFSR0/1/2
– BDX0/1/2
•
8 HPI data pins
– HD0-HD7
The general-purpose I/O function of these pins is only available when the primary pin function is not required.
3.13.1 McBSP Pins as General-Purpose I/O
When the receive or transmit portion of a McBSP is in reset, its pins can be configured as general-purpose inputs or outputs. For more details on this feature, see
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3.13.2 HPI Data Pins as General-Purpose I/O
The 8-bit bidirectional data bus of the HPI can be used as general-purpose input/output (GPIO) pins when the HPI is disabled (HPIENA = 0) or when the HPI is used in HPI16 mode (HPI16 = 1). Two memory-mapped registers are used to control the GPIO function of the HPI data pins—the general-purpose I/O control register (GPIOCR) and the general-purpose I/O status register (GPIOSR). The
GPIOCR is shown in
15 8
Reserved
0
7 6 5 4
DIR7 DIR6 DIR5 DIR4
R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
3
DIR3
R/W-0
2
DIR2
R/W-0
1
DIR1
R/W-0
Figure 3-20. General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]
0
DIR0
R/W-0
The direction bits (DIRx) are used to configure HD0-HD7 as inputs or outputs.
The status of the GPIO pins can be monitored using the bits of the GPIOSR. The GPIOSR is shown in
15 8
Reserved
0
7 6 5 4
IO7 IO6 IO5 IO4
R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R = Read, W = Write, n = value present after reset
3
IO3
R/W-0
2
IO2
R/W-0
1
IO1
R/W-0
Figure 3-21. General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]
0
IO0
R/W-0
3.14 Device ID Register
A read-only memory-mapped register has been added to the device to allow user application software to identify on which device the program is being executed.
15 8
CHIP ID
R
7 4
CHIP REVISION
R
LEGEND: R = Read, W = Write, n = value present after reset
3
SUBSYSID
R
Figure 3-22. Device ID Register (CSIDR) [MMR Address 003Eh]
0
BIT
15-8
7-4
3-0
Table 3-14. Device ID Register (CSIDR) Bits
FUNCTION
Chip ID (hex code of 16)
Chip revision ID
Subsystem ID (0000b for single core devices)
44
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NAME
AR5
AR6
AR7
SP
BK
AR0
AR1
AR2
AR3
AR4
BRC
RSA
REA
PMST
XPC
—
AH
AG
BL
BH
BG
TREG
TRN
IMR
IFR
—
ST0
ST1
AL
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 www.ti.com
3.15 Memory-Mapped Registers
The device has 27 memory-mapped CPU registers, which are mapped in data memory space address 0h to 1Fh. Each device also has a set of memory-mapped registers associated with peripherals.
gives a list of CPU memory-mapped registers (MMRs) available.
shows additional peripheral
MMRs associated with the device.
16
17
18
19
20
11
12
13
14
15
6
7
8
9
10
DEC
0
1
2-5
29
30
31
26
27
28
21
22
23
24
25
Table 3-15. CPU Memory-Mapped Registers
ADDRESS
DESCRIPTION
10
11
12
13
14
B
C
D
E
F
6
7
8
9
A
HEX
0
1
2-5
1D
1E
1F
1A
1B
1C
15
16
17
18
19
Interrupt mask register
Interrupt flag register
Reserved for testing
Status register 0
Status register 1
Accumulator A low word (15-0)
Accumulator A high word (31-16)
Accumulator A guard bits (39-32)
Accumulator B low word (15-0)
Accumulator B high word (31-16)
Accumulator B guard bits (39-32)
Temporary register
Transition register
Auxiliary register 0
Auxiliary register 1
Auxiliary register 2
Auxiliary register 3
Auxiliary register 4
Auxiliary register 5
Auxiliary register 6
Auxiliary register 7
Stack pointer register
Circular buffer size register
Block repeat counter
Block repeat start address
Block repeat end address
Processor mode status (PMST) register
Extended program page register
Reserved
NAME
DRR20
DRR10
DXR20
DXR10
TIM
PRD
TCR
Table 3-16. Peripheral Memory-Mapped Registers for Each DSP Subsystem
34
35
36
37
38
ADDRESS
DEC HEX
32
33
20
21
22
23
24
25
26
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McBSP 0 Data Receive Register 2
McBSP 0 Data Receive Register 1
McBSP 0 Data Transmit Register 2
McBSP 0 Data Transmit Register 1
Timer Register
Timer Period Register
Timer Control Register
DESCRIPTION
Functional Overview
45
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
Table 3-16. Peripheral Memory-Mapped Registers for Each DSP Subsystem (continued)
NAME
—
SPSA0
SPSD0
—
GPIOCR
GPIOSR
CSIDR
—
DRR21
DRR11
—
SWWSR
BSCR
—
SWCR
HPIC
—
DRR22
DRR12
DXR22
DXR12
SPSA2
SPSD2
DXR21
DXR11
—
SPSA1
SPSD1
—
DMPREC
DMSA
DMSDI
DMSDN
CLKMD
—
66
67
68-71
72
73
61
62
63
64
65
74-83
84
85
86
87
88
89-95
54-55
56
57
58-59
60
49
50
51
52
53
ADDRESS
DEC
39
HEX
27
40
41
28
29
42
43
44
45-47
48
2A
2B
2C
2D-2F
30
36-37
38
39
3A-3B
3C
31
32
33
34
35
42
43
44-47
48
49
3D
3E
3F
40
41
4A-53
54
55
56
57
58
59-5F
DESCRIPTION
Reserved
Software Wait-State Register
Bank-Switching Control Register
Reserved
Software Wait-State Control Register
HPI Control Register (HMODE = 0 only)
Reserved
McBSP 2 Data Receive Register 2
McBSP 2 Data Receive Register 1
McBSP 2 Data Transmit Register 2
McBSP 2 Data Transmit Register 1
McBSP 2 Subbank Address Register
(1)
McBSP 2 Subbank Data Register
(1)
Reserved
McBSP 0 Subbank Address Register
(1)
McBSP 0 Subbank Data Register
(1)
Reserved
General-Purpose I/O Control Register
General-Purpose I/O Status Register
Device ID Register
Reserved
McBSP 1 Data Receive Register 2
McBSP 1 Data Receive Register 1
McBSP 1 Data Transmit Register 2
McBSP 1 Data Transmit Register 1
Reserved
McBSP 1 Subbank Address Register
(1)
McBSP 1 Subbank Data Register
(1)
Reserved
DMA Priority and Enable Control Register
DMA Subbank Address Register
(2)
DMA Subbank Data Register with Autoincrement
(2)
DMA Subbank Data Register
(2)
Clock Mode Register (CLKMD)
Reserved
(1) See
for a detailed description of the McBSP control registers and their subaddresses.
(2) See
for a detailed description of the DMA subbank addressed registers.
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3.16 McBSP Control Registers and Subaddresses
The control registers for the multichannel buffered serial port (McBSP) are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The McBSP subbank address register (SPSA) is used as a pointer to select a particular register within the subbank. The McBSP data register (SPSDx) is used to access (read or write) the selected register.
shows the McBSP control registers and their corresponding subaddresses.
Table 3-17. McBSP Control Registers and Subaddresses
McBSP0
NAME
SPCR10
ADDRESS
39h
McBSP1
NAME
SPCR11
ADDRESS
49h
SPCR20
RCR10
39h
39h
SPCR21
RCR11
49h
49h
RCR20
XCR10
XCR20
SRGR10
SRGR20
39h
39h
39h
39h
39h
RCR21
XCR11
XCR21
SRGR11
SRGR21
49h
49h
49h
49h
49h
MCR10
MCR20
RCERA0
RCERB0
XCERA0
XCERB0
PCR0
39h
39h
39h
39h
39h
39h
39h
MCR11
MCR21
RCERA1
RCERB1
XCERA1
XCERB1
PCR1
49h
49h
49h
49h
49h
49h
49h
RCERC0
RCERD0
XCERC0
XCERD0
RCERE0
RCERF0
XCERE0
XCERF0
RCERG0
RCERH0
XCERG0
XCERH0
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
39h
RCERC1
RCERD1
XCERC1
XCERD1
RCERE1
RCERF1
XCERE1
XCERF1
RCERG1
RCERH1
XCERG1
XCERH1
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
49h
McBSP2
NAME ADDRESS
SPCR12 35h
SPCR22
RCR12
35h
35h
RCR22
XCR12
XCR22
SRGR12
SRGR22
35h
35h
35h
35h
35h
MCR12
MCR22
RCERA2
RCERA2
XCERA2
XCERA2
PCR2
35h
35h
35h
35h
35h
35h
35h
RCERC2
RCERD2
XCERC2
XCERD2
RCERE2
RCERF2
XCERE2
XCERF2
RCERG2
RCERH2
XCERG2
XCERH2
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
35h
SUB-
ADDRESS
06h
07h
08h
09h
0Ah
00h
01h
02h
03h
04h
05h
0Bh
0Ch
0Dh
0Eh
010h
011h
012h
013h
014h
015h
016h
017h
018h
019h
01Ah
01Bh
DESCRIPTION
Serial port control register 1
Serial port control register 2
Receive control register 1
Receive control register 2
Transmit control register 1
Transmit control register 2
Sample rate generator register 1
Sample rate generator register 2
Multichannel control register 1
Multichannel control register 2
Receive channel enable register partition A
Receive channel enable register partition B
Transmit channel enable register partition A
Transmit channel enable register partition B
Pin control register
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
Additional channel enable register for
128-channel selection
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47
NAME
DMCTR2
DMSFC2
DMMCR2
DMSRC3
DMDST3
DMCTR3
DMSFC3
DMMCR3
DMSRC4
DMDST4
DMSRC0
DMDST0
DMCTR0
DMSFC0
DMMCR0
DMSRC1
DMDST1
DMCTR1
DMSFC1
DMMCR1
DMSRC2
DMDST2
DMCTR4
DMSFC4
DMMCR4
DMSRC5
DMDST5
DMCTR5
DMSFC5
DMMCR5
DMSRCP
DMDSTP
DMIDX0
DMIDX1
48
Functional Overview
ADDRESS
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 www.ti.com
3.17 DMA Subbank Addressed Registers
The direct memory access (DMA) controller has several control registers associated with it. The main control register (DMPREC) is a standard memory-mapped register. However, the other registers are accessed using the subbank addressing scheme. This allows a set or subbank of registers to be accessed through a single memory location. The DMA subbank address (DMSA) register is used as a pointer to select a particular register within the subbank, while the DMA subbank data (DMSD) register or the DMA subbank data register with autoincrement (DMSDI) is used to access (read or write) the selected register.
When the DMSDI register is used to access the subbank, the subbank address is automatically postincremented so that a subsequent access affects the next register within the subbank. This autoincrement feature is intended for efficient, successive accesses to several control registers. If the autoincrement feature is not required, the DMSDN register should be used to access the subbank.
shows the DMA controller subbank addressed registers and their corresponding subaddresses.
Table 3-18. DMA Subbank Addressed Registers
16h
17h
18h
19h
1Ah
11h
12h
13h
14h
15h
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
0Ch
0Dh
0Eh
0Fh
10h
07h
08h
09h
0Ah
0Bh
SUB-
ADDRESS
00h
01h
02h
03h
04h
05h
06h
DESCRIPTION
DMA channel 0 source address register
DMA channel 0 destination address register
DMA channel 0 element count register
DMA channel 0 sync select and frame count register
DMA channel 0 transfer mode control register
DMA channel 1 source address register
DMA channel 1 destination address register
DMA channel 1 element count register
DMA channel 1 sync select and frame count register
DMA channel 1 transfer mode control register
DMA channel 2 source address register
DMA channel 2 destination address register
DMA channel 2 element count register
DMA channel 2 sync select and frame count register
DMA channel 2 transfer mode control register
DMA channel 3 source address register
DMA channel 3 destination address register
DMA channel 3 element count register
DMA channel 3 sync select and frame count register
DMA channel 3 transfer mode control register
DMA channel 4 source address register
DMA channel 4 destination address register
DMA channel 4 element count register
DMA channel 4 sync select and frame count register
DMA channel 4 transfer mode control register
DMA channel 5 source address register
DMA channel 5 destination address register
DMA channel 5 element count register
DMA channel 5 sync select and frame count register
DMA channel 5 transfer mode control register
DMA source program page address (common channel)
DMA destination program page address (common channel)
DMA element index address register 0
DMA element index address register 1
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NAME
DMGSA2
DMGDA2
DMGCR2
DMGFR2
DMGSA3
DMGDA3
DMGCR3
DMGFR3
DMGSA4
DMGDA4
DMFRI0
DMFRI1
DMGSA0
DMGDA0
DMGCR0
DMGFR0
XSRCDP
XDSTDP
DMGSA1
DMGDA1
DMGCR1
DMGFR1
DMGCR4
DMGFR4
DMGSA5
DMGDA5
DMGCR5
DMGFR5 www.ti.com
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
56h/57h
ADDRESS
Table 3-18. DMA Subbank Addressed Registers (continued)
2Eh
2Fh
30h
31h
32h
29h
2Ah
2Bh
2Ch
2Dh
SUB-
ADDRESS
22h
23h
24h
25h
26h
27h
28h
38h
39h
3Ah
3Bh
3Ch
3Dh
33h
34h
35h
36h
37h
DESCRIPTION
DMA frame index register 0
DMA frame index register 1
DMA global source address reload register, channel 0
DMA global destination address reload register, channel 0
DMA global count reload register, channel 0
DMA global frame count reload register, channel 0
DMA extended source data page (currently not supported)
DMA extended destination data page (currently not supported)
DMA global source address reload register, channel 1
DMA global destination address reload register, channel 1
DMA global count reload register, channel 1
DMA global frame count reload register, channel 1
DMA global source address reload register, channel 2
DMA global destination address reload register, channel 2
DMA global count reload register, channel 2
DMA global frame count reload register, channel 2
DMA global source address reload register, channel 3
DMA global destination address reload register, channel 3
DMA global count reload register, channel 3
DMA global frame count reload register, channel 3
DMA global source address reload register, channel 4
DMA global destination address reload register, channel 4
DMA global count reload register, channel 4
DMA global frame count reload register, channel 4
DMA global source address reload register, channel 5
DMA global destination address reload register, channel 5
DMA global count reload register, channel 5
DMA global frame count reload register, channel 5
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3.18 Interrupts
Vector-relative locations and priorities for all internal and external interrupts are shown in
.
NAME
RS, SINTR
NMI, SINT16
SINT17
SINT18
SINT19
SINT20
SINT21
SINT22
SINT23
SINT24
SINT25
SINT26
SINT27
SINT28
SINT29
SINT30
INT0, SINT0
INT1, SINT1
INT2, SINT2
TINT, SINT3
RINT0, SINT4
XINT0, SINT5
RINT2, SINT6
XINT2, SINT7
INT3, SINT8
HINT, SINT9
RINT1, SINT10
XINT1, SINT11
DMAC4,SINT12
DMAC5,SINT13
Reserved
68
72
76
80
84
48
52
56
60
64
28
32
36
40
44
0
4
8
12
16
20
24
88
92
96
100
104
108
112
116
120-127
Table 3-19. Interrupt Locations and Priorities
12
13
14
15
16
10
11
7
8
9
TRAP/INTR
NUMBER (K)
0
1
2
3
4
5
6
22
23
24
25
26
17
18
19
20
21
27
28
29
30-31
LOCATION DECIMAL HEX PRIORITY
44
48
4C
50
54
30
34
38
3C
40
1C
20
24
28
2C
00
04
08
0C
10
14
18
58
5C
60
64
68
6C
70
74
78-7F
4
5
6
7
8
—
—
—
—
3
—
—
—
—
—
—
—
—
—
—
1
2
9
10
11
12
13
14
15
16
—
FUNCTION
Reset (hardware and software reset)
Nonmaskable interrupt
Software interrupt #17
Software interrupt #18
Software interrupt #19
Software interrupt #20
Software interrupt #21
Software interrupt #22
Software interrupt #23
Software interrupt #24
Software interrupt #25
Software interrupt #26
Software interrupt #27
Software interrupt #28
Software interrupt #29
Software interrupt #30
External user interrupt #0
External user interrupt #1
External user interrupt #2
Timer interrupt
McBSP #0 receive interrupt (default)
McBSP #0 transmit interrupt (default)
McBSP #2 receive interrupt (default)
McBSP #2 transmit interrupt (default)
External user interrupt #3
HPI interrupt
McBSP #1 receive interrupt (default)
McBSP #1 transmit interrupt (default)
DMA channel 4 (default)
DMA channel 5 (default)
Reserved
The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in
15
Reserved
14 13
DMAC5
12
DMAC4
11
XINT1
10
RINT1
9
HINT
8
INT3
7 6 5 4
XINT2 RINT2 XINT0 RINT0
LEGEND: R = Read, W = Write, n = value present after reset
3
TINT
2
INT2
Figure 3-23. IFR and IMR Registers
1
INT1
0
INT0
50
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4 Support
4.1
Documentation Support
Extensive documentation supports all TMS320™ DSP family of devices from product announcement through applications development. The following types of documentation are available to support the design and use of the C5000™ platform of DSPs:
SPRU307:
TMS320C54x DSP Family Functional Overview
Provides a functional overview of the devices included in the TMS320C54x™ DSP generation of digital signal processors. Included are descriptions of the CPU architecture, bus structure, memory structure, on-chip peripherals, and instruction set.
SPRA164:
Calculation of TMS320LC54x Power Dissipation
Describes the power-saving features of the TMS320LC54x and presents techniques for analyzing systems and device conditions to determine operating current levels and power dissipaton. From this information, informed decisions can be made regarding power supply requirements and thermal management considerations.
The five-volume TMS320C54x DSP Reference Set consists of:
SPRU131:
TMS320C54x DSP Reference Set, Volume 1: CPU
Describes the TMS320C54x 16-bit fixed-point general-purpose digital signal processors.
Covered are its architecture, internal register structure, data and program addressing, and the instruction pipeline. Also includes development support information, parts lists, and design considerations for using the XDS510 emulator.
SPRU172:
TMS320C54x DSP Reference Set, Volume 2: Mnemonic Instruction Set
Describes the TMS320C54x digital signal processor mnemonic instructions individually. Also includes a summary of instruction set classes and cycles.
SPRU179:
TMS320C54x DSP Reference Set, Volume 3: Algebraic Instruction Set
Describes the TMS320C54x digital signal processor algebraic instructions individually. Also includes a summary of instruction set classes and cycles.
SPRU173:
TMS320C54x DSP Reference Set, Volume 4: Applications Guide
Describes software and hardware applications for the TMS320C54x digital signal processor.
Also includes development support information, parts lists, and design considerations for using the XDS510 emulator.
SPRU302:
TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals
Describes the enhanced peripherals available on the TMS320C54x digital signal processors.
Includes the multichannel buffered serial ports (McBSPs), direct memory access (DMA) controller, interprocessor communications, and the HPI-8 and HPI-16 host port interfaces.
The reference set describes in detail the TMS320C54x™ DSP products currently available and the hardware and software applications, including algorithms, for fixed-point TMS320™ DSP family of devices.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal processing research and education. The TMS320 DSP newsletter, Details on Signal Processing, is published quarterly and distributed to update TMS320 DSP customers on product information.
Information regarding TI DSP porducts is also available on the web at www.ti.com.
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4.2
Device and Development-Support Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
TMS320 DSP devices and support tools. Each TMS320 DSP commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320C6412GDK600). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX
Experimental device that is not necessarily representative of the final device's electrical specifications
TMP
Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification
TMS
Fully qualified production device
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal qualification testing.
Fully qualified development-support product
TMDS
TMX and TMP devices and TMDX development-support tools are shipped with appropriate disclaimers describing their limitations and intended uses.
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.
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5 Electrical Specifications
This section provides the absolute maximum ratings and the recommended operating conditions for the
TMS320VC5416 DSP.
5.1
Absolute Maximum Ratings
The absolute maximum ratings are measure over operating case temperature range. Stresses beyond those listed under
"absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to
DV
SS
.
DV
DD
CV
DD
V
I
V
O
T
C
T stg
Supply voltage I/O range
Supply voltage core range
Input voltage range
Output voltage range
Operating case temperature range
Storage temperature range
– 0.3 V to 4.0 V
– 0.3 V to 2.0 V
– 0.3 V to 4.5 V
– 0.3 V to 4.5 V
– 40
°
C to 100
°
C
– 55
°
C to 150
°
C
5.2
Recommended Operating Conditions
DV
DD
CV
DD
CV
DD
DV
SS
CV
SS
Device supply voltage, I/O
Device supply voltage, core (VC5416-160)
Device supply voltage, core (VC5416-120)
Supply voltage, GND
MIN
2.7
1.55
1.42
NOM
3.3
1.6
1.5
0
V
IH
High-level input voltage, I/O
Low-level input voltage
High-level output current
(1) (2)
Low-level output current
(1) (2)
Operating case temperature
RS, INTn, NMI, X2/CLKIN,
CLKMDn, BCLKRn, BCLKXn,
HCS, HDS1, HDS2, HAS,
TRST, BIO, Dn, An, HDn, TCK
DV
DD
= 2.7 V to 3.6 V
All other inputs
2.4
V
IL
I
OH
I
OL
T
C
2
– 0.3
– 40
(1) The maximum output currents are DC values only. Transient currents may exceed these values.
(2) These output current limits are used for the test conditions on V
OL and V
OH
, except where noted otherwise.
MAX UNIT
3.6
V
1.65
1.65
V
V
V
DV
DD
+ 0.3
V
DV
DD
+ 0.3
0.8
V
– 8 mA
8 mA
100
°
C
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5.3
Electrical Characteristics
The electrical charactheristics are measured over recommended operating case temperature range (unless otherwise noted).
All values are typical unless otherwise specified.
I
V
V
I
OH
OL
PARAMETER
High-level output voltage
(1)
Low-level output voltage
(1)
X2/CLKIN
Input current
(V
I
= DV
SS to DV
DD
)
TRST, HPI16
HPIENA
TMS, TCK, TDI, HPI
(2)
A[17:0], D[15:0],
HD[7:0]
TEST CONDITIONS
DV
DD
= 2.7 V to 3 V, I
OH
= – 2 mA
DV
DD
= 3 V to 3.6 V, I
OH
= MAX
I
OL
= MAX
With internal pulldown
With internal pulldown, RS = 0
With internal pullups
Bus holders enabled, DV
DD
= MAX
(3)
MIN
2.2
2.4
– 40
– 10
– 10
– 400
– 275
TYP MAX
0.4
40
800
400
10
275
UNIT
µ
µ
V
V
A
A
I
I
I
DDC
DDP
DD
Supply current, pins
Supply current, standby
All other input-only pins
Supply current, core CPU
IDLE2
IDLE3 Divide-by-two mode, CLKIN stopped
CV
DD
= 1.6 V, f x
DV
DD
= 3.0 V, f x
= 160 ,
(4)
T
C
= 160 MHz,
= 25
°
C
(4)
T
C
= 25
°
C
PLL
×
1 mode, 20 MHz input
T
C
T
C
= 25
°
C
= 100
°
C
– 5
60
40
(5)
(6)
2
1
30
5 mA mA mA
C i
C o
Input capacitance
Output capacitance
5
5 pF pF
(1) All input and output voltage levels except RS, INT0-INT3, NMI, X2/CLKIN, CLKMD1-CLKMD3, BCLKRn, BCLKXn, HCS, HAS, HDS1,
HDS2, BIO, TCK, TRST, Dn, An, HDn are LVTTL-compatible.
(2) HPI input signals except for HPIENA and HPI16, when HPIENA = 0.
(3) V
IL(MIN)
≤
V
I
≤
V
IL(MAX) or V
IH(MIN)
≤
V
I
≤
V
IH(MAX)
(4) Clock mode: PLL
×
1 with external source
(5) This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being executed.
(6) This value was obtained with single-cycle external writes, CLKOFF = 0 and load = 15 pF. For more details on how this calculation is performed, refer to the Calculation of TMS320LC54x Power Dissipation application report (literature number SPRA164).
5.3.1
Test Loading
Tester Pin Electronics
Data Sheet Timing Reference Point
42
W
3.5 nH
4.0 pF 1.85 pF
Transmission Line
Z0 = 50
W
(see note)
Output
Under
Test
Device Pin
(see note)
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
Figure 5-1. Tester Pin Electronics
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5.3.2 Timing Parameter Symbology
Timing parameter symbols used in the timing requirements and switching characteristics tables are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows:
Lowercase subscripts and their meanings:
a access time c cycle time (period) d delay time dis disable time f en enable time fall time h hold time t r rise time su setup time transition time v valid time w pulse duration (width)
X Unknown, changing, or don't care level
Letters and symbols and their meanings:
H High
L Low
V Valid
Z High impedance
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5.3.3 Internal Oscillator With External Crystal
The internal oscillator is enabled by selecting the appropriate clock mode at reset (this is device-dependent; see
) and connecting a crystal or ceramic resonator across X1 and
X2/CLKIN. The CPU clock frequency is one-half, one-fourth, or a multiple of the oscillator frequency. The multiply ratio is determined by the bit settings in the CLKMD register.
The crystal should be in fundamental-mode operation, and parallel resonant, with an effective series resistance of 30 Ω maximum and power dissipation of 1 mW. The connection of the required circuit, consisting of the crystal and two load capacitors, is shown in
Figure 5-2 . The load capacitors, C
1 should be chosen such that the equation below is satisfied. C
L and C
2
(recommended value of 10 pF) in the
, equation is the load specified for the crystal.
C
L
+
C
1
C
2
(C
1
)
C
2
)
Table 5-1. Input Clock Frequency Characteristics
MIN MAX Unit
f x
Input clock frequency 10
(1)
20
(2)
MHz
(1) This device utilizes a fully static design and therefore can operate with t c(CI) approaching 0 Hz approaching
∞
. The device is characterized at frequencies
(2) It is recommended that the PLL multiply by N clocking option be used for maximum frequency operation.
X1 X2/CLKIN
Crystal
C1 C2
Figure 5-2. Internal Divide-By-Two Clock Option With External Crystal
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5.4
Clock Options
The frequency of the reference clock provided at the CLKIN pin can be divided by a factor of two or four or multiplied by one of several values to generate the internal machine cycle.
5.4.1
Divide-By-Two and Divide-By-Four Clock Options
The frequency of the reference clock provided at the X2/CLKIN pin can be divided by a factor of two or four to generate the internal machine cycle. The selection of the clock mode is described in
When an external clock source is used, the frequency injected must conform to specifications listed in
An external frequency source can be used by applying an input clock to X2/CLKIN with X1 left unconnected.
shows the configuration options for the CLKMD pins that generate the external divide-by-2 or divide-by-4 clock option.
and
assume testing over recommended operating conditions and
H = 0.5t
c(CO)
(see
).
Table 5-2. Clock Mode Pin Settings for the Divide-By-2 and By Divide-By-4 Clock Options
CLKMD1
0
1
1
CLKMD2
0
0
1
CLKMD3
0
1
1
Clock Mode
1/2, PLL disabled
1/4, PLL disabled
1/2, PLL disabled t c(CI) t f(CI) t r(CI) t w(CIL) t w(CIH)
Table 5-3. Divide-By-2 and Divide-By-4 Clock Options Timing Requirements
Cycle time, X2/CLKIN
Fall time, X2/CLKIN
Rise time, X2/CLKIN
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
5416-120
5416-160
MIN MAX
20
4
4
4
4
Unit
ns ns ns ns ns
Table 5-4. Divide-By-2 and Divide-By-4 Clock Options Switching Characteristics
t c(CO) t d(CIH-CO) t f(CO) t r(CO) t w(COL) t w(COH)
PARAMETER
Cycle time, CLKOUT
Delay time, X2/CLKIN high to CLKOUT high/low
Fall time, CLKOUT
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
MIN
8.33
(1)
4
H – 2
H – 2
5416-120
TYP
7
1
1
H
H
MAX MIN
(2)
6.25
(1)
11 4
5416-160
TYP
H + 1
H + 1
H – 2
H – 2
MAX
(2)
7
1
11
1
H H + 1
H H + 1
Unit
(1) It is recommended that the PLL clocking operation be used for maximum frequency operation.
(2) This device utilizes a fully static design and therefore can operate with t c(Cl) approaching
∞
. The device is characterized at frequencies approaching 0 Hz.
ns ns ns ns ns ns
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t w(CIH) t r(CI) t w(CIL) t f(CI) t c(CI)
X2/CLKIN t c(CO) t d(CIH-CO) t f(CO) t r(CO) t w(COH) t w(COL)
CLKOUT
(see Note A)
A.
The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as
00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5-3. External Divide-By-Two Clock Timing
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5.4.2
Multiply-By-N Clock Option (PLL Enabled)
The frequency of the reference clock provided at the X2/CLKIN pin can be multiplied by a factor of N to generate the internal machine cycle. The selection of the clock mode and the value of N is described in
Following reset, the software PLL can be programmed for the desired multiplication factor. Refer to the
TMS320C54x DSP Reference Set, Volume 1: CPU and Peripherals (literature number SPRU131) for detailed information on programming the PLL.
When an external clock source is used, the external frequency injected must conform to specifications listed in
and
assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Table 5-5. Multiply-By-N Clock Option Timing Requirements
t c(CI)
Cycle time, X2/CLKIN t f(CI) t r(CI) t w(CIL) t w(CIH)
Fall time, X2/CLKIN
Rise time, X2/CLKIN
Pulse duration, X2/CLKIN low
Pulse duration, X2/CLKIN high
(1) N is the multiplication factor.
Integer PLL multiplier N (N = 1-15)
(1)
PLL multiplier N = x.5
(1)
PLL multiplier N = x.25, x.75
(1)
5416-120
5416-160
MIN MAX
20 200
20
20
100
50
4
4
4
4
Unit
ns ns ns ns ns t c(CO) t d(CI-CO) t f(CO) t r(CO) t w(COL) t w(COH) t p
Table 5-6. Multiply-By-N Clock Option Switching Characteristics
PARAMETER
Cycle time, CLKOUT
Delay time, X2/CLKIN high/low to CLKOUT high/low
Fall time, CLKOUT
Rise time, CLKOUT
Pulse duration, CLKOUT low
Pulse duration, CLKOUT high
Transitory phase, PLL lock-up time
MIN
5416-120
TYP MAX
8.33
4 7
2
11
H – 2
H – 2
MIN
5416-160
TYP MAX
6.25
4 7
2
11
2
H H + 1 H – 2
H H + 1 H – 2
30
2
H
H
H + 1
H + 1
30
Unit
ns ns ns ns ns ns ms
t w(CIH) t f(CI) t c(CI) t w(CIL) t r(CI)
X2/CLKIN t p
Unstable t d(CI-CO) t c(CO) t w(COH) t f(CO) t w(COL) t r(CO)
CLKOUT
(see Note A)
A.
The CLKOUT timing in this diagram assumes the CLKOUT divide factor (DIVFCT field in the BSCR) is configured as
00 (CLKOUT not divided). DIVFCT is configured as CLKOUT divided-by-4 mode following reset.
Figure 5-4. Multiply-By-One Clock Timing
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5.5
Memory and Parallel I/O Interface Timing
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5.5.1
Memory Read
External memory reads can be performed in consecutive or nonconsecutive mode under control of the CONSEC bit in the BSCR.
and
assume testing over recommended operating conditions with
MSTRB = 0 and H = 0.5t
c(CO)
(see
and
Table 5-7. Memory Read Timing Requirements
t a(A)M1 t a(A)M2 t su(D)R t h(D)R
Access time, read data access from address valid, first read access
(1)
Access time, read data access from address valid, consecutive read accesses
Setup time, read data valid before CLKOUT low
Hold time, read data valid after CLKOUT low
(1) Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
(1)
5416-120
5416-160
MIN MAX
4H–9
2H–9
7
0
UNIT
ns ns ns ns
Table 5-8. Memory Read Switching Characteristics
PARAMETER
t d(CLKL-A) t d(CLKL-MSL) t d(CLKL-MSH)
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to MSTRB low
Delay time, CLKOUT low to MSTRB high
(1)
(1) Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
5416-120
5416-160
MIN MAX
–1 4
–1
0
4
4
UNIT
ns ns ns
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CLKOUT
A[22:0]
(see Note A) t d(CLKL-A) t d(CLKL-MSL) t d(CLKL-MSH) t a(A)M1
D[15:0] t su(D)R
MSTRB
R/W
(see Note A)
PS/DS
(see Note A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-5. Nonconsecutive Mode Memory Reads t h(D)R
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CLKOUT t d(CLKL-A) t d(CLKL-MSL)
A[22:0]
(see Note A) t a(A)M1 t d(CLKL-A) t d(CLKL-A) t d(CLKL-MSH) t a(A)M2
D[15:0] t su(D)R t h(D)R
MSTRB
R/W
(see Note A)
PS/DS
(see Note A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-6. Consecutive Mode Memory Reads t su(D)R t h(D)R
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5.5.2
Memory Write
assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5t
c(CO)
(see
Table 5-9. Memory Write Switching Characteristics
PARAMETER
t d(CLKL-A) t su(A)MSL t d(CLKL-D)W t su(D)MSH t h(D)MSH t d(CLKL-MSL) t w(SL)MS t d(CLKL-MSH)
Delay time, CLKOUT low to address valid
Hold time, data valid after MSTRB high
Delay time, CLKOUT low to MSTRB low
Pulse duration, MSTRB low
Delay time, CLKOUT low to MSTRB high
(1)
Setup time, address valid before MSTRB low
Delay time, CLKOUT low to data valid
Setup time, data valid before MSTRB high
(1)
(1) Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
5416-120
5416-160
MIN
–1
MAX
4
2H – 3
–1 4
2H – 4 2H + 6
2H – 5 2H + 6
–1 4
2H – 2
0 4
UNIT
ns ns ns ns ns ns ns ns
CLKOUT t d(CLKL-A) t d(CLKL-A) t d(CLKL-D)W t su(A)MSL
A[22:0]
(see Note A) t su(D)MSH t h(D)MSH
D[15:0] t d(CLKL-MSL) t d(CLKL-MSH) t w(SL)MS
MSTRB
R/W
(see Note A)
PS/DS
(see Note A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-7. Memory Write (MSTRB = 0)
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5.5.3
I/O Read
and
assume testing over recommended operating conditions, IOSTRB = 0, and
H = 0.5t
c(CO)
(see
).
Table 5-10. I/O Read Timing Requirements
t a(A)M1 t su(D)R t h(D)R
Access time, read data access from address valid, first read access
Setup time, read data valid before CLKOUT low
Hold time, read data valid after CLKOUT low
(1)
(1) Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
5416-120
5416-160
MIN MAX
4H – 9
7
0
UNIT
ns ns ns
Table 5-11. I/O Read Switching Characteristics
PARAMETER
t d(CLKL-A) t d(CLKL-IOSL) t d(CLKL-IOSH)
Delay time, CLKOUT low to address valid
Delay time, CLKOUT low to IOSTRB low
Delay time, CLKOUT low to IOSTRB high
(1)
(1) Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
5416-120
5416-160
MIN
– 1
MAX
4
– 1
0
4
4
UNIT
ns ns ns
CLKOUT t d(CLKL-A) t d(CLKL-A) t d(CLKL-IOSL) t d(CLKL-IOSH)
A[22:0]
(see Note A) t a(A)M1 t su(D)R t h(D)R
D[15:0]
IOSTRB
R/W
(see Note A)
IS
(see Note A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-8. Parallel I/O Port Read (IOSTRB = 0)
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5.5.4
I/O Write
assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5t
c(CO)
(see
Table 5-12. I/O Write Switching Characteristics
PARAMETER
t d(CLKL-A) t su(A)IOSL t d(CLKL-D)W t su(D)IOSH t h(D)IOSH t d(CLKL-IOSL) t w(SL)IOS t d(CLKL-IOSH)
Delay time, CLKOUT low to address valid
Hold time, data valid after IOSTRB high
Delay time, CLKOUT low to IOSTRB low
Pulse duration, IOSTRB low
Delay time, CLKOUT low to IOSTRB high
(1)
Setup time, address valid before IOSTRB low
Delay time, CLKOUT low to write data valid
Setup time, data valid before IOSTRB high
(1)
(1) Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
5416-120
5416-160
MIN
– 1
MAX
4
2H – 3
– 1 4
2H – 4 2H + 6
2H – 5 2H + 6
– 1 4
2H – 2
0 4
UNIT
ns ns ns ns ns ns ns ns
CLKOUT t d(CLKL-A) t d(CLKL-A)
A[22:0]
(see Note A) t d(CLKL-D)W t d(CLKL-D)W t su(A)IOSL
D[15:0] t su(D)IOSH t d(CLKL-IOSH) t d(CLKL-IOSL) t h(D)IOSH
IOSTRB
R/W
(see Note A) t w(SL)IOS
IS
(see Note A)
A.
Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.
Figure 5-9. Parallel I/O Port Write (IOSTRB = 0)
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5.5.5 Ready Timing for Externally Generated Wait States
and
assume testing over recommended operating conditions and H = 0.5t
c(CO)
).
(see
Table 5-13. Ready Timing Requirements for Externally Generated Wait States
(1)
5416-120
5416-160
UNIT
t su(RDY) t h(RDY) t v(RDY)MSTRB t h(RDY)MSTRB t v(RDY)IOSTRB t h(RDY)IOSTRB
Setup time, READY before CLKOUT low
Hold time, READY after CLKOUT low
Valid time, READY after MSTRB low
(2)
Hold time, READY after MSTRB low
(2)
Valid time, READY after IOSTRB low
(2)
Hold time, READY after IOSTRB low
(2)
MIN MAX
7
0
4H
4H
4H – 4
4H – 4 ns ns ns ns ns ns
(1) The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY, as least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
(2) These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.
Table 5-14. Ready Switching Characteristics for Externally Generated Wait States
(1)
t d(MSCL) t d(MSCH)
PARAMETER
Delay time, CLKOUT low to MSC low
Delay time, CLKOUT low to MSC high
5416-120
5416-160
MIN
0
0
MAX
4
4
UNIT
ns ns
(1) The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by READY, as least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.
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CLKOUT
A[22:0]
D[15:0]
READY
MSTRB
MSC t su(RDY) t h(RDY) t v(RDY)MSTRB t h(RDY)MSTRB t d(MSCL) t d(MSCH)
Leading
Cycle
Wait States
Generated Internally
Wait
States
Generated by READY
Figure 5-10. Memory Read With Externally Generated Wait States
Trailing
Cycle
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CLKOUT
A[22:0]
D[15:0]
READY
MSTRB
MSC t su(RDY) t h(RDY) t v(RDY)MSTRB t h(RDY)MSTRB t d(MSCL) t d(MSCH)
Leading
Cycle
Wait
States
Generated
Internally
Wait
States
Generated by READY
Figure 5-11. Memory Write With Externally Generated Wait States
Trailing
Cycle
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CLKOUT
A[22:0]
D[15:0]
READY
IOSTRB
MSC t su(RDY) t h(RDY) t v(RDY)IOSTRB t h(RDY)IOSTRB t d(MSCL) t d(MSCH)
Leading
Cycle
Wait States
Generated Internally
Wait
States
Generated by READY
Figure 5-12. I/O Read With Externally Generated Wait States
Trailing
Cycle
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CLKOUT
A[22:0]
D[15:0]
READY
IOSTRB
MSC t su(RDY) t h(RDY) t v(RDY)IOSTRB t h(RDY)IOSTRB t d(MSCL) t d(MSCH)
Leading
Cycle
Wait
States
Generated
Internally
Wait
States
Generated by READY
Figure 5-13. I/O Write With Externally Generated Wait States
Trailing
Cycle
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5.5.6 HOLD and HOLDA Timings
and
assume testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Table 5-15. HOLD and HOLDA Timing Requirements
t w(HOLD) t su(HOLD)
Pulse duration, HOLD low duration
Setup time, HOLD before CLKOUT low
(1)
5416-120
5416-160
MIN MAX
4H+8
7
UNIT
(1) This input can be driven from an asynchronous source, therefore, there are no specific timing requirments with respect to CLKOUT.
However, if this timing is met, the input will be recognized on the CLKOUT edge referenced.
ns ns
Table 5-16. HOLD and HOLDA Switching Characteristics
t dis(CLKL-A) t dis(CLKL-RW) t dis(CLKL-S) t en(CLKL-A) t en(CLKL-RW) t en(CLKL-S) t v(HOLDA) t w(HOLDA)
PARAMETER
Disable time, Address, PS, DS, IS high impedance from CLKOUT low
Disable time, R/W high impedance from CLKOUT low
Disable time, MSTRB, IOSTRB high impedance from CLKOUT low
Enable time, Address, PS, DS, IS valid from CLKOUT low
Enable time, R/W enabled from CLKOUT low
Enable time, MSTRB, IOSTRB enabled from CLKOUT low
Valid time, HOLDA low after CLKOUT low
Valid time, HOLDA high after CLKOUT low
Pulse duration, HOLDA low duration
5416-120
5416-160
MIN MAX
3
2H+3
3
3
– 1
2H–3
2H+3
2 2H+3
– 1 4
4
UNIT
ns ns ns ns ns ns ns ns ns
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CLKOUT t su(HOLD) t w(HOLD)
HOLD
HOLDA
A[22:0]
PS, DS, IS
D[15:0]
R / W
MSTRB
IOSTRB t su(HOLD) t v(HOLDA) t v(HOLDA) t w(HOLDA) t dis(CLKL−A) t dis(CLKL−RW) t dis(CLKL−S) t dis(CLKL−S)
Figure 5-14. HOLD and HOLDA Timings (HM = 1) t en(CLKL−A)
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t en(CLKL−RW) t en(CLKL−S) t en(CLKL−S)
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5.5.7 Reset, BIO, Interrupt, and MP/MC Timings
assumes testing over recommended operating conditions and H = 0.5t
c(CO)
).
(see
Table 5-17. Reset, BIO, Interrupt, and MP/MC Timing Requirements
5416-120
5416-160
UNIT
t h(RS) t h(BIO) t h(INT) t h(MPMC) t w(RSL) t w(BIO)S t w(BIO)A t w(INTH)S t w(INTH)A t w(INTL)S t w(INTL)A t w(INTL)WKP t su(RS) t su(BIO) t su(INT) t su(MPMC)
Hold time, RS after CLKOUT low
(1)
Hold time, BIO after CLKOUT low
(1)
Hold time, INTn, NMI, after CLKOUT low
(1) (2)
Hold time, MP/MC after CLKOUT low
(1)
Pulse duration, RS low
(3) (4)
Pulse duration, BIO low, synchronous
Pulse duration, BIO low, asynchronous
Pulse duration, INTn, NMI high (synchronous)
Pulse duration, INTn, NMI high (asynchronous)
Pulse duration, INTn, NMI low (synchronous)
Pulse duration, INTn, NMI low (asynchronous)
Pulse duration, INTn, NMI low for IDLE2/IDLE3 wakeup
Setup time, RS before X2/CLKIN low
Setup time, BIO before CLKOUT low
(2) (1)
(1)
Setup time, INTn, NMI, RS before CLKOUT low
Setup time, MP/MC before CLKOUT low
(1)
(1)
MIN MAX
2
4
0
4
4H + 3
2H + 3
4H
2H + 2
4H
2H + 2
4H
7
3
7
7
5 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(1) These inputs can be driven from an asynchronous source, therefore, there are no specific timing requirements with respect to CLKOUT, however, if setup and hod timings are met, the input will be recognized on the CLKOUT edge referenced.
(2) The external interrupts (INT0-INT3, NMI) are synchronized to the core CPU by way of a two-flip-flop synchronizer that samples these inputs with consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a1-0-0 sequence at the timing that is corresponding to three CLKOUTs sampling sequence.
(3) If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50
µ s to ensure synchronization and lock-in of the PLL.
(4) Note that RS may cause a change in clock frequency, therefore changing the value of H.
X2/CLKIN t su(RS) t w(RSL)
RS, INTn, NMI t su(INT) t h(RS)
CLKOUT t su(BIO) t h(BIO)
BIO t w(BIO)S
Figure 5-15. Reset and BIO Timings
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CLKOUT t su(INT)
INT, NMI t su(INT) t w(INTH)A t w(INTL)A
Figure 5-16. Interrupt Timing
CLKOUT
RS
MP/MC t su(MPMC)
Figure 5-17. MP/MC Timing t h(INT) t h(MPMC)
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5.5.8 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
assumes testing over recommended operating conditions and H = 0.5t
c(CO)
(see
Table 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
t d(CLKL-IAQL) t d(CLKL-IAQH) t d(CLKL-IACKL) t d(CLKL-IACKH) t d(CLKL-A) t w(IAQL) t w(IACKL)
PARAMETER
Delay time, CLKOUT low to IAQ low
Delay time, CLKOUT low to IAQ high
Delay time, CLKOUT low to IACK low
Delay time, CLKOUT low to IACK high
Delay time, CLKOUT low to address valid
Pulse duration, IAQ low
Pulse duration, IACK low
5416-120
5416-160
MIN MAX
– 1 4
– 1
– 1
– 1
4
4
4
4 – 1
2H – 2
2H – 2
UNIT
ns ns ns ns ns ns ns
CLKOUT t d(CLKL−A) t d(CLKL−A)
A[22:0] t d(CLKL − IAQL) t d(CLKL − IAQH)
IAQ t w(IAQL) t d(CLKL − IACKL) t d(CLKL − IACKH) t w(IACKL)
IACK
Figure 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings
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5.5.9 External Flag (XF) and TOUT Timings
assumes testing over recommended operating conditions and H = 0.5t
c(CO) and
(see
t d(XF) t d(TOUTH) t d(TOUTL) t w(TOUT)
Table 5-19. External Flag (XF) and TOUT Switching Characteristics
PARAMETER
Delay time, CLKOUT low to XF high
Delay time, CLKOUT low to XF low
Delay time, CLKOUT low to TOUT high
Delay time, CLKOUT low to TOUT low
Pulse duration, TOUT
5416-120
5416-160
MIN MAX
– 1 4
– 1
– 1
– 1
2H – 4
4
4
4
UNIT
ns ns ns ns
CLKOUT t d(XF)
XF
Figure 5-19. External Flag (XF) Timing
CLKOUT t d(TOUTH) t d(TOUTL)
TOUT t w(TOUT)
Figure 5-20. TOUT Timing
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5.5.10 Multichannel Buffered Serial Port (McBSP) Timing
5.5.10.1
McBSP Transmit and Receive Timings
and
assume testing over recommended operating conditions (see
and
Table 5-20. McBSP Transmit and Receive Timing Requirements
(1)
t t t t t t c(BCKRX) w(BCKRX) su(BFRH-BCKRL) h(BCKRL-BFRH) su(BDRV-BCKRL) h(BCKRL-BDRV)
Cycle time, BCLKR/X
(2)
Pulse duration, BCLKR/X high or BCLKR/X low
(2)
Setup time, external BFSR high before BCLKR low
Hold time, external BFSR high after BCLKR low
Setup time, BDR valid before BCLKR low
Hold time, BDR valid after BCLKR low
BCLKR/X ext
BCLKR/X ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKR int
BCLKR ext
BCLKX int
5416-120
5416-160
MIN MAX
4P
2P–1
(3)
(3)
8
1
1
2
7
1
2
3
8
UNIT
ns ns ns ns ns ns t t su(BFXH-BCKXL) h(BCKXL-BFXH)
Setup time, external BFSX high before BCLKX low
Hold time, external BFSX high after BCLKX low
BCLKX ext
BCLKX int
BCLKX ext
1
0
2 ns ns t r(BCKRX) t f(BCKRX)
Rise time, BCKR/X
Fall time, BCKR/X
BCLKR/X ext
BCLKR/X ext
6
6 ns ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If the polaritiy of any of the signals is inverted, then the timing references of that signal are also inverted.
(2) Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A separate detailed timing analysis should be performend for each specific McBSP interface.
(3) P = 0.5 * processor clock.
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Table 5-21. McBSP Transmit and Receive Switching Characteristics
(1)
t t t t t t t t c(BCKRX) w(BCKRXH) w(BCKRXL) d(BCKRH-BFRV) d(BCKXH-BFXV) dis(BCKXH-BDXHZ) d(BCKXH-BDXV) d(BFXH-BDXV)
Cycle time, BCLKR/X
(2)
PARAMETER
Pulse duration, BCLKR/X high
(2)
Pulse duration, BCLKR/X low
(2)
Delay time, BCLKR high to internal BFSR valid
Delay time, BCLKX high to internal BFSX valid
Disable time, BCLKX high to BDX high impedance following last data bit of transfer
Delay time, BCLKX high to BDX valid
Delay time, BFSX high to BDX valid
DXENA = 0
DXENA = 1
ONLY applies when in data delay 0 (XDATDLY = 00b) mode
5416-120
5416-160
MAX
BCLKR/X int
MIN
4P
(3)
BCLKR/X int D – 1
(4)
BCLKR/X int C – 1
(4)
D + 1
C + 1
(4)
(4)
BCLKR int
BCLKR ext
BCLKX int
BCLKX ext
BCLKX int
– 3
0
– 1
3 11
6
3
6
5
BCLKX ext
BCLKX int
BCLKX ext
BCLKX int
BCLKX ext
BFSX int
BFSX ext
– 1
(5)
3
– 1
(5)
3
–1
(5)
3
20
30
7
11
10
10
20
UNIT
ns ns ns ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If the polaritiy of any of the signals is inverted, then the timing references of that signal are also inverted.
(2) Note that in some cases, for example when driving another 54x device McBSP, maximum serial port clocking rates may not be achievable at maximum CPU clock frequency due to transmitted data timings and corresponding receive timing requirements. A separate detailed timing analysis should be performend for each specific McBSP interface.
(3) P = 0.5 * processor clock.
(4) T = BCLKRX period = (1 + CLKGDV) * 2P
C = BCLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 +1) * 2P when CLKGDV is even
(5) Minimum delay times also represent minimum output hold times.
ns ns ns ns ns
t c(BCKRX) t w(BCKRXH) t w(BCKRXL) t r(BCKRX) t f(BCKRX)
BCLKR t d(BCKRH-BFRV) t d(BCKRH-BFRV)
BFSR (int) t su(BFRH-BCKRL) t h(BCKRL-BFRH)
BFSR (ext)
BDR t su(BDRV-BCKRL) t h(BCKRL-BDRV)
(n-2)
Bit(n-1)
Figure 5-21. McBSP Receive Timings
(n-3)
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t c(BCKRX)
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Fixed-Point Digital Signal Processor
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t r(BCKRX) t f(BCKRX) t w(BCKRXH) t w(BCKRXL)
BCLKX
BFSX (int) t d(BCKXH-BFXV) t su(BFXH-BCKXL)
BFSX (ext)
BFSX
(XDATDLY=00b)
BDX t dis(BCKXH-BDXHZ)
Bit 0 t h(BCKXL-BFXH) t d(BCKXH-BDXV) t d(BFXH-BDXV) t d(BCKXH-BDXV)
Bit(n-1) (n-2)
Figure 5-22. McBSP Transmit Timings
(n-3)
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5.5.10.2
McBSP General-Purpose I/O Timing
and
assume testing over recommended operating conditions (see
Table 5-22. McBSP General-Purpose I/O Timing Requirements
t su(BGPIO-COH) t h(COH-BGPIO)
Setup time, BGPIOx input mode before CLKOUT high
Hold time, BGPIOx input mode after CLKOUT high
(1)
(1)
(1) BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
5416-120
5416-160
MIN MAX
7
0
UNIT
ns ns
Table 5-23. McBSP General-Purpose I/O Switching Characteristics
PARAMETER
t d(COH-BGPIO)
Delay time, CLKOUT high to BGPIOx output mode
(1)
(1) BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose output.
5416-120
5416-160
MIN MAX
– 2 4
UNIT
ns
CLKOUT t su(BGPIO-COH) t d(COH-BGPIO) t h(COH-BGPIO)
BGPIOx Input Mode
(see Note A)
BGPIOx Output Mode
(see Note B)
A.
BGPIOx refers to BCLKRx, BFSRx, BDRx, BCLKXx, or BFSXx when configured as a general-purpose input.
B.
BGPIOx refers to BCLKRx, BFSRx, BCLKXx, BFSXx, or BDXx when configured as a general-purpose output.
Figure 5-23. McBSP General-Purpose I/O Timings
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5.5.10.3
McBSP as SPI Master or Slave Timing
to
assume testing over recommended operating conditions (see
Table 5-24. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
(1)
5416-120
5416-160
MASTER
MIN MAX
t su(BDRV-BCKXL) t h(BCKXL-BDRV)
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
12
4
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 0.5 * processor clock.
SLAVE
MIN MAX
2 – 6P
(2)
5 + 12P
(2)
UNIT
ns ns
Table 5-25. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
(1)
t t t t h(BCKXL-BFXL) d(BFXL-BCKXH) d(BCKXH-BDXV) dis(BCKXL-BDXHZ)
PARAMETER
Hold time, BFSX low after BCLKX low
(3)
Delay time, BFSX low to BCLKX high
(4)
Delay time, BCLKX high to BDX valid
Disable time, BDX high impedance following last data bit from
BCLKX low
MASTER
(2)
MIN MAX
5416-120
5416-160
SLAVE
MIN
T – 3 T + 4
C – 4 C + 3
– 4 5 6P + 2
(5)
C – 2 C + 3
MAX
10P + 17
(5)
UNIT
ns ns ns ns t dis(BFXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BFSX high
Delay time, BFSX low to BDX valid
2P– 4
(5)
6P + 17
(5) ns t d(BFXL-BDXV)
4P+ 2
(5)
8P + 17
(5) ns
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) *2P when CLKGDV is even
(3) FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP
CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP
(4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX).
(5) P = 0.5 * processor clock.
LSB
MSB
BCLKX t h(BCKXL-BFXL) t d(BFXL-BCKXH)
BFSX t dis(BFXH-BDXHZ) t dis(BCKXL-BDXHZ)
BDX
BDR
Bit 0
Bit 0 t su(BDRV-BCLXL) t d(BFXL-BDXV) t d(BCKXH-BDXV)
Bit(n-1) (n-2)
Bit(n-1) t h(BCKXL-BDRV)
(n-2)
(n-3)
(n-3)
(n-4)
(n-4)
Figure 5-24. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
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Table 5-26. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0)
(1)
t su(BDRV-BCKXL) t h(BCKXH-BDRV)
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX high
5416-120
5416-160
MASTER
MIN MAX
12
4
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 0.5 * processor clock.
SLAVE
MIN MAX
2 – 6P
(2)
5 + 12P
(2)
UNIT
ns ns
Table 5-27. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)
(1)
5416-120
5416-160
PARAMETER
MASTER
(2)
UNIT
t h(BCKXL-BFXL) t d(BFXL-BCKXH) t d(BCKXL-BDXV)
Hold time, BFSX low after BCLKX low
Delay time, BFSX low to BCLKX high
Delay time, BCLKX low to BDX valid
(3)
(4)
MIN MAX
C –3
T – 4
– 4
C + 4
T + 3
SLAVE
MIN
5 6P + 2
(5)
MAX
10P + 17
(5) ns ns ns t dis(BCKXL-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX low
Delay time, BFSX low to BDX valid
– 2 4 6P – 4
(5)
10P + 17
(5) ns t d(BFXL-BDXV)
D – 2 D + 4 4P + 2
(5)
8P + 17
(5) ns
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) *2P when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and (CLKGDV/2 + 1) * 2P when CLKGDV is even
(3) FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP
CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP
(4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX).
(5) P = 0.5 * processor clock.
LSB
MSB
BCLKX t h(BCKXL-BFXL) t d(BFXL-BCKXH)
BFSX t dis(BCKXL-BDXHZ)
BDX Bit 0
BDR t d(BFXL-BDXV) t su(BDRV-BCKXL)
Bit(n-1) t d(BCKXL-BDXV)
(n-2) t h(BCKXH-BDRV)
(n-2)
(n-3)
(n-3) Bit 0 Bit(n-1)
Figure 5-25. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
(n-4)
(n-4)
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Table 5-28. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)
(1)
5416-120
5416-160
MASTER
MIN MAX
t su(BDRV-BCKXH) t h(BCKXH-BDRV)
Setup time, BDR valid before BCLKX high
Hold time, BDR valid after BCLKX high
12
4
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 0.5 * processor clock.
SLAVE
MIN MAX
2 – 6P
(2)
5 + 12P
(2)
UNIT
ns ns
Table 5-29. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)
(1)
t t t h(BCKXH-BFXL) t d(BFXL-BCKXL) t d(BCKXL-BDXV) dis(BCKXH-BDXHZ) dis(BFXH-BDXHZ)
PARAMETER
Hold time, BFSX low after BCLKX high
(3)
Delay time, BFSX low to BCLKX lowTNote9543
(4)
Delay time, BCLKX low to BDX valid
Disable time, BDX high impedance following last data bit from
BCLKX high
Disable time, BDX high impedance following last data bit from
BFSX high
Delay time, BFSX low to BDX valid
MASTER
(2)
MIN MAX
T – 3 T + 4
5416-120
5416-160
SLAVE
MIN
D – 4 D + 3
– 4
D – 2
5 6P + 2
(5)
D + 3
2P – 4
(5)
MAX
10P + 17
6P + 17
(5)
(5)
UNIT
ns ns ns ns ns t d(BFXL-BDXV)
4P + 2
(5)
8P + 17
(5) ns
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) T = BCLKX period = (1 + CLKGDV) * 2P
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and (CLKGDV/2 + 1) * 2P when CLKGDV is even
(3) FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP
CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP
(4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX).
(5) P = 0.5 * processor clock.
LSB
MSB
BCLKX t h(BCKXH-BFXL) t d(BFXL-BCKXL)
BFSX
BDX
BDR
Bit 0 t dis(BFXH-BDXHZ) t dis(BCKXH-BDXHZ) t su(BDRV-BCKXH) t d(BFXL-BDXV)
Bit(n-1) t d(BCKXL-BDXV)
(n-2) t h(BCKXH-BDRV)
(n-2)
(n-3)
(n-3) Bit 0 Bit(n-1)
Figure 5-26. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
(n-4)
(n-4)
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Table 5-30. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
(1)
5416-120
5416-160
MASTER
MIN MAX
t su(BDRV-BCKXL) t h(BCKXL–BDRV)
Setup time, BDR valid before BCLKX low
Hold time, BDR valid after BCLKX low
12
4
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) P = 0.5 * processor clock.
SLAVE
MIN
2 – 6P
(2)
5 + 12P
(2)
MAX
UNIT
ns ns
Table 5-31. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
(1)
5416-120
5416-160
PARAMETER
MASTER
(2)
UNIT
t h(BCKXH-BFXL) t d(BFXL-BCKXL) t d(BCKXH-BDXV)
Hold time, BFSX low after BCLKX high
Delay time, BFSX low to BCLKX low
Delay time, BCLKX high to BDX valid
(4)
(3)
MIN MAX
D – 3
T – 4
– 4
D + 4
T + 3
SLAVE
MIN
5 6P + 2
(5)
MAX
10P + 17
(5) ns ns ns t dis(BCKXH-BDXHZ)
Disable time, BDX high impedance following last data bit from
BCLKX high
Delay time, BFSX low to BDX valid
– 2 4 6P – 4
(5)
10P + 17
(5) ns t d(BFXL-BDXV)
C – 2 C + 4 4P + 2
(5)
8P + 17
(5) ns
(1) For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.
(2) T = BCLKX period = (1 + CLKGDV) * 2P
C = BCLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * 2P when CLKGDV is even
D = BCLKX high pulse width = T/2 when CLKGDV is odd or zero and (CLKGDV/2 + 1) * 2P when CLKGDV is even
(3) FSRP = FSXP = 1. As a SPI master, BFSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input on BFSX and BFSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FRSRM = 2 for master McBSP
CLKXM = CLKRm = FSXM = FSRM = 0 for slave McBSP
(4) BFSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master clock (BCLKX).
(5) P = 0.5 * processor clock.
LSB
MSB
BCLKX t h(BCKXH-BFXL) t d(BFXL-BCKXL)
BFSX t dis(BCKXH-BDXHZ)
BDX Bit 0
BDR t d(BFXL-BDXV) t su(BDRV-BCKXL)
Bit(n-1) t d(BCKXH-BDXV)
(n-2) t h(BCKXL-BDRV)
(n-2)
(n-3)
(n-3) Bit 0 Bit(n-1)
Figure 5-27. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
(n-4)
(n-4)
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5.5.11 Host-Port Interface Timing
5.5.11.1
HPI8 Mode
and
assume testing over recommended operating conditions and P = 0.5 * processor clock (see
through
Figure 5-31 ). In the following tables, DS refers to the logical OR
of HCS, HDS1, and HDS2. HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). HAD stands for HCNTL0, HCNTL1, and HR/W.
Table 5-32. HPI8 Mode Timing Requirements
t su(DSL-HBV) t h(DSL-HBV) t su(HSL-DSL) t w(DSL) t w(DSH) t su(HDV-DSH) t h(DSH-HDV)W t su(GPIO-COH) t h(GPIO-COH)
Setup time, HBIL and HAD valid before DS low (when HAS is not used), or HBIL and HAD valid before HAS low
Hold time, HBIL and HAD valid after DS low (when HAS is not used), or HBIL and HAD valid after HAS low
Setup time, HAS low before DS low
Pulse duration, DS low
Pulse duration, DS high
Setup time, HD valid before DS high, HPI write
Hold time, HD valid after DS high, HPI write
Setup time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
Hold time, HDx input valid before CLKOUT high, HDx configured as general-purpose input
5416-120
5416-160
MIN MAX
6
UNIT
ns
3
8
13
7
3
2
3
0 ns ns ns ns ns ns ns ns
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Table 5-33. HPI8 Mode Switching Characteristics
t t t t t t en(DSL-HD) d(DSL-HDV1) d(DSL-HDV2) t h(DSH-HDV)R t v(HYH-HDV) t d(DSH-HYL) d(DSH-HYH) d(HCS-HRDY) t d(COH-HYH) t d(COH-HTX) d(COH-GPIO)
PARAMETER
Enable time, HD driven from DS low
Delay time, DS low to HD valid for first byte of an HPI read
Case 1a: Memory accesses when DMAC is active in 32-bit mode and t w(DSH)
< 36P
(1)
Case 1b: Memory accesses when DMAC is active in 32-bit mode and t w(DSH)
≥
36P
(1)
Case 1c: Memory accesses when DMAC is active in 16-bit mode and t w(DSH)
< I8P
(1)
Case 1d: Memory accesses when DMAC is active in 16-bit mode and t w(DSH)
≥
I8P
(1)
Case 2a: Memory accesses when DMAC is inactive and t w(DSH)
< 10P
(1)
Case 2b: Memory accesses when DMAC is inactive and t w(DSH)
≥
10P
(1)
Case 3: Register accesses
Delay time, DS low to HD valid for second byte of an HPI read
Hold time, HD valid after DS high, for a HPI read
Valid time, HD valid after HRDY high
Delay time, DS high to HRDY low
(2)
Case 1a: Memory accesses when DMAC is active in 16-bit mode
(1)
Case 1b: Memory accesses when DMAC is active in 32-bit mode
(1)
Delay time, DS high to HRDY high
(2)
Case 2: Memory accesses when DMAC is inactive
(1)
Case 3: Write accesses to HPIC register
(3)
Delay time, HCS low/high to HRDY low/high
Delay time, CLKOUT high to HRDY high
Delay time, CLKOUT high to HINT change
Delay time, CLKOUT high to HDx output change. HDx is configured as a general-purpose output
MIN
0
0
5416-120
5416-160
36P + 10 – w(DSH)
10
18P + 10 –
10P + 10 – t t t
UNIT
MAX
10 ns w(DSH)
10 w(DSH)
10
10
10
18P + 6
36P + 6
10P + 6
6P + 6
6
9
6
5 ns ns ns
2 ns
8 ns ns ns ns ns ns
(1) DMAS stands for direct memory access controller. The HPI8 shares the internal DMA bus with the DMAC, thus HPI8 access times are affected by DMAC activity.
(2) The HRDY output is always high when the HCS input is high, regardless of DS timings.
(3) This timing applies when writing a one to the DSPINT bit or HINT bit of the HPIC register. All other writes to the HPIC occur asynchronously, and do not cause HRDY to be deasserted.
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HAS
HAD
(see Note A) t
Second Byte t su(HBV-DSL) su(HBV-DSL)
‡
First Byte
Valid t su(HSL-DSL) t h(DSL-HBV) t h(DSL-HBV)
(see Note B)
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
Valid
Second Byte
HBIL
HCS t w(DSH) t w(DSL)
HDS t d(DSH-HYH) t d(DSH-HYL)
HRDY
HD READ t en(DSL-HD) t d(DSL-HDV2) t h(DSH-HDV)R
Valid
Valid t su(HDV-DSH) t h(DSH-HDV)W t d(DSL-HDV1)
Valid t v(HYH-HDV)
Valid
HD WRITE Valid Valid t d(COH-HYH)
Processor
CLK
A.
HAD refers to HCNTL0, HCNTL1, and HR/W.
B.
When HAS is not used (HAS always high)
Figure 5-28. Using HDS to Control Accesses (HCS Always Low)
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HCS
www.ti.com
HDS t d(HCS-HRDY)
HRDY
Figure 5-29. Using HCS to Control Accesses
CLKOUT t d(COH-HTX)
HINT
Figure 5-30. HINT Timing
In
Figure 5-31 , GPIOx refers to HD0, HD1, HD2, ...HD7, when the HD bus is configured for
general-purpose input/output (I/O).
CLKOUT t su(GPIO-COH) t h(GPIO-COH)
GPIOx Input Mode
(see Note A) t d(COH-GPIO)
GPIOx Output Mode
(see Note A)
Figure 5-31. GPIOx Timings
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5.5.11.2
HPI16 Mode
and
assume testing over recommended operating conditions and P = 0.5 * processor clock (see
through
Figure 5-34 ). In the following tables, DS refers to the logical OR
of HCS, HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These timings are shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP
Reference Set,Volume 5: Enhanced Peripherals (literature number SPRU302) for additional information.
t su(HBV-DSL) t h(DSL-HBV) t su(HAV-DSH) t su(HAV-DSL) t h(DSH-HAV) t w(DSL) t w(DSH) t c(DSH-DSH)
Table 5-34. HPI16 Mode Timing Requirements
Setup time, HR/W valid before DS falling edge
Hold time, HR/W valid after DS falling edge
Setup time, address valid before DS rising edge (write)
Setup time, address valid before DS falling edge (read)
Hold time, address valid after DS rising edge
Pulse duration, DS low
Pulse duration, DS high
Memory accesses with no DMA activity.
Cycle time, DS rising edge to Memory accesses with 16-bit DMA next DS rising edge activity.
Memory accesses with 32-bit DMA activity.
t su(HDV-DSH)W t h(DSH-HDV)W
Setup time, HD valid before DS rising edge
Hold time, HD valid after DS rising edge, write
(1) P = 0.5 * processor clock.
5416-120
5416-160
MIN MAX
6
5
5
–(4P– 6)
(1)
1
30
10
Reads 10P + 30
(1)
Writes 10P + 10
(1)
Reads 16P + 30
(1)
Writes 16P + 10
(1)
Reads 24P + 30
(1)
Writes 24P + 10
(1)
8
2
UNIT
ns ns ns ns ns ns ns ns ns ns
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SPRS095P – MARCH 1999 – REVISED OCTOBER 2008 t d(DSL-HDD) t d(DSL-HDV1) t d(DSH-HYH) t v(HYH-HDV) t h(DSH-HDV)R t d(COH-HYH) t d(DSL-HYL) t d(DSH-HYL) www.ti.com
Table 5-35. HPI16 Mode Switching Characteristics
PARAMETER
Delay time, DS low to HD driven
Case 1a: Memory accesses initiated immediately following a write when DMAC is active in 32-bit mode and t w(DSH) was < 26P
Case 1b: Memory access not immediately following a write when
DMAC is active in 32-bit mode
Delay time, DS low to HD valid
Case 1c: Memory accesses initiated immediately following a write when DMAC is active in 16-bit mode and t w(DSH) was < 18P for first word of Case 1d: Memory accesses not immediately following a write when an HPI read
DMAC is active in 16-bit mode
Case 2a: Memory accesses initiated immediately following a write when DMAC is inactive and t w(DSH) was < 10P
Case 2b: Memory accesses not immediately following a write when
DMAC is inactive
Delay time, DS
Memory writes when no DMA is active high to HRDY Memory writes with one or more 16-bit DMA channels active high
Memory writes with one or more 32-bit DMA channels active
Valid time, HD valid after HRDY high
Hold time, HD valid after DS rising edge, read
Delay time, CLKOUT rising edge to HRDY high
Delay time, DS low to HRDY low
Delay time, DS high to HRDY low
MIN
0
5416-120
5416-160
MAX
10
48P + 20 – t w(DSH)
1
24P + 20
32P + 20 – t w(DSH)
16P + 20
20P + 20 – t w(DSH)
10P + 20
10P + 5
16P + 5
24P + 5
5
12
7
6
12
UNIT
ns ns ns ns ns ns ns
HCS t w(DSH) t c(DSH−DSH)
HDS t su(HBV−DSL) t su(HBV−DSL) t h(DSL−HBV) t w(DSL) t h(DSL−HBV)
HR/W
HA[17:0] t su(HAV−DSL)
Valid Address t h(DSH−HDV)R t h(DSH−HAV)
Valid Address t d(DSL−HDV1) t d(DSL−HDV1) t h(DSH−HDV)R
HD[15:0] t d(DSL−HDD) t v(HYH−HDV)
Data t d(DSL−HDD)
Data t v(HYH−HDV)
HRDY t d(DSL−HYL) t d(DSL−HYL)
Figure 5-32. Nonmultiplexed Read Timings
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HCS
HDS
HR/W
HA[17:0]
HD[15:0]
HRDY
TMS320VC5416
Fixed-Point Digital Signal Processor
SPRS095P – MARCH 1999 – REVISED OCTOBER 2008
t w(DSH) t c(DSH−DSH) t su(HBV−DSL) t h(DSL−HBV) t su(HBV−DSL) t h(DSL−HBV) t su(HAV−DSH) t w(DSL) t h(DSH−HAV)
Valid Address
Data Valid t su(HDV−DSH)W t h(DSH−HDV)W t su(HDV−DSH)W
Valid Address
Data Valid t d(DSH−HYH) t d(DSH−HYL)
Figure 5-33. Nonmultiplexed Write Timings
HRDY t d(COH−HYH)
CLKOUT
Figure 5-34. HRDY Relative to CLKOUT t h(DSH−HDV)W
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6 Mechanical Data
The following mechanical package diagram(s) reflect the most current released mechanical data available for the designated device(s).
6.1
Package Thermal Resistance Characteristics
provides the estimated thermal resistance characteristics for the recommended package types used on the device.
PARAMETER
R
θ
JA
R
θ
JC
Table 6-1. Thermal Resistance Characteristics
GGU PACKAGE
38
5
PGE PACKAGE
56
5
UNIT
°
C/W
°
C/W
92
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PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2013
PACKAGING INFORMATION
Orderable Device
TMS320VC5416GGU120
TMS320VC5416GGU160
TMS320VC5416PGE120
Status
(1)
ACTIVE
ACTIVE
ACTIVE
Package Type Package
Drawing
Pins Package
Qty
GGU 144 160 BGA
MICROSTAR
BGA
MICROSTAR
GGU 144 160
LQFP PGE 144 60
Eco Plan
(2)
TBD
TBD
Green (RoHS
& no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
SNPB
Op Temp (°C)
Level-3-220C-168 HR -40 to 100
SNPB
CU NIPDAU
Level-3-220C-168 HR
Level-1-260C-UNLIM
-40 to 100
-40 to 100
Top-Side Markings
(4)
DVC5416GGU
120
DVC5416GGU
160
320VC5416PGE
120
TMS
TMS320VC5416PGE16
TMS320VC5416PGE160
TMS320VC5416ZGU120
OBSOLETE
ACTIVE
ACTIVE
LQFP
LQFP
BGA
MICROSTAR
PGE
PGE
ZGU
144
144
144
60
160
TBD
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Call TI Call TI
CU NIPDAU Level-1-260C-UNLIM
SNAGCU
-40 to 100
-40 to 100
Level-3-260C-168 HR -40 to 100
320VC5416
PGE
160
TMS
DVC5416ZGU
120
TMS320VC5416ZGU160 ACTIVE BGA
MICROSTAR
ZGU 144 160 Green (RoHS
& no Sb/Br)
SNAGCU Level-3-260C-168 HR -40 to 100 DVC5416ZGU
160
TMSDVC5416GGUR160 OBSOLETE BGA
MICROSTAR
GGU 144 TBD Call TI Call TI -40 to 100
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
DVC5416GGU
160
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320VC5416 :
•
Military: SMJ320VC5416
NOTE: Qualified Version Definitions:
•
Military - QML certified for Military and Defense Applications
Addendum-Page 2
MECHANICAL DATA
MPBG021C – DECEMBER 1996 – REVISED MAY 2002
PLASTIC BALL GRID ARRAY GGU (S–PBGA–N144)
0,95
0,85
A1 Corner
0,55
0,45
12,10
11,90
SQ
0,08
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice
C. MicroStar BGA t
configuration
0,80
9,60 TYP
J
H
G
F
E
D
C
B
A
N
M
L
K
1 2 3 4 5 6 7 8 9 10 11 12 13
Bottom View
1,40 MAX
Seating Plane
0,10
0,45
0,35
4073221-2/C 12/01
MicroStar BGA is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
PGE (S-PQFP-G144)
108
109
MECHANICAL DATA
MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996
PLASTIC QUAD FLATPACK
73
72
0,27
0,17
0,08
M
0,50
144
1
17,50 TYP
20,20
19,80
SQ
22,20
21,80
SQ
1,45
1,35
1,60 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
36
37
0,13 NOM
0,05 MIN
0,25
0,75
0,45
Gage Plane
0
°
– 7
°
Seating Plane
0,08
4040147 / C 10/96
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
IMPORTANT NOTICE
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