ADC088S022 8-Channel, 50 ksps to 200 ksps, 8-Bit A/D Converter ADC088S022 FEATURES DESCRIPTION
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SNAS341F – SEPTEMBER 2005 – REVISED MARCH 2013
ADC088S022 8-Channel, 50 ksps to 200 ksps, 8-Bit A/D Converter
Check for Samples: ADC088S022
1
FEATURES
23
• Eight Input Channels
• Variable Power Management
• Independent Analog and Digital Supplies
• SPI™/ QSPI™/MICROWIRE/DSP Compatible
• Packaged in 16-Lead TSSOP
APPLICATIONS
• Automotive Navigation
• Portable Systems
• Medical Instruments
• Mobile Communications
• Instrumentation and Control Systems
KEY SPECIFICATIONS
• Conversion Rate: 50 ksps to 200 ksps
• DNL (V
A
= V
D
= 2.7V to 5.25V): ±0.2 LSB (Max)
• INL (V
A
= V
D
= 2.7V to 5.25V): ±0.2 LSB (Max)
• Power Consumption
– 3V Supply: 0.9 mW (Typ)
– 5V Supply: 5.5 mw (Typ)
DESCRIPTION
The ADC088S022 is a low-power, eight-channel
CMOS 8-bit analog-to-digital converter specified for conversion throughput rates of 50 ksps to 200 ksps.
The converter is based on a successiveapproximation register architecture with an internal track-and-hold circuit. It can be configured to accept up to eight input signals at inputs IN0 through IN7.
The output serial data is straight binary and is compatible with several standards, such as SPI™,
QSPI™, MICROWIRE, and many common DSP serial interfaces.
The ADC088S022 may be operated with independent analog and digital supplies. The analog supply (V
A
) can range from +2.7V to +5.25V, and the digital supply (V
D
) can range from +2.7V to V
A
. Normal power consumption using a +3V or +5V supply is 0.9
mW and 5.5 mW, respectively. The power-down feature reduces the power consumption to 0.03 µW using a +3V supply and 0.15 µW using a +5V supply.
The ADC088S022 is packaged in a 16-lead TSSOP package. Operation over the extended industrial temperature range of − 40°C to +105°C is ensured.
Connection Diagram
CS
V
A
AGND
IN0
IN1
IN2
IN3
IN4
1
2
3
7
8
4
ADC088S022
13
5 12
6 11
10
9
16
15
14
SCLK
DOUT
DIN
V
D
DGND
IN7
IN6
IN5
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
SPI, QSPI are trademarks of Motorola, Inc..
3
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
ADC088S022
SNAS341F – SEPTEMBER 2005 – REVISED MARCH 2013
Block Diagram
IN0
.
.
.
IN7
MUX T/H
AGND
8-BIT
SUCCESSIVE
APPROXIMATION
ADC
V
A
AGND
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ADC088S022
CONTROL
LOGIC
V
D
SCLK
CS
DIN
DOUT
DGND
PIN DESCRIPTIONS
Pin No.
ANALOG I/O
4 - 11
DIGITAL I/O
16
15
14
1
POWER SUPPLY
2
13
3
12
Symbol
IN0 to IN7
SCLK
DOUT
DIN
CS
Digital clock input. The specified performance range of frequencies for this input is 0.8 MHz to 3.2 MHz. This clock directly controls the conversion and readout processes.
Digital data output. The output samples are clocked out of this pin on the falling edges of the SCLK pin.
Digital data input. The ADC088S022's Control Register is loaded through this pin on rising edges of the SCLK pin.
Chip select. On the falling edge of CS, a conversion process begins. Conversions continue as long as CS is held low.
Description
Analog inputs. These signals can range from 0V to V
REF
.
V
V
A
D
AGND
DGND
Positive analog supply pin. This voltage is also used as the reference voltage. This pin should be connected to a quiet +2.7V to +5.25V source and bypassed to GND with 1 µF and 0.1 µF monolithic ceramic capacitors located within 1 cm of the power pin.
Positive digital supply pin. This pin should be connected to a +2.7V to V
A supply, and bypassed to GND with a 0.1 µF monolithic ceramic capacitor located within 1 cm of the power pin.
The ground return for the analog supply and signals.
The ground return for the digital supply and signals.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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Absolute Maximum Ratings
(1) (2) (3)
Analog Supply Voltage V
A
Digital Supply Voltage V
D
Voltage on Any Pin to GND
Input Current at Any Pin
(4)
Package Input Current
(4)
Power Dissipation at T
A
= 25°C
ESD Susceptibility
(6)
Human Body Model
Machine Model
− 0.3V to 6.5V
− 0.3V to V
A
+ 0.3V, max 6.5V
− 0.3V to V
A
+0.3V
±10 mA
±20 mA
See
(5)
2500V
250V
+150°C
− 65°C to +150°C
Junction Temperature
Storage Temperature
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
degrade when the device is not operated under the listed test conditions.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and specifications.
(3) For soldering specifications, see http://www.ti.com/lit/SNOA549
(4) When the input voltage at any pin exceeds the power supplies (that is, V
IN
< AGND or V
IN
> V
A or V
D
), the current at that pin should be limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10 mA to two.
(5) The absolute maximum junction temperature (T
J max) for this device is 150°C. The maximum allowable power dissipation is dictated by
T
J max, the junction-to-ambient thermal resistance ( θ
JA
), and the ambient temperature (T
A
), and can be calculated using the formula
P
D
MAX = (T
J max − T
A
)/ θ
JA
. In the 16-pin TSSOP, θ
JA is 96°C/W, so P
D
MAX = 1,200 mW at 25°C and 625 mW at the maximum operating ambient temperature of 105°C. Note that the power consumption of this device under normal operation is a maximum of 12 mW. The values for maximum power dissipation listed above will be reached only when the ADC088S022 is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Obviously, such conditions should always be avoided.
(6) Human body model is 100 pF capacitor discharged through a 1.5 k Ω resistor. Machine model is 220 pF discharged through ZERO ohms
Operating Ratings
(1) (2)
Operating Temperature
V
A
Supply Voltage
V
D
Supply Voltage
Digital Input Voltage
Analog Input Voltage
Clock Frequency
−
40°C
≤
T
A
≤
+105°C
+2.7V to +5.25V
+2.7V to V
A
0V to V
A
0V to V
A
50 mHz to 16 MHz
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
degrade when the device is not operated under the listed test conditions.
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.
Package Thermal Resistance
Package
16-lead TSSOP on 4-layer, 2 oz. PCB
θ
JA
96°C / W
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ADC088S022 Converter Electrical Characteristics
(1)
The following specifications apply for V
A
50 ksps to 200 ksps, and C
L
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 50pF, unless otherwise noted. Boldface limits apply for T
A
= 0.8 MHz to 3.2 MHz, f
= T
MIN to T
MAX
SAMPLE
: all other limits T
A
=
= 25°C.
Symbol Parameter Conditions Typical Limits
(2)
Units
STATIC CONVERTER CHARACTERISTICS
8
Bits
INL
Resolution with No Missing Codes
Integral Non-Linearity (End Point
Method)
DNL
V
OFF
OEM
Differential Non-Linearity
Offset Error
FSE
FSEM
Offset Error Match
Full Scale Error
Full Scale Error Match
DYNAMIC CONVERTER CHARACTERISTICS
FPBW Full Power Bandwidth ( − 3dB)
SINAD
SNR
THD
Signal-to-Noise Plus Distortion Ratio
Signal-to-Noise Ratio
Total Harmonic Distortion
SFDR
ENOB
ISO
Spurious-Free Dynamic Range
Effective Number of Bits
Channel-to-Channel Isolation
Intermodulation Distortion, Second
Order Terms
IMD
Intermodulation Distortion, Third Order
Terms
ANALOG INPUT CHARACTERISTICS
V
IN
I
DCL
Input Range
DC Leakage Current
C
INA
Input Capacitance f
IN
= 39.9 kHz, − 0.02 dBFS f
IN
= 39.9 kHz, − 0.02 dBFS f
IN
= 39.9 kHz, − 0.02 dBFS f
IN
= 39.9 kHz, − 0.02 dBFS f
IN
= 39.9 kHz f
IN
= 20 kHz f a
= 19.5 kHz, f b
= 20.5 kHz f a
= 19.5 kHz, f b
= 20.5 kHz
Track Mode
Hold Mode
±0.04
±0.04
+0.6
±0.02
+0.5
±0.02
8
49.5
49.5
− 70.1
67.7
7.93
65.3
− 75.0
− 71.9
0 to V
A
33
3
±0.2
49.2
49.2
− 56.8
64.2
7.88
±0.2
±0.7
±0.2
±0.6
±0.2
±1
LSB (max)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
MHz dB (min) dB (min) dB (max) dB (min)
Bits (min) dB dB dB
V
µA (max) pF pF
DIGITAL INPUT CHARACTERISTICS
V
IH
Input High Voltage
V
A
= V
D
= +2.7V to +3.6V
V
A
= V
D
= +4.75V to +5.25V
V
IN
= 0V or V
D
±0.01
2
2.1
2.4
0.8
±1
4
V (min)
V (min)
V (max)
µA (max) pF (max)
V
IL
I
IN
Input Low Voltage
Input Current
C
IND
Digital Input Capacitance
DIGITAL OUTPUT CHARACTERISTICS
Output High Voltage V
OH
V
OL
I
OZH
, I
OZL
C
OUT
Output Low Voltage
Hi-Impedance Output Leakage Current
Hi-Impedance Output Capacitance
(1)
Output Coding
I
SOURCE
= 200 µA,
I
SINK
= 200 µA to 1.0 mA,
2
V
D
− 0.5
0.4
±1
V (min)
V (max)
µA (max)
4
pF (max)
Straight (Natural) Binary
(1) Data sheet min/max specification limits are ensured by design, test, or statistical analysis.
(2) Tested limits are ensured to AOQL (Average Outgoing Quality Level).
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ADC088S022 Converter Electrical Characteristics
(continued)
The following specifications apply for V
A
50 ksps to 200 ksps, and C
L
= V
D
= +2.7V to +5.25V, AGND = DGND = 0V, f
SCLK
= 50pF, unless otherwise noted. Boldface limits apply for T
A
= 0.8 MHz to 3.2 MHz, f
= T
MIN to T
MAX
SAMPLE
: all other limits T
A
=
= 25°C.
Symbol Parameter Conditions Typical Limits
(2)
Units
POWER SUPPLY CHARACTERISTICS (C
L
= 10 pF)
2.7
V (min)
V
A
, V
D
Analog and Digital Supply Voltages V
A
≥ V
D
5.25
V (max)
I
A
+ I
D
P
C
Total Supply Current Normal Mode
(CS low)
Total Supply Current Shutdown Mode
(CS high)
Power Consumption Normal Mode
(CS low)
Power Consumption Shutdown Mode
(CS high)
V
A
= V
D f
SAMPLE
= +2.7V to +3.6V,
= 200 kSPS, f
IN
= 40 kHz
V
A
= V
D f
SAMPLE
= +4.75V to +5.25V,
= 200 kSPS, f
IN
= 40 kHz f
V
A
= V
D
SCLK
= +2.7V to +3.6V,
= 0 ksps f
V
A
= V
D
SCLK
= +4.75V to +5.25V,
= 0 ksps f
V
A
IN
= V
D
= +3.0V, f
= 40 kHz
SAMPLE
= 200 kSPS,
V
A f
IN
= V
D
= +5.0V, f
= 40 kHz
SAMPLE
= 200 kSPS,
V
A
= V
D
= +3.0V, f
SCLK
= 0 ksps
V
A
= V
D
= +5.0V, f
SCLK
= 0 ksps
0.3
1.1
10
30
0.9
5.5
0.03
0.15
0.74
1.55
2.2
7.8
mA (max) mA (max) nA nA mW (max) mW (max)
µW
µW
AC ELECTRICAL CHARACTERISTICS
f
SCLK
MIN Minimum Clock Frequency f
SCLK
Maximum Clock Frequency 16 f
S t
CONVERT
DC t
ACQ t
AD
Sample Rate
Continuous Mode
Conversion (Hold) Time
SCLK Duty Cycle
Acquisition (Track) Time
Throughput Time
Aperture Delay
Acquisition Time + Conversion Time
1000
30
70
4
13
40
60
3
16
0.8
3.2
50
200
MHz (min)
MHz (max) ksps (min) ksps (max)
SCLK cycles
% (min)
% (max)
SCLK cycles
SCLK cycles ns
ADC088S022 Timing Specifications
The following specifications apply for V
50 ksps to 200 ksps, and C
L
A
= V
D
= +2.7V to 5.25V, AGND = DGND = 0V, f
= 50pF. Boldface limits apply for T
A
= T
MIN to T
MAX
SCLK
= 0.8 MHz to 3.2 MHz, f
SAMPLE
: all other limits T
A
= 25°C.
=
Symbol Parameter Conditions Typical Limits
(1)
Units
t
CSH t
CSS t
EN t
DACC t
DHLD t
DS t
DH t
CH t
CL t
DIS
CS Hold Time after SCLK Rising Edge
CS Setup Time prior to SCLK Rising Edge
CS Falling Edge to DOUT enabled
DOUT Access Time after SCLK Falling Edge
DOUT Hold Time after SCLK Falling Edge
DIN Setup Time prior to SCLK Rising Edge
DIN Hold Time after SCLK Rising Edge
SCLK High Time
SCLK Low Time
CS Rising Edge to DOUT High-Impedance
DOUT falling
DOUT rising
4
3
3
0
5
5
17
2.4
0.9
10
10
30
27
10
10
0.4 x t
SCLK
0.4 x t
SCLK
20
20
ns (min) ns (min) ns (max) ns (max) ns (typ) ns (min) ns (min) ns (min) ns (min) ns (max) ns (max)
(1) Tested limits are ensured to AOQL (Average Outgoing Quality Level).
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Timing Diagrams
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Power
Down
Track
Power Up
Hold Track
Power Up
Hold
CS
SCLK
1 2 3 4 5 6 7
8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8
Control register
ADD2 ADD1 ADD0
ADD2 ADD1 ADD0 DIN
DOUT
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Figure 1. ADC088S022 Operational Timing Diagram
CS
SCLK
DOUT
DIN t
ACQ t
CONVERT
1 2 3 t
CL
4 t
CH
5 t
DHLD
6 7 8 t
DACC
12 13 14 15 t
EN t
DS
FOUR ZEROS t
DH
DB7 DB6 DB5 DB4 B1 DB0
DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC
Figure 2. ADC088S022 Serial Timing Diagram
FOUR ZEROS
16
DB7 DB6 DB5 t
DIS
SCLK t
CSS
CS t
CSH
CS
Figure 3. SCLK and CS Timing Parameters
Specification Definitions
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold capacitor is charged by the input voltage.
APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is internally acquired or held for conversion.
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input voltage to a digital word.
CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another channel.
CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-to-
Channel Isolation, except for the sign of the data.
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DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The specification here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input.
FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below
V
REF
+ and is defined as:
V
FSE
= V max
+ 1.5 LSB – V
REF
+
(1) where V max is the voltage at which the transition to the maximum code occurs. FSE can be expressed in Volts,
LSB or percent of full scale range.
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (V
REF
LSB), after adjusting for offset error.
- 1.5
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as the ratio of the power in both the second or the third order intermodulation products to the power in one of the original frequencies. Second order products are f a order products are (2f a
± f b
) and (f a
± 2f b
± f b
, where f a and f b are the two sine wave input frequencies. Third
). IMD is usually expressed in dB.
MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be reached with any input value. The ADC088S022 is ensured not to have any missing codes.
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +
0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms value of the sum of all other spectral components below one-half the sampling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the input signal to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum that is not present at the input, including harmonics but excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated as
THD = 20
‡ log
10
A f2
2
+ +
A f1
2
A f6
2
(2) where A f1 is the RMS power of the input frequency at the output and A first 5 harmonic frequencies.
f2 through A f6 are the RMS power in the
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the acquisition time plus the conversion and read out times. In the case of the ADC088S022, this is 16 SCLK periods.
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Typical Performance Characteristics
V
A
= V
D
= +5.0V, T
A
= +25°C, f
SAMPLE
= 200 ksps, f
SCLK
= 3.2 MHz, f
IN
= 39.9 kHz unless otherwise stated.
DNL DNL www.ti.com
Figure 4.
INL
Figure 6.
DNL vs. Supply
Figure 5.
INL
Figure 7.
INL vs. Supply
Figure 8.
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Typical Performance Characteristics (continued)
V
A
= V
D
= +5.0V, T
A
= +25°C, f
SAMPLE
= 200 ksps, f
SNR vs. Supply
SCLK
= 3.2 MHz, f
IN
= 39.9 kHz unless otherwise stated.
THD vs. Supply
Figure 10.
ENOB vs. Supply
Figure 11.
DNL vs. V
D with V
A
= 5.0 V
Figure 12.
INL vs. V
D with V
A
= 5.0 V
Figure 13.
DNL vs. SCLK Duty Cycle
Figure 14.
Figure 15.
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Typical Performance Characteristics (continued)
V
A
= V
D
= +5.0V, T
A
= +25°C, f
SAMPLE
= 200 ksps, f
INL vs. SCLK Duty Cycle
SCLK
= 3.2 MHz, f
IN
= 39.9 kHz unless otherwise stated.
SNR vs. SCLK Duty Cycle www.ti.com
Figure 16.
THD vs. SCLK Duty Cycle
Figure 17.
ENOB vs. SCLK Duty Cycle
Figure 18.
DNL vs. SCLK
Figure 19.
INL vs. SCLK
Figure 20.
Figure 21.
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Typical Performance Characteristics (continued)
V
A
= V
D
= +5.0V, T
A
= +25°C, f
SAMPLE
= 200 ksps, f
SNR vs. SCLK
SCLK
= 3.2 MHz, f
IN
= 39.9 kHz unless otherwise stated.
THD vs. SCLK
Figure 22.
ENOB vs. SCLK
Figure 23.
DNL vs. Temperature
Figure 24.
INL vs. Temperature
Figure 25.
SNR vs. Temperature
Figure 26.
Figure 27.
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Typical Performance Characteristics (continued)
V
A
= V
D
= +5.0V, T
A
= +25°C, f
SAMPLE
= 200 ksps, f
THD vs. Temperature
SCLK
= 3.2 MHz, f
IN
= 39.9 kHz unless otherwise stated.
ENOB vs. Temperature www.ti.com
Figure 28.
SNR vs. Input Frequency
Figure 29.
THD vs. Input Frequency
Figure 30.
ENOB vs. Input Frequency
Figure 31.
Power Consumption vs. SCLK
Figure 32.
Figure 33.
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SNAS341F – SEPTEMBER 2005 – REVISED MARCH 2013
Functional Description
The ADC088S022 is a successive-approximation analog-to-digital converter designed around a chargeredistribution digital-to-analog converter.
ADC088S022 OPERATION
Simplified schematics of the ADC088S022 in both track and hold operation are shown in
and
respectively. In
Figure 34 , the ADC088S022 is in track mode: switch SW1 connects the sampling capacitor to
one of eight analog input channels through the multiplexer, and SW2 balances the comparator inputs. The
ADC088S022 is in this state for the first three SCLK cycles after CS is brought low.
shows the ADC088S022 in hold mode: switch SW1 connects the sampling capacitor to ground, maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital representation of the analog input voltage. The ADC088S022 is in this state for the last thirteen SCLK cycles after CS is brought low.
IN0
IN7
CHARGE
REDISTRIBUTION
DAC
MUX
SAMPLING
CAPACITOR
SW1 +
-
SW2
AGND
V
A
/2
Figure 34. ADC088S022 in Track Mode
CONTRO
C
IN0
IN7
MUX
SAMPLING
CAPACITOR
SW1
+
-
SW2
AGND
V
A
/2
Figure 35. ADC088S022 in Hold Mode
CHARGE
REDISTRIBUTION
DAC
CONTROL
LOGIC
SERIAL INTERFACE
An operational timing diagram and a serial interface timing diagram for the ADC088S022 are shown in
. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock) controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC088S022's Control Register is placed on DIN, the serial data input pin. New data is written to DIN with each conversion.
A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS is brought high.
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During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13
SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock out leading zeros, falling edges 5 through 12 clock out the conversion result, MSB first, and falling edges 13 through 16 clock out trailing zeros. If there is more than one conversion in a frame (continuous conversion mode), the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK. "N" is an integer value.
The ADC088S022 enters track mode under three different conditions. In
Figure 1 , CS goes low with SCLK high
and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with
SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as the first falling edge of SCLK. In the third condition, CS and SCLK go low simultaneously and the ADC enters track mode. While there is no timing restriction with respect to the rising edges of CS and SCLK, see
for setup and hold time requirements for the falling edge of CS with respect to the rising edge of SCLK.
While a conversion is in progress, the address of the next input for conversion is clocked into a control register through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. See
,
, and
There is no need to incorporate a power-up delay or dummy conversion as the ADC088S022 is able to acquire the input signal to full resolution in the first conversion immediately following power-up. The first conversion result after power-up will be that of IN0.
Bit 7 (MSB)
DONTC
Bit 6
DONTC
Bit 5
ADD2
Table 1. Control Register Bits
Bit 4
ADD1
Bit 3
ADD0
Bit 2
DONTC
Bit 1
DONTC
Bit 0
DONTC
4
3
Bit #:
7, 6, 2, 1, 0
5
Symbol:
DONTC
ADD2
ADD1
ADD0
Table 2. Control Register Bit Descriptions
Description
Don't care. The values of these bits do not affect the device.
These three bits determine which input channel will be sampled and converted at the next conversion cycle. The mapping between codes and channels is shown in
ADD2
0
0
0
0
1
1
1
1
ADD1
0
0
1
1
0
0
1
1
Table 3. Input Channel Selection
ADD0
0
1
0
1
0
1
0
1
Input Channel
IN0 (Default)
IN1
IN2
IN3
IN4
IN5
IN6
IN7
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ADC088S022 TRANSFER FUNCTION
The output format of the ADC088S022 is straight binary. Code transitions occur midway between successive integer LSB values. The LSB width for the ADC088S022 is V
A
/ 256. The ideal transfer characteristic is shown in
V
A
/ 512. Other code transitions occur at steps of one LSB.
111...111
111...110
111...000
011...111
|
1 LSB = V
A
/256
000...010
000...001
000...000
0V
0.5 LSB
ANALOG INPUT
+V
A
- 1.5 LSB
Figure 36. Ideal Transfer Characteristic
ANALOG INPUTS
An equivalent circuit for one of the ADC088S022's input channels is shown in
provide ESD protection for the analog inputs. The operating range for the analog inputs is 0V to V
A beyond this range will cause the ESD diodes to conduct and result in erratic operation.
. Going
The capacitor C1 in
has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track / hold switch and is typically 500 ohms. Capacitor C2 is the
ADC088S022 sampling capacitor, and is typically 30 pF. The ADC088S022 will deliver best performance when driven by a low-impedance source (less than 100 ohms). This is especially important when using the
ADC088S022 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or lowpass filter which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing filters.
V
A
D1
R1
C2
30 pF
V
IN
C1
3 pF
D2
Conversion Phase - Switch Open
Track Phase - Switch Closed
Figure 37. Equivalent Input Circuit
DIGITAL INPUTS AND OUTPUTS
The ADC088S022's digital inputs (SCLK, CS, and DIN) have an operating range of 0V to V
A
. They are not prone to latch-up and may be asserted before the digital supply (V
D
) without any risk. The digital output (DOUT) operating range is controlled by V
D
. The output high voltage is V
D
- 0.5V (min) while the output low voltage is
0.4V (max).
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APPLICATIONS INFORMATION
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TYPICAL APPLICATION CIRCUIT
A typical application is shown in
. The split analog and digital supply pins are both powered in this example by the TI LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor network located close to the ADC088S022. The digital supply is separated from the analog supply by an isolation resistor and bypassed with additional capacitors. The ADC088S022 uses the analog supply (V
A
) as its reference voltage, so it is very important that V
A be kept as clean as possible. Due to the low power requirements of the
ADC088S022, it is also possible to use a precision reference as a power supply.
To minimize the error caused by the changing input capacitance of the ADC088S022, a capacitor is connected from each input pin to ground. The capacitor, which is much larger than the input capacitance of the
ADC088S022 when in track mode, provides the current to quickly charge the sampling capacitor of the
ADC088S022. An isolation resistor is added to isolate the load capacitance from the input source.
51 :
0.1 P F 1.0 P F
0.1 P F 1.0 P F
LP2950
0.1 P F
5V
1 P F
INPUT
22 :
1 nF
IN0
.
.
.
IN7
V
D
ADC088S022
V
A
SCLK
CS
DIN
DOUT
AGND
DGND
MICROPROCESSOR
DSP
Figure 38. Typical Application Circuit
POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this product: power supply sequencing, power management, and the effect of digital supply noise on the analog supply.
Power Supply Sequence
The ADC088S022 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital supply (V
D
) cannot exceed the analog supply (V
A
) by more than 300 mV, not even on a transient basis.
Therefore, V
A must ramp up before or concurrently with V
D
.
Power Management
The ADC088S022 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with one exception. If operating in continuous conversion mode, the ADC088S022 automatically enters power-down mode between SCLK's 16th falling edge of a conversion and the SCLK's 1st falling edge of the subsequent conversion (see
).
In continuous conversion mode, the ADC088S022 can perform multiple conversions back to back. Each conversion requires 16 SCLK cycles and the ADC088S022 will perform conversions continuously as long as CS is held low. Continuous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical specifications.
in the
Typical Performance Characteristics
shows the typical power consumption of the
ADC088S022. To calculate the power consumption (P
C
), simply multiply the fraction of time spent in the normal mode (t
N
) by the normal mode power consumption (P
N
), and add the fraction of time spent in shutdown mode (t multiplied by the shutdown mode power consumption (P
S
) as shown in
S
)
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P
C
= t
N t
N
+ t
S u
P
N
+ t
S t
N
+ t
S u
P
S
SNAS341F – SEPTEMBER 2005 – REVISED MARCH 2013
(3)
Power Supply Noise Considerations
The charging of any output load capacitance requires current from the digital supply, V
D
. The current pulses required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if the analog and digital supplies are tied directly together, the noise on the digital supply will be coupled directly into the analog supply, causing greater performance degradation than would noise on the digital supply alone.
Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low will dump current into the die substrate, which is resistive. Load discharge currents will cause "ground bounce" noise in the substrate that will degrade noise performance if that current is large enough. The larger the output capacitance, the more current flows through the die substrate and the greater the noise coupled into the analog channel.
The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 Ω series resistor at the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge current of the output capacitance and improve noise performance. Since the series resistor and the load capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.
LAYOUT AND GROUNDING
Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor performance. The solution is to keep the analog circuitry separated from the digital circuitry and the clock line as short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise generated could have significant impact upon system noise performance. To avoid performance degradation of the ADC088S022 due to supply noise, do not use the same supply for the ADC088S022 that is used for digital logic.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize accuracy in high resolution systems, avoid crossing analog and digital lines altogether. It is important to keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line should also be treated as a transmission line and be properly terminated.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to the reference input pin and ground should be connected to a very clean point in the ground plane.
We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal chain that are connected to ground should be connected together with short traces and enter the analog ground plane at a single, quiet point.
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REVISION HISTORY
Changes from Revision E (March 2013) to Revision F Page
• Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM
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13-Sep-2014
PACKAGING INFORMATION
Orderable Device
ADC088S022CIMT
ADC088S022CIMT/NOPB
Status
(1)
NRND
ACTIVE
Package Type Package
Drawing
Pins Package
Qty
TSSOP PW 16 92
TSSOP PW 16 92
Eco Plan
(2)
TBD
Green (RoHS
& no Sb/Br)
Lead/Ball Finish
(6)
Call TI
CU SN
MSL Peak Temp
(3)
Call TI
Level-1-260C-UNLIM
Op Temp (°C)
-40 to 105
-40 to 105
Device Marking
(4/5)
88S022
CIMT
88S022
CIMT
ADC088S022CIMTX NRND TSSOP PW 16 2500 TBD Call TI Call TI -40 to 105 88S022
CIMT
ADC088S022CIMTX/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
CU SN Level-1-260C-UNLIM
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
-40 to 105 88S022
CIMT
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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13-Sep-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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TAPE AND REEL INFORMATION
PACKAGE MATERIALS INFORMATION
6-Nov-2015
*All dimensions are nominal
Device
ADC088S022CIMTX
ADC088S022CIMTX/NOP
B
Package
Type
Package
Drawing
TSSOP
TSSOP
PW
PW
Pins
16
16
SPQ
2500
2500
Reel
Diameter
(mm)
Reel
Width
W1 (mm)
330.0
12.4
330.0
12.4
A0
(mm)
6.95
6.95
B0
(mm)
5.6
5.6
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
www.ti.com
PACKAGE MATERIALS INFORMATION
6-Nov-2015
*All dimensions are nominal
Device
ADC088S022CIMTX
ADC088S022CIMTX/NOP
B
Package Type Package Drawing Pins
TSSOP
TSSOP
PW
PW
16
16
SPQ
2500
2500
Length (mm) Width (mm) Height (mm)
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
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