16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC /

16-Bit, 4-Channel/8-Channel, 250 kSPS PulSAR ADC /

Data Sheet

FEATURES

16-bit resolution with no missing codes

4-channel ( AD7682 )/8-channel ( AD7689 ) multiplexer with choice of inputs

Unipolar single-ended

Differential (GND sense)

Pseudobipolar

Throughput: 250 kSPS

INL: ±0.4 LSB typical, ±1.5 LSB maximum (±23 ppm or FSR)

Dynamic range: 93.8 dB

SINAD: 92.5 dB at 20 kHz

THD: −100 dB at 20 kHz

Analog input range: 0 V to V

REF

with V

REF

up to VDD

Multiple reference types

Internal selectable 2.5 V or 4.096 V

External buffered (up to 4.096 V)

External (up to VDD)

Internal temperature sensor (TEMP)

Channel sequencer, selectable 1-pole filter, busy indicator

No pipeline delay, SAR architecture

Single-supply 2.3 V to 5.5 V operation with 1.8 V to 5.5 V logic interface

Serial interface compatible with SPI, MICROWIRE, QSPI, and DSP

Power dissipation

3.5 mW at 2.5 V/200 kSPS

12.5 mW at 5 V/250 kSPS

Standby current: 50 nA

Low cost grade available

20-lead 4 mm × 4 mm LFCSP package

20-lead 2.4 mm × 2.4 mm WLCSP package

APPLICATIONS

Multichannel system monitoring

Battery-powered equipment

Medical instruments: ECG/EKG

Mobile communications: GPS

Power line monitoring

Data acquisition

Seismic data acquisition systems

Instrumentation

Process control

16-Bit, 4-Channel/8-Channel,

250 kSPS PulSAR ADC

AD7682 / AD7689

FUNCTIONAL BLOCK DIAGRAM

0.5V TO VDD – 0.5V

0.1µF

0.5V TO VDD

10µF

2.3V TO 5.5V

REFIN REF VDD

BAND GAP

REF

TEMP

SENSOR

AD7682/AD7689

VIO

1.8V

TO

VDD

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

MUX

16-BIT SAR

ADC

ONE-POLE

LPF

SEQUENCER

SPI SERIAL

INTERFACE

CNV

SCK

SDO

DIN

GND

Figure 1.

GENERAL DESCRIPTION

The AD7682 / AD7689 are 4-channel/8-channel, 16-bit, charge redistribution successive approximation register (SAR) analogto-digital converters (ADCs) that operate from a single power supply, VDD.

The AD7682 / AD7689 contain all components for use in a multichannel, low power data acquisition system, including a true 16-bit SAR ADC with no missing codes; a 4-channel

( AD7682 ) or 8-channel ( AD7689 ) low crosstalk multiplexer that is useful for configuring the inputs as single-ended (with or without ground sense), differential, or bipolar; an internal low drift reference (selectable 2.5 V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order.

The AD7682 / AD7689 use a simple SPI interface for writing to the configuration register and receiving conversion results. The

SPI interface uses a separate supply, VIO, which is set to the host logic level. Power dissipation scales with throughput.

The AD7682 / AD7689 are housed in a tiny 20-lead LFCSP and

20-lead WLCSP with operation specified from −40°C to +85°C.

Table 1. Multichannel 14-/16-Bit PulSAR® ADC

Type

Channels 250 kSPS 500 kSPS ADC Driver

14-Bit

16-Bit

16-Bit

8

4

8

AD7949

AD7682

AD7689

ADA4841

ADA4841

-x

-x

AD7699 ADA4841 -x

Rev. E Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice.

No license is granted by implication or otherwise under any patent or patent rights of Analog

Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 ©2008–2015 Analog Devices, Inc. All rights reserved.

Technical Support www.analog.com

AD7682/AD7689

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 4

Timing Specifications .................................................................. 7

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 14

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 18

Overview ...................................................................................... 18

Converter Operation .................................................................. 18

Transfer Functions...................................................................... 19

Typical Connection Diagrams .................................................. 20

Analog Inputs .............................................................................. 21

Driver Amplifier Choice ............................................................ 23

Data Sheet

Voltage Reference Output/Input .............................................. 23

Power Supply ............................................................................... 25

Supplying the ADC from the Reference .................................. 25

Digital Interface .............................................................................. 26

Reading/Writing During Conversion, Fast Hosts .................. 26

Reading/Writing After Conversion, Any Speed Hosts .......... 26

Reading/Writing Spanning Conversion, Any Speed Host .... 26

Configuration Register, CFG .................................................... 26

General Timing Without a Busy Indicator ............................. 28

General Timing with a Busy Indicator .................................... 29

Channel Sequencer .................................................................... 30

Read/Write Spanning Conversion Without a Busy

Indicator ...................................................................................... 31

Read/Write Spanning Conversion with a Busy Indicator ..... 32

Applications Information .............................................................. 33

Layout .......................................................................................... 33

Evaluating the AD7682/AD7689 Performance ........................ 33

Outline Dimensions ....................................................................... 34

Ordering Guide .......................................................................... 35

REVISION HISTORY

1/15—Rev. D to Rev. E

Added WLCSP (Throughout) ......................................................... 1

Added WLCSP Signal-to-Noise and SINAD Parameters;

Table 2 ................................................................................................ 3

Changed θ

JA

Thermal Impedance (LFCSP) from 47.6°C/W to

48°C/W .............................................................................................. 9

Added Figure 6, Figure 7, and Table 8 ......................................... 12

Changes to Layout Section ............................................................ 33

Added Figure 47; Outline Dimensions ........................................ 34

Changes to Ordering Guide .......................................................... 35

4/12—Rev. C to Rev. D

Changes to Figure 27 ...................................................................... 18

Changed Internal Reference Section to Internal

Reference/Temperature Sensor Section ....................................... 21

Changes to Internal Reference/Temperature Sensor Section ... 21

Changed External Reference/Temperature Sensor Section to

External Reference Section ............................................................ 22

Changes to External Reference and Internal Buffer Section and

External Reference Section ............................................................ 22

Changes to REF Bit, Function Column, Table 10 ...................... 25

Updated Outline Dimensions ....................................................... 32

9/11—Rev. B to Rev. C

Changes to Internal Reference Section ........................................ 21

Changes to the External Reference and Internal Buffer

Section .............................................................................................. 22

Changes to the External Reference/Temperature Sensor

Section .............................................................................................. 22

Changes to Table 10, REF Bit Description .................................. 25

6/09—Rev. A to Rev. B

Changes Table 6 ................................................................................. 8

Changes to Figure 37...................................................................... 25

Changes to Figure 38...................................................................... 26

3/09—Rev. 0 to Rev. A

Changes to Features Section, Applications Section, and

Figure 1 ............................................................................................... 1

Added Table 2; Renumbered Sequentially ..................................... 3

Changed VREF to V

REF

..................................................................... 4

Changes to Table 3 ............................................................................. 5

Changes to Table 4 ............................................................................. 6

Changes to Table 5 ............................................................................. 7

Deleted Endnote 2 in Table 6 ........................................................... 8

Changes to Figure 4, Figure 5, and Table 7 .................................... 9

Changes to Figure 6, Figure 9, and Figure 10 ............................. 11

Rev. E | Page 2 of 35

Data Sheet

Changes to Figure 22 ...................................................................... 13

Changes to Overview Section and Converter Operation

Section .............................................................................................. 15

Changes to Table 8 .......................................................................... 16

Changes to Figure 26 and Figure 27 ............................................. 17

Changes to Bipolar Single Supply Section and Analog Inputs

Section .............................................................................................. 18

Changes to Internal Reference/Temperature Sensor Section .... 20

Added Figure 31; Renumbered Sequentially ............................... 20

Changes to External Reference and Internal Buffer Section and

External Reference Section ............................................................ 21

Added Figure 32 and Figure 33 ..................................................... 21

Changes to Power Supply Section ................................................. 22

Changes to Digital Interface Section, Reading/Writing After

Conversion, Any Speed Hosts Section, and Configuration

Register, CFG Section ..................................................................... 23

Changes to Table 10 ........................................................................ 24

AD7682/AD7689

Added General Timing Without a Busy Indicator Section and

Figure 37 ........................................................................................... 25

Added General Timing With a Busy Indicator Section and

Figure 38 ........................................................................................... 26

Added Channel Sequencer Section and Figure 39 ..................... 27

Changes to Read/Write Spanning Conversion Without a Busy

Indicator Section and Figure 41 .................................................... 28

Changes to Read/Write Spanning Conversion with a Busy

Indicator and Figure 43 .................................................................. 29

Changes to Evaluating AD7682/AD7689 Performance

Section .............................................................................................. 30

Added Exposed Pad Notation to Outline Dimensions .............. 31

Changes to Ordering Guide ........................................................... 31

5/08—Revision 0: Initial Version

Rev. E | Page 3 of 35

AD7682/AD7689

SPECIFICATIONS

VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V

REF

= VDD, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 2.

Parameter

RESOLUTION

Conditions/Comments

ANALOG INPUT

Voltage Range Unipolar mode

Bipolar mode

Absolute Input Voltage Positive input, unipolar and bipolar modes

Negative or COM input, unipolar mode

Analog Input CMRR

Negative or COM input, bipolar mode f

IN

= 250 kHz

Acquisition phase Leakage Current at

25°C

Input Impedance 1

THROUGHPUT

Conversion Rate

Full Bandwidth 2

¼ Bandwidth 2

Transient Response

VDD = 4.5 V to 5.5 V

VDD = 2.3 V to 4.5 V

VDD = 4.5 V to 5.5 V

VDD = 2.3 V to 4.5 V

Full-scale step, full bandwidth

Full-scale step,

¼ bandwidth

ACCURACY

No Missing Codes

Integral Linearity Error

Differential Linearity

Error

Transition Noise

Gain Error

4

Gain Error Match

Gain Error Temperature

Drift

Offset Error

4

REF = VDD = 5 V

VDD = 4.5 V to 5.5 V

Offset Error Match

Offset Error Temperature

Drift

VDD = 2.3 V to 4.5 V

Power Supply Sensitivity VDD = 5 V ± 5%

0

0

0

0

250

200

62.5

50

1.8

0

0

0

0

+0.1

250

200

62.5

50

1.8

Data Sheet

kSPS kSPS kSPS kSPS

μs

V

V

Unit

Bits

V

V

REF

/2 − 0.1 V

REF

/2 V

REF

/2 + 0.1 V

REF

/2 − 0.1 V

REF

/2 V

REF

/2 + 0.1 V

15

−4

Min

16

0

−V

REF

/2

−0.1

−0.1

−32

−32

AD7689A

Typ Max

+V

+V

V

REF

REF

REF

/2

+ 0.1

68

1

0.6

±2

±1

±32

±2

±1

+32

±1.5

+0.1

14.5

+4

+32

−8

−4

−8

−4

Min

16

0

−V

REF

/2

−0.1

AD7682B/AD7689B

Typ Max

+V

+V

V

REF

REF

REF

/2

+ 0.1

−0.1

16

−1.5

−1

68

1

14.5

±0.4 +1.5

±0.25 +1.5

0.5

±1 +8

±0.5 +4

±1

±1 +8

±5

±0.5 +4

±1

±1.5 dB nA

μs

Bits

LSB 3

LSB

LSB

LSB

LSB ppm/°C

LSB

LSB

LSB ppm/°C

LSB

Rev. E | Page 4 of 35

Data Sheet AD7682/AD7689

Parameter

AC ACCURACY 5

Dynamic Range

Signal-to-Noise

LFCSP

WLFCSP

SINAD

LFCSP

WLFCSP

Conditions/Comments

f

IN

= 20 kHz, V

REF

= 5 V f

IN

= 20 kHz, V

REF

=

4.096 V, internal REF f

IN

= 20 kHz, V

REF

= 2.5 V, internal REF f

IN

= 20 kHz, V

REF

= 5 V f

IN

= 20 kHz, V

REF

=

4.096 V, internal REF f

IN

= 20 kHz, V

REF

= 2.5 V, internal REF f

IN

= 20 kHz, V

REF

= 5 V f

IN

= 20 kHz, V

REF

= 5 V,

−60 dB input f

IN

= 20 kHz, V

REF

=

4.096 V internal REF f

IN

= 20 kHz, V

REF

= 2.5 V internal REF f

IN

= 20 kHz, V

REF

= 5 V f

IN

= 20 kHz, V

REF

= 5 V,

−60 dB input f

IN

= 20 kHz, V

REF

=

4.096 V internal REF f

IN

= 20 kHz, V

REF

= 2.5 V internal REF

Min

AD7689A

Typ

90.5

90

89

86

89

30.5

88

86

Max Min

92.5

91

87.5

91

89.5

86

91

90

87

89.5

88.5

85.5

AD7682B/AD7689B

Typ

93.8

93.5

92.3

88.8

92

91

87.5

92.5

33.5

91

88.4

91

32

89.5

87

Max Unit

dB 6 dB dB dB dB dB dB dB dB dB dB dB dB dB dB

SAMPLING DYNAMICS

Total Harmonic

Distortion (THD)

Spurious-Free Dynamic

Range

Channel-to-Channel

Crosstalk

−3 dB Input Bandwidth f f

IN

IN

= 20 kHz

= 20 kHz f

IN

= 100 kHz on adjacent channel(s)

Full bandwidth

¼ bandwidth

−97

105

−120

1.7

0.425

−100

110

−125

1.7

0.425 dB dB dB

MHz

MHz

Aperture Delay VDD = 5 V 2.5 2.5 ns

1

See the Analog Inputs section.

2

The bandwidth is set in the configuration register.

3 LSB means least significant bit. With the 5 V input range, one LSB is 76.3 µV.

4

See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.

5 With VDD = 5 V, unless otherwise noted.

6

All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified.

Rev. E | Page 5 of 35

AD7682/AD7689

VDD = 2.3 V to 5.5 V, VIO = 1.8 V to VDD, V

REF

= VDD, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 3.

Parameter

INTERNAL REFERENCE

REF Output Voltage

REFIN Output Voltage 1

REF Output Current

Temperature Drift

Line Regulation

Long-Term Drift

Turn-On Settling Time

EXTERNAL REFERENCE

Voltage Range

Current Drain

2

TEMPERATURE SENSOR

Output Voltage 3

Temperature Sensitivity

DIGITAL INPUTS

Logic Levels

V

IL

V

IH

I

IL

I

IH

DIGITAL OUTPUTS

Data Format 4

Pipeline Delay 5

V

OL

V

OH

POWER SUPPLIES

VDD

VIO

Standby Current 6, 7

Power Dissipation

Energy per Conversion

TEMPERATURE RANGE 8

Specified Performance

Conditions/Comments

2.5 V at 25°C

4.096 V at 25°C

2.5 V at 25°C

4.096 V at 25°C

VDD = 5 V ± 5%

1000 hours

C

REF

= 10 µF

REF input

REFIN input (buffered)

250 kSPS, REF = 5 V

25°C

I

SINK

= +500 µA

I

SOURCE

= −500 µA

Specified performance

Specified performance

VDD and VIO = 5 V at 25°C

VDD = 2.5 V, 100 SPS throughput

VDD = 2.5 V, 200 kSPS throughput

VDD = 5 V, 250 kSPS throughput

VDD = 5 V, 250 kSPS throughput with internal reference

VDD = 5 V

T

MIN

to T

MAX

1 This is the output from the internal band gap.

2 This is an average current and scales with throughput.

3 The output voltage is internal and present on a dedicated multiplexer input.

4 Unipolar mode is serial 16-bit straight binary. Bipolar mode is serial 16-bit twos complement.

5 Conversion results available immediately after completed conversion.

6 With all digital inputs forced to VIO or GND as required.

7

During acquisition phase.

8 Contact an Analog Devices, Inc., sales representative for the extended temperature range.

−40

60

2.3

1.8

−0.3

0.7 × VIO

−1

−1

VIO − 0.3

Min

2.490

4.086

0.5

0.5

Typ Max

2.500 2.510

4.096 4.106

1.2

2.3

±300

±10

±15

50

5

50

283

1

VDD + 0.3 V

VDD − 0.5 V

µA mV mV/°C

Unit

V

V

V

V

µA ppm/°C ppm/V ppm ms

+0.3 × VIO V

VIO + 0.3

+1

+1

0.4

V

µA

µA

50

5.5 V

VDD + 0.3 V nA

1.7

3.5

12.5 18

15.5 21

µW mW mW mW

V

V

+85

Data Sheet

nJ

°C

Rev. E | Page 6 of 35

Data Sheet

TIMING SPECIFICATIONS

VDD = 4.5 V to 5.5 V, VIO = 1.8 V to VDD, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 4.

Parameter 1

CONVERSION TIME

CNV Rising Edge to Data Available

ACQUISITION TIME

TIME BETWEEN CONVERSIONS

DATA WRITE/READ DURING CONVERSION

SCK

Period

Low Time

High Time

Falling Edge to Data Remains Valid

Falling Edge to Data Valid Delay

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV

Pulse Width

Low to SDO D15 MSB Valid

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

High or Last SCK Falling Edge to SDO High Impedance

Low to SCK Rising Edge

DIN

Valid Setup Time from SCK Rising Edge

Valid Hold Time from SCK Rising Edge

1

See Figure 2 and Figure 3 for load conditions.

Symbol

t

CONV t

ACQ t

CYC t

DATA t

SCK t

SCKL t

SCKH t

HSDO t

DSDO t

CNVH t

EN t

DIS t

CLSCK t

SDIN t

HDIN

5

5

Min

1.8

4.0

10

10

4 t

DSDO

+ 2

11

11

AD7682/AD7689

18

23

28

1.2

22

25

32

18

Max

2.2

Typ

ns ns ns ns

µs ns ns ns ns ns ns ns ns ns

Unit

µs

µs

µs ns ns

Rev. E | Page 7 of 35

AD7682/AD7689

VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications T

MIN

to T

MAX

, unless otherwise noted.

Table 5.

Parameter

1

CONVERSION TIME

CNV Rising Edge to Data Available

ACQUISITION TIME

TIME BETWEEN CONVERSIONS

DATA WRITE/READ DURING CONVERSION

SCK

Period

Low Time

High Time

Falling Edge to Data Remains Valid

Falling Edge to Data Valid Delay

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

CNV

Pulse Width

Low to SDO D15 MSB Valid

VIO Above 3 V

VIO Above 2.7 V

VIO Above 2.3 V

VIO Above 1.8 V

High or Last SCK Falling Edge to SDO High Impedance

Low to SCK Rising Edge

DIN

Valid Setup Time from SCK Rising Edge

Valid Hold Time from SCK Rising Edge

Symbol

t

CONV t

ACQ t

CYC t

DATA t

SCK t

SCKL t

SCKH t

HSDO t

DSDO t

EN t

CNVH t

DIS t

CLSCK t

SDIN t

HDIN

Min

5

5

10

10

5

1.8

5 t

DSDO

+ 2

12

12

Typ

1

See Figure 2 and Figure 3 for load conditions.

500µA

I

OL

Data Sheet

Max

3.2

1.2

38

48

24

30

21

27

35

45

50

Unit

µs

µs

µs

µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

TO SDO

C

L

50pF

1.4V

500µA I

OH

Figure 2. Load Circuit for Digital Interface Timing

70% VIO

30% VIO t

DELAY

2V OR VIO – 0.5V

1

0.8V OR 0.5V

2 t

DELAY

2V OR VIO – 0.5V

1

0.8V OR 0.5V

2

1

2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.

2

0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.

Figure 3. Voltage Levels for Timing

Rev. E | Page 8 of 35

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 6.

Parameter Rating

Analog Inputs

INx,

1

COM GND − 0.3 V to VDD + 0.3 V or VDD ± 130 mA

REF, REFIN

Supply Voltages

VDD, VIO to GND

VIO to VDD

DIN, CNV, SCK to GND

SDO to GND

Storage Temperature Range

Junction Temperature

θ

JA

Thermal Impedance (LFCSP)

θ

JC

Thermal Impedance (LFCSP)

1

See the Analog Inputs section.

GND − 0.3 V to VDD + 0.3 V

−0.3 V to +7 V

−0.3 V to VDD + 0.3 V

−0.3 V to VIO + 0.3 V

−0.3 V to VIO + 0.3 V

−65°C to +150°C

150°C

48°C/W

4.4°C/W

AD7682/AD7689

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

ESD CAUTION

Rev. E | Page 9 of 35

AD7682/AD7689

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VDD

REF

REFIN

GND

GND

1

2

3

4

5

PIN 1

INDICATOR

AD7682

TOP VIEW

(Not to Scale)

15 VIO

14 SDO

13 SCK

12 DIN

11 CNV

VDD

REF

REFIN

GND

GND

1

2

3

4

5

PIN 1

INDICATOR

AD7689

TOP VIEW

(Not to Scale)

15 VIO

14 SDO

13 SCK

12 DIN

11 CNV

Data Sheet

NOTES

1. NC = NO CONNECT.

2. THE EXPOSED PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED

RELIABILITY OF THE SOLDER JOINTS, IT

IS RECOMMENDED THAT THE PAD BE

SOLDERED TO THE SYSTEM

GROUND PLANE.

Figure 4. AD7682 LFCSP Pin Configuration

NOTES

1. THE EXPOSED PAD IS NOT CONNECTED

INTERNALLY. FOR INCREASED

RELIABILITY OF THE SOLDER JOINTS, IT

IS RECOMMENDED THAT THE PAD BE

SOLDERED TO THE SYSTEM

GROUND PLANE.

Figure 5. AD7689 LFCSP Pin Configuration

Table 7. AD7682 LFCSP and AD7689 LFCSP Pin Function Descriptions

Pin

No.

AD7682

LFCSP

Mnemonic

AD7689

LFCSP

Mnemonic Type 1

Description

1, 20 VDD VDD

2

3

9

10

4, 5

6

7

8

11

12

REF

REFIN

GND

NC

IN2

NC

IN3

COM

CNV

DIN

REF

REFIN

GND

IN4

IN5

IN6

IN7

COM

CNV

DIN

AI

AI

AI

AI

P Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for a

2.5 V output, the minimum must be 3.0 V. When using the internal reference for 4.096 V output, the minimum must be 4.6 V.

AI/O

Reference Input/Output. See the Voltage Reference Output/Input section. When the

internal reference is enabled, this pin produces a selectable system reference of 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD − 0.5 V, maximum), which is useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor

connected as close to REF as possible. See the Reference Decoupling section.

AI/O

Internal Reference Output/Reference Buffer Input. See the Voltage Reference

Output/Input section. When using the internal reference, the internal unbuffered

reference voltage is present and requires decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is buffered to the REF pin, as described in the REF pin description.

P

AI

Power Supply Ground.

No Connection ( AD7682 ).

DI

DI

Analog Input Channel 4 ( AD7689 ).

Analog Input Channel 2 ( AD7682 ).

Analog Input Channel 5 ( AD7689 ).

No Connection ( AD7682 ).

Analog Input Channel 6 ( AD7689 ).

Analog Input Channel 3 ( AD7682 ).

Analog Input Channel 7 ( AD7689 ).

Common Channel Input. All input channels, IN[7:0], can be referenced to a commonmode point of 0 V or V

REF

/2 V.

Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held low, the busy indictor is enabled.

Data Input. Use this input for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion.

Rev. E | Page 10 of 35

Data Sheet AD7682/AD7689

Pin

No.

13

14

15

16

17

18

19

21

AD7682

LFCSP

Mnemonic

SCK

SDO

VIO

IN0

NC

IN1

NC

EPAD

AD7689

LFCSP

Mnemonic Type 1

Description

SCK DI Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion.

SDO DO

VIO

IN0

IN1

P

AI

AI

Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement.

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

Analog Input Channel 0.

No Connection ( AD7682 ).

IN2

IN3

EPAD

AI

AI

NC

Analog Input Channel 1 (

Analog Input Channel 1 (

Analog Input Channel 2 (

No Connection ( AD7682

Analog Input Channel 3 (

AD7682

AD7689

).

AD7689 ).

Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane.

AD7689 ).

).

).

1

AI means analog input, AI/O means analog input/output, DI means digital input, DO means digital output, P means power, and NC means no internal connection.

Rev. E | Page 11 of 35

AD7682/AD7689

6

AD7682

5 4 9 8 7

A NC IN1

3

IN0

2 1

VIO

Data Sheet

A

9 8 7

IN3

6

AD7689

5 4

IN2

3

IN0

2 1

VIO

B VDD VDD NC SDO

B VDD VDD IN1 SDO

C

REF REFIN DIN SCK

D GND GND IN3 CNV

C REF REFIN DIN SCK

D GND GND IN7 CNV

E NC IN2 NC

Figure 6. AD7682 WLCSP Pin Configuration

COM

E IN4 IN5 IN6

Figure 7. AD7689 WLCSP Pin Configuration

COM

Table 8. AD7682 WLCSP and AD7689 WLCSP Pin Function Descriptions

Pin

No.

AD7682

WLCSP

Mnemonic

AD7689

WLCSP

Mnemonic Type 1

Description

B6, B8 VDD VDD

C9

C7

REF

REFIN

E3

D4

E1

D6, D8 GND

A7

E5

NC

IN2

NC

IN3

COM

D2 CNV

REF

REFIN

GND

IN3

IN5

IN6

IN7

COM

CNV

AI

AI

AI

AI

AI

P

AI/O

Power Supply. Nominally 2.5 V to 5.5 V when using an external reference and decoupled with 10 μF and 100 nF capacitors. When using the internal reference for a

2.5 V output, the minimum must be 3.0 V. When using the internal reference for 4.096 V output, the minimum must be 4.6 V.

Reference Input/Output. See the Voltage Reference Output/Input section. When the

internal reference is enabled, this pin produces a selectable system reference of 2.5 V or 4.096 V. When the internal reference is disabled and the buffer is enabled, REF produces a buffered version of the voltage present on the REFIN pin (VDD − 0.5 V, maximum), which is useful when using low cost, low power references. For improved drift performance, connect a precision reference to REF (0.5 V to VDD). For any reference method, this pin needs decoupling with an external 10 μF capacitor

connected as close to REF as possible. See the Reference Decoupling section.

AI/O

Internal Reference Output/Reference Buffer Input. See the Voltage Reference

Output/Input section. When using the internal reference, the internal unbuffered

reference voltage is present and requires decoupling with a 0.1 μF capacitor. When using the internal reference buffer, apply a source between 0.5 V and (VDD − 0.5 V) that is buffered to the REF pin, as described in the REF pin description.

P Power Supply Ground.

DI

No Connection (

No Connection (

AD7682

Analog Input Channel 3 (

Analog Input Channel 2 (

Analog Input Channel 5 (

AD7682

Analog Input Channel 6 (

Analog Input Channel 3 (

Analog Input Channel 7 (

).

AD7689

AD7682

AD7689

).

AD7689

AD7682

AD7689 mode point of 0 V or V

REF

/2 V.

).

).

).

).

).

).

Common Channel Input. All input channels, IN[7:0], can be referenced to a common-

Conversion Input. On the rising edge, CNV initiates the conversion. During conversion, if CNV is held low, the busy indictor is enabled.

Rev. E | Page 12 of 35

Data Sheet AD7682/AD7689

Pin

No.

C5

C3

B2

A1

A3

B4

A5

AD7682

WLCSP

Mnemonic

DIN

SCK

SDO

VIO

IN0

NC

IN1

AD7689

WLCSP

Mnemonic Type 1

Description

DIN DI Data Input. Use this input for writing to the 14-bit configuration register. The configuration register can be written to during and after conversion.

SCK DI

SDO

VIO

IN0

DO

P

AI

Serial Data Clock Input. This input is used to clock out the data on SDO and clock in data on DIN in an MSB first fashion.

Serial Data Output. The conversion result is output on this pin, synchronized to SCK. In unipolar modes, conversion results are straight binary; in bipolar modes, conversion results are twos complement.

Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V, or 5 V).

Analog Input Channel 0.

IN1

IN2

AI

AI

No connection ( AD7682 ).

Analog Input Channel 1 ( AD7689 ).

Analog Input Channel 1 ( AD7682 ).

E7 NC IN4 AI

Analog Input Channel 2 (

No Connection ( AD7682

Analog Input Channel 4 (

AD7689

).

AD7689

).

).

1 AI means analog input, AI/O means analog input/output, DI means digital input, DO means digital output, P means power, and NC means no internal connection.

Rev. E | Page 13 of 35

AD7682/AD7689

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = 2.5 V to 5.5 V, V

REF

= 2.5 V to 5 V, VIO = 2.3 V to VDD, unless otherwise noted.

1.5

INL MAX = +0.34 LSB

INL MIN = –0.44 LSB

1.0

1.5

DNL MAX = +0.20 LSB

DNL MIN = –0.22 LSB

1.0

0.5

0.5

0

0

–0.5

–0.5

–1.0

–1.5

0 16,384 32,768

CODES

49,152 65,536

Figure 8. Integral Nonlinearity vs. Code, V

REF

= VDD = 5 V

200k

σ = 0.50

V

REF

= VDD = 5V

180k

160k

140k

135,326

124,689

120k

100k

80k

60k

40k

20k

0

0 0 487 619 0 0 0

7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002

CODE IN HEX

Figure 9. Histogram of a DC Input at Code Center

0

–20

–40

–60

–80

V

REF f f

= VDD = 5V

S

= 250kSPS

IN

= 19.9kHz

SNR = 92.9dB

SINAD = 92.4dB

THD = –102dB

SFDR = 103dB

SECOND HARMONIC = –111dB

THIRD HARMONIC = –104dB

–100

–120

–140

–160

–180

0 125 25 50 75

FREQUENCY (kHz)

100

Figure 10. 20 kHz FFT, V

REF

= VDD = 5 V

Data Sheet

120k

100k

80k

60k

40k

–1.0

0 16,384 32,768

CODES

49,152 65,536

Figure 11. Differential Nonlinearity vs. Code, V

REF

= VDD = 5 V

160k

σ = 0.78

V

REF

= VDD = 2.5V

140k

135,207

63,257

51,778

20k

6649

0

1 78

4090

60 1

7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003

CODE IN HEX

Figure 12. Histogram of a DC Input at Code Center

0

–20

–40

–60

–80

V

REF f f s

= VDD = 2.5V

= 200kSPS

IN

= 19.9kHz

SNR = 88.0dB

SINAD = 87.0dB

THD = –89dB

SFDR = 89dB

SECOND HARMONIC = –105dB

THIRD HARMONIC = –90dB

–100

–120

–140

–160

–180

0 25 50

FREQUENCY (kHz)

75

Figure 13. 20 kHz FFT, V

REF

= VDD = 2.5 V

100

Rev. E | Page 14 of 35

Data Sheet

100

75

70

65

60

0

85

80

95

90

V

REF

V

REF

V

REF

V

REF

= VDD = 5V, –0.5dB

= VDD = 5V, –10dB

= VDD = 2.5V, –0.5dB

= VDD = 2.5V, –10dB

50 100

FREQUENCY (kHz)

150

Figure 14. SNR vs. Frequency

200

96 17.0

86

84

82

90

88

94

92

SNR @ 2kHz

SINAD @ 2kHz

SNR @ 20kHz

SINAD @ 20kHz

ENOB @ 2kHz

ENOB @ 20kHz

80

1.0

1.5

2.0

2.5

3.0

3.5

4.0

REFERENCE VOLTAGE (V)

4.5

5.0

5.5

13.0

Figure 15. SNR, SINAD, and ENOB vs. Reference Voltage

96 f

IN

= 20kHz

94

V

REF

= VDD = 5V

14.5

14.0

13.5

16.5

16.0

15.5

15.0

92

90

88

86

V

REF

= VDD = 2.5V

84

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

Figure 16. SNR vs. Temperature

85 105

125

AD7682/AD7689

100

95

90

85

80

75

70

65

V

REF

V

REF

V

REF

V

REF

= VDD = 5V, –0.5dB

= VDD = 5V, –10dB

= VDD = 2.5V, –0.5dB

= VDD = 2.5V, –10dB

130

125

100

95

90

85

120

115

110

105

80

75

70

1.0

60

0 50 100

FREQUENCY (kHz)

150

Figure 17. SINAD vs. Frequency

200

–60

–65

SFDR = 2kHz

SFDR = 20kHz

THD = 20kHz

THD = 2kHz

1.5

2.0

2.5

3.0

3.5

4.0

REFERENCE VOLTAGE (V)

4.5

5.0

Figure 18. SFDR and THD vs. Reference Voltage

–70

–75

–80

–85

–90

–95

–100

–105

–110

–115

5.5

–120

–90 f

IN

= 20kHz

–95

V

REF

= VDD = 5V

V

REF

= VDD = 2.5V

–100

–105

–110

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

Figure 19. THD vs. Temperature

85 105

125

Rev. E | Page 15 of 35

AD7682/AD7689

–60

–70

–80

–90

–100

–110

–120

0

95

94 f

IN

= 20kHz

90

89

88

93

92

91

87

86

85

–10 –8

50 100

V

REF

V

REF

= VDD = 5V, –0.5dB

= VDD = 2.5V, –0.5dB

V

REF

V

REF

= VDD = 2.5V, –10dB

= VDD = 5V, –10dB

150 200

FREQUENCY (kHz)

Figure 20. THD vs. Frequency

V

REF

= VDD = 5V

V

REF

= VDD = 2.5V

–6 –4

INPUT LEVEL (dB)

–2 0

Figure 21. SNR vs. Input Level

3

2

1

0

–1

–2

UNIPOLAR ZERO

UNIPOLAR GAIN

BIPOLAR ZERO

BIPOLAR GAIN

–3

–55 –35 –15 5 25 45 65

TEMPERATURE (°C)

85 105

125

Figure 22. Offset and Gain Errors vs. Temperature

Rev. E | Page 16 of 35

Data Sheet

2000

1750

1500

1250

3000

2750

2500

2250

2.5V INTERNAL REF

4.096V INTERNAL REF

INTERNAL BUFFER, TEMP ON

INTERNAL BUFFER, TEMP OFF

EXTERNAL REF, TEMP ON

EXTERNAL REF, TEMP OFF

VIO

1000

2.5

3.0

3.5

4.0

VDD SUPPLY (V)

4.5

5.0

Figure 23. Operating Currents vs. Supply

3000

2750

2500 f

S

= 200kSPS

VDD = 5V, INTERNAL 4.096V REF f

S

= 200kSPS

40

30

60

50

20

5.5

80

70

100

90

180

160

140

2250

2000

1750

VDD = 5V, EXTERNAL REF

1500 60

VDD = 2.5, EXTERNAL REF

1250 40

1000

–55 –35 –15

VIO

5 25 45 65

TEMPERATURE (°C)

85 105 125

20

Figure 24. Operating Currents vs. Temperature

25

120

100

80

VDD = 2.5V, 85°C

20

15

VDD = 2.5V, 25°C

10

VDD = 5V, 85°C

VDD = 5V, 25°C

5

VDD = 3.3V, 85°C

VDD = 3.3V, 25°C

0

0 20 40 60 80

SDO CAPACITIVE LOAD (pF)

100 120

Figure 25. t

DSDO

Delay vs. SDO Capacitance Load and Supply

Data Sheet

TERMINOLOGY

Least Significant Bit (LSB)

The LSB is the smallest increment represented by a converter.

For an ADC with N bits of resolution, the LSB expressed in volts is

LSB

(V) =

V

2

REF

N

Integral Nonlinearity Error (INL)

INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from

the middle of each code to the true straight line (see Figure 27).

Differential Nonlinearity Error (DNL)

In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed.

Offset Error

The first transition must occur at a level ½ LSB above analog ground. The offset error is the deviation of the actual transition from that point.

Gain Error

The last transition (from 111…10 to 111…11) must occur for an analog voltage 1½ LSB below the nominal full scale. The gain error is the deviation in LSB (or percentage of full-scale range) of the actual level of the last transition from the ideal level after the offset error is adjusted out. Closely related is the full-scale error (also in LSB or percentage of full-scale range), which includes the effects of the offset error.

Aperture Delay

Aperture delay is the measure of the acquisition performance. It is the time between the rising edge of the CNV input and the point at which the input signal is held for a conversion.

Transient Response

Transient response is the time required for the ADC to accurately acquire its input after a full-scale step function is applied.

Dynamic Range

Dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together.

The value for dynamic range is expressed in decibels.

AD7682/AD7689

Signal-to-Noise Ratio (SNR)

SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels.

Signal-to-(Noise + Distortion) Ratio (SINAD)

SINAD is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for

SINAD is expressed in decibels.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels.

Spurious-Free Dynamic Range (SFDR)

SFDR is the difference, in decibels, between the rms amplitude of the input signal and the peak spurious signal.

Effective Number of Bits (ENOB)

ENOB is a measurement of the resolution with a sine wave input. It is related to SINAD by the formula

ENOB = (SINAD dB

− 1.76)/6.02 and is expressed in bits.

Channel-to-Channel Crosstalk

Channel-to-channel crosstalk is a measure of the level of crosstalk between any two adjacent channels. It is measured by applying a dc to the channel under test and applying a full-scale, 100 kHz sine wave signal to the adjacent channel(s). The crosstalk is the amount of signal that leaks into the test channel, and is expressed in decibels.

Reference Voltage Temperature Coefficient

Reference voltage temperature coefficient is derived from the typical shift of output voltage at 25°C on a sample of parts at the maximum and minimum reference output voltage (V

REF

) measured at T

MIN

, T (25°C), and T

MAX

. It is expressed in ppm/°C as

TCV

REF

( ppm/

°

C )

=

V

V

REF

REF

(

Max

(

25

°

C

)

×

) –

V

REF

(

T

MAX

(

Min

)

T

MIN

)

×

10

6 where:

V

REF

(Max) = maximum V

REF

at T

MIN

, T (25°C), or T

MAX

.

V

REF

(Min) = minimum V

REF

at T

MIN

, T (25°C), or T

MAX

.

V

REF

(25°C) = V

REF

at 25°C.

T

MAX

= +85°C.

T

MIN

= –40°C.

Rev. E | Page 17 of 35

AD7682/AD7689

THEORY OF OPERATION

INx+

Data Sheet

REF

GND

32,768C

MSB

16,384C

32,768C 16,384C

MSB

4C 2C

4C 2C

C

C

C

C

LSB SW+

SWITCHES CONTROL

COMP

CONTROL

LOGIC

BUSY

OUTPUT CODE

LSB SW–

CNV

INx– OR

COM

Figure 26. ADC Simplified Schematic

OVERVIEW

The AD7682 / AD7689 are 4-channel/8-channel, 16-bit, charge redistribution SAR ADCs. These devices are capable of converting 250,000 samples per second (250 kSPS) and power down between conversions. For example, when operating with an external reference at 1 kSPS, they consume 17 µW typically, ideal for battery-powered applications.

The AD7682 / AD7689 contain all of the components for use in a multichannel, low power data acquisition system, including

• 16-bit SAR ADC with no missing codes

• 4-channel/8-channel, low crosstalk multiplexer

• Internal low drift reference and buffer

• Temperature sensor

• Selectable one-pole filter

• Channel sequencer

These components are configured through an SPI-compatible,

14-bit register. Conversion results, also SPI compatible, can be read after or during conversions with the option for reading back the configuration associated with the conversion.

The AD7682 / AD7689 provide the user with an on-chip trackand-hold and do not exhibit pipeline delay or latency.

The AD7682 / AD7689 are specified from 2.3 V to 5.5 V and can be interfaced to any 1.8 V to 5 V digital logic family. They are housed in a 20-lead, 4 mm × 4 mm LFCSP and a 20-lead,

2.4 mm × 2.4 mm WLCSP that combine space savings and allow flexible configurations. They are pin-for-pin compatible with the 16-bit AD7699 and 14-bit AD7949 .

CONVERTER OPERATION

The AD7682 / AD7689 are successive approximation ADCs

based on a charge redistribution DAC. Figure 26 shows the

simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs.

During the acquisition phase, terminals of the array tied to the comparator input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs.

The capacitor arrays are used as sampling capacitors and acquire the analog signal on the INx+ and INx− (or COM) inputs. When the acquisition phase is complete and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− open first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the INx+ and INx− (or COM) inputs captured at the end of the acquisition phase applies to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps

(V

REF

/2, V

REF

/4...V

REF

/32,768). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the device returns to the acquisition phase, and the control logic generates the ADC output code and a busy signal indicator.

Because the AD7682 / AD7689 have an on-board conversion clock, the serial clock, SCK, is not required for the conversion process.

Rev. E | Page 18 of 35

Data Sheet

TRANSFER FUNCTIONS

With the inputs configured for unipolar range (single-ended,

COM with ground sense, or paired differentially with INx− as ground sense), the data output is straight binary.

With the inputs configured for bipolar range (COM = V

REF

/2 or paired differentially with INx− = V

REF

/2), the data outputs are twos complement.

The ideal transfer characteristic for the AD7682 / AD7689 is

shown in Figure 27 and for both unipolar and bipolar ranges

with the internal 4.096 V reference.

TWOS

COMPLEMENT

STRAIGHT

BINARY

011...111

011...110

011...101

111...111

111...110

111...101

AD7682/AD7689

Table 9. Output Codes and Ideal Input Voltages

Description

FSR − 1 LSB

Unipolar Analog Input 1

V

REF

= 4.096 V

4.095938 V

Midscale + 1 LSB 2.048063 V

Midscale 2.048 V

Midscale − 1 LSB 2.047938 V

−FSR + 1 LSB 62.5 μV

Digital Output Code

(Straight Binary Hex)

0xFFFF

0x8001

0x8000

0x7FFF

0x0001

3

−FSR 0 V 0x0000 4

1

2

With COM or INx− = 0 V or all INx referenced to GND.

3

With COM or INx− = V

REF

/2.

This is also the code for an overranged analog input ((INx+) − (INx−), or COM, above V

REF

4

− GND).

This is also the code for an underranged analog input ((INx+) − (INx−), or COM, below GND).

100...010

100...001

100...000

000...010

000...001

000...000

–FSR

–FSR + 1LSB

–FSR + 0.5LSB

+FSR – 1LSB

+FSR – 1.5LSB

ANALOG INPUT

Figure 27. ADC Ideal Transfer Function

Bipolar Analog Input

V

REF

= 4.096 V

2

2.047938 V

62.5 μV

0 V

−62.5 μV

−2.047938 V

−2.048 V

Digital Output Code

(Twos Complement Hex)

0x7FFF

3

0x0001

0x0000

0xFFFF

0x8001

0x8000 4

Rev. E | Page 19 of 35

AD7682/AD7689

TYPICAL CONNECTION DIAGRAMS

5V 1.8V TO VDD

100nF 100nF

10µF

2

100nF

V+

0V TO V

REF

ADA4841-x

3

V–

V+

IN0

REF

REFIN VDD

AD7689

IN[7:1]

VIO

DIN

SCK

SDO

CNV

MOSI

SCK

MISO

SS

0V TO V

REF

ADA4841-x

3

V–

0V OR

V

REF

/2

COM

GND

NOTES

1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR

REFERENCE SELECTION.

2. C

REF

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.

4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.

Figure 28. Typical Application Diagram with Multiple Supplies

+5V

1.8V TO VDD

100nF

10µF

2

V+

ADA4841-x

3

V–

100nF

REF

IN0

100nF

REFIN VDD

AD7689

VIO

V+

ADA4841-x

3

V–

IN[7:1]

DIN

SCK

SDO

CNV

V

REF

p-p

V

REF

/2

COM

GND

NOTES

1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR

REFERENCE SELECTION.

2. C

REF

IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).

3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS.

4. SEE THE DIGITAL INTERFACE SECTION FOR CONFIGURING AND READING CONVERSION DATA.

Figure 29. Typical Application Diagram Using Bipolar Input

MOSI

SCK

MISO

SS

Data Sheet

Rev. E | Page 20 of 35

Data Sheet

Unipolar or Bipolar

Figure 28 shows an example of the recommended connection

diagram for the AD7682 / AD7689 when multiple supplies are available.

Bipolar Single Supply

Figure 29 shows an example of a system with a bipolar input

using single supplies with the internal reference (optional different VIO supply). This circuit is also useful when the amplifier/signal conditioning circuit is remotely located with some common mode present. Note that for any input configuration, the INx inputs are unipolar and are always referenced to GND (no negative voltages even in bipolar range).

For this circuit, a rail-to-rail input/output amplifier can be used; however, take the offset voltage vs. input common-mode range into consideration (1 LSB = 62.5 μV with V

REF

= 4.096 V). Note that the conversion results are in twos complement format when using the bipolar input configuration. Refer to the

AN-581 Application Note , Biasing and Decoupling Op Amps in

Single Supply Applications, for additional details about using single-supply amplifiers.

ANALOG INPUTS

Input Structure

Figure 30 shows an equivalent circuit of the input structure of

the AD7682 / AD7689 . The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward biased and to start conducting current.

These diodes can handle a maximum forward-biased current of

130 mA. For instance, these conditions may eventually occur when the input buffer supplies are different from VDD. In such a case, for example, an input buffer with a short circuit, the current limitation can be used to protect the device.

VDD

INx+

OR INx–

OR COM

D1

R

IN

C

IN

C

PIN

D2

GND

Figure 30. Equivalent Analog Input Circuit

This analog input structure allows the sampling of the true differential signal between INx+ and COM or INx+ and INx−.

(COM or INx− = GND ± 0.1 V or V

REF

± 0.1 V). By using these differential inputs, signals common to both inputs are rejected,

as shown in Figure 31.

AD7682/AD7689

60

55

70

65

50

45

40

35

30

1 10 100

FREQUENCY (kHz)

1k

Figure 31. Analog Input CMRR vs. Frequency

10k

During the acquisition phase, the impedance of the analog inputs can be modeled as a parallel combination of the capacitor, CPIN, and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 2.2 kΩ and is a lumped component composed of serial resistors and the on resistance of the switches. CIN is typically 27 pF and is mainly the ADC sampling capacitor.

Selectable Low-Pass Filter

During the conversion phase, when the switches are opened, the input impedance is limited to C

PIN

. While the AD7682 / AD7689 are acquiring, R

IN

and C

IN

make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise from the driving circuitry. The low-pass filter can be programmed for the full bandwidth or ¼ of the bandwidth with CFG[6], as

shown in Table 11. This setting changes R

IN

to 19 kΩ. Note that the converter throughput must also be reduced by ¼ when using the filter. If the maximum throughput is used with the bandwidth (BW) set to ¼, the converter acquisition time, t

ACQ

, is violated, resulting in increased THD.

Rev. E | Page 21 of 35

AD7682/AD7689

Input Configurations

Figure 32 shows the different methods for configuring the

analog inputs with the configuration register, CFG[12:10]. Refer

to the Configuration Register, CFG, section for more details.

The analog inputs can be configured as shown in

• Figure 32 (A), single-ended referenced to system ground;

CFG[12:10] = 111

2

. In this configuration, all inputs

(IN[7:0]) have a range of GND to V

REF

.

• Figure 32 (B), bipolar differential with a common reference

point; COM = V

REF

/2; CFG[12:10] = 010

2

. Unipolar differential with COM connected to a ground sense;

CFG[12:10] = 110

2

. In this configuration, all inputs IN[7:0] have a range of GND to V

REF

.

• Figure 32 (C), bipolar differential pairs with the negative

input channel referenced to V

REF

/2; CFG[12:10] = 00X

2

.

Unipolar differential pairs with the negative input channel referenced to a ground sense; CFG[12:10] = 10X

2

. In these configurations, the positive input channels have the range of GND to V

REF

. The negative input channels are a sense referred to V

REF

/2 for bipolar pairs, or GND for unipolar pairs. The positive channel is configured with CFG[9:7]. If

CFG[9:7] is even, then IN0, IN2, IN4, and IN6 are used. If

CFG[9:7] is odd, then IN1, IN3, IN5, and IN7 are used, as

indicated by the channels with parentheses in Figure 32 (C).

For example, for IN0/IN1 pairs with the positive channel on IN0, CFG[9:7] = 000

2

. For IN4/IN5 pairs with the positive channel on IN5, CFG[9:7] = 101

2

. Note that for the

sequencer, detailed in the Channel Sequencer section, the

positive channels are always IN0, IN2, IN4, and IN6.

• Figure 32 (D), inputs configured in any of the preceding

combinations (showing that the AD7682 / AD7689 can be configured dynamically).

Data Sheet

CH0+

CH1+

CH2+

CH3+

CH4+

CH5+

CH6+

CH7+

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

A—8 CHANNELS,

SINGLE ENDED

CH0+

CH1+

CH2+

CH3+

CH4+

CH5+

CH6+

CH7+

COM–

IN4

IN5

IN6

IN7

COM

GND

IN0

IN1

IN2

IN3

B—8 CHANNELS,

COMMON REFERNCE

CH0+ (–)

CH0– (+)

CH1+ (–)

CH1– (+)

CH2+ (–)

CH2– (+)

CH3+ (–)

CH3– (+)

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

CH0+ (–)

CH0– (+)

CH1+ (–)

CH1– (+)

CH2+

CH3+

CH4+

CH5+

COM–

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

COM

GND

C—4 CHANNELS,

DIFFERENTIAL

D—COMBINATION

Figure 32. Multiplexed Analog Input Configurations

Sequencer

The AD7682 / AD7689 include a channel sequencer useful for

scanning channels in a repeated fashion. Refer to the Channel

Sequencer section for further details on the sequencer

operation.

Source Resistance

When the source impedance of the driving circuit is low, the

AD7682 / AD7689 can be driven directly. Large source impedances significantly affect the ac performance, especially THD.

The dc performances are less sensitive to the input impedance.

The maximum source impedance depends on the amount of

THD that can be tolerated. The THD degrades as a function of the source impedance and the maximum input frequency.

Rev. E | Page 22 of 35

Data Sheet

DRIVER AMPLIFIER CHOICE

Although the AD7682 / AD7689 are easy to drive, the driver amplifier must meet the following requirements:

 The noise generated by the driver amplifier must be kept as low as possible to preserve the SNR and transition noise performance of the AD7682 / AD7689 . Note that the

AD7682 / AD7689 have a noise much lower than most other

16-bit ADCs and, therefore, can be driven by a noisier amplifier to meet a given system noise specification. The noise from the amplifier is filtered by the AD7682 / AD7689 analog input circuit low-pass filter made by R

IN

and C

IN

, or by an external filter, if one is used. Because the typical noise of the AD7682 / AD7689 is 35 μV rms (with V

REF

=

5 V), the SNR degradation due to the amplifier is

SNR

LOSS

20 log

35

2

π

2

35

f

3dB

(

Ne

N

)

2

 where:

f

–3dB

is the input bandwidth in megahertz of the AD7682 /

AD7689 (1.7 MHz in full BW or 425 kHz in ¼ BW), or the cutoff frequency of an input filter, if one is used.

N is the noise gain of the amplifier (for example, 1 in buffer configuration).

e

N

is the equivalent input noise voltage of the op amp, in nV/√Hz.

 For ac applications, the driver must have a THD performance commensurate with the AD7682 / AD7689 .

Figure 20 shows THD vs. frequency for the

AD7682 /

AD7689 .

 For multichannel, multiplexed applications on each input or input pair, the driver amplifier and the AD7682 /

AD7689 analog input circuit must settle a full-scale step onto the capacitor array at a 16-bit level (0.0015%). In amplifier data sheets, settling at 0.1% to 0.01% is more commonly specified. This may differ significantly from the settling time at a 16-bit level and must be verified prior to driver selection.

Table 10. Recommended Driver Amplifiers

ADA4841 -x

AD8655

AD8021

AD8022

OP184

AD8605 ,

AD8615

Very low noise, small, and low power

5 V single supply, low noise

Very low noise and high frequency

Low noise and high frequency

Low power, low noise, and low frequency

5 V single supply, low power

AD7682/AD7689

VOLTAGE REFERENCE OUTPUT/INPUT

The AD7682 / AD7689 allow the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference.

The internal reference of the AD7682 / AD7689 provide excellent performance and can be used in almost all applications.

There are six possible choices of voltage reference schemes,

briefly described in Table 11, with more details in each of the

following sections.

Internal Reference/Temperature Sensor

The precision internal reference, suitable for most applications, can be set for either a 2.5 V or a 4.096 V output, as detailed in

Table 11. With the internal reference enabled, the band gap

voltage is also present on the REFIN pin, which requires an external 0.1 μF capacitor. Because the current output of REFIN is limited, it can be used as a source if followed by a suitable buffer, such as the AD8605 . Note that the voltage of REFIN changes depending on the 2.5 V or 4.096 V internal reference.

Enabling the reference also enables the internal temperature sensor, which measures the internal temperature of the

AD7682 / AD7689 , and is therefore useful for performing a system calibration. For applications requiring the use of the temperature sensor, the internal reference must be active

(internal buffer can be disabled in this case). Note that, when using the temperature sensor, the output is straight binary referenced from the AD7682 / AD7689 GND pin.

The internal reference is temperature compensated to within

10 mV. The reference is trimmed to provide a typical drift of

±10 ppm/°C.

Connect the AD7682 / AD7689

as shown in Figure 33 for either

a 2.5 V or 4.096 V internal reference.

10µF

REF

100nF

REFIN

AD7682/

AD7689

TEMP

GND

Figure 33. 2.5 V or 4.096 V Internal Reference Connection

Rev. E | Page 23 of 35

AD7682/AD7689

External Reference and Internal Buffer

For improved drift performance, an external reference can be

used with the internal buffer, as shown in Figure 34. The

external source is connected to REFIN, the input to the on-chip unity-gain buffer, and the output is produced on the REF pin.

An external reference can be used with the internal buffer with

or without the temperature sensor enabled. Refer to Table 11 for

register details. With the buffer enabled, the gain is unity and is limited to an input/output of VDD = −0.2 V; however, the maximum voltage allowable must be ≤(VDD − 0.5 V).

The internal reference buffer is useful in multiconverter applications because a buffer is typically required in these applications. In addition, a low power reference can be used because the internal buffer provides the necessary performance to drive the SAR architecture of the AD7682 / AD7689 .

REF SOURCE

≤ (VDD – 0.5V)

10µF 100nF

REF REFIN

AD7682/

AD7689

TEMP

GND

Figure 34. External Reference Using Internal Buffer

External Reference

In any of the six voltage reference schemes, an external reference can be connected directly on the REF pin as shown in

Figure 35 because the output impedance of REF is >5 kΩ. To

reduce power consumption, power down the reference and

buffer. Refer to Table 11 for register details. For improved drift

performance, an external reference such as the ADR43x or

ADR44x is recommended.

10µF

REF

REF SOURCE

0.5V < REF < (VDD + 0.3V)

NO CONNECTION

REQUIRED

REFIN

AD7682/

AD7689

TEMP

GND

Figure 35.External Reference

Note that the best SNR is achieved with a 5 V external reference as the internal reference is limited to 4.096 V. The SNR degradation is as follows:

SNR

LOSS

=

20 log

4 .

096

5

Rev. E | Page 24 of 35

Data Sheet

Reference Decoupling

Whether using an internal or external reference, the AD7682 /

AD7689 voltage reference output/input, REF, has a dynamic input impedance and must be driven by a low impedance source with efficient decoupling between the REF and GND pins. This decoupling depends on the choice of the voltage reference but usually consists of a low ESR capacitor connected to REF and GND with minimum parasitic inductance. A 10 µF

(X5R, 1206 size) ceramic chip capacitor is appropriate when using the internal reference, the ADR43x / ADR44x external reference, or a low impedance buffer such as the AD8031 or the

AD8605 .

The placement of the reference decoupling capacitor is also important to the performance of the AD7682 / AD7689 , as

explained in the Layout section. Mount the decoupling capacitor

with a thick PCB trace on the same side as the ADC at the REF pin. The GND must also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias.

If desired, smaller reference decoupling capacitor values down to 2.2 µF can be used with a minimal impact on performance, especially on DNL.

Regardless, there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nF) between the REF and GND pins.

For applications that use multiple AD7682 / AD7689 devices or other PulSAR devices, it is more effective to use the internal reference buffer to buffer the external reference voltage, thus reducing SAR conversion crosstalk.

The voltage reference temperature coefficient (TC) directly impacts full scale; therefore, in applications where full-scale accuracy matters, care must be taken with the TC. For instance, a ±10 ppm/°C TC of the reference changes full scale by

±1 LSB/°C.

Data Sheet

POWER SUPPLY

The AD7682 / AD7689 use two power supply pins: an analog and digital core supply (VDD), and a digital input/output interface supply (VIO). VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the

VIO and VDD pins can be tied together. The AD7682 / AD7689 are independent of power supply sequencing between VIO and

VDD. Additionally, they are very insensitive to power supply

variations over a wide frequency range, as shown in Figure 36.

75

50

45

40

35

70

65

60

55

30

1 10 100

FREQUENCY (kHz)

1k 10k

Figure 36. PSRR vs. Frequency

The AD7682 / AD7689 power down automatically at the end of each conversion phase; therefore, the operating currents and power scale linearly with the sampling rate. This makes the device ideal for low sampling rates (even of a few hertz), and low battery-powered applications.

10,000

1000 VDD = 5V, INTERNAL REF

100

10

1

0.1

0.010

VDD = 5V, EXTERNAL REF

VDD = 2.5V, EXTERNAL REF

VIO

0.001

10 100 1k 10k

SAMPLING RATE (SPS)

100k

Figure 37. Operating Currents vs. Sampling Rate

1M

AD7682/AD7689

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7682 / AD7689 , with their low operating current, can be supplied directly using an

external reference circuit like the one shown in Figure 38.

The reference line can be driven by

• The system power supply directly.

• A reference voltage with enough current output capability, such as the ADR43x / ADR44x.

• A reference buffer, such as the

AD8605 , which can also

filter the system power supply, as shown in Figure 38.

5V

5V

5V

10kΩ

1µF

AD8605

10µF

1

10

1µF

0.1µF 0.1µF

REF VDD

AD7689

VIO

1

OPTIONAL REFERENCE BUFFERAND FILTER.

Figure 38. Example of an Application Circuit

Rev. E | Page 25 of 35

AD7682/AD7689

DIGITAL INTERFACE

The AD7682 / AD7689 use a simple 4-wire interface and are compatible with SPI, MICROWIRE™, QSPI™, digital hosts, and

DSPs (for example, Blackfin® ADSP-BF53x, SHARC®, ADSP-

219x, and ADSP-218x).

The interface uses the CNV, DIN, SCK, and SDO signals and allows CNV, which initiates the conversion, to be independent of the readback timing. This is useful in low jitter sampling or simultaneous sampling applications.

A 14-bit register, CFG[13:0], is used to configure the ADC for the channel to be converted, the reference selection, and other

components, which are detailed in the Configuration Register,

CFG, section.

When CNV is low, reading/writing can occur during conversion, acquisition, and spanning conversion (acquisition plus conversion). The CFG word is updated on the first 14 SCK rising edges, and conversion results are output on the first 15

(or 16, if busy mode is selected) SCK falling edges. If the CFG readback is enabled, an additional 14 SCK falling edges are required to output the CFG word associated with the conversion results with the CFG MSB following the LSB of the conversion result.

A discontinuous SCK is recommended because the device is selected with CNV low, and SCK activity begins to write a new configuration word and clock out data.

The timing diagrams indicate digital activity (SCK, CNV, DIN, and SDO) during the conversion. However, due to the possibility of performance degradation, digital activity occurs only prior to the safe data reading/writing time, t

DATA

, because the AD7682 / AD7689 provide error correction circuitry that can correct for an incorrect bit during this time. From t

DATA

to t

CONV

, there is no error correction, and conversion results may be corrupted. Configure the AD7682 / AD7689 and initiate the busy indicator (if desired) prior to t

DATA

. It is also possible to corrupt the sample by having SCK or DIN transitions near the sampling instant. Therefore, it is recommended to keep the digital pins quiet for approximately 20 ns before and 10 ns after the rising edge of CNV, using a discontinuous SCK whenever possible to avoid any potential performance degradation.

READING/WRITING DURING CONVERSION,

FAST HOSTS

When reading/writing during conversion (n), conversion results are for the previous (n − 1) conversion, and writing the

CFG register is for the next (n + 1) acquisition and conversion.

After the CNV is brought high to initiate conversion, it must be brought low again to allow reading/writing during conversion.

Reading/writing must only occur up to t

DATA

and, because this time is limited, the host must use a fast SCK.

Data Sheet

The SCK frequency required is calculated by

f

SCK

Number

_

SCK t

DATA

_

Edges

The time between t

DATA

and t

CONV

is a safe time when digital activity must not occur, or sensitive bit decisions may be corrupt.

READING/WRITING AFTER CONVERSION, ANY

SPEED HOSTS

When reading/writing after conversion, or during acquisition

(n), conversion results are for the previous (n − 1) conversion, and writing is for the (n + 1) acquisition.

For the maximum throughput, the only time restriction is that the reading/writing take place during the t

ACQ

(minimum) time.

For slow throughputs, the time restriction is dictated by the throughput required by the user, and the host is free to run at any speed. Thus for slow hosts, data access must take place during the acquisition phase.

READING/WRITING SPANNING CONVERSION, ANY

SPEED HOST

When reading/writing spanning conversion, the data access starts at the current acquisition (n) and spans into the conversion (n). Conversion results are for the previous (n − 1) conversion, and writing the CFG register is for the next (n + 1) acquisition and conversion.

Similar to reading/writing during conversion, reading/writing must only occur up to t

DATA

. For the maximum throughput, the only time restriction is that reading/writing take place during the t

ACQ

+ t

DATA

time.

For slow throughputs, the time restriction is dictated by the required throughput, and the host is free to run at any speed.

Similar to reading/writing during acquisition, for slow hosts, the data access must take place during the acquisition phase with additional time into the conversion.

Data access spanning conversion requires the CNV to be driven high to initiate a new conversion, and data access is not allowed when CNV is high. Therefore, the host must perform two bursts of data access when using this method.

CONFIGURATION REGISTER, CFG

The AD7682 / AD7689 use a 14-bit configuration register

(CFG[13:0]), as detailed in Table 11, to configure the inputs, the

channel to be converted, the one-pole filter bandwidth, the reference, and the channel sequencer. The CFG register is latched (MSB first) on DIN with 14 SCK rising edges. The

CFG update is edge dependent, allowing for asynchronous or synchronous hosts.

Rev. E | Page 26 of 35

Data Sheet

The register can be written to during conversion, during acquisition, or spanning acquisition/conversion, and is updated at the end of conversion, t

CONV

(maximum). There is always a one deep delay when writing the CFG register. At power-up, the

CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions

(CFG[13:0] = 0x3FFF). This sets the AD7682 / AD7689 for the following:

13

CFG

12

INCC

11

INCC

10

INCC

9

INx

8

INx

7

INx

AD7682/AD7689

• IN[7:0] unipolar referenced to GND, sequenced in order.

• Full bandwidth for a one-pole filter.

• Internal reference/temperature sensor disabled, buffer enabled.

• Enables the internal sequencer.

• No readback of the CFG register.

Table 11 summarizes the configuration register bit details. See

the Theory of Operation section for more details.

6

BW

5

REF

4

REF

3

REF

2

SEQ

1

SEQ

0

RB

[2:1]

[0]

[6]

[5:3]

Table 11. Configuration Register Description

Bit(s) Name Description

[13] CFG Configuration update.

0 = keep current configuration settings.

[12:10] INCC Input channel configuration. Selection of pseudo bipolar, pseudo differential, pairs, single-ended, or temperature sensor.

Refer to the Input Configurations section.

1 = overwrite contents of register.

Bit 12

0

0

0

Bit 11

0

1

1

Bit 10

X 1

0

1

Function

Bipolar differential pairs; INx− referenced to V

REF

Bipolar; INx referenced to COM = V

Temperature sensor.

REF

/2 ± 0.1 V.

/2 ± 0.1 V.

1

1

1

0

1

1

X 1

0

1

Unipolar differential pairs; INx− referenced to GND ± 0.1 V.

Unipolar, INx referenced to COM = GND ± 0.1 V.

Unipolar, INx referenced to GND.

[9:7] INx

SEQ

RB

BW

REF

Input channel selection in binary fashion.

AD7682 AD7689

Bit 9

X 1

X

1

X 1

X 1

1

1

Bit 8

0

0

0

1

Bit 7

0

1

Channel Bit 9

IN0 0

IN1 0

IN2

IN3

1

Bit 8

0

0

1

Bit 7

0

1

1

Channel

IN0

IN1

IN7

Select bandwidth for low-pass filter. Refer to the Selectable Low-Pass Filter section.

0 = ¼ of BW, uses an additional series resistor to further bandwidth limit the noise. Maximum throughput must be reduced to ¼.

1 = full BW.

Reference/buffer selection. Selection of internal, external, external buffered, and enabling of the on-chip temperature sensor.

Refer to the Voltage Reference Output/Input section.

1

1

0

0

Bit 5

0

0

1

1

1

1

Bit 4

0

0

0

1

0

1

Bit 3

0

1

Function

Internal reference, REF = 2.5 V output, temperature enabled.

Internal reference, REF = 4.096 V output, temperature enabled.

External reference, temperature enabled.

External reference, internal buffer, temperature enabled.

External reference, temperature disabled.

External reference, internal buffer, temperature disabled.

Channel sequencer. Allows for scanning channels in an IN0 to IN[7:0] fashion. Refer to the Channel Sequencer section.

0

1

Bit 2

0

1

Bit 1

0

1

0

1

Function

Disable sequencer.

Update configuration during sequence.

Scan IN0 to IN[7:0] (set in CFG[9:7]), then temperature.

Scan IN0 to IN[7:0] (set in CFG[9:7]).

Read back the CFG register.

0 = read back current configuration at end of data.

1 = do not read back contents of configuration.

1 X means don’t care.

Rev. E | Page 27 of 35

AD7682/AD7689 Data Sheet

GENERAL TIMING WITHOUT A BUSY INDICATOR

Figure 39 details the timing for all three modes: read/write

during conversion (RDC), read/write after conversion (RAC), and read/write spanning conversion (RSC). Note that the gating item for both CFG and data readback is at the end of conversion

(EOC). At EOC, if CNV is high, the busy indicator is disabled.

As detailed in the Digital Interface section, the data access must

occur up to safe data reading/writing time, t

DATA

. If the full CFG word is not written to prior to EOC, it is discarded and the current configuration remains. If the conversion result is not read out fully prior to EOC, it is lost as the ADC updates SDO with the MSB of the current conversion. For detailed timing,

refer to Figure 42 and Figure 43, which depict reading/writing

spanning conversion with all timing details, including setup, hold, and SCK.

PHASE

POWER

UP

SOC t

CYC

EOC t

CONV

CONVERSION

(n – 2) UNDEFINED

ACQUISITION

(n – 1) UNDEFINED t

DATA

CONVERSION

(n – 1) UNDEFINED

EOC

ACQUISITION

(n)

When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − 1.

The SCK can idle high or low depending on the clock polarity

(CPOL) and clock phase (CPHA) settings if SPI is used. A simple solution is to use CPOL = CPHA = 0 as shown in

Figure 39 with SCK idling low.

From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the second EOC; therefore, two dummy conversions are required. If the state machine writes the CFG during the power-up state (RDC shown), the CFG register must be rewritten at the next phase. The first valid data occurs in phase

(n + 1) when the CFG register is written during phase (n − 1).

CONVERSION

(n)

EOC

ACQUISITION

(n + 1)

CONVERSION

(n + 1)

EOC

ACQUISITION

(n + 2)

NOTE 1

CNV

DIN

RDC

SDO

SCK

MSB

XXX

XXX

1

DATA (n – 3)

XXX

16

CFG (n)

1

DATA (n – 2)

XXX

16

NOTE 2

MSB

XXX

CFG (n + 1)

1

DATA (n – 1)

XXX

16

CFG (n + 2)

1

DATA (n)

16

NOTE 1

CNV

DIN

RAC

SDO

SCK

CFG (n)

DATA (n – 2)

XXX

1 16

NOTE 2

NOTE 1

CFG (n + 1)

1

DATA (n – 1)

XXX

16 1

CFG (n + 2)

DATA (n)

16

1

CFG (n + 3)

DATA (n + 1)

CNV

DIN

RSC

SDO

CFG (n)

DATA (n – 2)

XXX

CFG (n)

DATA (n – 2)

XXX

CFG (n + 1)

DATA (n – 1)

XXX

CFG (n + 1)

DATA (n – 1)

XXX

CFG (n + 2)

DATA (n)

CFG (n + 2)

DATA (n)

SCK

1 n n + 1

16 1 n n + 1

16

1 n n + 1

16

1

NOTE 2

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.

2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS

REQUIRED TO RETURN SDO TO HIGH-Z.

Figure 39. General Interface Timing for the AD7682 / AD7689 Without a Busy Indicator

CFG (n + 3)

DATA (n + 1) n

Rev. E | Page 28 of 35

Data Sheet AD7682/AD7689

GENERAL TIMING WITH A BUSY INDICATOR

Figure 40 details the timing for all three modes: RDC, RAC, and

RSC. Note that the gating item for both CFG and data readback is at EOC. The data access must occur up to safe data reading/writing time, t

DATA

. If the full CFG word is not written to prior to EOC, it is discarded and the current configuration remains.

At the EOC, if CNV is low, the busy indicator enables. In addition, to generate the busy indicator properly, the host must assert a minimum of 17 SCK falling edges to return SDO to high impedance because the last bit on SDO remains active.

Unlike the case detailed in the Read/Write Spanning

Conversion Without a Busy Indicator section, if the conversion

result is not read out fully prior to EOC, the last bit clocked out remains. If this bit is low, the busy signal indicator cannot be generated because the busy generation requires either a high impedance or a remaining bit high-to-low transition. A good example of this occurs when an SPI host sends 16 SCKs because

PHASE

POWER

UP t

CONV t

CYC

EOC

START OF CONVERSION

(SOC) t

DATA

CONVERSION

(n – 2) UNDEFINED

ACQUISITION

(n – 1) UNDEFINED

CONVERSION

(n – 1) UNDEFINED

EOC

ACQUISITION

(n)

these are usually limited to 8-bit or 16-bit bursts; therefore, the LSB remains. Because the transition noise of the AD7682 /

AD7689 is 4 LSBs peak-to-peak (or greater), the LSB is low 50% of the time. For this interface, the SPI host needs to burst

24 SCKs, or a QSPI interface can be used and programmed for

17 SCKs.

The SCK can idle high or low depending on the CPOL and

CPHA settings if SPI is used. A simple solution is to use CPOL =

CPHA = 1 (not shown) with SCK idling high.

From power-up, in any read/write mode, the first three conversion results are undefined because a valid CFG does not take place until the second EOC; thus, two dummy conversions are required. Also, if the state machine writes the CFG during the power-up state (RDC shown), the CFG register needs to be rewritten again at the next phase. The first valid data occurs in phase (n + 1) when the CFG register is written during phase

(n − 1).

CONVERSION

(n)

EOC

ACQUISITION

(n + 1)

CONVERSION

(n + 1)

EOC

ACQUISITION

(n + 2)

CNV

DIN

RDC

SDO

SCK

XXX

NOTE 1

CFG (n) CFG (n + 1) CFG (n + 2)

1 17 1 17

NOTE 2

1 17 1

CNV

RAC

DIN

SDO

SCK

NOTE 1

CFG (n) CFG (n + 1) CFG (n + 2)

1

DATA (n)

17 1 17

NOTE 2

1 17

CNV

RSC

DIN

SDO

NOTE 1

CFG (n)

CFG (n + 1) CFG (n + 2)

DATA (n)

SCK

1 n n + 1 17 1 n n + 1 17 1

NOTE 2

NOTES

1. CNV MUST BE LOW PRIOR TO THE END OF CONVERSION (EOC) TO GENERATE THE BUSY INDICATOR.

2. A TOTAL OF 17 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,

A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

n

Figure 40. General Interface Timing for the AD7682 / AD7689 With a Busy Indicator

n + 1

DATA (n)

17

17

1

CFG (n + 3)

DATA (n + 1)

1

CFG (n + 3)

DATA (n + 1)

Rev. E | Page 29 of 35

AD7682/AD7689 Data Sheet

CHANNEL SEQUENCER

The AD7682 / AD7689 include a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced.

The sequencer starts with IN0 and finishes with IN[7:0] set in

CFG[9:7]. For paired channels, the channels are paired depending on the last channel set in CFG[9:7]. Note that in sequencer mode, the channels are always paired with the positive input on the even channels (IN0, IN2, IN4, and IN6), and with the negative input on the odd channels (IN1, IN3, IN5, and IN7).

For example, setting CFG[9:7] = 110 or 111 scans all pairs with the positive inputs dedicated to IN0, IN2, IN4, and IN6.

CFG[2:1] are used to enable the sequencer. After the CFG register is updated, DIN must be held low while reading data out for Bit 13, or the CFG register begins updating again.

Conversion Without a Busy Indicator section for more details.

The sequencer can also be used with the busy indicator and

details for these timings can be found in the General Timing

with a Busy Indicator section and the Read/Write Spanning

Conversion with a Busy Indicator section.

For sequencer operation, the CFG register must be set during the (n − 1) phase after power-up. On phase (n), the sequencer setting takes place and acquires IN0. The first valid conversion result is available at phase (n + 1). After the last channel set in

CFG[9:7] is converted, the internal temperature sensor data is output (if enabled), followed by acquisition of IN0.

Examples

With all channels configured for unipolar mode to GND, including the internal temperature sensor, the sequence scans in the following order:

IN0, IN1, IN2, IN3, IN4, IN5, IN6, IN7, TEMP, IN0, IN1, IN2…

Note that while operating in a sequence, some bits of the CFG register can be changed. However, if changing CFG[11] (paired or single channel) or CFG[9:7] (last channel in sequence), the sequence reinitializes and converts IN0 (or IN0/IN1 pairs) after the CFG register is updated.

Figure 41 details the timing for all three modes without a busy

indicator. Refer to the Read/Write Spanning Conversion

Without a Busy Indicator section and the Read/Write Spanning

SOC t

CYC

EOC EOC

POWER

UP t

CONV t

DATA

PHASE

CONVERSION

(n – 2) UNDEFINED

ACQUISITION

(n – 1) UNDEFINED

CONVERSION

(n – 1) UNDEFINED

ACQUISITION

(n), IN0

For paired channels with the internal temperature sensor enabled, the sequencer scans in the following order:

IN0, IN2, IN4, IN6, TEMP, IN0…

Note that IN1, IN3, IN5, and IN7 are referenced to a GND sense or V

REF

/2, as detailed in the Input Configurations section.

CONVERSION

(n), IN0

EOC

ACQUISITION

(n + 1), IN1

CONVERSION

(n + 1), IN1

EOC

ACQUISITION

(n + 2), IN2

NOTE 1

CNV

DIN

RDC

SDO

SCK

MSB

XXX

XXX

1

DATA (n – 3)

XXX

16

2

CFG (n)

1

DATA (n – 2)

XXX

16

NOTE 2

MSB

XXX

1

DATA (n – 1)

XXX

16 1

DATA IN0

16

CNV

DIN

RAC

SDO

SCK

CFG (n)

1

DATA (n – 2)

XXX

16

NOTE 2

1

DATA (n – 1)

XXX

16 1

DATA IN0

16

CNV

DIN

RSC

SDO

CFG (n)

DATA (n – 2)

XXX

CFG (n)

DATA (n – 2)

XXX

DATA (n – 1)

XXX

DATA (n – 1)

XXX

DATA IN0

SCK 1 n n + 1

16 1 n n + 1

16

NOTE 2

NOTES

1. CNV MUST BE HIGH PRIOR TO THE END OF CONVERSION (EOC) TO AVOID THE BUSY INDICATOR.

2. A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED,

A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z.

1

Figure 41. General Channel Sequencer Timing Without a Busy Indicator

n n + 1

DATA IN0

16

1

DATA IN1

1

DATA IN1 n

Rev. E | Page 30 of 35

Data Sheet

READ/WRITE SPANNING CONVERSION WITHOUT

A BUSY INDICATOR

This mode is used when the AD7682 / AD7689 are connected to any host using an SPI, serial port, or FPGA. The connection

diagram is shown in Figure 42, and the corresponding timing is given in Figure 43. For the SPI, the host must use CPHA =

CPOL = 0. Reading/writing spanning conversion is shown,

which covers all three modes detailed in the Digital Interface

section. For this mode, the host must generate the data transfer based on the conversion time. For an interrupt driven transfer

that uses a busy indicator, refer to the Read/Write Spanning

Conversion with a Busy Indicator section.

A rising edge on CNV initiates a conversion, forces SDO to high impedance, and ignores data present on DIN. After a conversion initiates, it continues until completion, irrespective of the state of CNV. CNV must be returned high before the safe data transfer time (t

DATA

), and held high beyond the conversion time (t

CONV

) to avoid generation of the busy signal indicator.

After the conversion is complete, the AD7682 / AD7689 enter the acquisition phase and power-down. When the host brings

CNV low after t

CONV

(maximum), the MSB enables on SDO. The

AD7682/

AD7689

CNV

SDO

DIN

SCK

AD7682/AD7689

host also must enable the MSB of the CFG register at this time

(if necessary) to begin the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG, and the first 15 SCK falling edges clock out the conversion results starting with

MSB − 1. The restriction for both configuring and reading is that they both must occur before the t

DATA

time of the next conversion elapses. All 14 bits of CFG[13:0] must be written or they are ignored. In addition, if the 16-bit conversion result is not read back before t

DATA

elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the 16 th (or 30 th ) SCK falling edge, or when

CNV goes high (whichever occurs first), SDO returns to high impedance.

If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 30 SCK falling edges is required to return SDO to high impedance if this is enabled.

DIGITAL HOST

SS

MISO

MOSI

SCK

CNV t

DATA

> t

CONV t

CONV

FOR SPI USE CPHA = 0, CPOL = 0.

Figure 42. Connection Diagram for the AD7682 / AD7689 Without a Busy Indicator

t

CYC t

DATA t

CONV

EOC t

CNVH

RETURN CNV HIGH

FOR NO BUSY t

ACQ

EOC

RETURN CNV HIGH

FOR NO BUSY

ACQUISITION

(n - 1) t

CONVERSION (n – 1) t

SCK

SCKH

(QUIET

TIME)

UPDATE (n)

CFG/SDO

ACQUISITION (n) CONVERSION (n)

SCK

14 15

16/

30

1

2 14 15

SEE NOTE

16/

30 t

SCKL t

CLSCK

DIN

SDO t

EN

CFG

LSB

X

END CFG (n)

X

LSB t

EN

CFG

MSB t

SDIN t

HDIN

BEGIN CFG (n + 1) t

HSDO t

DSDO

MSB t

EN

CFG

LSB

X

END CFG (n + 1)

X

LSB

SEE NOTE t

DIS t

DIS

END DATA (n – 2) t

DIS

BEGIN DATA (n – 1) t

DIS

END DATA (n – 1)

NOTES

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF

15 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.

Figure 43. Serial Interface Timing for the AD7682 / AD7689 Without a Busy Indicator

(QUIET

TIME)

UPDATE (n + 1)

CFG/SDO

Rev. E | Page 31 of 35

AD7682/AD7689

READ/WRITE SPANNING CONVERSION WITH A

BUSY INDICATOR

This mode is used when the AD7682 / AD7689 are connected to any host using an SPI, serial port, or FPGA with an interrupt

input. The connection diagram is shown in Figure 44, and the corresponding timing is given in Figure 45. For the SPI, the host

must use CPHA = CPOL = 1. Reading/writing spanning conversion is shown, which covers all three modes detailed in the

Digital Interface section.

A rising edge on CNV initiates a conversion, ignores data present on DIN, and forces SDO to high impedance. After the conversion initiates, it continues until completion, irrespective of the state of CNV. CNV must be returned low before the safe data transfer time (t

DATA

), and then held low beyond the conversion time (t

CONV

) to generate the busy signal indicator.

When the conversion is complete, SDO transitions from high impedance to low (data ready), and with a pull-up to VIO, SDO can be used to interrupt the host to begin data transfer.

After the conversion is complete, the AD7682 / AD7689 enter the acquisition phase and power-down. The host must enable the MSB of the CFG register at this time (if necessary) to begin

VIO

AD7682/

AD7689

SDO t

DATA

CNV

DIN

SCK

Data Sheet

the CFG update. While CNV is low, both a CFG update and a data readback take place. The first 14 SCK rising edges are used to update the CFG register, and the first 16 SCK falling edges clock out the conversion results starting with the MSB. The restriction for both configuring and reading is that they both occur before the t

DATA

time elapses for the next conversion. All

14 bits of CFG[13:0] must be written or they are ignored. If the

16-bit conversion result is not read back before t

DATA

elapses, it is lost.

The SDO data is valid on both SCK edges. Although the rising edge can capture the data, a digital host using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time. After the optional 17 th (or 31 st ) SCK falling edge,

SDO returns to high impedance. If the optional SCK falling edge is not used, the busy feature cannot be detected, as

described in the General Timing with a Busy Indicator section.

If CFG readback is enabled, the CFG register associated with the conversion result is read back MSB first following the LSB of the conversion result. A total of 31 SCK falling edges is required to return SDO to high impedance if this is enabled.

DIGITAL HOST

MISO

IRQ

SS

MOSI

SCK

FOR SPI USE CPHA = 1, CPOL = 1.

Figure 44. Connection Diagram for the AD7682 / AD7689 with a Busy Indicator

t

CYC t

ACQ t

DATA t

CONV t

CNVH

CNV

CONVERSION

(n – 1) t

SCKH

CONVERSION (n – 1) t

SCK

(QUIET

TIME)

UPDATE (n)

CFG/SDO

ACQUISITION (n)

SCK

DIN

SDO t

SCKL

15

X

END CFG (n)

16

X

LSB

+ 1

END DATA (n – 2)

17/

31

X

LSB t

DIS

1 2

CFG

MSB t

HDIN t

SDIN

CFG

MSB –1

BEIGN CFG (n + 1) t

HSDO t

DSDO

MSB

MSB

– 1

BEGIN DATA (n – 1) t

EN

NOTES:

1. THE LSB IS FOR CONVERSION RESULTS OR THE CONFIGURATION REGISTER CFG (n – 1) IF

16 SCK FALLING EDGES = LSB OF CONVERSION RESULTS.

30 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER.

ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE.

OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW.

t

EN t

DIS

CONVERSION (n)

15

SEE NOTE

16

17/

31

(QUIET

TIME)

ACQUISITION

(n + 1)

UPDATE (n + 1)

CFG/SDO

X

X

X

END CFG (n + 1)

LSB

+ 1

END DATA (n – 1)

LSB

SEE NOTE t

DIS t

EN

Figure 45. Serial Interface Timing for the AD7682 / AD7689 with a Busy Indicator

Rev. E | Page 32 of 35

Data Sheet

APPLICATIONS INFORMATION

LAYOUT

The printed circuit board (PCB) that houses the AD7682 /

AD7689 must be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pin configuration of the AD7682 / AD7689 , with all its analog signals on the left side and all its digital signals on the right side, eases this task.

Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the

AD7682 / AD7689 is used as a shield. Fast switching signals, such as CNV or clocks, must not run near analog signal paths. Avoid crossover of digital and analog signals.

Use at least one ground plane. It can be common or split between the digital and analog sections. In the latter case, join the planes underneath the AD7682 / AD7689 .

The AD7682 / AD7689 voltage reference input, REF, has a dynamic input impedance and must be decoupled with minimal parasitic inductances. This is achieved by placing the reference decoupling ceramic capacitor close to (ideally, right up against)

AD7682/AD7689

the REF and GND pins and connecting them with wide, low impedance traces.

Finally, the power supplies of the AD7682 / AD7689 (VDD and

VIO) must be decoupled with ceramic capacitors, typically

100 nF, placed close to the AD7682 / AD7689 , and connected using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines.

The AN-617 Application Note has information on PCB layout and assembly. This information is particularly important for guiding customers who do not have experience with WLCSP.

EVALUATING THE

AD7682

/

AD7689

PERFORMANCE

Other recommended layouts for the AD7682 / AD7689 are outlined in the documentation of the evaluation board for the

AD7682 / AD7689 ( EVAL-AD7682EDZ / EVAL-AD7689EDZ ).

The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the converter and evaluation development data capture board, EVAL-CED1Z .

Rev. E | Page 33 of 35

AD7682/AD7689

OUTLINE DIMENSIONS

PIN 1

INDICATOR

0.80

0.75

0.70

SEATING

PLANE

4.10

4.00 SQ

3.90

TOP VIEW

0.50

BSC

15

16

0.30

0.25

0.20

EXPOSED

PAD

20

1

PIN 1

INDICATOR

2.65

2.50 SQ

2.35

11

10

BOTTOM VIEW

6

5

0.50

0.40

0.30

0.25 MIN

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.20 REF

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COMPLIANT

TO JEDEC STANDARDS MO-220-WGGD.

Figure 46. 20-Lead Lead Frame Chip Scale Package (LFCSP_WQ)

4 mm × 4 mm Body, Very Very Thin Quad

(CP-20-10)

Dimensions shown in millimeters

BALL A1

IDENTIFIER

0.560

0.500

0.440

SEATING

PLANE

2.430

2.390 SQ

2.350

0.433

REF

0.50 REF

9 8

BOTTOM VIEW

(BALL SIDE UP)

7 6 5 4 3 2 1

0.50 REF

A

D

E

B

C

TOP VIEW

(BALL SIDE DOWN)

SIDE VIEW

0.300

0.260

0.220

0.25 REF

0.330

0.300

0.270

COPLANARITY

0.05

0.230

0.200

0.170

Figure 47. 20-Ball Wafer Level Chip Scale Package (WLCSP)

(CB-20-12)

Dimensions shown in millimeters

Data Sheet

Rev. E | Page 34 of 35

Data Sheet AD7682/AD7689

ORDERING GUIDE

Model 1, 2

AD7682BCPZ

AD7682BCPZRL7

AD7689ACPZ

AD7689ACPZRL7

AD7689BCPZ

AD7689BCPZRL7

AD7689BCBZ-RL7

Integral

Nonlinearity

±2 LSB max

±2 LSB max

±6 LSB max

±6 LSB max

±2 LSB max

±2 LSB max

±2 LSB max

No Missing

Code

16 bits

16 bits

15 bits

15 bits

16 bits

16 bits

16 bits

Temperature

Range

−40°C to +85°C

Package Description

−40°C to +85°C 20-Lead LFCSP_WQ

−40°C to +85°C 20-Lead LFCSP_WQ

−40°C to +85°C 20-Lead LFCSP_WQ

−40°C to +85°C 20-Lead LFCSP_WQ

−40°C to +85°C 20-Lead LFCSP_WQ

−40°C to +85°C 20-Lead LFCSP_WQ

20-Ball WLCSP

Package

Option

CP-20-10

Ordering

Quantity

CP-20-10 Tray, 490

Reel, 1,500

CP-20-10 Tray, 490

CP-20-10 Reel, 1,500

CP-20-10 Tray, 490

CP-20-10 Reel, 1,500

CB-20-12

EVAL-AD7682EDZ

EVAL-AD7689EDZ

EVAL-CED1Z Converter Evaluation and

Development Board

1 Z = RoHS Compliant Part.

2 The EVAL-CED1Z controller board allows a PC to control and communicate with all Analog Devices evaluation boards whose model numbers end in ED.

Reel, 1,500

©2008–2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D07353-0-1/15(E)

Rev. E | Page 35 of 35

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