AN11226 TTL bias switching Rev. 01 — 10 August 2012 Application note

AN11226 TTL bias switching Rev. 01 — 10 August 2012 Application note
AN11226
TTL bias switching
Rev. 01 — 10 August 2012
Application note
Document information
Info
Content
Keywords
BLA6H0912-500, gate switching, IFF transponder, LDMOS transistor,
high-power, FET, MTF
Abstract
Modern Identification Friend or Foe (IFF) systems require high dynamic
range transmit and receive paths and the ability to transmit in excess of
1 kW of power. These requirements on the transmit path require the use of
amplifier modules with multiple stages operating near to Class A or heavily
biased Class AB. To increase the performance of such systems a gate
bias switching circuit is proposed.
AN11226
NXP Semiconductors
TTL bias switching
Revision history
Rev
Date
Description
01
20120810
Initial version
Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
AN11226
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
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TTL bias switching
1. Introduction
Modern Identification Friend or Foe (IFF) systems require high dynamic range transmit
and receive paths and the ability to transmit in excess of 1 kW of power. These
requirements on the transmit path require the use of amplifier modules with multiple
stages operating near to Class A or heavily biased Class AB.
Amplifiers that draw high bias current have an advantage in that they operate in the linear
region but also have two main disadvantages. First the device is less efficient so requires
a higher amount of prime power, costing more to operate the system. The second concern
is that as a result of drawing higher bias current, the devices have an elevated junction
temperature and usually produce a lower peak power which decreases the linear range of
the amplifier and reduces the operating lifetime of the transistor.
2. Solution
IFF transponders have several different timing schemes but the basic building blocks are
of short, high-powered pulses that operate at low long-term duty cycles <10 %. The
presence and timing of these pulses are known, as they are generated by the IFF system
in response either to a received request or an initiation by the pilot. As information about
these pulses is known, a transponder system can generate a trigger that could “gate” or
“window” the voltage that is used to bias the transistor. The term “window” is used here to
avoid confusion with the term “gate voltage” which is used later.
The described approach deals with enhancement mode Laterally Diffused Metal Oxide
Semiconductor (LDMOS) transistors but this technique can be used for both depletion and
enhancement mode FETs.
3. Requirements
The minimum pulse width used in IFF systems is 0.8 s and with spectral mask concerns
there are finite rise and fall times formed on the edges of the pulsed RF waveform. These
rise and fall times are in the order of 50 ns at either end of the pulse. To maximize the
benefit of the gated bias voltage, if possible, gate each pulse as tightly as possible with
respect to the edges of the RF pulse itself.
In reality, the circuitry needs time to accept a signal and set up a stable voltage on the
transistor gate. For this implementation the “Window” around the bias control is set up and
reaches steady state in maximum 75 ns from when the control signal is detected; see
Figure 1.
AN11226
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
3 of 13
AN11226
NXP Semiconductors
TTL bias switching
aaa-004043
1.5
normalized
linear envelope
1
(1)
0.5
(2)
0
-0.5
0
200
400
600
800
1000
ns
(1) RF envelope.
(2) Bias gate.
Fig 1.
Ideal bias voltage gate timing; basic pulse shape 50 ns rise and fall times
4. LDMOS Bias conditions
LDMOS transistors are enhancement mode devices which require a positive voltage on
the gate of the device in order to bias them. High-power amplifier transistors are
considered here as they benefit most from windowing the gate voltage, but there are
benefits to gating each device in the amplifier chain. Consider the BLA6H0912-500 which
is a 500 W LDMOS device that can be biased as a linear amplifier giving the response
shown in Figure 2.
AN11226
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
4 of 13
AN11226
NXP Semiconductors
TTL bias switching
aaa-004044
30
Gain
(dB)
26
(1)
(2)
(3)
22
18
14
10
20
30
40
50
60
Po (dBm)
(1) 4 C.
(2) 22 C.
(3) 80 C.
Amplifier biased to 3 A minimum, 35 dB dynamic range; VDD = 48 V; pulse 1s, 2 %.
Fig 2.
BLA6H0912-500 linear response
In order to get a wide dynamic range from a device with this power capability, a quiescent
current (IDq) of 3 A is needed. The BLA6H0912-500 utilizes NXP Semiconductor
high-voltage LDMOS technology, with a drain voltage (VDS) of 50 V which results in 150 W
of quiescent power required before there is any RF “work” done.
If we assume that (j-c) taken from data sheet BLA6H0912-500 for a 2400 s pulse is
basically DC (or equal to the thermal time constant of the device) then the rise in junction
temperature for this static DC condition is 30 C. If this constant bias is reduced, the
junction temperature is lower which causes an increase in MTF based on the curve in
Figure 3. In the case where this assumption is not valid, the situation becomes more
troublesome as (j-c) increases and higher junction temperatures occur, further
highlighting the need for some dynamic control of the gate voltage.
Table 1.
AN11226
Application note
BLA6H0912-500 thermal impedance data
Symbol
Parameter
Conditions
Zth(j-c)
transient thermal impedance from
junction to case
Tcase = 85 C; PL = 450 W
tp = 32 s;  = 2 %
Unit
0.03
K/W
tp = 128 s;  = 10 %
0.08
K/W
tp = 2400 s;  = 6.4 %
0.2
K/W
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
Typ
© NXP B.V. 2012. All rights reserved.
5 of 13
AN11226
NXP Semiconductors
TTL bias switching
aaa-004045
1011
t50 % × lDS2
(hrs × A2)
1010
109
108
107
106
105
80
120
160
200
240
Tj (°C)
Fig 3.
MTF data BLA6H0912-500
IFF waveforms have very low duty cycles in the order of 2 %. In this case the ideal power
reduction using this windowing technique, given square pulses and zero setup and hold
times, would result in the quiescent power consumption being:
150  0.02 = 3 WAVG
The DC jc is not used here but the lower pulsed value of 0.03 K/W taken from the data
sheet BLA6H0912-500 is used and the resulting temperature is:
Trise = 3  0.03 = 0.1 C
This bias voltage is usually supplied from a low impedance bias controller similar to that
described in NXP Semiconductors Report R_10032: LDMOS bias module CA-330-11.
This bias voltage is commonly fed to the device through a shorted quarter wave section
line that has been optimized for the design frequency. This bias line is an obvious location
to insert the switch, which will either apply the proper gate voltage to the transistor, or pull
it to ground through a resistor to drain the gate voltage on the falling edge.
5. Switch circuit
There are many fast switches on the market today that can meet the requirement of both
switching and being stable within 75 ns. An analog switch, the Vishay DG4599 with a
minimum switching speed of 30 ns was chosen which allows the switch to react fast
enough for any conditioning if necessary.
AN11226
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
6 of 13
AN11226
NXP Semiconductors
TTL bias switching
SC-70
IN
1
6
NO (Source1)
V+
2
5
COM
GND
3
4
NC (Source2)
Top View
Device Marking: 4J
Fig 4.
aaa-004046
Analog switch Vishay DG4599
Table 2.
Truth table
Logic
NC
NO
0[1]
ON
OFF
1[2]
OFF
ON
[1]
Logic “0”  0.8 V
[2]
Logic “1”  2.4 V.
The Vishay DG4599 accepts a TTL waveform as defined in Table 2 (taken from the data
sheet DG4599). It requires a single 5 V supply and has a very low current draw of 1 A. A
simple solution to power this switch is to apply the 8 V regulator voltage on the LDMOS
bias module R_10032 to a high impedance resistor divider to generate the required
voltage.
Figure 5 shows the schematic diagram of the switching circuit. When a logic 1 is received,
the switch presents the transistor with the correct bias voltage generated by the LDMOS
bias module. When a logic 0 is received, the switch presents a 1.5  impedance to the
bias network to drain the voltage on the gate of the transistor. If the TTL signal is removed
and the input is left floating, a 10 k pull-down resistor (R3) ensures that the amplifier is
not biased.
Alternatively if the failure condition was that the amplifier remained in the “on” mode, R3
could be pulled up to the VDD of the switch. This would result in an increased junction
temperature as earlier mentioned, but if this were a military application that failure mode
would be preferable, considering that an incorrect response could instigate a missile
launch.
AN11226
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
7 of 13
AN11226
NXP Semiconductors
TTL bias switching
C2
gate voltage from
LDMOS module
1 nF
TTL source
1
C3
R3
10 kΩ
22 pF
C4
10 nF
C5
U1
IN
V+
R1
+8 V from
LDMOS module
6.2 kΩ
GND
R2
9.1 kΩ
1
100 nF
6
2 DG4599 5
3
4
C1
1 μF
NO
COM
NC
R5
gate voltage
5.1 Ω
R4
1.5 Ω
C6
1000 pF
C1
100 pF
aaa-004047
Fig 5.
Gate voltage switching circuit
Figure 6 and Figure 7 show the respective results for the rising and falling edges during
circuit testing. It can be seen that the switch turns on within 10 ns of receiving the control
input and has an overshoot due to the fast switching time and inductance of the bias feed
lines. Capacitor C1 provides the 100 pF gate bias decoupling required for proper RF
operation and has a minimal effect on the ringing caused by the fast switching. Damped
responses such as this are never ideal so capacitor C6 (1000 pF) is added to the bias line
on the switch side of capacitor C1 to smooth the response. The final switching time is
approximately 60 ns which presents a stable VGS to the amplifier and does not add gate
bias modulation onto the RF pulse.
AN11226
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
8 of 13
AN11226
NXP Semiconductors
TTL bias switching
aaa-004048
3.5
(V)
(1)
(2)
(3)
(4)
2.5
1.5
0.5
-0.5
-50
-10
30
70
110
nSec
(1) Trigger.
(2) No capacitors.
(3) 100 pF.
(4) 1100 pF.
Fig 6.
Rising edge timing
aaa-004049
4
(V)
(1)
(2)
(3)
(4)
2
0
-2
-40
0
40
80
120
nSec
(1) Trigger.
(2) No capacitors.
(3) 100 pF.
(4) 1100 pF.
Fig 7.
Falling edge timing
Figure 8 shows the measured response of the circuit with and without the gate circuit
being gated. The windowed gate response provides 3 % more efficiency than the constant
bias condition and approximately 25 W more power. The measured flange temperature for
the constant bias condition with a cold plate temperature of 24 C was 60 C and the
AN11226
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
9 of 13
AN11226
NXP Semiconductors
TTL bias switching
flange temperature for the windowed bias case was 25 C. Many military applications
have an ambient temperature requirement of +85 C and this 35 C difference results in
an MTF of 4e8 versus 6e9: a reduction factor of 15 times in device lifetime.
aaa-004050
30
60
Gain
(dB)
η
(%)
26
48
(1)
(2)
22
36
(1)
(2)
18
24
14
12
10
0
30
40
50
60
Po (dBm)
(1) Constant bias.
(2) Pulsed bias.
VDD = 48 V; pulse 1s, 2 %.
Fig 8.
AN11226
Application note
Windowed gate voltage as a function of constant bias performance
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
10 of 13
AN11226
NXP Semiconductors
TTL bias switching
aaa-004051
Small switching circuit circled in red.
Fig 9.
BLA6H0912-500 test circuit with switched bias control
6. Conclusion
Modern IFF systems require amplifiers with high linearity and high output power greater
than 1 kW. In order to improve both reliability and dynamic range, a switch can be used to
“window” the gate voltage of the transistor making the amplifier more efficient, providing a
high dynamic range and reducing junction temperatures. Ultimately this leads to better
reliability at higher output powers. Any system that can detect when a signal will be sent
and operates at lower duty cycles can use this technique. There is an added benefit when
this technique is used in pulsed radar applications. In modern radars, windowing the
transmit power amplifiers during a receive operation can reduce the thermal noise that
leaks through the duplexer into the receive path which would otherwise reduce the signal
to noise ratio and limit the sensitivity of the system.
7. Abbreviations
Table 3.
AN11226
Application note
Abbreviations
Acronym
Description
IFF
Identification Friend or Foe
LDMOS
Laterally Diffused Metal-Oxide Semiconductor
MTF
Modulation Transfer Function
TTL
Transistor-Transistor Logic
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
11 of 13
AN11226
NXP Semiconductors
TTL bias switching
8. Legal information
8.1
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
8.2
Disclaimers
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be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
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punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
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contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
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authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
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risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
AN11226
Application note
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
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applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Evaluation products — This product is provided on an “as is” and “with all
faults” basis for evaluation purposes only. NXP Semiconductors, its affiliates
and their suppliers expressly disclaim all warranties, whether express, implied
or statutory, including but not limited to the implied warranties of
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entire risk as to the quality, or arising out of the use or performance, of this
product remains with customer.
In no event shall NXP Semiconductors, its affiliates or their suppliers be liable
to customer for any special, indirect, consequential, punitive or incidental
damages (including without limitation damages for loss of business, business
interruption, loss of use, loss of data or information, and the like) arising out
the use of or inability to use the product, whether or not based on tort
(including negligence), strict liability, breach of contract, breach of warranty or
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Notwithstanding any damages that customer might incur for any reason
whatsoever (including without limitation, all damages referenced above and
all direct or general damages), the entire liability of NXP Semiconductors, its
affiliates and their suppliers and customer’s exclusive remedy for all of the
foregoing shall be limited to actual damages incurred by customer based on
reasonable reliance up to the greater of the amount actually paid by customer
for the product or five dollars (US$5.00). The foregoing limitations, exclusions
and disclaimers shall apply to the maximum extent permitted by applicable
law, even if any remedy fails of its essential purpose.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
8.3
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 10 August 2012
© NXP B.V. 2012. All rights reserved.
12 of 13
AN11226
NXP Semiconductors
TTL bias switching
9. Contents
1
2
3
4
5
6
7
8
8.1
8.2
8.3
9
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
LDMOS Bias conditions . . . . . . . . . . . . . . . . . . 4
Switch circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . 12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 10 August 2012
Document identifier: AN11226
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