4.5-V to 14.5-V Input, 6-A Synchronous Buck, Integrated Power Solution TPS84620 FEATURES DESCRIPTION

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4.5-V to 14.5-V Input, 6-A Synchronous Buck, Integrated Power Solution TPS84620 FEATURES DESCRIPTION | Manualzz

TPS84620 www.ti.com

9 mm × 15 mm × 2.8 mm

SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

4.5-V to 14.5-V Input, 6-A Synchronous Buck, Integrated Power Solution

Check for Samples: TPS84620

1

FEATURES

2

• Complete Integrated Power Solution Allows

Small Footprint, Low-Profile Design

• Efficiencies Up To 96%

• Wide-Output Voltage Adjust

1.2 V to 5.5 V, with 1% Reference Accuracy

• Optional Split Power Rail allows input voltage down to 1.7 V

• Adjustable Switching Frequency

(480 kHz to 780 kHz)

• Synchronizes to an External Clock

• Adjustable Slow-Start

• Output Voltage Sequencing / Tracking

• Power Good Output

• Programmable Undervoltage Lockout (UVLO)

• Output Overcurrent Protection

• Over Temperature Protection

• Pre-bias Output Start-up

• Operating Temperature Range: –40°C to 85°C

• Enhanced Thermal Performance: 13°C/W

• Meets EN55022 Class B Emissions

• For Design Help Including SwitcherPro™ visit http://www.ti.com/tps84620

DESCRIPTION

The TPS84620RUQ is an easy-to-use integrated power solution that combines a 6-A DC/DC converter with power MOSFETs, an inductor, and passives into a low profile, BQFN package. This total power solution allows as few as 3 external components and eliminates the loop compensation and magnetics part selection process.

The 9×15×2.8 mm BQFN package is easy to solder onto a printed circuit board and allows a compact point-of-load design with greater than 90% efficiency and excellent power dissipation with a thermal impedance of 13°C/W junction to ambient. The device delivers the full 6-A rated output current at

85°C ambient temperature without airflow.

The TPS84620 offers the flexibility and the featureset of a discrete point-of-load design and is ideal for powering performance DSPs and FPGAs. Advanced packaging technology afford a robust and reliable power solution compatible with standard QFN mounting and testing techniques.

SIMPLIFIED APPLICATION

PVIN

V

IN

PWRGD

VIN

APPLICATIONS

• Broadband & Communications Infrastructure

• Automated Test and Medical Equipment

• Compact PCI / PCI Express / PXI Express

• DSP and FPGA Point of Load Applications

• High Density Distributed Power Systems

C

IN

TPS84620

VOUT

RT/CLK

SENSE+

INH/UVLO

SS/TR

VADJ

V

OUT

C

OUT

100

95

90

85

80

75

70

65

60

55

50

0

V

OUT

= 3.3 V f

SW

= 630 kHz

STSEL

PGND

AGND

R

SET

UDG-10021

1 2 3

Output Current (A)

4

PV

IN

= V

IN

= 5 V

PV

IN

= V

IN

= 12 V

5 6

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

SwitcherPro is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2010–2012, Texas Instruments Incorporated

TPS84620

SLVSA43D – OCTOBER 2010 – REVISED OCT 2012 www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

For the most current package and ordering information, see the Package Option Addendum at the end of this datasheet, or see the TI website at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1) over operating temperature range (unless otherwise noted)

Input Voltage

Output Voltage

VIN

PVIN

INH/UVLO

VADJ

PWRGD

SS/TR

STSEL

RT/CLK

PH

PH 10ns Transient

V

DIFF

(GND to exposed thermal pad)

Source Current

Sink Current

RT/CLK

PH

PH

PVIN

PWRGD

Operating Junction Temperature

Storage Temperature

Mechanical Shock

Mechanical Vibration

Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted

Mil-STD-883D, Method 2007.2, 20-2000Hz

VALUE

–0.3 to 16

–0.3 to 16

–0.3 to 6

–0.3 to 3

–0.3 to 6

–0.3 to 3

–0.3 to 3

–0.3 to 6

–1 to 20

–3 to 20

–0.2 to 0.2

±100

Current Limit

Current Limit

Current Limit

–0.1 to 5

–40 to 125

(2)

–65 to 150

1500

20

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) See the temperature derating curves in the Typical Characteristics section for thermal information.

°C

°C

G

µA

A

A

A mA

V

V

V

V

V

UNIT

V

V

V

V

V

V

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SLVSA43D – OCTOBER 2010 – REVISED OCT 2012 www.ti.com

THERMAL INFORMATION

θ

JA

θ

JCtop

θ

JB

ψ

JT

ψ

JB

θ

JCbot

THERMAL METRIC

Junction-to-ambient thermal resistance

Junction-to-board thermal resistance

(4)

(2)

Junction-to-case (top) thermal resistance

(3)

Junction-to-top characterization parameter

(1)

(5)

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

(6)

(7)

TPS84620

RUQ47

47 PINS

13

9

6

2.5

5

3.8

UNITS

°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953 .

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ

JT

, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ

JA

, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ

JB

, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θ

JA

, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

Spacer

PACKAGE SPECIFICATIONS

TPS84620

Weight

Flammability Meets UL 94 V-O

MTBF Calculated reliability Per Bellcore TR-332, 50% stress, T

A

= 40°C, ground benign

UNIT

1.26 grams

33.9 MHrs

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ELECTRICAL CHARACTERISTICS

over -40°C to 85°C free-air temperature, PVIN = VIN = 12 V, V

OUT

C

IN1

= 2x 22 µF ceramic, C

IN2

= 68 µF poly-tantalum, C

OUT1

= 1.8 V, I

OUT

= 6A,

= 4x 47 µF ceramic (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

I

OUT

VIN

PVIN

UVLO

V

OUT(adj)

V

OUT

η

I

LIM

Output current

Input bias voltage range

T

A

= 85°C, natural convection

Over I

OUT range

Input switching voltage range Over I

OUT range

VIN = increasing

VIN Undervoltage lockout

VIN = decreasing

Output voltage adjust range

Set-point voltage tolerance

Temperature variation

Over I

OUT range

T

A

= 25°C, I

OUT

= 0A

-40°C ≤ T

A

≤ +85°C, I

OUT

= 0A

Line regulation Over PVIN range, T

A

= 25°C, I

OUT

= 0A

Load regulation Over I

OUT range, T

A

= 25°C

Total output voltage variation Includes set-point, line, load, and temperature variation

Efficiency

I

I

PVIN = VIN = 12 V

O

= 3 A

PVIN = VIN = 5 V

O

= 3 A

V

OUT

= 5V, f

SW

= 780kHz

V

OUT

= 3.3V, f

SW

= 630kHz

V

OUT

= 2.5V, f

SW

= 530kHz

V

OUT

= 1.8V, f

SW

= 480kHz

V

OUT

= 1.5V, f

SW

= 480kHz

V

OUT

= 1.2V, f

SW

= 480kHz

V

OUT

= 3.3V, f

SW

= 630kHz

V

OUT

= 2.5V, f

SW

= 530kHz

V

OUT

= 1.8V, f

SW

= 480kHz

V

OUT

= 1.5V, f

SW

= 480kHz

V

OUT

= 1.2V, f

SW

= 480kHz

Output voltage ripple

Overcurrent threshold

20 MHz bandwith

Transient response 1.0 A/µs load step from 50 to 100% I

OUT(max)

Recovery time

V

OUT over/undershoot

0

4.5

1.7

(1)

3.5

1.2

4.0

3.85

±0.3%

±0.1%

±0.1%

93 %

90 %

89 %

87 %

85 %

83 %

94 %

92 %

90 %

88 %

86 %

60

30

11

80

V

INH-H

V

INH-L

I

I(stby)

Power

Good

Inhibit Control

INH Input current

INH Hysteresis current

Input standby current

PWRGD Thresholds

Inhibit High Voltage

Inhibit Low Voltage

INH < 1.1 V

INH > 1.26 V

INH pin to AGND

V

OUT rising

V

OUT falling

Good

Fault

Fault

Good

1.30

–0.3

-1.15

-3.4

2

94%

109%

91%

106%

MAX

6

14.5

14.5

4.5

5.5

±1.0%

(2)

±1.5%

(2)

Open

(3)

1.05

4 f

SW f

CLK

V

CLK-H

V

CLK-L

D

CLK

PWRGD Low Voltage

Switching frequency

Synchronization frequency

CLK High-Level Threshold

CLK Low-Level Threshold

CLK Duty cycle

Thermal Shutdown

I(PWRGD) = 2 mA

Over VIN and I

OUT ranges, RT/CLK pin OPEN

CLK Control

Thermal shutdown

Thermal shutdown hysteresis

400

480

2.0

20%

160

480

175

10

0.3

560

780

5.5

0.8

80%

UNIT

A

V

V

V

V

V

μ A

μ A

µA mV

PP

A

µs mV

V kHz kHz

V

V

°C

°C

(1) The minimum PVIN voltage is 1.7V or (V

OUT

+ 0.5V) , whichever is greater. VIN must be greater than 4.5V.

(2) The stated limit of the set-point voltage tolerance includes the tolerance of both the internal voltage reference and the internal adjustment resistor. The overall output voltage tolerance will be affected by the tolerance of the external R

SET resistor.

(3) This control pin has an internal pullup. If this pin is left open circuit, the device operates when input power is applied. A small lowleakage (<300 nA) MOSFET is recommended for control. See the application section for further guidance.

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SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

ELECTRICAL CHARACTERISTICS (continued)

over -40°C to 85°C free-air temperature, PVIN = VIN = 12 V, V

OUT

C

IN1

= 2x 22 µF ceramic, C

IN2

= 68 µF poly-tantalum, C

OUT1

= 1.8 V, I

OUT

= 6A,

= 4x 47 µF ceramic (unless otherwise noted)

PARAMETER TEST CONDITIONS

C

IN

External input capacitance

Ceramic

Ceramic

Non-ceramic

MIN

44

(4)

68

(4)

47

(5)

C

OUT

External output capacitance Non-ceramic

TYP

200

220

(5)

Equivalent series resistance (ESR)

MAX

1500

5000

35

UNIT

µF

µF m Ω

(4) A minimum of 100µF of polymer tantalum and/or ceramic external capacitance is required across the input (VIN and PVIN connected) for proper operation. Locate the capacitor close to the device. See

Table 5

for more details. When operating with split VIN and PVIN rails, place 4.7µF of ceramic capacitance directly at the VIN pin.

(5) The amount of required output capacitance varies depending on the output voltage (see

Table 3

). The amount of required capacitance must include at least 1x 47µF ceramic capacitor. Locate the capacitance close to the device. Adding additional capacitance close to the load improves the response of the regulator to load transients. See

Table 3

and

Table 5

more details.

DEVICE INFORMATION

FUNCTIONAL BLOCK DIAGRAM

PWRGD

VSENSE+

VADJ

SS/TR

STSEL

RT/CLK

AGND

PWRGD

Logic

Thermal Shutdown

OCP

Shutdown

Logic

VIN

UVLO

VREF

+

+

Comp

Power

Stage and

Control

Logic

OSC w/PLL

INH/UVLO

VIN

PVIN

PH

VOUT

PGND

TPS84620

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SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

NAME

AGND

TERMINAL

NO.

1

2

34

45

8

INH/UVLO

9

DNC

PGND

PH

PWRGD

PVIN

38

10

11

12

13

30

31

32

36

37

33

39

40

41

14

17

46

18

19

20

22

23

15

16

3

4

5

RT/CLK 35

SENSE+ 44

SS/TR

STSEL

VADJ

VIN

6

7

43

42

PIN DESCRIPTIONS

DESCRIPTION

Zero VDC reference for the analog control circuitry. Connect AGND to PGND at a single point. Connect near the output capacitors.

Inhibit and UVLO adjust pin. Use an open drain or open collector output logic to control the INH function. A resistor divider between this pin, AGND and VIN adjusts the UVLO voltage. Tie both pins together when using this control.

Do not connect. These pins must remain isolated from one another. Do not connect these pins to AGND or to any voltage. These pins must be soldered to isolated pads.

Common ground connection for the PVIN, VIN, and VOUT power connections.

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Phase switch node. These pins should be connected by a small copper island under the device for thermal relief. Do not place any external component on this pin or tie it to a pin of another function.

Power good fault pin. Asserts low if the output voltage is low. A pull-up resistor is required.

Input switching voltage. this pin supplies voltage the power switches of the converter.

This pin automatically selects between RT mode and CLK mode. An external timing resistor adjusts the switching frequency of the device. In CLK mode, the device synchronizes to an external clock.

Remote sense connection. Connect this pin to VOUT at the load for improved regulation. This pin must be connected to VOUT at the load, or at the device pins.

Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time.

A voltage applied to this pin allows for tracking and sequencing control.

Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor with a SS interval of approximately 1.1 ms. Leave this pin open to enable the TR feature.

Connecting a resistor between this pin and AGND sets the output voltage.

Input bias voltage pin. Supplies the control circuitry of the power converter.

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TPS84620

PIN DESCRIPTIONS (continued)

DESCRIPTION

SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

NAME

VOUT

TERMINAL

NO.

21

24

25

26

27

28

29

47

Output voltage. Connect output capacitors between these pins and PGND.

RUQ PACKAGE

47 PIN

TOP VIEW

AGND 1

10

11

12

13

14

7

8

9

2

3

4

5

6

AGND

DNC

DNC

DNC

SS/TR

STSEL

INH/UVLO

INH/UVLO

PH

PH

PH

PH

PH

46

PH

DNC 15

45

AGND

37 PGND

47

VOUT

28

27

26

25

24

36

35

34

33

32

31

30

29

VOUT

VOUT

VOUT

VOUT

VOUT

PGND

RT/CLK

AGND

PWRGD

DNC

DNC

DNC

VOUT

23 DNC

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SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

100

95

90

85

80

75

70

65

60

55

50

0

TYPICAL CHARACTERISTICS (PVIN = VIN = 12 V)

(1) (2)

100

80

V

OUT

= 5.0 V, f

SW

= 780 kHz

V

OUT

= 3.3 V, f

SW

= 630 kHz

V

OUT

= 2.5 V, f

SW

= 530 kHz

V

OUT

= 1.8 V, f

SW

= 480 kHz

V

OUT

= 1.2 V, f

SW

= 480 kHz

60

PVIN = 12 V

VIN = 12 V

V

OUT

= 5.0 V, f

SW

= 780 kHz

V

OUT

= 3.3 V, f

SW

= 630 kHz

V

OUT

= 2.5 V, f

SW

= 530 kHz

V

OUT

= 1.8 V, f

SW

= 480 kHz

V

OUT

= 1.2 V, f

SW

= 480 kHz

1 2 3

Output Current (A)

4 5

Figure 1. Efficiency vs. Output Current

6

40 www.ti.com

20

PVIN = 12 V

VIN = 12 V

0

0 1 2 3

Output Current (A)

4 5

Figure 2. Voltage Ripple vs. Output Current

6

4

3.5

3

2.5

2

1.5

V

OUT

= 5.0 V, f

SW

= 780 kHz

V

OUT

= 3.3 V, f

SW

= 630 kHz

V

OUT

= 2.5 V, f

SW

= 530 kHz

V

OUT

= 1.8 V, f

SW

= 480 kHz

V

OUT

= 1.2 V, f

SW

= 480 kHz

1

0.5

PVIN = 12

VIN = 12

0

1 2 3 4

Output Current (A)

5

Figure 3. Power Dissipation vs. Output Current

6

90

80

70

60

50

40

30

20

1

Over All Output Voltages

2 3 4

Output Current (A)

Natural Convection

5 6

Figure 4. Safe Operating Area

40

30

20

10

0

−10

120

90

60

30

0

−30

−20 −60

−30

−40

1000

Gain

Phase

10000

Frequency (Hz)

PVIN = 12 V

VIN = 12 V

100000

−90

−120

400000

Figure 5. V

OUT

=1.2 V, I

OUT

=3 A, C

OUT1

=47 µF ceramic, C

OUT2

= 330 µF POSCAP, f

SW

=480 kHz

(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to

Figure 1 , Figure 2 , and Figure 3 .

(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.

Applies to

Figure 4 .

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TYPICAL CHARACTERISTICS (PVIN = VIN = 5 V)

(1) (2)

100 100

95

90

85

80

75

70

65

60

55

50

0

PVIN = 5 V

VIN = 5 V

V

OUT

= 3.3 V, f

SW

= 630 kHz

V

OUT

= 2.5 V, f

SW

= 530 kHz

V

OUT

= 1.8 V, f

SW

= 480 kHz

V

OUT

= 1.2 V, f

SW

= 480 kHz

1 2 3

Output Current (A)

4 5

Figure 6. Efficiency vs. Output Current

6

80

60

40

SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

V

OUT

= 3.3 V, f

SW

= 630 kHz

V

OUT

= 2.5 V, f

SW

= 530 kHz

V

OUT

= 1.8 V, f

SW

= 480 kHz

V

OUT

= 1.2 V, f

SW

= 480 kHz

20

PVIN = 5 V

VIN = 5 V

0

0 1 2 3

Output Current (A)

4 5

Figure 7. Voltage Ripple vs. Output Current

6

4

3.5

3

2.5

2

1.5

V

OUT

= 3.3 V, f

SW

= 630 kHz

V

OUT

= 2.5 V, f

SW

= 530 kHz

V

OUT

= 1.8 V, f

SW

= 480 kHz

V

OUT

= 1.2 V, f

SW

= 480 kHz

1

0.5

PVIN = 5 V

VIN = 5 V

0

1 2 3 4

Output Current (A)

5

Figure 8. Power Dissipation vs. Output Current

6

90

80

70

60

50

40

30

20

1

Over All Output Voltages

2 3 4

Output Current (A)

Natural Convection

5 6

Figure 9. Safe Operating Area

40

30

20

10

0

−10

120

90

60

30

0

−30

−20 −60

−30

−40

1000

Gain

Phase

10000

Frequency (Hz)

PVIN = 5 V

VIN = 5 V

100000

−90

−120

400000

Figure 10. V

OUT

=1.2 V, I

OUT

=3 A, C

OUT1

=47 µF ceramic, C

OUT2

= 330 µF POSCAP, f

SW

=480 kHz

(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to

Figure 6 , Figure 7 , and Figure 8 .

(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.

Applies to

Figure 9 .

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TYPICAL CHARACTERISTICS (PVIN = 12 V, VIN = 5 V)

(1) (2)

100 100

95

90

85

80

75

70

65

60

55

50

0

PVIN = 12 V

VIN = 5 V

V

OUT

= 5.0 V, f

SW

= 780 kHz

V

OUT

= 3.3 V, f

SW

= 630 kHz

V

OUT

= 2.5 V, f

SW

= 530 kHz

V

OUT

= 1.8 V, f

SW

= 480 kHz

V

OUT

= 1.2 V, f

SW

= 480 kHz

1 2 3

Output Current (A)

4 5

Figure 11. Efficiency vs. Output Current

6

80

60

40

V

OUT

= 5.0 V, f

SW

= 780 kHz

V

OUT

= 3.3 V, f

SW

= 630 kHz

V

OUT

= 2.5 V, f

SW

= 530 kHz

V

OUT

= 1.8 V, f

SW

= 480 kHz

V

OUT

= 1.2 V, f

SW

= 480 kHz

20

PVIN = 12 V

VIN = 5 V

0

0 1 2 3

Output Current (A)

4 5

Figure 12. Voltage Ripple vs. Output Current

6

4

3.5

3

2.5

2

1.5

V

OUT

= 5.0 V, f

SW

= 780 kHz

V

OUT

= 3.3 V, f

SW

= 630 kHz

V

OUT

= 2.5 V, f

SW

= 530 kHz

V

OUT

= 1.8 V, f

SW

= 480 kHz

V

OUT

= 1.2 V, f

SW

= 480 kHz

1

0.5

PVIN = 12 V

VIN = 5 V

0

1 2 3 4

Output Current (A)

5

Figure 13. Power Dissipation vs. Output Current

6

90

80

70

60

50

40

30

20

1

V

OUT

= 5 V

2

100 LFM

Natural Convection

3 4

Output Current (A)

Figure 14. Safe Operating Area

5 6

70

60

50

90

80

40

40

30

20

10

0

−10

−20

−30

−40

1000

120

90

60

30

0

−30

−60

PVIN = 12 V

VIN = 5 V

100000

−90

−120

400000

30

20

1

V

OUT

< 5 V

2

Natural Convection

3 4

Output Current (A)

Figure 15. Safe Operating Area

5 6

Gain

Phase

10000

Frequency (Hz)

Figure 16. V

OUT

=1.2 V, I

OUT

C

OUT2

=3 A, C

OUT1

= 330 µF POSCAP, f

SW

=47 µF ceramic,

=480 kHz

(1) The electrical characteristic data has been developed from actual products tested at 25°C. This data is considered typical for the converter. Applies to

Figure 11

,

Figure 12

, and

Figure 13 .

(2) The temperature derating curves represent the conditions at which internal components are at or below the manufacturer's maximum operating temperatures. Derating limits apply to devices soldered directly to a 100 mm × 100 mm double-sided PCB with 1 oz. copper.

Applies to

Figure 14

and

Figure 15 .

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2.7

2.8

2.9

3.0

3.1

3.2

3.3

2.2

2.3

2.4

2.5

2.6

V

OUT

(V)

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

2.1

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SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

APPLICATION INFORMATION

ADJUSTING THE OUTPUT VOLTAGE

The VADJ control sets the output voltage of the TPS84620. The output voltage adjustment range is from 1.2V to

5.5V. The adjustment method requires the addition of R

SET

, which sets the output voltage, the connection of

SENSE+ to VOUT, and in some cases R

RT which sets the switching frequency. The R

SET resistor must be connected directly between the VADJ (pin 43) and AGND (pin 45). The SENSE+ pin (pin 44) must be connected to VOUT either at the load for improved regulation or at VOUT of the device. The R

RT directly between the RT/CLK (pin 35) and AGND (pin 34).

resistor must be connected

Table 1

gives the standard external R

SET

R

RT resistor for that output voltage.

resistor for a number of common bus voltages, along with the required

RESISTORS

R

SET

(k Ω )

R

RT

(k Ω )

Table 1. Standard R

SET

Resistor Values for Common Output Voltages

1.2

2.87

open

1.5

1.62

open

OUTPUT VOLTAGE V

OUT

(V)

1.8

1.13

2.5

0.665

open 1000

3.3

0.453

332

5.0

0.267

165

For other output voltages, the value of the required resistor can either be calculated using the following formula, or simply selected from the range of values given in

Table 2 .

R

SET

=

1.43

æ

ç

è

æ

è

V

OUT

0.8

ö

ø

-

1

ö

÷

ø

(1)

0.806

0.750

0.715

0.665

0.634

0.604

0.562

0.536

0.511

0.499

0.475

0.453

R

SET

(k Ω )

2.87

2.26

1.91

1.62

1.43

1.27

1.13

1.02

0.953

0.866

Table 2. Standard R

SET

Resistor Values

1000

1000

1000

499

499

499

332 open open open open

1000

R

RT

(k Ω ) open open open open open open open open open open

530

530

530

580

580

580

630

480

480

480

480

530 f

SW

(kHz)

480

480

480

480

480

480

480

480

480

480

4.9

5.0

5.1

5.2

5.3

5.4

5.5

4.4

4.5

4.6

4.7

4.8

V

OUT

(V)

3.4

3.5

3.6

3.7

3.8

3.9

4.0

4.1

4.2

4.3

0.316

0.309

0.301

0.294

0.287

0.280

0.267

0.267

0.261

0.255

0.249

0.243

R

SET

(k Ω )

0.442

0.422

0.402

0.392

0.374

0.365

0.357

0.348

0.332

0.324

165

165

165

165

165

165

165

196

196

196

196

165

R

RT

(k Ω )

332

332

332

332

249

249

249

249

196

196

780

780

780

780

780

780

780

730

730

730

730

780 f

SW

(kHz)

630

630

630

630

680

680

680

680

730

730

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CAPACITOR RECOMMENDATIONS FOR THE TPS84620 POWER SUPPLY

www.ti.com

Capacitor Technologies

Electrolytic, Polymer-Electrolytic Capacitors

When using electrolytic capacitors, high-quality, computer-grade electrolytic capacitors are recommended.

Polymer-electrolytic type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo OS-CON capacitor series is suggested due to the lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Aluminum electrolytic capacitors provide adequate decoupling over the frequency range of 2 kHz to 150 kHz, and are suitable when ambient temperatures are above 0°C.

Ceramic Capacitors

The performance of aluminum electrolytic capacitors is less effective than ceramic capacitors above 150 kHz.

Multilayer ceramic capacitors have a low ESR and a resonant frequency higher than the bandwidth of the regulator. They can be used to reduce the reflected ripple current at the input as well as improve the transient response of the output.

Tantalum, Polymer-Tantalum Capacitors

Polymer-tantalum type capacitors are recommended for applications where the ambient operating temperature is less than 0°C. The Sanyo POSCAP series and Kemet T530 capacitor series are recommended rather than many other tantalum types due to their lower ESR, higher rated surge, power dissipation, ripple current capability, and small package size. Tantalum capacitors that have no stated ESR or surge current rating are not recommended for power applications.

Input Capacitor

The TPS84620 requires a minimum input capacitance of 100 μ F of ceramic and/or polymer-tantalum capacitors.

The ripple current rating of the capacitor must be at least 450 mArms.

Table 5

includes a preferred list of capacitors by vendor.

Output Capacitor

The required output capacitance is determined by the output voltage of the TPS84620. See

Table 3

for the amount of required capacitance. The required output capacitance can be comprised of either all ceramic capacitors, or a combination of ceramic and bulk capacitors. The required output capacitance must include at least 1x 47 µF ceramic capacitor. When adding additional non-ceramic bulk capacitors, low-ESR devices like the ones recommended in

Table 5

are required. The required capacitance above the minimum is determined by actual transient deviation requirements. See

Table 4

for typical transient response values for several output voltage, input voltage and capacitance combinations.

Table 5

includes a preferred list of capacitors by vendor.

MIN

1.2

3.0

4.0

Table 3. Required Output Capacitance

V

OUT

RANGE (V)

MINIMUM REQUIRED C

OUT

(µF)

MAX

< 3.0

< 4.0

5.5

(1) Minimum required must include at least one 47 µF ceramic capacitor.

200

(1)

100

(1)

47 µF ceramic

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Table 4. Output Voltage Transient Response

C

IN1

= 2 x 22 µF CERAMIC, C

IN2

= 68 µF POSCAP, LOAD STEP = 3 A, 1 A/µs

V

OUT

(V) PV

IN

(V) C

OUT1

Ceramic C

OUT2

BULK

VOLTAGE

DEVIATION (mV)

1.2

3.3

5

12

4x 47 µF

1x 47 µF

4x 47 µF

1x 47 µF

4x 47 µF

None

330 µF

None

330 µF

None

73

50

63

45

45

3.3

1x 47 µF

4x 47 µF

1x 47 µF

330 µF

None

220 µF

35

80

65

1.5

5

12

3.3

4x 47 µF

1x 47 µF

4x 47 µF

1x 47 µF

4x 47 µF

1x 47 µF

4x 47 µF

1.8

5

None

220 µF

None

220 µF

None

220 µF

None

60

60

45

50

90

72

80

12

3.3

1x 47 µF

4x 47 µF

1x 47 µF

4x 47 µF

1x 47 µF

220 µF

None

220 µF

None

100 µF

67

60

60

108

93

2.5

3.3

5.0

5

12

5

12

5

12

4x 47 µF

1x 47 µF

4x 47 µF

1x 47 µF

2x 47 µF

1x 47 µF

2x 47 µF

1x 47 µF

1x 47 µF

1x 47 µF

1x 47 µF

1x 47 µF

None

100 µF

None

100 µF

None

100 µF

None

100 µF

None

100 µF

None

100 µF

110

140

100

200

150

180

150

100

92

88

80

160

PEAK-PEAK (mV)

132

120

119

214

186

98

100

180

142

160

70

160

130

115

120

137

90

117

85

109

220

280

200

400

300

360

300

200

180

174

157

320

75

110

75

110

100

110

80

110

75

110

100

100

100

100

130

100

130

RECOVERY TIME

(µs)

70

75

70

75

70

80

70

80

110

80

75

80

70

80

70

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SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

Table 5. Recommended Input/Output Capacitors

(1)

VENDOR

Murata

TDK

Murata

Sanyo

Kemet

Sanyo

Sanyo

Kemet

Kemet

Sanyo

Sanyo

SERIES

X5R

X5R

X5R

POSCAP

T520

POSCAP

POSCAP

T530

T530

POSCAP

POSCAP

PART NUMBER

GRM32ER61E226K

C3225X5R0J476K

GRM32ER60J476M

16TQC68M

T520V107M010ASE025

6TPE100MI

2R5TPE220M7

T530D227M006ATE006

T530D337M006ATE010

2TPF330M6

6TPE330MFL www.ti.com

WORKING

VOLTAGE

(V)

CAPACITOR CHARACTERISTICS

CAPACITANCE

(µF)

ESR

(m Ω )

(2)

16

6.3

6.3

22

47

47

2

2

2

16

10

6.3

2.5

6.3

6.3

2.0

6.3

68

100

100

220

220

330

330

330

7

6

10

6

50

25

25

15

(1) Capacitor Supplier Verification

Please verify availability of capacitors identified in this table.

RoHS, Lead-free and Material Details

Please consult capacitor suppliers regarding material composition, RoHS status, lead-free status, and manufacturing process requirements.

(2) Maximum ESR @ 100kHz, 25°C.

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Transient Response

TPS84620

SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

Figure 17. PVIN = 12V, VOUT = 1.2V, 3A Load Step Figure 18. PVIN = 5V, VOUT = 1.2V, 3A Load Step

Figure 19. PVIN = 12V, VOUT = 1.8V, 3A Load Step Figure 20. PVIN = 5V, VOUT = 1.8V, 3A Load Step

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Figure 21. PVIN = 12V, VOUT = 2.5V, 3A Load Step Figure 22. PVIN = 5V, VOUT = 2.5V, 3A Load Step

Figure 23. PVIN = 12V, VOUT = 3.3V, 3A Load Step Figure 24. PVIN = 5V, VOUT = 3.3V, 3A Load Step

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Application Schematics

V

IN

/ P

VIN

4.5 V to 14.5 V

+

C

IN2

68 mF

C

IN1

47 mF

R

SET

1.13 k W

TPS84620

VIN

PWRGD

PVIN

INH/UVLO

SENSE+

VOUT

SS/TR

RT/CLK

VADJ

STSEL AGND PGND

V

OUT

1.8 V

C

OUT1

47 mF

+ C

OUT2

220 mF

UDG-10130

Figure 25. Typical Schematic

PVIN = VIN = 4.5 V to 14.5 V, VOUT = 1.8 V

V

IN

/ P

VIN

4.5 V to 14.5 V

+

C

IN2

68 mF

C

IN1

47 mF

VIN

PVIN

TPS84620

PWRGD

SENSE+

INH/UVLO VOUT

SS/TR

RT/CLK

VADJ

R

RT

332 kW R

SET

453 W

STSEL AGND PGND

V

OUT

3.3 V

C

OUT1

47 mF

+ C

OUT2

100 mF

Figure 26. Typical Schematic

PVIN = VIN = 4.5 V to 14.5 V, VOUT = 3.3 V

UDG-10129

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SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

PV

IN

3.3 V

+

C

IN2

68 mF

V

IN

4.5 V to 14.5 V

C

IN3

4.7 mF

C

IN1

47 mF

VIN

PVIN

TPS84620

PWRGD

SENSE+

INH/UVLO VOUT

R

SET

2.87 kW

SS/TR

RT/CLK

VADJ

STSEL AGND PGND

V

OUT

1.2 V

C

OUT1

47 mF

+ C

OUT2

330 mF www.ti.com

UDG-10131

Figure 27. Typical Schematic

PVIN = 3.3 V, VIN = 4.5 V to 14.5 V, VOUT = 1.2 V

VIN and PVIN Input Voltage

The TPS84620 allows for a variety of applications by using the VIN and PVIN pins together or separately. The

VIN voltage supplies the internal control circuits of the device. The PVIN voltage provides the input voltage to the power converter system.

If tied together, the input voltage for the VIN pin and the PVIN pin can range from 4.5 V to 14.5 V. If using the

VIN pin separately from the PVIN pin, the VIN pin must be between 4.5 V and 14.5 V, and the PVIN pin can range from as low as 1.7 V to 14.5 V. A voltage divider connected to the INH/UVLO pin can adjust the either input voltage UVLO appropriately. See the

Programmable Undervoltage Lockout (UVLO)

section of this datasheet for more information.

Power Good (PWRGD)

The PWRGD pin is an open drain output. Once the voltage on the SENSE+ pin is between 94% and 106% of the set voltage, the PWRGD pin pull-down is released and the pin floats. The recommended pull-up resistor value is between 10 k Ω and 100 k Ω to a voltage source that is 5.5 V or less. The PWRGD pin is in a defined state once

VIN is greater than 1.0 V, but with reduced current sinking capability. The PWRGD pin achieves full current sinking capability once the VIN pin is above 4.5V. The PWRGD pin is pulled low when the voltage on SENSE+ is lower than 91% or greater than 109% of the nominal set voltage. Also, the PWRGD pin is pulled low if the input

UVLO or thermal shutdown is asserted, the INH pin is pulled low, or the SS/TR pin is below 1.4 V.

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Power-Up Characteristics

When configured as shown in the front page schematic, the TPS84620 produces a regulated output voltage following the application of a valid input voltage. During the power-up, internal soft-start circuitry slows the rate that the output voltage rises, thereby limiting the amount of in-rush current that can be drawn from the input source. The soft-start circuitry introduces a short time delay from the point that a valid input voltage is recognized.

Figure 28

shows the start-up waveforms for a TPS84620, operating from a 5-V input (PVIN=VIN) and with the output voltage adjusted to 1.8 V.

Figure 29

shows the start-up waveforms for a TPS84620 starting up into a pre-biased output voltage. The waveforms were measured with a 3-A constant current load.

Figure 28. Start-Up Waveforms Figure 29. Start-up into Pre-bias

Pre-Biased Start-Up

The TPS84620 has been designed to prevent discharging a pre-biased output. During monotonic pre-biased startup, the TPS84620 does not allow current to sink until the SS/TR pin voltage is higher than 1.4 V.

Remote Sense

The SENSE+ pin must be connected to V

OUT at the load, or at the device pins.

Connecting the SENSE+ pin to V

OUT at the load improves the load regulation performance of the device by allowing it to compensate for any I-R voltage drop between its output pins and the load. An I-R drop is caused by the high output current flowing through the small amount of pin and trace resistance. This should be limited to a maximum of 300 mV.

NOTE

The remote sense feature is not designed to compensate for the forward drop of nonlinear or frequency dependent components that may be placed in series with the converter output. Examples include OR-ing diodes, filter inductors, ferrite beads, and fuses. When these components are enclosed by the SENSE+ connection, they are effectively placed inside the regulation control loop, which can adversely affect the stability of the regulator.

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Output On/Off Inhibit (INH)

The INH pin provides electrical on/off control of the device. Once the INH pin voltage exceeds the threshold voltage, the device starts operation. If the INH pin voltage is pulled below the threshold voltage, the regulator stops switching and enters low quiescent current state.

The INH pin has an internal pull-up current source, allowing the user to float the INH pin for enabling the device.

If an application requires controlling the INH pin, use an open drain/collector device, or a suitable logic gate to interface with the pin.

Figure 30

shows the typical application of the inhibit function. The Inhibit control has its own internal pull-up to

VIN potential. An open-collector or open-drain device is recommended to control this input.

Turning Q1 on applies a low voltage to the inhibit control (INH) pin and disables the output of the supply, shown in

Figure 31 . If Q1 is turned off, the supply executes a soft-start power-up sequence, as shown in Figure 32 . A

regulated output voltage is produced within 10 ms. The waveforms were measured with a 3-A constant current load.

TPS84620

INH/UVLO

Q1

INH

Control

AGND STSEL

Figure 30. Typical Inhibit Control

UDG-10081

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Figure 31. Inhibit Turn-Off Figure 32. Inhibit Turn-On

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Slow Start (SS/TR)

Connecting the STSEL pin to AGND and leaving SS/TR pin open enables the internal SS capacitor with a slow start interval of approximately 1.1 ms. Adding additional capacitance between the SS pin and AGND increases the slow start time.

Table 6

shows an additional SS capacitor connected to the SS/TR pin and the STSEL pin connected to AGND. See

Table 6

below for SS capacitor values and timing interval.

TPS84620

SS/TR

C

SS

(Optional) AGND STSEL

UDG-10082

Figure 33. Slow-Start Capacitor (C

SS

) and STSEL Connection

C

SS

(pF)

SS Time (msec)

Table 6. Slow-Start Capacitor Values and Slow-Start Time open

1.1

2200

1.9

4700

2.8

10000

4.6

15000

6.4

22000

8.8

25000

9.8

Overcurrent Protection

For protection against load faults, the TPS84620 uses current limiting. The device is protected from overcurrent conditions by cycle-by-cycle current limiting. During an overcurrent condition the output current is limited and the output voltage is reduced, as shown in

Figure 34 . When the overcurrent condition is removed, the output voltage

returns to the established voltage, as shown in

Figure 35 .

Figure 34. Overcurrent Limiting

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Figure 35. Removal of Overcurrent Condition

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Synchronization (CLK)

An internal phase locked loop (PLL) has been implemented to allow synchronization between 480 kHz and

780 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.8 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in .

Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to th CLK mode and the

RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by the RT resistor (R

RT

).

TPS84620

External Clock

480 kHz to 780 kHz

RT/CLK

R

RT

AGND

UDG-10128

Figure 36. CLK/RT Configuration

The synchronization frequency must be selected based on the output voltages of the devices being synchronized.

Table 7

shows the allowable frequencies for a given range of output voltages. For the most efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires synchronizing three TPS84620 devices with output voltages of 1.2 V, 1.8 V and 2. 5 V, all powered from PVIN =

12 V.

Table 7

shows that all three output voltages can be synchronized to either 530 kHz, 580 kHz, or 630 kHz.

For best efficiency, choose 530 kHz as the sychronization frequency.

SYNCHRONIZATION

FREQUENCY (kHz)

480

530

580

630

680

730

780

Table 7. Synchronization Frequency vs Output Voltage

R

RT

(k Ω )

OPEN

1000

499

332

249

196

165

1.2

1.2

1.2

1.3

1.4

1.5

PVIN = 12 V

V

OUT

RANGE (V)

MIN

1.2

MAX

2.5

2.9

3.2

3.7

4.1

4.7

5.5

PVIN = 5 V

V

OUT

RANGE (V)

MIN MAX

1.2

4.5

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Sequencing (SS/TR)

Many of the common power supply sequencing methods can be implemented using the SS/TR, INH and

PWRGD pins. The sequential method is illustrated in

Figure 37

using two TPS84620 devices. The PWRGD pin of the first device is coupled to the INH pin of the second device which enables the second power supply once the primary supply reaches regulation.

Figure 38

shows sequential turn-on waveforms of two TPS84620 devices.

TPS84620

INH/UVLO

PWRGD

SS/TR

TPS84620

INH/UVLO

PWRGD

SS/TR

UDG-10106

Figure 37. Sequencing Schematic Figure 38. Sequencing Waveforms

Simultaneous power supply sequencing can be implemented by connecting the resistor network of R1 and R2 shown in

Figure 39

to the output of the power supply that needs to be tracked or to another voltage reference source.

Figure 40

shows simultaneous turn-on waveforms of two TPS84620 devices. Use

Equation 2

and

Equation 3

to calculate the values of R1 and R2.

R1

=

(

V

OUT2

´

12.6

)

0.8

(2)

R2

=

0.8

´

R1

(

V

OUT2

-

0.8

)

(3)

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TPS84620

VOUT

INH/UVLO

STSEL SS/TR

V

OUT1

TPS84620

VOUT

INH/UVLO

V

OUT2

R1

STSEL SS/TR

R2

UDG-10107

Figure 39. Simultaneous Tracking Schematic Figure 40. Simultaneous Tracking Waveforms

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Product Folder Links: TPS84620

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TPS84620

SLVSA43D – OCTOBER 2010 – REVISED OCT 2012 www.ti.com

Programmable Undervoltage Lockout (UVLO)

The TPS84620 implements internal UVLO circuitry on the VIN pin. The device is disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 4.5 V(max) with a typical hysteresis of 150 mV.

If an application requires either a higher UVLO threshold on the VIN pin or a higher UVLO threshold for a combined VIN and PVIN, then the UVLO pin can be configured as shown in

Figure 41

or

Figure 42 .

Table 8

lists standard values for R

UVLO1 and R

UVLO2 to adjust the VIN UVLO voltage up.

PVIN

TPS84620

VIN

PVIN

TPS84620

VIN

R

UVLO1

R

UVLO1

INH/UVLO INH/UVLO

R

UVLO2

R

UVLO2

UDG-10108

Figure 41. Adjustable VIN UVLO

UDG-10109

Figure 42. Adjustable VIN and PVIN Undervoltage

Lockout

VIN UVLO (V)

R

UVLO1

(k Ω )

R

UVLO2

(k Ω )

Hysteresis (V)

5.0

68.1

21.5

400

Table 8. Standard Resistor values for Adjusting VIN UVLO

5.5

68.1

18.7

415

6.0

68.1

16.9

430

6.5

68.1

15.4

450

7.0

68.1

14.0

465

7.5

68.1

13.0

480

8.0

68.1

12.1

500

8.5

68.1

11.3

515

9.0

68.1

10.5

530

9.5

68.1

9.76

550

10.0

68.1

9.31

565

For a split rail application, if a secondary UVLO on PVIN is required, VIN must be ≥ 4.5V.

Figure 43

shows the

PVIN UVLO configuration. Use

Table 9

to select R

UVLO1 and R

UVLO2 for PVIN. If PVIN UVLO is set for less than

3.0 V, a 5.1-V zener diode should be added to clamp the voltage on the UVLO pin below 6 V.

> 4.5 V

VIN

TPS84620

PVIN

R

UVLO1

INH/UVLO

R

UVLO2

UDG-10110

Figure 43. Adjustable PVIN Undervoltage Lockout, (VIN ≥ 4.5 V)

26

Table 9. Standard Resistor Values for Adjusting PVIN UVLO, (VIN ≥ 4.5 V)

PVIN UVLO (V)

R

UVLO1

(k Ω )

R

UVLO2

(k Ω )

Hysteresis (V)

2.0

68.1

95.3

300

2.5

68.1

60.4

315

3.0

68.1

44.2

335

3.5

68.1

34.8

350

4.0

68.1

28.7

365

4.5

68.1

24.3

385

For higher PVIN UVLO voltages see

Table UV for resistor values

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SLVSA43D – OCTOBER 2010 – REVISED OCT 2012

Thermal Shutdown

The internal thermal shutdown circuitry forces the device to stop switching if the junction temperature exceeds

175°C typically. The device reinitiates the power up sequence when the junction temperature drops below 165°C typically.

Layout Considerations

To achieve optimal electrical and thermal performance, an optimized PCB layout is required.

Figure 44

, shows a typical PCB layout. Some considerations for an optimized layout are:

• Use large copper areas for power planes (VIN, VOUT, and PGND) to minimize conduction loss and thermal stress.

• Place ceramic input and output capacitors close to the device pins to minimize high frequency noise.

• Locate additional output capacitors between the ceramic capacitor and the load.

• Place a dedicated AGND copper area beneath the TPS84620.

• Isolate the PH copper area from the VOUT copper area using the AGND copper area.

• Connect the AGND and PGND copper area at one point; near the output capacitors.

• Place R

SET

, R

RT

, and C

SS as close as possible to their respective pins.

• Use multiple vias to connect the power planes to internal layers.

VOUT

SENSE+

Via

C

OUT2

C

OUT1

PGND

R

RT

C

IN1

C

IN2

AGND

PH

VIN/PVIN

R

SET

SENSE+

Via

C

SS

Figure 44. Typical Recommended Layout

Copyright © 2010–2012, Texas Instruments Incorporated

UDG-10132

Submit Documentation Feedback 27

Product Folder Links: TPS84620

TPS84620

SLVSA43D – OCTOBER 2010 – REVISED OCT 2012 www.ti.com

EMI

The TPS84620 is compliant with EN55022 Class B radiated emissions.

Figure 45

and

Figure 46

show typical examples of radiated emissions plots for the TPS84620 operating from 5V and 12V respectively. Both graphs include the plots of the antenna in the horizontal and vertical positions.

Figure 45. Radiated Emissions 5-V Input, 1.8-V

Output, 6-A Load (EN55022 Class B)

Figure 46. Radiated Emissions 12-V Input, 1.8-V

Output, 6-A Load (EN55022 Class B)

28 Submit Documentation Feedback

Product Folder Links: TPS84620

Copyright © 2010–2012, Texas Instruments Incorporated

TPS84620

SLVSA43D – OCTOBER 2010 – REVISED OCT 2012 www.ti.com

Changes from Original (October 2010) to Revision A Page

• Changed EN maximum voltage value from 3 V to 6 V .........................................................................................................

2

• Changed (corrected) resistor label from R

RT to R

SET on schematic ...................................................................................

17

• Changed (corrected) minor typographical error on schematic ...........................................................................................

18

• Changed (corrected) typographical error. ...........................................................................................................................

18

• Changed (corrected) time axis division units label from 5 µs/div to 5 ms/div in Inhibit Turn-On waveform. ......................

21

Changes from Revision A (January 2011) to Revision B Page

• Added θ

JCbot in

THERMAL INFORMATION

..........................................................................................................................

3

• Changed updated footnote text reagarding internal pulllup of INH/UVLO pin ......................................................................

4

• Added updated more specific values in

Table 7

.................................................................................................................

23

Changes from Revision B (APRIL 2011) to Revision C Page

• Changed footnote (3) from "A small low-leakage (<100 nA) MOSFET is recommended for control." to "A small lowleakage (<300 nA) MOSFET is recommended for control. " ................................................................................................

4

• Added clarity to PH pin description .......................................................................................................................................

6

• Added clarity to package title ................................................................................................................................................

7

Changes from Revision C (SEPTEMBER 2011) to Revision D Page

• Added correct pin names ......................................................................................................................................................

7

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Product Folder Links: TPS84620

Submit Documentation Feedback 29

PACKAGE OPTION ADDENDUM www.ti.com

7-Nov-2014

PACKAGING INFORMATION

Orderable Device

TPS84620RUQR

Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

B1QFN RUQ 47 500

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU

MSL Peak Temp

(3)

Level-3-260C-168 HR

Op Temp (°C)

-40 to 85

Device Marking

(4/5)

(54620 ~ TPS84620)

TPS84620RUQT ACTIVE B1QFN RUQ 47 250 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

-40 to 85 (54620 ~ TPS84620)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1

Samples

PACKAGE OPTION ADDENDUM

7-Nov-2014 www.ti.com

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

www.ti.com

TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

7-Nov-2014

*All dimensions are nominal

Device Package

Type

Package

Drawing

Pins SPQ

TPS84620RUQR B1QFN RUQ 47 500

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

330.0

24.4

A0

(mm)

9.35

B0

(mm)

15.35

K0

(mm)

3.1

P1

(mm)

16.0

W

(mm)

24.0

Pin1

Quadrant

Q1

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

7-Nov-2014

*All dimensions are nominal

Device

TPS84620RUQR

Package Type Package Drawing Pins

B1QFN RUQ 47

SPQ

500

Length (mm) Width (mm) Height (mm)

383.0

353.0

58.0

Pack Materials-Page 2

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