4.5-V TO 18-V INPUT VOLTAGE, 2-A/3-A OUTPUT CURRENT, DUAL SYNCHRONOUS

4.5-V TO 18-V INPUT VOLTAGE, 2-A/3-A OUTPUT CURRENT, DUAL SYNCHRONOUS
TPS65270
www.ti.com
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
4.5-V TO 18-V INPUT VOLTAGE, 2-A/3-A OUTPUT CURRENT, DUAL SYNCHRONOUS
STEP-DOWN REGULATOR WITH INTEGRATED MOSFET
Check for Samples: TPS65270
FEATURES
1
•
2
•
•
•
•
•
•
•
•
Wide Input Supply Voltage Range
(4.5 V - 18 V)
0.8 V, ±1% Accuracy Reference
Up to 2-A (Buck 1) and 3-A (Buck 2) Maximum
Continuous Output Loading Current
Low Power Pulse Skipping Mode to Achieve
High Light Load Efficiency
Adjustable Switching Frequency
300 kHz - 1.4 MHz Set by External Resistor
Startup with a Pre-Biased Output Voltage
Dedicated Enable and Soft-Start for Each Buck
Peak Current-Mode Control with Simple
Compensation Circuit
Cycle-by-Cycle Over Current Protection
•
•
180° Out-of-Phase Operation to Reduce Input
Capacitance and Power Supply Induced Noise
Available in 24-Lead Thermally Enhanced
HTSSOP (PWP) and QFN 4-mm x 4-mm (RGE)
Packages
APPLICATIONS
•
•
•
•
•
•
•
DTV
DSL Modems
Cable Modems
Set Top Boxes
Car DVD Players
Home Gateway and Access Point Networks
Wireless Routers
DESCRIPTION/ORDERING INFORMATION
The TPS65270 is a monolithic dual synchronous buck regulator with wide operating input voltage that can
operate in 5-, 9-, 12- or 15-V bus voltages and battery chemistries. The converters are designed to simplify its
application while giving the designer the option to optimize their usage according to the target application.
The TPS65270 features a precision 0.8-V reference and can produce output voltages up to 15 V. Each converter
features enable pin that allows dedicated control each channel that provide flexibility for power sequencing. Softstart time in each channel can be adjustable by choosing different external capacitors. TPS65270 is also able to
startup with a pre-biased output. The converter begins switching when output voltage reaches pre-biased
voltage.
Constant frequency peak current mode control simplifies the compensation and provides fast transient response.
Cycle-by-Cycle over current protection and hiccup mode operation limit MOSFET power dissipation in short
circuit or over loading fault conditions. Low side reverse current protection also prevents excessive sinking
current from damaging the converter.
The switching frequency of the converters can be set from 300 KHz to 1.4 MHz with an external resistor. Two
converters have clock signal with 180° out-of-phase so as to minimize the input filter requirements and alleviate
EMI and input capacitor requirements.
TPS65270 also features a light load pulse skipping mode (PSM). The PSM mode allows a power loss reduction
on the input power supplied to the system at light loading in order to achieve light load high efficiency.
The TPS65270 is available in a 24-Lead thermally enhanced HTSSOP (PWP) package and 24-pin QFN
4-mm x 4-mm (RGE) package.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
TPS65270
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
TYPICAL APPLICATION
1
ENABLE Buck 1
EN1
BST1
FB1
VIN1
2
FB1
C3
2.2nF
24
R4b
32.4K
LX1
C10
22uF
4
C4
10uF
LX1
LOW_P
GND
VCC
GND
20
6
R3
383K
C5
2.2nF
R2
10K
L1
4.7uH
19
TPS65270
18
AGND
GND
ROSC
GND
COMP2
LX2
8
17
9
C6
10nF
C11
82pF
1.8V/2A
COMP1
7
C16
100pF
(optional)
R4a
40.2K
21
5
C17
100pF
(optional)
FB1
VIN
22
SS1
C2
10nF
C9
10uF
25V
23
3
R1
10K
C8
47nF
L2
4.7uH
16
1.2V/3A
15
10
LX2
SS2
R5a
40.2K
C14
22uF
C15
82pF
FB2
VIN
11
VIN2
FB2
12
ENABLE Buck 2
R5b
80.6K
14
13
BST2
EN2
FB2
C13
10uF
25V
C12
47nF
R3
383K
C5
2.2nF
C16
100pF
(optional)
R2
10K
2
3
4
19
COMP1
20
LOW_P
21
VCC
TPS65270
BST1
BST2
16
15
ENABLE Buck 2
C8
47nF
C9
VIN 10uF
14
13
L1
4.7uH
1.8V/2A
12
11
10
C14
22uF
C10
22uF
R5b
80.6K
2
17
LX1
LX1
GND
LX2
GND
VIN1
GND
VIN2
LX2
C15
82pF
22
EN1
EN2
7
R5a
40.2K
AGND
FB1
9
6
1.2V/3A
23
FB2
18
25V
5
L2
4.7uH
SS1
GND
C12
47nF
C2
10nF
SS2
8
C13
10uF VIN
25V
ROSC
24
1
C16
100pF
(optional)
R1
10K
COMP2
C6
10nF
ENABLE Buck 1
C3
2.2nF
C4
10uF
C11
82pF
R4a
40.2K
R4b
32.4K
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
TPS65270
www.ti.com
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
FUNCTIONAL BLOCK DIAGRAM
LOW_P
5
VCC
6
ROSC
8
Pre-Regulator, Voltage Reference,
Current Bias
Logic
Internal
LDO
OSC
23
VIN1
24
BST1
VIN1
o
180
ILIM
SLP
CS
S
SS1
0.8V
FB1
EN 1 Logic
EN2 Logic
FB1
2
COMP1
4
EN1
1
Q
Latch
3
COMP
R
21,22
LX1
19, 20
GND
VOUT BUCK1
Q
EN
EA
FB1
BUCK 1
12
EN2
17,18
9
COMP2
FB2
GND
FB2
11
FB2
same as Buck 1
10
SS2
15,16
VOUT BUCK2
LX2
13
BUCK 2
AGND
14
BST2
VIN2
VIN2
6
Note: Pin numbers in block diagram are for HTSSOP (PWP) 24-pin package.
ORDERING INFORMATION (1)
TA
–40°C to 85°C
(1)
(2)
PACKAGE
(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
PWP (R-PDSO-G)
TPS65270PWPR
TPS65270
RGE (S-PVQFN-N24)
TPS65270RGER or TPS65270RGET
TPS65270
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
3
TPS65270
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
www.ti.com
PIN OUT
PWP PACKAGE
(TOP VIEW)
EN1
1
24
BST1
FB1
2
23
VIN1
SS1
3
22
LX1
COMP1
4
21
LX1
LOW_P
5
20
GND
VCC
6
19
GND
Thermal Pad
AGND
7
18
GND
ROSC
8
17
GND
COMP2
9
16
LX2
SS2
10
15
LX2
FB2
11
14
VIN2
EN2
12
13
BST2
Exposed pad must be soldered to PCB for optimal thermal performance.
COMP2
ROSC
AGND
VCC
LOW_P
COMP1
RGE PACKAGE
(TOP VIEW)
24
23
22
21
20
19
SS2 1
18 SS1
FB2 2
17 FB1
EN2 3
16 EN1
Thermal Pad
7
8
9
10
11
12
LX1
13 LX1
GND
LX2 6
GND
14 VIN1
GND
VIN2 5
GND
15 BST1
LX2
BST2 4
Exposed pad must be soldered to PCB for optimal thermal performance.
4
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
TPS65270
www.ti.com
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
TERMINAL FUNCTIONS
NO.
(HTSSOP)
NO.
(QFN)
EN1
1
16
Enable for Buck 1. Logic high enables the Buck 1; Logic low disables
Buck 1. If pin is left open a weak internal pull-up to V5V will allow for
automatic enable; For a delayed start-up add a small ceramic capacitor
from this pin to ground.
FB1
2
17
Feedback voltage for Buck 1. Connect a resistor divider to set 0.8 V from
the output of the converter to ground.
SS1
3
18
Soft start input for Buck 1. An internal 5-µA charging current is sourcing to
this pin. Connect a small ceramic capacitor to this pin to set the Buck 1
soft start time.
COMP1
4
19
Loop compensation pin for Buck 1. Connect a series RC circuit to this pin
to compensate the control loop of this converter.
LOW_P
5
20
Low power operation mode. With active high, Buck 1 and Buck 2 operate
at pulse skipping mode at light load; active low forces both Buck 1 and
Buck 2 to PWM mode; this pin can’t be left open.
VCC
6
21
Internal 6.5-V power supply bias. Connect a 10-µF ceramic capacitor from
this pin to ground.
AGND
7
22
Analog ground. Connect all GND pins and power pad together.
ROSC
8
23
Oscillator frequency setup. Connect a resistor to ground to set the
frequency of internal oscillator clock.
COMP2
9
24
Loop compensation pin for Buck 2. Connect a series RC circuit to this pin
to compensate the control loop of this converter.
SS2
10
1
Soft start input for Buck 2. An internal 5-µA charging current is sourcing to
this pin. Connect a small ceramic capacitor to this pin to set the Buck 1
soft start time.
FB2
11
2
Feedback voltage for Buck 2. Connect a resistor divider to set 0.8 V from
the output of the converter to ground.
EN2
12
3
Enable for Buck 2. Logic high enables the Buck 2. Logic low disables
Buck 2. If pin is left open a weak internal pull-up to V5V will allow for
automatic enable; For a delayed start-up add a small ceramic capacitor
from this pin to ground.
BST2
13
4
Bootstrapped power supply to high side floating gate driver in Buck 2.
Connect a 47-nF ceramic capacitor from this pin to the switching node pin
LX2.
VIN2
14
5
Input supply for Buck 2. Connect a 10-µF ceramic capacitor close to this
pin.
LX2
15, 16
6, 7
GND
17, 18, 19, 20
8, 9, 10, 11
LX1
21, 22
12, 13
VIN1
23
14
Input supply for Buck 1. Conne ct a 10-µF ceramic capacitor close to this
pin.
BST1
24
15
Bootstrapped power supply to high side floating gate driver in Buck 1.
Connect a 47-nF ceramic capacitor from this pin to the switching node pin
LX1.
NAME
Thermal Pad
DESCRIPTION
Switching node connecting to inductor for Buck 2.
Power ground for Buck 1 and Buck 2.
Switching node connecting to inductor for Buck 1.
Must be soldered to PCB for optimal thermal performance. Have thermal
vias on the PCB to enhance power dissipation.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
5
TPS65270
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
ABSOLUTE MAXIMUM RATINGS
www.ti.com
(1)
over operating free-air temperature range (unless otherwise noted)
Voltage range at VIN1, VIN2, LX1, LX2
–0.3 to 18
V
Voltage range at LX1, LX2 (maximum withstand voltage transient < 10 ns)
–1 to 18
V
Voltage at BST1, BST2, referenced to LX1, LX2 pin
–0.3 to 7
V
Voltage at VCC, EN1, EN2, COMP1, COMP2, LOW_P
–0.3 to 7
V
Voltage at SS1, SS2, FB1, FB2, ROSC
–0.3 to 3.6
V
Voltage at AGND, GND
–0.3 to 0.3
V
TJ
Operating virtual junction temperature range
–40 to 125
°C
TSTG
Storage temperature range
–55 to 150
°C
(1)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VIN
Input operating voltage
4.5
18
V
TA
Ambient temperature
–40
85
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
Human body model (HBM)
Charge device model (CDM)
MAX
UNIT
2000
V
500
V
PACKAGE DISSIPATION RATINGS (1) (2) (3)
(1)
(2)
(3)
6
PACKAGE
θJA (°C/W)
θJC (°C/W)
TA = 25°C
POWER RATING (W)
TA = 55°C
POWER RATING (W)
TA = 85°C
POWER RATING (W)
PWP
32.6
10
3.07
2.15
1.23
RGE
32.6
10
3.07
2.15
1.23
This assumes a JEDEC JESD 51-5 standard board with thermal vias with High K profile - See Texas Instruments application report
(SLMA002) regarding thermal characteristics of the PowerPAD™ package.
This assumes junction to exposed PAD.
Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x .6-mm board with the following layer arrangement:
(a) Top layer: 2 Oz Cu, 6.7% coverage
(b) Layer 2: 1 Oz Cu, 90% coverage
(c) Layer 3: 1 Oz Cu, 90% coverage
(d) Bottom layer: 2 Oz Cu, 20% coverage
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
TPS65270
www.ti.com
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS
TA = -40°C to 125°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT SUPPLY
VIN
Input Voltage range
VIN1 and VIN2
IDDSDN
Shutdown
EN1 = EN2 = 0 V
IDDQ_nsw
Non switching quiescent power supply
current
VFB1 = VFB2 = 900 mV,
LOW_P = high
UVLO
VIN under voltage lockout
4.5
18
V
10
µA
1
mA
Rising VIN
4
4.20
4.45
Falling VIN
3.65
3.85
4.10
V
Hysteresis
0.35
6.25
V
VCC
Internal biasing supply
VCC load current = 0 A,
VIN = 12 V
VCC_drop
VCC LDO Drop-Out Voltage
VIN = 5 V,
VCC load current = 20 mA
180
mV
IVCC
VCC current limit
4.5 V < VIN < 18 V
200
mA
FEEDBACK AND ERROR AMPLIFIER
VFB
Regulated feedback voltage
VIN = 12 V , VCOMP = 1.2 V,
TJ = 25°C
-1%
0.8
1%
VIN = 12 V, VCOMP = 1.2 V,
TJ = -40°C to 125°C
-2%
0.8
2%
V
VLINEREG
Line regulation - DC
VIN = 4.5 V to 18 V,
IOUT = 1 A
0.5
%/V
VLOADREG
Load regulation - DC
IOUT = 10 % - 90%
IOUT,MAX
0.4
%/A
Gm_EA
Error amplifier trans-conductance
-2 µA < ICOMP < 2 µA
130
µs
Gm_SRC
COMP voltage to inductor current Gm
ILX = 0.5 A
10
A/V
ENABLE, PFM MODE AND SOFT-START
Rising
VEN
EN1 and EN2 pin threshold
VPSM
PSM low power mode threshold
ISS
SS1 and SS2 soft-start charging current
1.55
Falling
Rising
V
0.4
1.55
Falling
V
0.4
5
µA
OSCILLATOR
FSW_BK
Switching frequency range
FSW
Programmable frequency
Set by external resistor ROSC
0.3
1.4
MHz
ROSC = 250 kΩ
0.85
1
1.15
MHz
ROSC = 500 kΩ
425
500
575
kHz
PROTECTION
ILIMIT1
Buck 1 peak inductor current limit
4.5 V < VIN < 18 V
3.2
A
ILIMIT1_LS1
Buck 1 low side MOSFET current limit
4.5 V < VIN < 18 V
2
A
ILIMIT2
Buck 2 peak inductor current limit
4.5 V < VIN < 18V
4.1
A
ILIMIT1_LS2
Buck 2 low side MOSFET current limit
4.5 V < VIN < 18 V
2
A
MOSFET ON-RESISTANCES
Rdson_HS1
On resistance of high side FET on CH1
BST1 to LX1 = 6.25 V
120
mΩ
Rdson_LS1
On resistance of low side FET on CH1
VIN = 12 V
80
mΩ
Rdson_HS2
On resistance of high side FET on CH2
BST2 to LX2 = 6.25 V
95
mΩ
Rdson_LS2
On resistance of low side FET on CH2
VIN = 12 V
50
Ton_min
Minimum in time
80
mΩ
120
ns
THERMAL SHUTDOWN
TTRIP
Thermal protection trip point
THYST
Thermal protection hysteresis
Rising temperature
160
20
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
°C
°C
7
TPS65270
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
www.ti.com
TYPICAL CHARACTERISTICS
TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted)
1.25
1.85
1.24
1.83
1.23
PWM, Vout1, Vin = 12 V
PWM, Vout2, Vin = 12 V
1.22
1.21
1.81
1.2
PSM, Vout2, Vin = 12 V
PSM, Vout2, Vin = 12 V
1.19
1.79
1.18
`
1.17
1.77
1.16
1.15
1.75
0
0.5
1
1.5
2
2.5
0
3
0.5
1
Figure 1. Load Regulation
Buck 1 at 1.8 V, 1% Resistors
1.5
2
2.5
3
3.5
4
Figure 2. Load Regulation
Buck 1 at 1.2 V, 1% Resistor s
100
95
90
90
VI = 4.5 V
80
85
VI = 15 V
VI = 12 V
70
80
VI = 4.5 V
60
VI = 15 V
VI = 12 V
75
50
70
40
65
30
60
20
55
10
50
0
0
0.5
1
1.5
2
2.5
0
3
0.5
1
Figure 3. Efficiency
Buck 1 at 3.3 V
1.5
2
2.5
3
3.5
Figure 4. Efficiency
Buck 2 at 1 V
1
1
Vin = 12 V Vout1 = 3.3 V auto PSM-PWM
0.9
Vin = 12 V Vout2 = 5 V auto PSM-PWM
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
Forced PWM
0.5
Forced PWM
0.4
0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0
0
0.05
0.1
0.15
0.2
0
Figure 5. Efficiency
Buck 1 at 3.3 V
8
0.05
0.1
0.15
0.2
Figure 6. Efficiency
Buck 2 at 5 V
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
TPS65270
www.ti.com
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted)
Figure 7. Buck 1 and Buck 2 in Steady State
IO1 = 0 A, IO2 = 0 A
Figure 8. Buck 1 and Buck 2 in Steady State
IO1 = 2 A, IO2 = 3 A
Figure 9. Startup With EN
VO1 = 1.8 V, VO2 = 1.2 V
Figure 10. Buck 1 Load Transient
VO1 = 3.3 V, IO1 = 1 A - 2 A
Figure 11. Buck 2 Load Transient
VO2 = 1 V, IO1 = 1 A - 2 A
Figure 12. Buck 1 and Buck 2 in PSM Mode
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
9
TPS65270
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
www.ti.com
TYPICAL CHARACTERISTICS (continued)
TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted)
Figure 13. Buck 2 Hard Short and Recover
10
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
TPS65270
www.ti.com
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
OVERVIEW
TPS65270 is a power management IC with two step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. TPS65270 can support
4.5-V to 18-V input supply, 2-A continuous current for Buck 1 and 3 A for Buck 2. The buck converters have an
automatic PSM mode, which can improve power dissipation during light loads. Alternatively, the device
implements a constant frequency mode by connecting the LOW_P pin to ground. The wide switching frequency
of 300 kHz to 1.4 MHz allows for efficiency and size optimization. The switching frequency is adjustable by
selecting a resistor to ground on the ROSC pin. Input ripple is reduced by 180° out-of-phase operation between
Buck 1 and Buck 2.
Both buck converters have peak current mode control which simplifies the loop compensation. A traditional type
II compensation network can stabilize the system and achieve fast transient response. Moreover, an optional
capacitor in parallel with the upper resistor of the feedback divider provides one more zero and makes the
crossover frequency over 100 kHz. Each buck converter has an individual cycle-by-cycle current limit and low
side reverse current limit.
The device has a built-in LDO regulator. During a standby mode, the 6.5-V LDO can be used to drive MCU and
other active loads. with this LDO, system is able to turn off the two buck converters so as to reduce the power
consumption and improve the standby efficiency. Each converter has its own programmable soft start that can
reduce the input inrush current. The individual Enable pins for each independent control of each output voltage
and power sequence.
DETAILED DESCRIPTION
Adjustable Switching Frequency
To select the internal switching frequency connect a resistor from ROSC to ground. Figure 14 shows the required
resistance for a given switching frequency.
900
800
700
Resistance - W
600
500
400
300
200
100
0
0
0.5
1
1.5
2
fsw - Switching Frequency - MHz
2.5
3
Figure 14. ROSC vs Switching Frequency
ROSC(kW) = 239.13 · fSW -1.149
(1)
For operation at 800 kHz, a 300-kΩ resistor is required.
Out-of-Phase Operation
In order to reduce input ripple current, Buck 1 and Buck 2 operate 180° out-of-phase. This enables the system
having less input ripple, then to lower component cost, save board space and reduce EMI.
Delayed Start-Up
If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay
added is ~0.75 ms per nF connected to the pin. Note that the EN pins have a weak 1-MΩ pull-up to the 5-V rail.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
11
TPS65270
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
www.ti.com
Soft Start Time
The device has an internal pull-up current source of 5 µA that charges an external slow start capacitor to
implement a slow start time. Equation 2 shows how to select a slow start capacitor based on an expected slow
start time. The voltage reference (VREF) is 0.8 V and the slow start charge current (Iss) is 5 µA. The soft start
circuit requires 1 nF per 160 µs to be connected at the SS pin. An 800-µs soft-start time is implemented for all
converters fitting 4.7 nF to the relevant pins.
( )
Css(nF)
Tss(ms) = VREF(V) · Iss(µA)
(2)
Adjusting the Output Voltage
The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1%
tolerance or better divider resistors. In order to improve efficiency at light load, start with 40.2 kΩ for the R1
resistor and use the Equation 3 to calculate R2.
æ 0.8V ö
R 2 = R1 × ç
÷
è VO - 0.8V ø
(3)
Vo
TPS65270
R1
FB
R2
0.8V
+
Figure 15. Voltage Divider Circuit
Input Capacitor
Use 10-μF X7R/X5R ceramic capacitors at the input of the converter inputs. These capacitors should be
connected as close as physically possible to the input pins of the converters.
Bootstrap Capacitor
The device has two integrated boot regulators and requires a small ceramic capacitor between the BST and LX
pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor is
recommended to be 0.047 μF. A ceramic capacitor with an X7R or X5R grade dielectric is desired because of
the stable characteristics over temperature and voltage.
Error Amplifier
The device has a transconductance error amplifier. The transconductance of the error amplifier is 130 µA/V
during normal operation. The frequency compensation network is connected between the COMP pin and ground.
Loop Compensation
TPS65270 is a current mode control dc/dc converter. The error amplifier has 130-µA/V transconductance.
12
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
TPS65270
www.ti.com
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
Vo
iL
Co
RL
Resr
gmps=10A/V
R1
Current Sense
I/V Gain
Cff
FBx
Rc
Vref=0.8V
Cc
CRoll
R2
gm=130µA/V
Figure 16. Loop Compensation
A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60 and 90 degrees,
or type III (Rc, Cc and Cff) to improve the converter transient response. CRoll adds a high frequency pole to
attenuate high-frequency noise when needed. It may also prevent noise coupling from other rails if there is
possibility of cross coupling in between rails when layout is very compact.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
13
TPS65270
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
www.ti.com
To calculate the external compensation components follow the following steps:
TYPE II CIRCUIT
TYPE III CIRCUIT
Select switching frequency that is appropriate for
application depending on L, C sizes, output ripple, EMI
concerns and etc. Switching frequencies between 500 kHz
and 1 MHz give best trade off between performance and
cost. When using smaller L and Cs, switching frequency
can be increased. To optimize efficiency, switching
frequency can be lowered.
Use type III circuit for switching
frequencies higher than 500 kHz.
Select cross over frequency (fc) to be less than 1/5 to 1/10
of switching frequency.
Suggested
fc = fs/10
RC =
Set and calculate Rc.
2p × fc × Vo × Co
g M × Vref × gm ps
Calculate Cc by placing a compensation zero at or before
the converter dominant pole
Cc =
1
fp =
CO × RL × 2p
Suggested
fc = fs/10
RL × Co
Rc
RC =
2p × fc × Co
g M × gm ps
Cc =
RL × Co
Rc
Add CRoll if needed to remove large signal coupling to high
impedance COMP node. Make sure that
fpRoll =
1
2 × p × RC × CRoll
CRoll =
Re sr × Co
RC
CRoll =
Re sr × Co
RC
is at least twice the cross over frequency.
Calculate Cff compensation zero at low frequency to boost
the phase margin at the crossover frequency. Make sure
that the zero frequency (fzff is smaller than soft start
equivalent frequency (1/Tss).
NA
C ff =
1
2 × p × fz ff × R1
Slope Compensation
The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic
oscillations in peak current mode control when duty cycle becomes too large.
Over Current Protection
The current through the internal high side MOSFET is sampled and scaled through an internal pilot device during
the hig time. The sampled current is compared to over current limit. If the peak inductor current exceeds the over
current limit reference level, an internal over current fault counter is set to 1 and an internal flag is set. The
internal power MOSFET is immediately turned off and will not be turned on again until the next switching cycle.
The protection circuitry continues to monitor the current and turns off the internal MOSFET as described. If the
overcurrent condition persists for four sequential clock cycles, the over-current fault counter overflows indicating
an overcurrent fault condition exists. The regulator is shut down and power good goes low. If the overcurrent
condition clears prior to the counter reaching four consecutive cycles, the internal flag and counter are reset. The
protection circuitry attempts to recover from the overcurrent condition after waiting four soft-start cycles. The
internal overcurrent flag and counter are reset. A normal soft-start cycle is attempted and normal operation
continues if the fault condition has cleared. If the overcurrent fault counter overflows during soft-start, the
converter shuts down and this hiccup mode operation repeats.
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.
14
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
TPS65270
www.ti.com
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
Power Dissipation
The total power dissipation inside TPS65270 should not to exceed the maximum allowable junction temperature
of 125°C to maintain reliable operation. The maximum allowable power dissipation is a function of the thermal
resistance of the package (RJA) and ambient temperature.
To
1.
2.
3.
calculate the temperature inside the device under continuous loading use the following procedure.
Define the set voltage for each converter.
Define the continuous loading on each converter. Make sure do not exceed the converter maximum loading.
Determine from the graphs below the expected losses in watts per converter inside the device. The losses
depend on the input supply, the selected switching frequency, the output voltage and the converter chosen.
4. To calculate the maximum temperature inside the IC use the following formula:
THOT_SPOT = TA + PDIS · qJA
(4)
Where:
TA is the ambient temperature
PDIS is the sum of losses in all converters
θJA is the junction to ambient thermal impedance of the device and it is heavily dependant on board layout
xxx
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
1
1.2
I (A)
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
I (A)
Figure 17. Buck 1
VIN = 12 V, fSW = 500 kHz
VO (from top to bottom) = 5 V, 3.3 V,
2.5 V, 1.8 V, 1.2 V
Figure 18. Buck 1
VIN = 12 V, fSW = 1.1 MHz
VO (from top to bottom) = 5 V, 3.3 V,
2.5 V, 1.8 V, 1.2 V
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
15
TPS65270
SLVSAX7D – AUGUST 2011 – REVISED APRIL 2013
www.ti.com
1.6
1.6
1.4
1.4
1.2
1.2
1.0
1.0
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
1
1.2
I (A)
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
I (A)
Figure 19. Buck 2
VIN = 12 V, fSW = 500 kHz
VO (from top to bottom) = 5 V, 3.3 V,
2.5 V, 1.8 V, 1.2 V
Figure 20. Buck 2
VIN = 12 V, fSW = 1.1 MHz
VO (from top to bottom) = 5 V, 3.3 V,
2.5 V, 1.8 V, 1.2 V
Low Power Mode Operation
By pulling the Low_P pin high all converters will operate in pulse-skipping mode, greatly reducing the overall
power consumption at light and no load conditions. When LOW_P is tied to low, all converters run in forced PWM
mode.
Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.
Layout Recommendations
Layout is a critical portion of PMIC designs.
• Place VOUT, and LX on the top layer and an inner power plane for VIN.
• Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with
ground.
• The top layer ground area sould be connected to the bottom ground layer(s) using vias at the input bypass
capacitor, the output filter cpacitor and directly under the TPS65270 device to provide a thermal path from the
Powerpad land to ground.
• The AGND pin should be tied directly to the power pad under the IC and the power pad.
• For operation at full rated load, the top side ground area together with the bottom ground plane, must provide
adequate heat dissipating area.
• There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching
node, the output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
• The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.
Try to minimize this conductor length while maintaining adequate width.
• The compensation should be as close as possible to the COMP pins. The COMP and OSC pins are sensitive
to noise so the components associated to these pins should be located as close as possible to the IC and
routed with minimal lengths of trace.
16
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: TPS65270
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TPS65270PWPR
ACTIVE
HTSSOP
PWP
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS65270
TPS65270RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65270
TPS65270RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
TPS
65270
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jan-2015
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TPS65270PWPR
HTSSOP
PWP
24
2000
330.0
16.4
TPS65270RGER
VQFN
RGE
24
3000
330.0
TPS65270RGET
VQFN
RGE
24
250
180.0
6.95
8.3
1.6
8.0
16.0
Q1
12.4
4.25
4.25
1.15
8.0
12.0
Q2
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS65270PWPR
HTSSOP
PWP
24
2000
367.0
367.0
38.0
TPS65270RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
TPS65270RGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2015, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement