A HIGH SPEED DIGITAL COMPUTER

A HIGH SPEED  DIGITAL COMPUTER

A

HIGH SPEED DIGITAL COMPUTER

D I G I T A L E Q U I P M E N T C O R P O R A T I O N M A Y N A R D , M A S S A C H U S E T T S

Copyright 1965 Digital Equipment Corporation

FEATURES

INTEGRATED ALL-SILICON PROCESSOR CIRCUITS

All logic circuits of the basic PDP-8 are constructed from DEC's popular new FLIP CHIP modules.

FULLY PARALLEL ARITHMETIC OPERWION

Reliable high-speed transfers of data, and arithmetic and logical operations within the computer are effected in parallel.

CONTINUOUS DISPLAY OF ACTIVE REGISTERS

The content of the accumulator, link, memory ad- dress register, program counter, memory buffer register, instruction register, and major state gen- erator of the basic PDP-8 are continuously indicated by lamps on the operator console. The major regis- ters of optional processor equipment such as the extended arithmetic element and the memory exten- sion control are also indicated by lamps on the op- erator console with the addition of this equipment.

SINGLE STEP AND SINGLE INSTRUCTION MODES

Switches on the operator console allow a program to be advanced one instruction or one cycle at a time for classroom demonstration, program debugging, or maintenance purposes.

LINK BIT

To facilitate arithmetic operations a link bit is pro- vided so that a carry from the accumulator can be program sampled.

LARGE CORE MEMORY CAPACITY

The PDP-8 is a stored-program computer with a basic

4096-word core memory, capable of being expanded to 32,768 words in 4096-word increments.

INDIRECT ADDRESSING

Subroutine linkage and data accumulation is simpli- fied by the ability to specify addresses indirectly.

AUTO-INDEXING

Eight core memory registers serve as auto-indexing registers to facilitate program searching, multiple in put/output list processing, and sorting operat ions.

1.6 MICROSECOND CYCLE TIME

Instructions are executed in one or two cycles of 1.6 microsecond duration. Maximum execution time is

4.8 microseconds for instructions using indirect memory addressing.

MICRO-PROGRAMMABLE INSTRUCTIONS

All instructions which do not reference core memory

(which do not contain a memory address) can be micro-programmed; which allows the programmer to specify several shift, skip, or input/output transfer commands to be performed within one instruction.

PROGRAM INTERRUPT

Standard facilities of the PDP-8 allow a peripheral device to interrupt the operating program and initi- ate a subroutine.

HIGH

SPEED DATA BREAK

Facilities of the standard PDP-8 allow peripheral equipment to interrupt the operating program and effect data transfers to or from the computer core memory at a 1.6 microsecond per word transfer rate.

Slower transfers are automatically interlaced with execution of instructions in the main program.

PRE-WIRED OPTIONS

Optional equipment which is closely related to the processor, such as the extended arithmetic element, memory exteqsion control, and one of the analog-to- digital converter options, are pre-wired in the basic

PDP-8 so that the time, effort, and cost involved in adding these options at the factory or in the field is a minimum.

FLEXIBLE MECHANICAL DESIGN

Several physical configurations of the computer are available so that it can be used alone in the table model configuration, can be installed as a portion of a user's system by installation in any standard 19- inch electronic equipment cabinet, or can be pur- chased in a standard DEC computer cabinet with other optional equipment (see Figures 1 and

2).

CUSTOMER TESTED SOFTWARE

Software supplied with the PDP-8 has been use- tested in over 75 installations of the program- compatible PDP-5.

ONE-PASS FORTRAN SYMBOLIC COMPILER

A FORTRAN symbolic compiler which includes dy- namic error correcting mode for tape modification without recompiling is supplied with each PDP-8.

MACRO-8 SYMBOLIC ASSEMBLER

Programs can be written in a convenient, meaningful symbolic language consisting of user-defined macro- instructions for translation into machine language by the MACRO-8 program.

DDT-8 PROGRAM

This program allows a programmer to correct and improve a new object program by communicating with the PDP-8 in the source language, via the

Teletype unit.

SYMBOLIC TAPE EDITOR PROGRAM

Fast accurate checking, editing, and/or updating of a program can be accomplished with the aid of this program.

BUS 110 SYSTEM

Data, select code, and control signals which pass between the PDP-8 processor and peripheral equip- ment use bussed connections which simplify system cabling and permit system expansion without mak- ing changes to the processor.

BUFFERED INPUTIOUTPUT

All peripheral equipment contains an input/output buffer register for data to be transferred with the computer so that various devices can be operated simultaneously at their maximum speed. The proces- sor does not wait for a device to complete its cycle before continuing the program.

Figure 1

-

Model PDP-8 showing removeable covers and swinging palets that allow access t o all components.

Figure

2

-

Model PDP-8 showing sliding drawer that facilitates maintenance.

APPLICATIONS

PDP-8's functionally equivalent predecessor, the

PDP-5,

is being

used

for

the

following applications:

RESEARCH EXPERIMENTS

AND

MEASUREMENT

Pulse-height analysis

Time-of-flight and bubble-chamber measurements

General physics investigation and multichannel-multi- parameter analyzer

QUALIW CONTROL TESTING

AND

STATISTICAL ANALYSIS

Tensi le-strength testing

Electronic component testing

Analog

and

digital circuit module testing

Computer peripheral equipment testing

DATA ACQUISITION, LOGGING, REDUCTION,

AND

ANALYSIS

Oceanographic research

Biomedical research

Telemetry

Real-time analog signal monitoring

PROCESS CONTROL

Steel mill control

Typesetting

Chemical and Petroleum industry process control

Nuclear reactor monitor and control

DATA PROCESSING

Open shop computing

Hybrid processing

Media conversion

Multi-user time-shared computing

Message switching systems

Data

collection and processing from remote stations

EDUCATION AND TRAINING

The PDP-8 is an instruction-address, two's comple- ment binary computer which is ideally suited for teaching engineering and programming fundamentals in colleges, high schools, military and industrial schools.

Specific information about each of these applications can be obtained by contacting our Maynard office.

STANDARD PDP-8

FUNCTIONAL COMPONENTS

4

The standard PDP-8,

in

any physical configuration, consists of a processor, core memory, operator console, input/output facilities, and a Teletype input/output device. This equipment, shown

in

Figure 3,

constitutes

a complete

computer system

capable of performing

general purpose

computa- tions

and/or

control functions. Expansion of the system

by

addition of optional

equipment

can be

accomplished

to perform a specific

function

or to serve

in

a particular

application.

PROCESSOR

All logic and

arithmetic

operations, and

control functions

are performed by

the

processor.

The

major registers and

control elements

are as

follows:

Accumulator (AC)

The AC performs the major programmed arithmetic and logic operations and serves as the data input/output register. The AC also serves as a digital buffer register for the optional Analog-to-Digital Converter Type 189.

Link (L)

This one-bit register serves as an extension of the AC. The content of this register can be program sampled and program modified. Overflow into the L from the AC can be checked by the program to greatly simplify and speed up single and multiple precision arithmetic routines.

Program Counter (PC)

The PC determines the core memory address from which the next instruction of a stored program is to be taken. The sequence in which instructions are performed is called program control, and is determined by the PC.

Memory Address Register (MA)

The location in core memory which is selected for data storage or retrieval is determined by the MA. This register can directly address all 4096 words of the standard core memory or in any preselected field of extended core memory.

Memory Buffer Register (MB)

The MB serves as a buffer register for all information passing between the processor and the core memory, and serves as a buffer directly between core memory and peripheral equipment during data break information transfers. The MB is also used as a distributor shift register for the Analog-to-Digital Converter Type 189.

Instruction Register (IR)

When an instruction word is read from core memory the three most significant bits

(the operation code of all types of instructions) are loaded into the IR. The IR, then decodes the three-bit operation code and determines the basic functions to be performed by the computer, and determines the use to be made of the least signifi- cant nine bits of the instruction. When the operation code is decoded as octal num- ber

0

5, a memory reference instruction is specified so the least significant bits of the instruction are interpreted to select a core memory address for the operation. When the operation code is decoded as 68 or 78, an augmented instruction is designated so the least significant bits of the instruction serve as an extension of the operation code and are decoded into numerous microinstructions.

Major State Generator

One or more major control states are entered to determine and execute an instruc- tion. During any one instruction a state lasts for one computer cycle, or 1.6 micro- seconds. The major state generator determines the machine state during each cycle as a function of the current instruction, the current state, and the condition of the

Break Request signal supplied to an input bus by peripheral equipment.

Switch Register (SR)

Twelve toggle switches on the operator console provide a means of manually estab- lishing a word to be set into the computer. The content of the SR can be transferred into the PC as an address by pressing the LOAD ADDRESS key, or can be stored in core memory at the address contained in the PC by pressing the DEPOSIT key. The content of the SR can also be loaded into the AC under program control to allow program modification by programmed evaluation of the word manually set into the SR.

Output

Bus Drivers

All major output signals from the standard PDP-8, used in programmed and data break information transfers, are power amplified by bus driver modules to allow them to drive a very heavy circuit load.

CORE

Storage for instructions to be performed, or tor aata to be processed or distributed is

MEMORY

provided by the core memory. Core memory for the standard PDP-8 has a capacity of 4096 words, 12 bits in length. The PDP-8 is the only computer in its price range with a full-size coincident-current random-address, ferrite-core memory.

OPERATOR

Keys, switches, indicators, and the switch register on the operator console allow

CONSOLE

manual address and data storage, core memory data examination, the normal start/ stop/continue control, and single-step or single-instruction operation that allows each step or each instruction of the program to be monitored visually for demon- stration or maintenance.

EOUl

PMENT

USING

PROGRL

INPUT/OUTPUT

Standard equipment on the

PDP-8

includes facilities for instruction skipping, pro-

FACILITIES

gram interrupt, programmed data transfers, and data break transfers.

Instruction Skip Facility

This facility allows the program to modify itself, or branch, as a function of the content of the AC, the content of the L, or the status of external equipment. Instructions are included in the repertoire of each optional device that allow the program to sense the condition of the device and then skip or proceed to the next instruction as a function of the device status. This feature can be considered programmed decision ma king.

Program Interrupt Facility

This facility allows signals from external equipment to interrupt the program and initiate a subroutine that services the equipment issuing the signal. Operation using this facility speeds the transfer of the data and control information between the computer and peripheral equipment by allowing conditions in the equipment to initiate a transfer of program control to a subroutine that enacts a transfer, rather than waiting for the main routine to sample the condition and initiate the subroutine.

Programmed Data Transfer Facility

Normally data is transferred between the computer accumulator and an external device under program control. An input bus allows each device to clear the computer accumulator before transferring data into it.

Data Break Transfer Facility

Individual words or blocks of data can be transferred between a peripheral device and the computer core memory, via the MB, at a very rapid rate. A data break is entered upon receiving a Break Request signal and a Transfer Direction signal from the device. When the request is made the computer completes the current instruc- tion, then enters the Break state to enact the transfers. Transfers are performed during every computer cycle until the Break Request signal is removed by the device.

The core memory address of each transfer is specified by the peripheral device.

TELETYPE

A

Teletype

Model 33 Automatic Send Receive (ASR) set is included

in each

standard

INPUT/OUTPUT

PDP-8.

The

ASR set

transfers information

into the PDP-8 from

perforated

tape or a keyboard, and supplies output

information from

the computer in the

form

of perfor- ated

tape

and/or a

typed

message. The Teletype rate is 10 characters per second in

either direction.

STANDARD

PDP-8

INSTRUCTIONS

Instruction words are of two types: memory reference and augmented.

Memory reference instructions

store or retrieve data from core memory, while augmented

instructions

do not. All instructions utilize bits 0,

1,

and

2

to specify the operation

code.

Operation codes of O8 through 58 specify memory

reference

instructions and codes of 68 and

78

specify augmented instructions.

MEMORY

REFERENCE

INSTRUCTIONS

Since the standard PDP-8 system contains a 4096-word core memory, 12 bits are required to address all locations. To simplify addressing, the core memory is divided into blocks, or pages, of 128 words (ZOO8 address), A memory reference instruction can directly address any one of 256 words; 128 words on page 0 or 128 words on the current page. All other core memory locations are addressed indirectly. Word format of memory reference instructions is shown in Figure 4 and the instructions are listed in Table 1.

- . -

,

- .

.

OPERATION

CODES

015

c+,

MEMORY

-

PAGE

e

7

-

"

' s

I

I, t

T

ADORES

.

J

.

+'

INDIREGT

A'OORESSING

* ,

- L .

-

Figure

4 Memo; Reference lnstructkn Format

TABLE

1

MEMORY REFERENCE INSTRUCTIONS

Mnemonic Operation

Ey,"!On

Symbol Code (clsec,

Operation

ANDY

TAD Y

ISZ Y

0

1

2

3.2

Increment and skip if zero. The content of memory location Y is incremented b one. I f the resuft- ant content

O/Y equals zero, the content of the PC is incremented

by

one and the next instruction is

Mnemonic

Symbol operation

Eyg!On

Operation

(psec)

'Ode

3.2 Logicat AND. The AND operation

, is performed between the content of memory locatron Y and the content of the AC. The result is left in the AC the original con- tent of

the

A& is lost and the content of Y is unchetked. Cor- respondin bits of

the AC

and Y are operafed upon independntfy.

This ~nstwction often called ex- DCA Y tract or mask can be considered as a bit-by-bit multiplication.

3.2

Two's complement add. The con- tent of memory location Y is addeU to the content of Ute AC in two's com lement arithmetic The JMS Y result of this addition is heid in the AC the original content of the AC 'is lost and the content of

Y is unchan ed If there is a carry f r m A&, 'the link is com- plemented. Thts link feature Is ve useful iff multiple precision arghmetic. JMP Y

3

5

skipped. tf the resultant content of Y does not equal zem the program proceeds to the neit in- struction. The incremented content of Y is restored to memory. This instruction

is

useful for Sncrement- in$ operand addresses and in counting iterations,

3.2

Deposit and clear AC. The content of the AC

Is

deposited in core memory at address Y and the AC is cleared, The previous content of memory location Y is lost. This is the basic store instruction.

3.2

lum to subroutine The content of instruction is taken from core memory location Y linkage.

PC is. depokted in core memory location Y and the next

+

1.

This instruction is used for subroutine

1.6

Jump to

Y.

Address Y is set into

the

PC so that the next instruc- tion is taken from core memory address Y. The original content of the PC is lost. This instruction is used to transfer program control to randomly selected core memory locations.

*The time listed is for direct addressing. add onds to this time time.

1.6

microsec- to determine indirecf address execution

.

AUGMENTED

Instructions which do not reference core memory augment, or extend, the operation

~NSTRUCT~ONS

by causing various operations to occur as a function of the content of bits 3 through 11. Augmented instructions with a basic operation code of

6*

are input/

-

P I

*

output transfer (IOT) instructions which serve peripheral equipment. Augmented instructions with a basic operation code of are operate (OPR) instructions which deal with processing and sampling the information content of the AC and the

L.

Both of these instructions are microprogrammed, i.e., multiple operations can be specified and performed simultaneously according to the presence or absence of binary ones in bits 3 through 11.

INPUT/OUTPUT

Microinstructions of the IOT instruction addresses peripheral equipment to transfer

T~ANSFER

information with it or to initiate operations within

it.

This instruction contains a

6-bit device selection code and three bits which can be programmed to produce

INSTRUCTIONS

pulses in the selected device that effect a transfer or initiate an operation. Figure

5

shows this instruction format. When an operation code of

68

is detected the pause/ restart facility is used automatically to halt the program until the computer

generates

three command pulses at

1 microsecond intervals. These pulses are produced as a function of the content of bits 9, 10, and 11 of the instruction and are used to generate sequential command pulses in the selected device. Up to 64 individual devices can be selected to receive up to three command pulses, or up to 192 devices can each receive one command pulse. Use of the pause/restart facility allows IOT instructions to be performed in one computer cycle. The basic IOT microinstructions are listed in

Table

2,

:

Figure 5 IOT Instruction Format

TABLE 2 BASIC IOT MICROINSTRUCTIONS

Mnemonic &tat

Symbol Code

ION

IOF

ADC

6001

6002

Event

Time

Operation

PROGRAM INTERRUPT

Mnemonic

Symbol

1 Turn interrupt on and enable the TLS computer to res ond to an inter- rupt request. tion is given, the computer exe- cutes the next

en h i s instruc- instruction enables the interrupt.

hi then addi- tlonal instruction allows e x ~ t the iflterrupt subroutine before'

SMP

allowing another interrupt to occur.

CMP

2 Turn interrupt off i.e. disable the interrupt.

ANALOG-TO-DIGITAL CONVERTER TYPE 189

6004 3 Convert the analog a digital value. input signal to

CDF

KSF

KCC

KRS

KRB

TSF

TCF

TPC

I

6031

TELETYPE KEYBOARD/READER

1 Skip i f keyboard flag is a 1.

6032

6034

6036

2 Clear AC and clear keyboard flag. CIF

3 Read keyboard buffer static. (This is a static command i n that neither the AC nor the keyboard ftag is cleared.) The content of the TTI buffer is transferred into

AC4-11.

RDF

2, 3 Clear AC clear keyboard flag and read the'content of the keybard buffer into the content of AC4-11.

RIF

6041

TELETYPE TELEPRINTER/PUNCH

1 Skip i f teleprinter flag is a 1.

6042

6044

2 Clear teleprinter flag.

RIB

3 Load the TTO from the content of

AC4-11 and punt and/or punch RMF the character.

Octal

Code

6046

Event

Time

Operation

2, 3 Load the TT0 from the content of

AC4-11 clear the teleprinter flag and d r i n t and/or punch th; character.

6101

6102

MEMORY PARITY TYPE 188

1

Skip i f memory parity error flag

=

0.

2 Clear memory parity error flag.

MEMORY EXTENSION CONTROL TYPE 183

62N1

1

Change data field N. The data field register is loaded with the selected field number (0 to 7). All subsequent memory requests for o p e r a n d s a r e a u t o m a t i c a l l y switched to that data field until the data field number is changed by a new CDF command.

62N2 2 Prepare to change to instruction field N. The instruction field register is loaded with the se- lected field number (0 to

7).

The next JMP or JMS instruction causes the new field to be entered.

6214 3 Read data field into AC 6-8. Bits

0-5

and 9-11 of the AC are not affected.

6224

6234

3 Same as RDF except reads the tnstructron field.

3 Read interrupt buffer. The instruc- tion field and data field stored during

an

interrupt are read into

AC 6-8 and 9-11 respectively.

6244 3 Restore memory field. Used to exlt from a program interrupt.

'

OPERATE lNSTRUCTlONS

The OPR instruction consists of two basic groups of microinstructions. When bit 3 contains a binary zero, group OPR 1 is designated and

the

content of bits 4 through

11

is

decoded to cause clear, complement, rotate, and increment operations. When bit

3 contains a binary

one,

group OPR

2 is designated and the content of bits 4 through 11 is decoded to cause operations that check the content of the AC and the

L and continue to, or skip, the next instruction based on the results

of the

check.

Any logical combination of bits within one group can be microprogrammed

into

one instruction. Figures 6 and

7 show the format of group 1 and group

2 operate microinstructions,

and the

basic OPR microinstructions are listed

in

Table 3.

ROTATE

C

AND 1

RIGHT

K U l A l t 1

'OSITION IF A

l

POSITIONS

I F A

I

ROTATl

^"

PND

EFT

RTR

CML

CMA

CIA

Mnemonic Octal

Symbol Code

NOP

IAC

7000

7001

RTL

7004

7006

7010

7012

7020

7040

7041

CLL

CLL RAL

CLL RTL

CLL

RAR

CLL RTR

STL

7100

7104

7106

7110

7112

7120

CLA

CLA IAC

GLK

CLA CLL

STA

7200

7201

7204

7300

7240

Figure

7

Group

2

Operate Microinstruction Format

TABLE 3 OPERATE MICROINSTRUCTIONS

Event

Time

Operation Mnemonic Octal

Symbol Code

GROUP 1

-

NO operation. causes a 1.6 ~ s e c HLT program delay.

7402

2 Increment AC, The content of the AC is incremented by one in two's complement arithmetic.

2 Rotate AC and L left. The con- tent of the AC and the L are rotated left one place.

OSR 7404

2 Rotate two places to the left.

Equivalent to two successive

RAL operations.

2 Rotate AC and L r i ht. The con- tent of the AC and right one place.

1

are rotated

2 Rotate two places to the right.

Equivalent to two successive

RAR operations.

1 Complement 1.

1 Complement AC. The content of the AC is set to the one's com- plement of its current content.

1,2 Complement and increment ac- cumulator. Used to form two's complement.

SKP

SNL

SZL

SZA

SNA

SZA

SNL

SNA SZL

SMA

7410

7420

7430

7440

7450

7460

7470

7500

SPA 7510

1 Clear L.

1,

2 Shift positive number one left.

1, 2 Clear link, rotate two left.

1,2 Shift positive number one right.

1, 2 Clear link, rotate two right.

1 Set link. The L is set to contain a binary 1.

SMA SNL

SPA SZL

SMA SZA

SPA SNA

CLA

7520

7530

7540

7550

7600

1 Clear AC. To be used alone or in OPR 1 combinations.

1,2 Set AC

=

1

1, 2 Get link. Transfer L into AC11.

1

Clear AC and L.

1

Set AC

=

-1.

Each bit

AC is set to contain a

1. of the

LAS

SZA

CLA

SNA CLA

SMA CLA

SPA CLA

7604

7640

7650

7700

7710

Event

Time

Operation

GROUP 2

1 Halt. Stops the program. I f this instruction is combined with others in the OPR 2 group the computer stops immediately after completion of the cycle in process.

OR with switch register. The OR function is performed between the content of the SR and the content of the AC with the result left in the

~ d .

Skip unconditional The next insthiction is skipped.

Skip i f L # 0.

Skip i f L

=

0.

Skip i f AC

=

0.

Skip i f AC =#=

0.

Ski i f AC botR.

Skip i f AC

=

0, or L

=

1, or

#

O

and L

=

0.

Skip on minus AC. I f the con- tent of the AC is a negative number the next instruct~on is skipped.

Ski on positive AC. I f the con- ten! of the AC is a posltlve number the next instruction is ski p p d

Skip i f AC both.

<

0,

or L

=

1, or

Skip i f AC

Skip i f AC

Skip i f AC

>

0 and i f L

=

0.

5

0.

>

0.

Clear AC. To be used alone or in OPR 2 combinations.

Load AC with SR.

Skip i f AC

=

0, then clear AC.

Skip if AC

Skip i f AC

#

0, then clear AC.

<

0, then clear AC.

Skip i f AC

When the Extended Arithmetic Element Type 182 option is added to

the

PDP-8, a whole class of instructions is added to the OPR 2 instruction list. The extended arithmetic (EAE) microinstructions are specified by an operate instruction (operation code

7) in which bits

3 and 1 binary ones. Being augmented instructions, the

EAE commands are microprogrammed and can be combined with each other to perform non-conflicting logical operations. Format and bit assignments of the EAE commands are indicated in Figure 8 and the commands are listed in Table 4.

Fimre 8

EAE

Micrsinstructhn Format

TABLE 4 EAE MICROINSTRUCTIONS

Mnemonic Octal Event

Symbol Code Time

MUL 7405

DIV

NM I

SHL

ASR

7407

7411

7413

7415

Operation

Mnemonic Octal

Symbol Code

2 Multiply. The number held in the

MQ is multiplied by the number held in the next successive core memory location after the MUL command. At the conclusion of thls command the most slgnlficant

12 bits of the product are con- tained in the AC and the least significant 12 bits of the product are contained In the MQ.

2

5

M&

conclusion of the remainder is in contains a 1 divide over-

LSR

Divide. The 24.bit dividend held in the AC (most significant 12 blts) and the MQ least s~gn~ficant

12 bits] is divide6 by the. number held in the next successrve core memory location foltowmng the DIV command. At the fhis command the quotient

IS held

In the the AC and the L contains a 0.

If the flow occurred so the operat~on was concluded after the first cycle of the division.

LMQ

2

Normalize. This instruction is used as part of the conversion of a binary number to a fraction and an exponent for use in floating point arithmetic. The combined content of the AC and the MQ is shifted left by this one command until the content of ACO is not equal to the content of AC1, to form the fraction. Zeros are shifted into vacated M Q l l ~ o s i - tions for each shift. At the 'con-

MQA clusion of this operation the step counter contains a number equal to the number of shifts performed.

The content of L is lost.

2

Shift arithmetic left. This instruc- tion shifts the combined content of the AC and MQ to the left one position more than the number of positions indicated by the content of the next successive core memory lowtion following the

SHL command. Durin$ the shift- CLA in zeros aye shifted Into vacated

~ g i l

2 Arithmetic shift r i ht. The com- bined content of t i e AC and the

MQ is shifted right one position

7417

7421

7441

7501

7601

Event

Time

Operation more than the number contained i n the next successive core memory location following the

ASR command The sign bit con- enters vacated positions, the 'sign bit is pre- out of

M Q l l 'is losq and the L is un- disturbed durlng this operation.

2 Logical shift right. The combined content of the AC and MQ is shifted left one position more than the number contained in the next successive core memory lo- cation following the LSR com- mand. This command is similar to the ASR command except that zeros enter vacated positions instead of the sign bit entering these locations. Information shlfted out of M Q l l 1s lost and the L is undisturbed during this operation.

2 Load multiplier quotient. This command clears the MQ loads the content of the AC ihto the

MQ, then clears the AC.

2 Step counter load into accumula-

AC. The AC should be cleared prior to issuing this command or the CLA command can be com- bined with the SCA.

2 Multiplier quotient load into ac- cumulator. The content of the

MQ is transferred into the AC.

This command is given to load ths 12 least significant bits of the pioduct into the AC following a mult~pllcation or to load the uotient into the AC following a

AC should be cleared prlor to Issuing thls command or the CLA command can be combined with the MQA.

1

Clear accumulator. The AC is cleared during event time 1 al- lowing this command to be ;om- t h e o t h e r EAE commands that load the AC during event time 2 (such as SCA and

MQA).

The

programming

system for the PDP-8 consists of the MACROS Symbolic Assembler, FORTRAN

System

compiler,

Symbolic On-Line Debugging

Program,

Symbolic

Tape Editor,

Floating

Point

Package,

mathematical function subroutines, and utility and maintenance programs. All operate with the basic computer. Because the PDP-8 makes high-speed computing available to

many

new users, the

programming

system was designed to simplify and accelerate the process of learning to program.

At the same time, experienced programmers will find that it incorporates many advanced features.

The system is intended to make immediately available to each user the full, general-purpose data

processing

capability of the PDP-8 and to serve as the operating

nucleus

for a growing library of programs and routines to be made available to all

installations.

New techniques,

routines,

and programs are constantly being developed,

field-tested,

and documented in the Digital Program

Library for

incorporation

in users' systems.

MACRO*

The use of an assembly program has become standard practice in programming

SYMBOLIC

digital computers. This process allows the programmer to code his instructions in a symbolic language, one he can

work

with more

conveniently

than the 12-bit binary

ASSEMBLER

numbers which actually operate the

computer.

The assembly program then translates the symbolic language program into its machine code equivalent. The advantages are

significant:

the symbolic language is more

meaningful

and convenient to a programmer than a numeric

code;

instructions or data can be referred to by symbolic names without concern

for,

or even knowledge

of,

their actual addresses in core memory; decimal and alphabetical data can be expressed in a form more convenient than

binary

numbers; programs can, be altered without extensive changes; and debugging is considerably simplified.

The MACRO-8 Symbolic Assembler accepts source programs written in the symbolic language and converts core memory locations, computer instructions, and operand addresses from the symbolic to the binary form. It produces an object program tape, a symbol table defining memory allocations, and useful diagnostic messages.

Some of the outstanding features of this assembler are:

User-Defined MACROS: Groups of computer instructions required for the solution of specific operations or algorithms can be defined as a MACRO instruction by the user.

Double Precision Integer Pseudo Groups: Positive or negative double precision integers are allotted two consecutive core registers.

Double Precision Floating Point Constant: The format and rules for defining these constants is compatible with the format used by the PDP-8 Floating Point Package.

Operators: Symbols and integers may be combined with a number of operators

+ arithmetic plus

- arithmetic minus

: Boolean inclusive OR

& Boolean AND

- following a symbol indicating the following value should be assembled as an address

Literals: Symbolic or mnemonic literals (constants) are arranged automatically.

Variables: Variables can be assigned to page zero at any time and are assigned for the current page automatically.

Parameter Assignments: A symbol may be assigned the value of an expression.

Decimal and Octal Pseudo Operation Codes: The current radix may be specified by decimal or octal.

Text Facility: There are text facilities for single characters and blocks of text.

@

FORTRAN

The FORTRAN

(for

FORmula TRANslation)

System

compiler for the PDP-8 lets the

SYSTEM

user express the problem he is trying to solve in a mixture of English words and mathematical statements that is close to the language of mathematics and is also

COMPILER

intelligible to the computer. In addition to reducing the time needed lor program

preparation,

the compiler enables users with little or no knowledge of the computerQs organization and operating language to write effective programs for

it.

The FORTRAN

Compiler contains the

instructions

the

computer

requires to

perform

the clerical work of translating the FORTRAN

version of.

the problem statement into an object program in machine language. It also produces

diagnostic

messages. After compila- tion, the object program, the operating system and the data it will work with, are loaded into

the

computer

for

solution of the

problem.

The FORTRAN

language

consists of four

general

types of statements: arithmetic, logic,

control,

and input/output. Fixed and

floating

point arithmetic can be expressed in both simple and

complex

numbers. FORTRAN functions include addition, subtrac- tion,

multiplication, division,

sine, cosine, arctangent,

square

root, natural log, and exponential.

SYMBOLIC

On-line debugging with DDT-8

gives

the user dynamic printed program status infor-

ON-LINE

mation. It gives him close control over program execution, preventing errors

("bugs")

from

destroying

other portions of his program. He can monitor the execution of

DEBUGGING

single instructions or subsections, change instructions or data in any format, and

PROGRAM output

a

corrected

program at the end of the debugging session.

f4

Using

the

standard Teletype keyboardlreader and teleprinter/punch, the user can communicate

conveniently

with the PDP-8 in the symbols of his source language.

He can control the execution of any portion of his objkct program by inserting breaks,

- or traps, in

it.

When the computer

reaches

a break, it transfers control of the object program to DDT. The user can then examine and modify the content of individual core

memory

registers to correct and

improve

his object program.

SYMBOLIC

The Symbolic Tape Editor program is used to edit, correct, and update

symbolic

TAPE EDITOR

program tapes using the PDP-8 and the Teletype unit. With the editor in core memory, the user reads in

portions

of his symbolic

tape,

removes,

changes,

or adds instructions or

operands,

and gets back a

complete

new symbolic tape with errors removed. He can work through the program instruction by instruction, spot-check it, or

concentrate

on new

sections.

FLOATING'

The Floating Point Package permits the PDP-8 to perform arithmetic operations that

POINT

many other computers can perform only

after

the addition of costly optional hard- ware. Floating point operations automatically

align

the binary points of operands,

PACKAGE retaining the

maximum precision available by discarding leading zeros. In addition to increasing accuracy, floating

point operations

relieve the programmer of scaling problems common in fixed

point

operations.

This

is of particular advantage to the inexperienced

programmer.

MATHEMATICAL

The programming

system also

includes a set of mathematical function routines to

FUNCTION

perform the

following operations

in both single and double precision: addition, sub- traction,

multiplication,

division,

square

root,

sine,

cosine, arctangent, natural

logarithm,

and exponential.

UTILITY AND

PDP-8 utility programs

provide

printouts or punchouts of core memory content in

MAINTENANCE octal,

decimal, or

binary

form, as specified by the user. Subroutines are provided for octal or decimal data transfer and binary-to-decimal, decimal-to-binary, Teletype

PROGRAMS

tape conversion.

A complete set of standard diagnostic programs is provided to

simplify

and expedite

system maintenance. Program descriptions

and manuals permit the user to effectively test the

operation

of the computer for proper core memory

functioning

and proper execution of

instructions.

In

addition,

diagnostic programs to check the performance of standard and optional peripheral devices are provided with the devices.

OPTIONAL EQUIPMENT

Equipment available for inclusion in a devices, plotting and printing output machinery, CRT displays, analog-to-digital conversion equipment, magnetic drum and tape storage devices, communication equipment, and equipment housing hardware.

PROCESSOR OPTIONS

EXTENDED ARITHMETIC ELEMENT TYPE 182

This option consists of circuits that allow the PDP-8 to perform parallel arithmetic operations on positive binary numbers much faster than by programmed subroutine. The option multiplies two 12-bit unsigned numbers to obtain a 24-bit product in an average of 15.2 psec (including access), divides a 24-bit dividend by a 12-bit divisor to obtain a 12-bit quo- tient in an average of 30.2 psec (including access), and normalizes a 12-bit number in 1.6 psec

+

0.5 psec for each shift. When this element is added to the PDP-8 a whole group of microinstructions is added to the OPR instruction to permit automatic multiplication and division, and 24-bit shifting to normalize and scale arguments.

MEMORY EXTENSION CONTROL TYPE 183

The core memory address selection circuits are ex- tended by this option to allow addition of up to seven fields of 4096 words, or up to a total of 32,768 words.

MEMORY MODULE TYPE. 184

The basic PDP-8 core memory is extended by one field of 4096 words with the addition of each Type

184. From one to seven Memory Modules can be added to a PDP-8 containing a Memory Extension

Control Type 183. The Type 184A is a 12-bit, 4096- word core array similar to standard core memory.

The Type 184B is a 13-bit, 4096-word core array used to extend the memory of a system containing the Memory Parity Type 188.

MEMORY PARITY TYPE 188

Automatic checking of the transfer of each word between the processor and core memory is provided by this option. The Type 188 generates a 13th parity bit for each word written in core memory and checks parity during memory reading. A program interrupt is initiated upon detection of a parity error. With the addition of the Type 188 the standard 12-bit core memory and each field of extended memory (at additional cost), is replaced by a 13-bit core array to accommodate the parity bit.

DATA CHANNEL MULTIPLEXER TYPE 129

The Type 129 option expands the data break facili- ties of the computer to allow up to four input/output devices to transfer .data directly with the core memory, via the memory buffer register. Simulta- neous data break requests are serviced by the Type

129 according to a prewired priority.

READERS AND PUNCHES

HIGH SPEED PERFORATED TAPE READER

AND CONTROL TYPE 750

This equipment senses eight-channel, fan-fold, per- forated Mylar or paper tape photoelectrically at 300 characters per second. A Perforated Tape Spooler

Type 435 is available to facilitate use of rolled paper tape with the Type 750 in place of fan-fold tape.

HIGH SPEED PERFORATED TAPE PUNCH

AND CONTROL TYPE 75A

This equipment punches eight-channel, fanfold paper tape at 63.3. lines per second. A Perforated

Tape Spooler Type

436 option can be obtained to facilitate use of rolled paper tape with the Type 75A in place of fan-fold tape.

CARD READER AND CONTROL TYPE 451

Standard punched cards are read optically at up .to

200 cards per minute on the Type 451A or up to punched on the cards is read column by column in binary or alphanumeric

modes.

CARD PUNCH CONTROL TYPE 450

This device controls on-line buffered operation of a standard card punch machine, Cards are punched one row at a time at

40 millisecond intervals, pro- viding a punching rate of 100 cards per minute.

Any or all positions can be punched in any format.

PLOTTER

AND

PRINTER

INCREMENTAL PLOTTER CONTROL TYPE 350

One plotter selected from the following list of four models of California Computer Products Digital

Incremental Recorder can be operated from a DEC

Increment Plotter Control Type 350. Characteristics of the four recorders are:

Step

Size

(inches)

Speed

(steps/rninute)

Paper

Width

(inches)

The Type 350 provides high-speed plotting of points, continuous curves, points connected by curves, curve identification symbols, letters, and numerals under program control.

AUTOMATIC LINE PRINTER TYPE 6 4

This machine prints a selection of 63 characters on a

line of

120 characters at a rate of

300

lines per minute. Printing of one line of 120 characters can be carried out while the next 120

characters

are being loaded into the printer.

Loading,

printing, and format are under program control. Format is pro- gram selected from a punched format tape in the printer.

CATHODE

RAY TUBE

DISPLAYS

OSCILLOSCOPE DISPLAY TYPE 34B

Computer data can be plotted point-by-point

on

a

5-inch oscilloscope, such as the Tektronix Model

RM503, by this

option.

The horizontal axis of each

point

is determined by 10 binary bits, and the verti- cal axis is determined by another

10

binary bits.

This option

can

be obtained with or without the oscilloscope.

PRECISION CRT DISPLAY TYPE 3 0 N

The Type 30N is a

random-position

point-plotting

display with

a

self-contained,

16-inch CRT using magnetic deflection and focusing.

PHOTOMULTIPLIER LIGHT PEN TYPE 370

A fiber optic light pipe and photomultiplier

in

the light pen

allow

high-speed detection

of

information

displayed

on the Type 34B or 30N displays. Detec-

tion

of information by the Type 370 can be sampled by the

computer

to alter the program.

ANALOG

-TO-

DIGITAL CONVERTERS

ANALOG-TO-DIGITAL CONVERTER TYPE 1 8 9

This successive approximation

converter

uses the

AC

and MB of the computer for its

digital

registers and so provides an inexpensive device capable of selected accuracy

from

6 to 12 bits. This option is

wired

into the basic PDP-8 and

requires

modules

to

activate it. Analog input signal range

is

0 to

- volts.

GENERAL

PURPOSE

ANALOG-TO-DIGITAL

CONVERTER TYPE 1380

e*

Type 138D is a

high-speed, successive

approxi- mation

converter with

switch-selected

word length

from 6 to 11 bits and switch-selected. error from t 0 . 8 % to t 0 . 0 5 % . Conversion time varies from

6 to 45 microseconds according to these switch settings. Analog input signal range is 0 to 10 volts.

GENERAL PURPOSE MULTIPLEXER AND

CONTROL TYPE 1390

Up to 64 analog input channels can be selected for application t o the input of the Type 189 or Type

138D by the Type 139D. Channels can be program selected in sequence or by individual address. The number of channels that can be selected is deter- mined by the number of optional Multiplexer Switches

Type 15780 used in the Type 139D. Each Type

15780 can select four channels.

MAGNETIC DRUMS

AND

TAPES

SERIAL MAGNETIC

DRUM

SYSTEM TYPE 2 5 0

Blocks of 128 computer

words

are transferred be- tween the computer core memory and the Type 250.

Seven capacities are available

from

8,192

to

262,

144 words.

DECTAPE DUAL TRANSPORT TYPE 555

AND CONTROL TYPE 5 5 2

The DECtape system provides a unique fixed-address magnetic-tape facility for high-speed loading, read- out, and program updating. Each DECtape transport contains two independent tape drives. Up to four transports (eight drives) can be used with one control.

MAGNETIC TAPE SYSTEM TYPE 5 8 0

The Type 580 is a semi-automatic system consisting of a magnetic tape control and one magnetic tape transport. Data transfer with this system is com- pletely under program control and timing is con- trolled almost exclusively within this IBM-compatible system. Magnetic tape is read and written at 9,000 characters per second at a density of 200 bits per inch, or 25,000 cps at a density of 556 bpi.

AUTOMATIC

MAGNETIC

TAPE

CONTROL

TYPE 57A

Up to eight IBM or IBM-compatible tape transports can be used with the Type 57A to transfer informa- tion through the PDP-8 data break facility. Magnetic tape transports are controlled to read or write at densities of 200, 556, or 800 characters per inch at speeds of 75 or 112.5 inches per second.

MAGNETIC TAPE TRANSPORT TYPE 5 0

The Type 50 can be used with the Type 57A to read or write IBM-compatible magnetic tapes at transfer rates of 15,000 or 41,700 characters per second.

Tape speed is 75 inches per second at densities of

200 or 556 characters per inch.

-.

MAGNETIC TAPE TRANSPORT TYPE 570

The Type 570

is

a highly sophisticated tape trans- port that reads and writes at 75 or 112.5 inches per second at

program-selected

densities of 200, 556, or 800 characters per inch. Transfer rates of up to

90,000 characters per second can be obtained in

IBM-compatible

format.

The Type 570 contains a multiplex interface which

permits

time-shared use of the transport

by

two Type 57A tape controls on the same or different computers.

COMMUNICATION EQUIPMENT

DATA COMMUNICATION SYSTEMS TYPE 630

This system is a real-time interface between Teletype stations and the PDP-8 and is ideal for multi-user computer time-sharing, message switching systems, and data collection-processing systems. A variety of

Type 630 systems are available for half-diiplex and full-duplex operation with up to 64

stations.

EQUIPMENT HOUSING HARDWARE

EQUIPMENT CABINETS

The basic PDP-8 can be

housed

in a standard com-

puter cabinet

22

1/4

inches wide, 27

' / l 6

inches deep, and

691h inches

high. When

several optional

equip- ments are included in the PDP-8 system additional cabinets can be bolted together to

provide

an in- tegrated installation.

TABLES AND CHAIRS

Functional tables with adequate work space are

available

to support the table-model PDP-8 and the

Teletype

console,

or for installation on the front of

standard equipment cabinets.

Modern computer chairs are also available

E MODEL SIZE:

, and 21

1/4

32 inches high, 219'2 inches

POWER REQUIREMENTS:

115 volts, 60 cycles, 1 inches dee phase, 7.5 amperes for standard PDP-8 (can be construct

ABLE MODEL WEIGHT:

25 reauest).

220 volts or 50 cycles upon special

EONSOLE

nches wide,

31%

inches hieh. 1

V '

-

21

7/8

inches d

I L

OWER DISSIPATION:

780

watts

nches deep from front of con

3

vol

E O N S O L E MODEL WEIGHT:

ground a

ELETYPE SIZE (ON STAND): 33

inches high t o top

INTERNAL CIRCUIT POTENTIALS: f

console,

44Y4 inches high t o top of copy holder,

- volts.

2% inches wide, l8Y2 inches deep.

ELETYPE WEIGHT (WITH STAND):

40

~ O ~ I I U ~ .

STANDARD CABINET SIZE:

69% inches high, 22% inches wide (with end panels), and

271& inches

CYCLE T I M E :

1.6 deep.

STANDARD CABINET DOOR CLEARANCES:

inches at back.

1 4 %

WORD LENGTH:

12 bits

STANDARD CABINET WEIGHT:

two doors and two end panels)

225

TABLE (FOR TABLE MODEL) SIZE:

wide.

70%

inches

.INSTRUCTIONS:

8 basic instructions: 6 memory ref-

44 inches deepl and

27 inches high. merence and

2 augmented. The augmented instruc-

TABLE (FOR TABLE MODEL) WEIGHT:

100 are microp

TABLE

inches

27 inct

TABLE (FOR CABINET) WEIGHT:

75 po

TRAINING AND ASSISTANCE

Digital Equipment Corporation offers monthly courses in programming and maintaining each of its computer lines as part of the service provided to purchasers. These courses include instruction by experienced DEC personnel, training manuals, and supplies. Classes are kept small to insure ade- quate attention to individual students. DEC will assist you with specific programming problems before, during, and after installation of your computer and can provide a computer at our home office to permit you to check your programs under the guidance of DEC programmers.

DECUS LIBRARY AND NEWSLETTER

In addition to the Digital Program Library, users of DEC equipment have access to the growing

DECUS Library of utility programs, subroutines, and other programming materials. DECUS (for

Digital Equipment Computer Users' Society) was formed to promote a free and effective interchange of information. A principal channel for the dissemination of information is DECUSCOPE, a monthly technical newsletter t o which users contribute their ideas, techniques, routines, and program sum- maries. The DECUS Library distributes program descriptions and the corresponding program tapes and listings to members. Certification of these materials is under the direction of the users' program- ming committee, which also guides the operation of the Library. DECUS also publishes the proceed- ings of its annual symposiums and frequent seminars.

Z

ADDITIONAL INFORMATION

OTHER PDP-8 LITERATURE

The following PDP-8 literature is available upon request from DEC's maln office, or from any district sales office or representative. Upon request we will add your name to our PDP-8 literature distribution list so that you receive application notes and other current information.

USERS HANDBOOK, F-85:

contains computer organization information, detailed description of all instructions, basic PDP-8 programming data, and operating procedures.

.

INTERFACE BROCHURE:

contains detailed information on the interface characteristics of the PDP-8 in an easy-to-read format using many diagrams.

SOFWARE BROCHURE:

contains descriptive material and specifications for the programs supplied with each PDP-8 system.

INSTRUCTION LIST, F-86:

is a shirt-pocket list of all memory reference instructions, all augmented instruc- tions, the most common IOT instructions, and the ASCII code (used with most peripheral equipment).

FLIP CHIP MODULES CATALOG, C-105:

presents information pertaining to the function and specifications for the line of modules used in the PDP-8. This information is helpful in designing equipment to be connected to the PDP-8 or in learning the technical details of the circuits in the computer.

PRICE LIST, F-82:

contains current price information on standard PDP-8 optional equipment.

PRICE ESTIMATE

Your computer system requirements can be analyzed for implementation by a PDP-8 system by personnel from any of DEC's district sales offices or sales representatives.

DIGITAL SALES AND SERVICE

MAIN OFFICE AND PLANT

146 Main Street, Maynard, Massachusetts 01754

Telephone: From Metropolitan Boston: 646-8600

Elsewhere: AC617-897-8821

TWX: 71Q-347-0212 Cable: Digital Mayn. Telex: 092-027

DIGITAL SALES OFFICES

NORTHEAST OFFICE:

146 Main Street, Maynard, Massachusetts 01754

Telephone: AC617-646-8600 TWX: 710-347-0212

ANN ARBOR OFFICE:

3853 Research Park Drive, Ann Arbor, Mich. 48104

Telephone: AC313-761-1150 TWX: 810-223-6053

1259 Route 46, Parsippany, New Jersey 07054

LOS ANGELES OFFICE:

NEW YORK OFFICE:

8939 Sepulveda Boulevard, Los Angeles, Calif. 90045

Telephone: AC213-670-0690 TWX: 910-328-6121

Telephone: AC201-335-0710 TWX: 510-235-83 19 SAN FRANCISCO OFFICE:

WASHINGTON OFFICE:

1430 K. Street,

NW,

Washirrgton, D. C. 20005

Telephone: AC202-628-4262 TWX, 710-822-9435

SOUTH EAST OFFICE:

Suite 91, Hdiday Office Center

3322 Memorial Parkway, S.W., Huntsville, Ala. 3580

Telephone AC205-881-7730 TWX: 205-533-1267

2450 Hanover, Palo Alto, California 94304

Telephone: AC415-326-5640 TWX: 910-373-1266

I N CANADA:

Digital Equipment of Canada, Ltd.,

150 Rosamond Street, Carleton Place, Ontario. Canada

Telephone: AC613-237-0772 TWX: 610-561-1650

ORLANDO OFFICE:

1510 E. Colonial Drive, Orlando, Florida 32803

Telephone: AC305-422-4511 TWX: 305-275-0641

PITTSBURGH OFFICE:

300 Seco Road, Monroeville, Pennsylvania 15146

Telephone: AC412-35 1-0700 TWX: 710-797-3657

I N EUROPE:

Digital Equipment GmbH, Theresienstrasse 29

Munich 2/West Germany

Telephone: 29 9 4 07, 29 25 66 Telex: 841-5-24226

Digital Equipment Corporation

(UK) Ltd.

11 Castle Street

Reading, Berkshire, England

Telephone: Reading 57231 Telex: 851-84327

CHICAGO OFFICE:

910 North Busse Highway, Park Ridge, Illinois 60068

Telephone: AC312-825-6626 TWX: 312-823-3572

IN AUSTRALIA:

Digital Equipment Australia Pty. Ltd.,

89 Berry Street

North Sydney, New South Wales, Australia

Telephone: 92-0919 Telex: 790AA-20740

Cable: Digital, Sydney

I N THE SOUTHWEST:

DIGITAL SALES REPRESENTATIVES

DATRON ICS INC.

7800 Westglen Drive, Houston, Texas 77042

AC713-782-9851 TWX: 713-571-2154

IN THE NORTHWEST:

SHOWALTER-JUDD, INC.

1806 South Bush Place. Seattle. Washinaton 98144

Telephone: 206-324-7911 TWX: 206-$98-0323

DATRONICS INC.

Post Office Box 782, Kenner, Louisiana 70062

Telephone: AC504-721-1410

I N JAPAN:

RlKEl TRADING CO.,

12, 2-Chome, Shiba Tamura-cho, Minato-ku,

Tokyo, Japan

Telephone: 591-5246 Cable Rikeigood, Tokyo

DATRON ICS I NC.

Post Office Box 13384, Fort Worth, Texas 76118

Telephone: AC817-281- 1284 TWX: 817-281-3120

I N SWEDEN:

TELARE AB

Industrigatan 4, Stockholm K, Sweden

Telephone: 54 33 2 4 Telex: 854-10178

PRINTED IN U.S.A.

l o 2 6 8 3 3 0 7

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