# User manual | · . , DEC .

,

DEC

DEC

PER COPY

\$1.00

## digital equipment corporation

MAYNARD , MASSACHUSETTS

1960,

BY

DIGITAL EQUIPMENT CORPORATION

PRINTED IN THE UNITED STATES OF AMERICA

## INTRODUCTION

DEC Building Blocks are a coordinated set of digital circuits used for building and testing computer systems.

For use as test equipment , they are packaged for convenient patch cord interconnections. For use in systems, they are packaged in a unique plug-in unit construction. They are available in three compatible speed ranges with maximum frequencies of 500 kilocycles,

5

megacycles, and 10 megacycles.

DEC Building Blocks are designed to be easy to understand and easy to use. People with no knowledge of Boolean algebra can perform logical design with DEC Building

Blocks, and those who like to use Boolean mathematics can very quickly and easily implement their equations. Straightforward static logic is employed, and only a small number of modules is needed for most systems because of the high driving capability of each unit.

general logical

### principles

utilized are the same

all

Building Blocks.

### The

purpose of this booklet is to acquaint the

with these

### principles.

The rules governing loading will depend on the speed range of the equipment used.

### The

rules and illustrations in this

### book

are applicable principally to 500 KC and

5

MC Building Blocks.

3

DEC DIGITAL TEST EQUIPMENT ( TOP) AND DEC SYSTEM

BUILDING BLOCKS

4

## CONTENTS

. . .

. .

. .

.

.

5

7

15

16

17

17

23

28

32

32

Base

Input

~O,."'O,

Emitter

INVERTER

f

LEVEL - NEGATIVE

LEVEL - GROUND

---+

PULSE - NEGATIVE

~

PULSE POSITIVE

-cC

-d

### STATIC LOGIC

The logic used with DEC modules is "static." "ONES" and

"ZEROS" in this system are represented by two different DC voltage levels . The use of such a static system makes it possible to change the state of a system at any time. Logic is performed by the coincidence oflevels which are sampled by pulses. Unlike "dynamic" logic , where ONES and ZEROS are represented by the presence or absence of a train of pul s es, static logic is not tied to a fixed clock frequency and usually avoids precise timing problems.

### THE TRANSISTOR INVERTER

Most logical operations with DEC Building Blocks are performed with saturating PNP transistor inverters. When a junction transistor i s turned completely on or " saturated," the collector is practically a short circuit to the emitter of the transistor. If the emitter is at ground in this condition, the output from the collector will also be a t ground voltage.

When a junction transistor is turned completely off or "opened," the collector-to-emitter path is practically an open cir c uit.

If the collector is connected to a clamped load resistor , the collector will be at 3 volts.

-

3v 15 v

W

I

I

I

Out p ut

I

## "~

;:'.'

I

I

A

In verter r

Input

0-.-."".,...._ ....

I

.

1

+ 1 0 v

I

I

I l

FIGURE

2

FIGURE

1

Figure 1 is a schematic drawing of a DEC inverter and clamped load resistor. The capacitor shunting the input resistor is used to provide overdriving current to the transistor during input level changes, thus switching the transistor much more rapidly. The re-

7

sistor to +10 volts biases off the transistor to protect against noise voltage. The load resistor is clamped to -3 volts with a diode so that, when the transistor is off , the output signal is always at -3 volts regardless of the loading on the inverter output.

To simplify logic drawings, the symbology of Figure 2 is used.

When the input is negative, the output is "shorted" to ground.

When the input is positive or at ground level, the transistor is open circuited and the output, if connected to a clamped load resistor, is at 3 volts.

I nput

Output

l

## o",""

,

I n put _ _ _ _

FIGURE

3

The inverter switch is analogous to the mechanical switch, as shown in Figure 3. The logical designer can often build networks of inverters in the same manner as he would if he were using mechanical relays or simple switches.

A

B c

FIGURE 4

FIGURE

5

Figure 4 shows three mechanical switches connected in a series to form an "AND" circuit. All switches A and Band C must be closed in order to ground the output. Similarly, in the series inverter network of Figure 5, all transistor inputs A and Band C must be negative in order to short the output to ground . If any input in

Figure 5 is ground, that transistor will be an open circuit, and the output will be

3 volts. Therefore , the network also acts as an

"OR" circuit for ground levels.

8

If any of the switches of Figure 6 close, the output will be shorted to ground. If A or B or C in Figure 7 is negative, the output will be shorted to ground. Only if all inputs are at ground will the network output be negative. The parallel arrangement in Figure 7 is an OR gate for negative levels and an AND gate for ground levels.

I

FIGURE

6

FIGURE

7

Inverters can be stacked in complicated series-parallel combinations, like that of Figure 8, to perform sophisticated logical operations. There are some rules, however, since the inverters are not quite ideal switches. These rules are discussed in the sections beginning on Page 28.

C

A .......

C--".A...I

" " - " - " G

A---..~

Ho C+( B +A D) ( E+F ) G

H=C - [B (AT D )+E F+ GJ

FIGURE

8

### DIODE LOGIC

All logical systems could be constructed using only parallel and series combinations of transistors in inverter networks. However, as the number of inputs to a particular gate increases, it becomes more economical to perform the gating action with diode gates. The

9

outputs of diode gates are permanently connected to a transistor inverter which re-establishes the reference level after every gate.

Thus, DEC diode gates may be connected in tandem indefinitely.

Ao---KII---,---tL.U

B

o---iO---I

c

o---iO---I

o

o---iO---I

E

o---iO---I

F

o--.f<I--...I

FIGURE

9

DEC negative diode units are six-input diodes tied to an inverter, as in Figure 9, so that anyone of the input terminals can turn on the inverter. This makes a six-input OR circuit for negative levels or pulses because A, B, C, D, E, or F can turn on the inverter and "short circuit" its output. This, of course, also acts as an AND circuit for ground levels.

A

o---f>I---,-I

B

O---f>I--I

c

o---f>I--I

o

O---f>I--I

E

o---f>I---t

F

o---f>I----I

FIGURE

10

The positive-type diode circuit, Figure 10, provides an AND circuit for negative levels and an OR circuit for ground levels. This unit is available only in DEC System Building Blocks because

DEC Digital Test Equipment is usually employed in small systems and the economy resulting from the use of this type of unit is small.

10

### FLIP-FLOPS

FIGURE

11

If two grounded inverters are interconnected, as in Figure 11, a bi-stable "flip-flop" is obtained. When one side is cut off, its output is negative. This holds the other side on, which, in turn, holds the first side off.

FIGURE

12

If a grounded inverter A is connected to the off side B of the flipflop in Figure 12, the state of the flip-flop can be changed by pulsing the base of transistor A with a negative signal. This extra transistor will short the collector of transistor B to ground and will cut off transistor C, which will turn on transistor B. The flip-flop will then stay in that state even after the signal is removed from A.

Simple flip-flops, such as in Figure 12, can be used wherever the load on the output is light and economy is important. DEC System

Building Blocks Types 1213 and 4213 contain circuits similar to this one.

For general applications, it is desirable to have flip-flops with very low output impedance so that they can drive many other circuits. For this reason, most DEC flip-flops have buffer amplifiers on each side of the flip-flop.

11

FIGURE

1 3

A simple network is placed between the flip-flop in Figure 13 and the output amplifiers, which delays the change in the output. When the flip-flop is changed with a standard pulse, this delay is long enough so that the output does not change until after the pulse is over. This allows flip-flops to be sensed while they are being pulsed, which makes shift registers, counters and adders relatively simple.

FIGUR E

14

The symbol for a flip-flop is shown in Figure 14. In order to set the flip-flop to the desired state, the inputs at the bottom are

"shorted " through inverters to ground. When the input on the

ZERO side has been shorted to ground, the ZERO output is set to the -3 volt level and the ONE output is at ground. This is defined as the ZERO state. Similarly, when the flip-flop is in the ONE state , the ONE output is at -3 volts and the ZERO output is at ground.

P u l se

Input

FIGURE

15

12

Pul se

''"'--......... - I np ut

FIGURE

16

In p ut

Flip-flops are always changed by momentarily shorting an input to ground, as shown in Figure 15. The input to the inverter is a

DEC Standard Negative Pulse of 2.5 volts amplitude relative to ground.

To gate information into a flip-flop, two inverters can be connected in series, as in Figure 16. If the level input is at ground when the upper inverter is pulsed, the flip-flop terminal will not be shorted to ground; but if the level input is at

3 when the negative pulse arrives , the input is shorted and the flip-flop is cleared.

Since most DEC flip-flops have buffer amplifiers, it is permissible to use the buffer as the level gate . This added flexibility is useful since it allows reading into a flip-flop with only one inverter gate.

.......

~-P ulse

FIGURE

17

Figure 17 is a "jam transfer" gate employing DEC buffered flipflops. The contents of flip-flop A can be "jammed" into flip-flop B with a single pulse independent of the previous state of flip-flop

B.

The outputs of A are connected directly to the emitters of the pulse gates feeding the inputs of

B.

Both inverter pulse gates are pulsed simultaneously, but only the gate which has ground on its emitter will pass the pulse to set the flip-flop. For example , if flip-flop A holds a ONE, its ZERO output terminal will be at ground, allowing the right-hand gate to pass the pulse and set flip-flop B.

FIGURE

18

The shift register of Figure 18 is another use of the jam transfer gate of Figure 17. Since the outputs of the flip-flops do not change until the shift pulse has passed, no logical delays are needed between flip-flops.

13

When the inverters of Figure 19 are pulsed, the state of the flipflop will be changed or "complemented." On some of the DEC flip-flops this gating is done internally, and a complement terminal is brought out, as in Figure 20.

Complement

I n put

FIGURE

20

FIGURE

19

There is also a complement output terminal P which will deliver a DEC Stand ar d Negative Pulse every time the flip flop complement input is pulsed. This P pulse output is useful in counters and adders.

FIGURE

21

A typical counter arrangement using DEC complementing flipflops is shown in Figure 21. The pulses being counted enter on the right. They always complement flip-flop C and generate a standard pulse at P. This P pulse complements flip-flop B when flip-flop C

14

holds a ONE. When this P pulse gets through the gate and actually complements B, it will generate a P pulse out of

B.

The process is continued down the length of the counter. Only one inverter and one flip-flop are needed for each bit in the counter.

(.

Pulse

FI G URE

22

System Building Block flip-flops also have direct clear and set terminals which allow flip-flop registers to be set or cleared without the use of pulse gates on each flip-flop. The input to these terminals is a DEC Standard Positive Pulse of 2.5 volts amplitude relative to ground. These pulses can be produced by DEC delays, pulse amplifiers, clocks, and pulse generators. Figure 21 shows a register being set to 00100 using the direct inputs.

, /

### DELAYS

DEC Delay units are flip-flops which have only one stable state.

When the input terminal is "shorted" to ground by a Standard

Pulse, the level output terminal will switch from its normal ground level to the -3 volt level for a fixed period of time, which is adjustable. A standard pulse will be produced at the pulse output when the level output returns to its normal 0 volt condition. The pulse output comes from a pulse transformer which has both terminals available so that either positive or negative pulses may be obtained, depending on which terminal is grounded.

Level Output

L..-_.,J--uPulse Output

Pul se

~

Input

Level Output

-

-

~

J

Pulse Output

t

. r

--

## t ___

t

J

FIGURE

23

Typical waveforms for a delay unit are shown in Figure 23.

15

START

PULSE

FIGURE

24

Delay units are particularly useful in generating delayed standard pulses or signals of arbitrary width. The network of delays in

Figure 24 will produce the waveform in Figure 25.

FIGURE

25

### PULSE AMPLIFIERS

DEC pulse amplifiers are a powerful logical element because they not only amplify and standardize the shape of pulses but also gate pulses. When the same logical gating is to be done on a whole register of flip-flops, it often can be done once before the pulse amplifier drives the register.

~

-

+

~

26

FIGURE

The outputs of the pulse amplifiers come from pulse transformers, which have both terminals available so that either positive or negative pulses may be obtained, depending on which terminal is grounded. Positive pulses are used to direct set and clear flip-flops without inverters. Negative pulses are used for setting, clearing and complementing with inverters.

16

### CLOCKS

DEC clocks produce standard pulses from stable, variable frequency, RC-coupled oscillators which have a wide range of frequencies available. These clocks are often used as a primary source of timing for large systems. Where very precise timing is needed, crystal clocks which contain a single-frequency crystal oscillator are available.

I

Cl o ck i

~

+

FIGURE

27

### PULSE GENERATORS

DEC pulse generators are used to initiate action as a result of outside activity. Every time the input of these pulse generators goes more negative than

-231

volts after having been more positive than -1 volt, a standard pulse is generated. Most outside actions can be converted into voltage levels that will fill this criterion.

~

Pul se

G en

+

I

I

~1

E x t erna l

-:SWit c h

~.J

-15

FIGURE

28

It is difficult to generate a single pulse from a switch or relay closure because contacts bounce many times before they finally make a solid contact. If these are connected directly to a pulse generator, they will produce a pulse for each contact bounce. An integrating circuit is included which can be connected between the pulse generator and the contact. This circuit converts the many fast voltage changes into a single slow change, which generates a single pulse.

17

### COUNTERS

Building a counter with DEC flip-flops is straightforward due to the built-in delay and the availability of the P pulse terminal. A carry pulse is created when the P pulse is fed to the base of a gate which is conditioned by the ONE state of the flip-flop.

STRAIGHT BINARY COUNTING

' - : - I . . . o . . . - -

P ulses

T o

B e

FIGURE

2 9

STRAIGHT BINARY COUNTER

( DEC Flip-Fl ops Type 201, 1201, 3201, or 42 01 )

COUNTING

SEQUENCE o

0000

1 0001

2 0010

3 0011

4 0100

5 0101

6 0110

7 0111

8 1000

9 1001

10 1010

11 1011

12 1100

13 1101

14 1110

1 5 1111

When flip-flop D in Figure 29 is in the ONE state, its ZERO output terminal is ground. When it receives a complement pulse, the gate will pass a P pulse into the complement input terminal of flip-flop C.

If flip-flop D had been in a ZERO state , the P pulse would have been prevented from complementing flip-flop C. The series connection of P pulses and gates is the high-speed carry chain. The carry propagate time per digit is much less than the flip-flop's total transition time.

To assure that flip flop D will not be in the process of changing state while flip-flop C is receiving its carry pulse, a delay has been built into each flip-flop package. This insures that the ONE and

ZERO output terminals will not change until after the carry pulse has been gated.

Each bit of the counter requires one flip-flop and one transistor gate. There are two gates contained in each DEC Flip-Flop Type

201, 1201,3201, and 4201. If DEC Digital Test Equipment is used, the results can be read by means of the indicator lights on the

18

front panel. DEC System Building Blocks Types 1201 and 4201 are compatible with Indicator Driver s, Types 1675 and 1669, which are suitable for driving remote indicator lights.

~

SPECIAL COUNTS

Often it is desirable to build a counter that will produce a signal after a particular number eN ) of events have occurred. If

N

is an integer power of 2, the output is automatically produced by the final digit of a counter of appropriate length. If

N

is not a power of 2, gating must be performed to detect the desired number, generate a signal, and reset the counter to O.

P u l s es

GJI+---+-----Cil'll--C:~~:d

P .

FIGURE

30

ARBITRARY COUNT COUNT OF

11 ~LLUSTRATED

( DEC Flip-Flops Type 201, 1201, 3201, or 4201 )

Transistor inverter gates or diode gates may be used to sense the number N-1, close the input to the counter, and re-route the

Nth input pulse so that it will clear the counter and generate an output signal. Although this is not always the optimum method, it is a completely general method which will work for any value of

N.

19

Pul s e s

UL~-+----~uu~--ToBe

Counted

COUNTING

SEQUENCE o

I

00

2 10

FIGURE

31

COUNT OF

3

( DEC Flip-Flop s Type 2 01 , 1 2 01 , 3201, or 4201 )

A typical counting sequence is shown for N

=

3 in Figure 3l.

The progress of the count is shown in the table. When the count of

2 is reached, the next pulse will clear the counter and generate an output signal.

Co unt Of 2 Cou n t of 3

__

------~Jl~------

__

Pul ses

T o B e

C o u n t ed

COUNTING

S EQUENCE o

000

1 001

2 010

3 011

4 100

5 101

FIGURE

32

COUNT OF

6

( DEC Flip Flops T y pe 2 01, 1201 , 3 201 , or 4 2 01 )

A counter for 6 is made from the counter for 3 by preceding it with a binary counter ( Figure 32 ) . Examination of the c ounting sequence shows that the least significant digit alternates between

ZERO and ONE, while the two most significant digits follow the same pattern as the count of 3. The circuit for flip-flops A and B is identical to that for the count of 3 except that two additional gates are necessary. These are required because the input to the countof-3 portion includes a conditioning level, as well as a pulse .

20

BINARY CODED DECIMAL COUNTING

COUNTING

SEQUENCE o

000

1 001

2 010

3 011

4 100

Pulses

~--+----------------[~'--ToBe

Counted

\

I

FIGURE

33

COUNT OF

5

(DEC Flip-Flops Type 201, 1201, 3201, or 4201 )

From the simple count-of-5 circuit, binary coded decimal counters may be generated.

Count of 5

## ------------~~------------

r---o() ' \

Count Of 2

Pulses

........

,~.---

To Be

Counted

COUNTING

SEQUENCE o

0000

1 0001

2 0010

3 0011

4 0100

5 0101

6

0110

7 0111

8 1000

9 1001

I

,

FIGURE

34

COUNT OF

10 -

BINARY CODED DECIMAL

( DEC Flip-Flops Type 201 , 1201, 3201, or 4201 )

To give a count of 10, the counter for 5 is preceded by a binary counter (Figure 34 ) . This circuit is compatible with DEC 's BCD

Decoder and Light Driver Type 1671, which has 10 output lines for driving a decimal output display.

A counter for 100 can be made by cascading two BCD stages.

Be cause the complement input to A is used only at the time the decade is cleared, the P pulse can feed the next stage without being gated. Any number of BCD stages may be cascaded in a similar manner.

21

DOWN COUNTERS

.. 0

Pul ses

·--;--""'O"--T o B e

Co un ted

D o w n

FI G URE 35

DOWN COUNT E R

( DEC Flip-Flops Type 201 , 1 2 01 , 3201 , o r 4 2 01 )

In a down counter , each successive pulse will decrease the count by 1. The method for building a down counter is es s entially the same as that used in the up counter , except that each flip-flop input is conditioned by the ZERO state of the previous flip-flop. In this way, the P pulse chain will form a high speed borrow circuit instead of a carry circuit.

Cou n t e r

H as Ove r f l owed

C o u n ter H a s

G one N ega t i ve

F IG URE 3 6

BI N A RY U P -DOWN COUNTER

( DEC Flip-Fl o p s Type 1 2 01 or 4201 )

22

An up-down counter combines the technique s found in the individual up and down counters. This is made possible by use of

DEC Flip-Flops Type 1201 or 4201. Each of these units contains a flip-flop with two independent sets of complement and associated

P pulse terminals. Thus , it is possible to connect one set to form a high-speed carry circuit, while the other set forms a high-speed borrow circuit. Of course , the add and subtract pulses should not be allowed to arrive simultaneously.

10

MEGACYCLE COUNTING

FIGURE

3 7

10

MC BINARY COUNTER

( DEC Fl i p-Flops Type 52 01 or 6201 )

The logic behind a 10 MC counter is the same as that for a 5 Me or 500 KC counter ; however, the loading rules differ . Two inverters are required for each bit. The pulse must go to the lower inverter, as shown , to insure sufficient pulse gain to propagate the carries.

Only one 10 MC flip-flop is needed for counting at 10 megacycles where carry propagate time is not important. Such a mixed system is shown in Figure 38. In the transition from one type of equipment to another, a pulse amplifier with feedback is required to lengthen the pulse.

Addition of the contents of the incident number register to the contents of the accumulator is accomplished in two discrete steps, a half-add and a carry. This is made possible by using DEC

Flip-Flops Types 1201 or 4201 as in Figure 39. These units have two discrete complement inputs, each with its own P pulse terminal.

The first step is half-add. Each digit of the accumulator is complemented if the corresponding digit of the incident number is a

ONE.

23

-

5~~r7e~ ~~ ~ oG~r B 4 L ~~ K S ~

- - - - - - - - - - -

5 M C B L D G. BL OCK S

S erie s 1 00 or 1000

-=-

_ 1 0 M e BLD G . BL OCK S _

S e ri es 5 0 00 o r 6000

-=-

FIGURE

38

10

MC COUNTER, MIXED SYSTEM SHOWING PULSE STRETCHING

( Lower cost t h an Figure 37 c ounter, b u t longer prop a gate time )

~

1 0 MC

40 NS

Pu lses

-=-

t-:)

01

" . . .

Carry to Next

Stage, o r End

"<E--,...-+--.

A r ound Carry

.. £::]..

."

£::]..

,"

Ca r ry

(Step 2)

End Around

Carry

FIGURE

39

(Accumu lato r Flip-Flops DEC Type 1201 or 4201)

The second step is carry . A carry will be generated if a digit in the accumulator is ZERO and the corresponding incident number digit is ONE. A carry will be prop a g a ted if an accumu l ator digit is ONE and it a l so receives a carry pulse from the next less signif icant accumulator digit . Mter the carrie s have propagated , the contents of the incident number register may be modified to add another number to the accumulator.

Table I provides some examples .

In c i dent

Numb er

001

001

001

Ori g in a l

A cc umu la tor

Numb e r

010

001

011

A cc umula t or

Af ter Half-A dd

011

000

010

TABLE

I

Accumu lato r

Af te r C a rr y

011

010

100

Variat i ons of t h is technique can be used to make a subtracter, a multiplier, a divider, etc . A faster adder can be built by using

10

Me

Flip Flops Type 6202, as shown in Figure 40.

Carry to N ext

+-

### -----,....-------

.....

- - - - - - - r 4 - - -

Carry

(S t ep 2)

Stage, or E nd

Around Carry

FIGURE

40

10 MC

FLIP FLOPS

(Accumulator F l ip F l ops DEC Type 6202 )

2 6

L..-_ _ nd Around

Carr y

In c i den t N umber

R egister

### SUBTRACTER

An adder may be used for subtraction as well as addition. To subtract a number from the accumulator, the number is made negative and added to the accumulator. The steps involved in performing a subtraction depend on whether the "one's complement" or the "two's complement" number system is used to represent a negative number.

The "one's complement" number system is easiest to implement.

To subtract a number from the accumulator, the steps are: ( 1 ) complement the incident number, ( 2 ) h a lf-add , and ( 3 ) carry. With this number system it is necessary to implement an "end-around carry" from the most to the least significant digit. This connection is shown in Figures 39 and 40.

Subtraction is performed in DEC's PDP computers by ( 1 ) complementing the accumulator, ( 2 ) half-add, ( 3 ) carry, and ( 4 ) recomplementing the accumulator .

c onv ~e~rt+-

____

-+ __

__

~~Jr

### ;-______

"~~~

FIGURE

41

GRAY-To-BINARY CONVERTER

(DEC Flip-Flops Type 201, 1201, 3201, 4201, 4209, 5201, or 6201)

A frequent problem in digital control work is to convert a Gray coded number, such as a shaft position, into a pure binary number so that it can be used conveniently in arithmetic operations. The

DEC converter begins examination with the most significant bit

27

and proceeds down the line, making use of two basic conversion principles: (1) the most significant digit is identical in Gray and binary and (2) if a digit is a 1 after being converted to binary, the following digit is complemented.

The DEC converter does not require any shifting or transferring of information. All logic is done by means of inverter gates, arranged in such a way that the convert pulse will simultaneously convert all digits from Gray to binary.

### INVERTER USAGE

5 MC

AND

500 KC

BUILDING BLOCKS

Saturated inverters are usually considered as simple switches when designing logical networks, but because they are not ideal switches, there are certain limitations which have to be taken into account. The voltage drop across saturated inverters is not zero; it is closer to 0.1 volts. As a result, inverters cannot be stacked indefinitely. Three inverters is the maximum which can be put in series if the output is to drive another inverter, as in Figure 42.

FIGURE

42

FIGURE

43

If inverters are in series with the output of a flip-flop, as in

Figure 43, the flip-flop buffer inverter is considered to be one of the three allowed series transistors.

When the output of a series of inverters is driving the input of a flip-flop, pulse amplifier or delay unit, as in Figure 44, four transistors can be placed in series where the fourth transistor is the pulsed inverter.

It is important to note that a clamped load resistor is tied to the

28

emitter of each pulse transistor when it is being driven from an inverter or a network of inverters, as in Figure 44.

*

FIGURE

44

Because inverters are not really ideal switches, each collector of a series string of DC inverters supplying a pulse inverter will go somewhat negative during the pulse. This means that, if a series of inverters is supplying both pulse current and a DC signal, care must be taken because a signal will occur in the DC output during the pulse.

FIGURE

45

In Figure 45, when the input C is negative, flip-flop A should be set by the pulse, but flip-flop B should not be set. However, during the pulse, collector E of the DC inverter feeding flip-flop A will go slightly negative. It will partly turn on the DC inverter feeding flip-flop B, and sometimes it will set flip-flop B as well as flip-flop

A.

This network will work only if the pulses are not simultaneous.

*The clamped load resistor is not n ee ded in 5 megacycle circuitry when the pulse inverter is driven from a single series of inverters and the length of wire between inverters is short .

In the 500 KC line this clamped load resistor can be replaced by a IN276 diode from the emitter of the puls e inverter to ground, connected so as to prevent this point from going positive .

29

FIGURE

46

The network shown in Figure 46 will work whether or not the pulses are simultaneous. Two additional inverters have been added so that collector E will no longer be pulled negative by the pulse, since the pulse current will now come directly from ground instead of collector E.

(If both outputs are feeding the same flip-flop, the network shown in Figure 45 can be used safely because the output of the A side will be much greater than that of the B side.

)

To facilitate the design of systems, a number of simple loading definitions and rules have been made. These do not cover all possible configurations, but they do serve as a useful guide.

A "BASE LOAD" is the current which must be taken from the base of a DC inverter to keep it in a saturated state. In this condition the inverter base input terminal is at 3 volts, the transistor base is at ground, and 1 rna current is drawn through the 3000 ohm base resistor.

Inverter load resistors, when clamped at 3 volts, have about 12 volts across their 1500 ohms, and they can accept about 8 milliamperes of current. Ideally, this would drive 8 units of BASE

LOAD, but tolerance considerations limit the number to 7.

A "PULSE LOAD" is the load presented to a pulse source when driving the base of an inverter.

Pulse amplifiers are usually limited to driving 16 pulse bases.

This number should be decreased if the bases are widely separated, and it can be increased to 18 if they are all close together. The

30

series inductance and shunt capacity of the connecting wires can make the pulses at the end of a string of bases either large or small.

Consequently, when a number near the maximum is being driven, the pulse amplitude should be carefully checked after installation.

A terminating resistor in the 100-to-300 ohm range is desirable to reduce ringing on a heavily loaded pulse line.

A "PULSE LOAD" is also the load seen by a pulse source when driving one direct set or direct clear input of a flip-flop. The loading on a pulse source is approximately the same as when driving a base.

One pulse source, of course, cannot drive both direct inputs of flipflops and inverter bases because the direct input pulses are positive from a normal ground level and base input pulses are negative from a normal ground leveL

A "PULSED EMITTER LOAD" is the load seen by the collector of an inverter driving the pulse input to a flip-flop, pulse amplifier or delay. The pulse current goes through all the inverters in series with the pulse input, and it should be assumed to be the load on each of the series inverters.

A "DC EMITTER LOAD" is a load seen by the collector of an inverter driving a clamped load resistor. This load is also seen by the collector of an inverter which is driving an emitter in a network of inverters which is terminated by a clamped load resistor.

FIGURE

47

The collector of an inverter driving an emitter in a network of transistors must also supply the base current leaving the inverters higher in the chain. This number is normally small, but in complex networks it must be considered. An inverter can drive no more than one clamped load resistor and six bases of "on" inverters. Since transistors are almost symmetrical, this "on" base current can also flow through the collector of a transistor whose emitter is open, as shown in Figure 47. In this case, the collector of the bottom "on" transistor must carry the current A from the load resistor and the base currents from

B,

C and D.

31

### MARGINAL CHECKING

Marginal checking is used in a system to find the margin of safety between the condition of a system and the point of failure. Marginal checking is normally used in routine maintenance to find deteriorating components before they cause system failure. In many instances routine marginal checking is not necessary due to the long life of modern transistors, but it is still invaluable in debugging a new system. Without marginal checking, a system may be assembled with a number of mistakes which do not cause failure but which do not provide the system with as much margin as it should have .

In systems made with DEC Building Blocks , the +10 volt bias on inverters is varied for marginal checking. In most Building

Blocks , the +10 inputs are broken into two groups to make possible most critical marginal checking. In large systems , like the DEC

Programmed Data Proce s sor, the +10 lines to the Building Blocks are broken down into several groups so that small portions of the system can be marginal checked at one time.

If the inverter transistor has marginal gain, it will fail when the

+

10 supply is increased less than 5 volts because the drive to the base of that transistor is lessened.

Reducing the positive bias on an inverter will detect noise on the inverter input or a condition where the input does not come sufficiently close to ground. Normal margins on a system are plus and minus 5 volts on the +10 volt supply.

### INDICATORS

In most systems an indicator lamp is connected to each flip-flop to show its logical state . In DEC Test Equipment the indicator lamps are built into the flip-flop unit s with their own transi s tor drivers.

Types 1669 and 1675 plug-in units are used to drive indicators with the System Building Blocks. The indicator drivers are power transistors in an inverter circuit, very much like a logic inverter except that the 3000 ohm resistor in the base is not bypassed with a capacitor . In the high speed lines, the 3000 ohm resistor is included in the flip-flop package and not in the 1675 package to avoid capacitive lo a ding on the flip-flop output . However , in the low speed line the base resistors are included in the 1669 package

.

The load of the inverter is the incandescent lamp, which is tied to the 15 supply. When the inverter is on, the full 15 volts is across the lamp bulb. Normally, a GE 327 aircraft-type indicator

32

lamp bulb is used. This is a conveniently small bulb with very good life characteristics. It is rated at 24 volts, but when operated at 15 volts the light output is pleasant, and the life of the lamp is very long.

The DEC Type 1671 BCD Light Driver is designed to drive a decimal display from either a binary coded decimal register or a

Gray coded decimal register. This unit decodes a decade ( four flip-flops ) into ten lines and amplifies the output. The output will produce up to 150 milliamperes at 20 volts . This is sufficient for a GE 47 lamp, su c h as those used in the Industrial Electronic Engineers Model 10000-47 decimal display unit.

### BOOLEAN ALGEBRA

Boolean algebra was introduced in 1847 by an English mathematician, George Boole. The purpose of the algebra was to find a shorthand notation for the system of logic originally set forth by

Aristotle. Ari s totle's system dealt with statement s which were considered to be either true or false, but never partially true or false . Boole's algebra was based on a single valued function with two discrete possible states.

Boolean algebra lay almost dormant until recent times. Today , however, it is gaining widespread recognition as an efficient method for handling any single valued function with only two possible states . When it is applied to binary arithmetic , the two states are

ZERO and ONE. When discussing a switch, the two values are

OPEN and CLOSED. r

= 0

FIGURE

Bl

The convention used will be that the OPEN state corresponds to the ZERO state while the CLOSED state corresponds to the

ONE state.

33

OR FUNCTION

C

A +B= C

0+ 0 = 0

0+ 1 = 1

1

+

0

=

1

1 + 1 = 1

FIGURE

B2

If two switche s ,

A

and

B ,

are connected in parallel to form a gate, inspe c tion shows that the gate can only transmit information if A or

B

or both are in the transmitting state , i.e., CLOSED.

This is written in equation form as

A +B

= C

( A

or

B

equals C )

Figure B2 shows the parallel combination of two switches along with its equivalent inverter gate and a table giving the value of C for all possible values of

A

and

B.

C

(A +B ) + C A+(B+C )

FIGURE

B3

A+B+C

By adding a third gate in parallel, as in Figure B3, it becomes obvious how the OR function may be extended to any number of variables. This figure also serves to illustrate that the commutative and associative laws are valid for the OR function, i.e.,

A+B=B+A

(A

+

B )

+

C ==

A

+

(B

+

C ) ==

A

+

B

+

C

34

AND FUNCTION c;

AS

=

C

00 = 0

0 1= 0

1 0= 0

1 1

=

1

FIGURE

B4

If two or more gates are placed in series , the result is known as an AND gate . Inspection of the arrangement in Figure B4 shows that the resulting gate will transmit only if both A and Bare

CLOSED , i.e.

, equal to ONE. The equivalent equation in Boolean form is

AB

=C

( A

and

B

equal C )

A ( SC ) _ AS C _ C S A

FIGURE

B 5

Figure B5 demonstrates how the AND function is applied to more than one variable. The commutative and associative laws also hold .

AB =BA

A ( BC )

==

(AB )

C

==

ABC

35

IDENTITIES

1 +A=1

A

!

0

~

y

O+A=A

A r r

1A=A OA=O

\

\

# "

~ , y

A(B+C)

FIGURE

B6

\\

\" \ '

AB+AC

To enable the simplification of Boolean functions , there are many identities which are helpfuL

In

Figure B6, the combinations of switches and corresponding equations demonstrate these identities.

COMPLEMENT

If two gates are connected so that the same signal will open both of them or close both of them simultaneously, then the switches are given the same symbo L If two gates are connected so that a single signal will open one gate while closing the other gate, and vice versa, then these gates are said to be the complement of each other. Thus , if one gate is labeled A, the other gate will be labeled

A

36

if

An entire function may also be complemented. For example, then

C =

A(B

+

C)

C

=

A(B

+

C )

The use of one label for more than one gate makes the following identities helpful:

A+A=A A+A=l A=A

AA =A AA =0

DE MORGAN'S LAWS

Two unique laws whi c h can be applied only to Boolean algebra are known as De Morgan's laws.

A

+

B

+

C

+ .

.. +

N

=

ABC

. ..

N

ABC

. ..

N

= if

+

B

+

C

+ ... +

N

These laws may be verified by constructing a table of various possible values.

BOOLEAN ALGEBRA FOR USE WITH VOLTAGE LEVELS

Since DEC voltage levels have only two poss i b l e v a lues , Boolean algebra can a l so be useful in the study of these levels.

FIG URE

B7

The basic unit of DEC Logic is the transistor inverter. The simplest use of the inverter is to perform a complement. If the emitter is at ground and a signal is applied to the ba s e, the resulting output is the complement of the base input .

37

A B C D E

Negat i ve Or G ate

A +B+ C +D+E+F=G

F

A B C D E

N egative An d

Ga te

ABCD E F=G

FIGURE

B8

F

A simple OR gate is formed by means of diodes, as shown in

Figure B8 .

If A or

B

or C or

D

or

E

or

F

or any combination of these is negative, the resulting output is negative.

A similar unit with the diodes reversed will form an AND gate.

Only if

A

and Band C and

D

and

E

and

F

are negative will the resulting output be negative.

Inspection of these diode units shows that the AND and OR gates will be interchanged if the levels are defined in the opposite manner. Th at is, if ground is defined as a ONE and negative is defined as a ZERO. This is a demonstration of De Morgan's law .

C

C

B

And Gate

AB=C

B

Or Gate

A+B=C

FIGURE

B9

If the signals are manipulated without the encumbrance of a permanent sign convention, the same gate may perform many functions. Figure B9 shows an inverter which serves as an AND gate if the following definitions are used:

A

= 1 if negative,

B

= 1 if ground, C =1 if ground. The same transistor can be used as an

OR gate if the opposite definitions are made, i.e.:

A

=

1 is positive ,

B

= 1 is negative , and C = 1 is negative.

For this reason, DEC uses the sign convention that the diamond arrowheads on signals indicate the required polarity for the desired a cti on . A solid diamond denotes a 3 volt level for assertion, while a hollow diamond denotes a ground level for assertion. By using this method, it is possible to combine amplification and gating without added inversions as would otherwise be necessary.

Several illustrations are shown in Figure BIO.

38

r-----~----~~C

A+B=C AB=C

B

AB=C

C

B

C

A+B=C

FIGURE

B10

C =AB+AEi

C=AB+ A B

39

! ,.,

'<;,/

.

'