Manual 21099939

Manual 21099939

r ·-

RICE UNIVERSITY COMPUTER

BASIC MACHINE OPERATION

January,

1962

The computer .described in this publication was constructed under UNITED STATES ATOMIC ENERGY

COMMISSION CONTRACT AT-(40-1)-1825.

r·---

:..

TABLE OF CONTENTS

SECTION

I

VII

VIII

IX x

XI

II

III

IV v

VI

XII

Computer Organization

Octal Notation

Numerical Word Structure

Arithmetic Section

Con.trol Section

Addressing System

Instruction Word Structure

Examples of Single Instructions

Special Registers and Tags

Magnetic Tapes

Binary Point Location and-Floating Point

Arithmetic

Manual Controls

,\\

MEMORY

UNITS

(4)

PARITY CHECK

CONSOLE

LIGHTS PAPER TAPE READER

MAGNETIC TAPE UNITS (4)

RICE COMPUTER

FLOOR PLAN AND INFORMATION FLOW

SCALE: 1"

=

APPROX. 3

1

- - D A T A

--CONTROL

FIG. 1

I .

COMPUTER,ORGANIZATION

The modern digital computer consists of five distinct groups of equipment which perform the following functions:

( 1) input

(2) memory or storage

(3) arithmetic

(4) control

( 5)

OU t put

The input section consists of a photoelectric reader which reads information from punched paper tape and stores i t in memory and an electric typewriter which can be used to type information into the arithmetic and control sections.

The arithmetic unit is always an intermediate in the flow of input information to memory. The information in question may be artything which can be stored in memory: numbers, instructions or alphabetical and numerical comment~.

The memory is an information-holding device composed of electrostatic storage tubes. One memory contains

56 storage tubes and is subdivided into distinct units called words.

The memory is needed to record numbers and hold instructions. Thus, each word may be a number, an instruction or a coded comment. Each memory unit is capable of recording up to 8,192 words, and the computer in its final

I-1

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - form will have 4 memory units.

The memory may be thought of as N boxes or locations where numbers or instructions can be located. Each of the locations is given an identification number from 8 to N

(the numbers Oto 7 are reserved for a purpose to be explained later). the label of a location is called its address (synonyms: cell, location, box)p Note that the address 1371 does not mean that we can find the numbar

1371 stored there except by accident; the address is purely a label or identifying number.

A memory location can hold only one word at a time, and placing a word in a location automatically destroys whatever was there previously. It is possible to read a number out of memory without destroying or removing i t .

The arithmetic section does what its name implies.

In addition to the basic arithmetic operations, this unit can shift numbers right and left and assist in certain operations which make i t possible for the computer to make decisions. If we use the analogy of a desk calculator, this section corresponds to the upper, lower and middle dials plus the wheels and gears that actually do the calculation .••

"Register" is a term commonly used in connection with these various units. It denotes a device for temporarily storing a piece of information while or until i t

:,,·I-2

is used. A register corresponds quiie closely to the dials on a desk calculator.

Not only numbers but also instructions may be stored in a regist~r.

The whole computer is controlled by a certain set of specified permissible operations, and no two such operations can occur simultaneously. The permissible operations may be executed in any desired sequence. I t is up to the user to specify the sequence of operations or, as i t is commonly called, the program. Each permissible operation can be specified in a concise coded form called an order

(synonym: instruction). In order to be solved on a computer, a problem must be broken down into a series of precise steps and stored in memory as code numbers. The correspondence between the set of perm~ssible operations and the set of numbers which specify them is called the order code and is described in the section on instructions.

The control section of the machine has the function of accepting orders one by one and of interpreting or decoding these instructions and then sending signals to the other units telling them what to do. The control unit is equivalent to the operation buttons which are pushed on a desk calculator. The control section is described in detail in another section.

The output units are an automatic punch for paper

.,.

- - - - - - - - - - - - - - --------------------------

to 600 lines per minute - each line containing up to 108 characters. Information may also be permanently recorded

(or written) on magnetic tape._

SUMMARY of MACHINE CHARACTERISTICS:

The Rice University Computer is a megacycle computer (i.e., a basic pulse iime .of about 1 microsecond) with a speed that is appropriate to:

(1) memory access time for reading of

10 microseconds

(2) memory access time fdr wrifing of 20 microseconds

(3) an addition time of 4 microseconds

(4) an average multiplication time of

120 microseconds.

The machine is asynchronous, binary and parallel in operation and will have a random access memory of 32,000 words •

--

----------------

-

-

- - - - - - - - - -

-------------~----------------- - - - - - - - - - - - - - - - - - - - -

II.

OCTAL NOTATION

Binary numbers are very well adapted to representation by electronic circuits. Since each digit can have only two different values, zero or one, the digits of a binary number can be put into one-to-one correspondence with the electrical conditions of off-on, open-closed, non-conducting-conducting, etc. We pay for this simplicity

(i.e., small amount of information per digit) by needing more digits to represent a given amount of information than if we had used a larger number base. For example, a decimal number with N significant figures is equivalent to a binary number with N ln 10/ln 2

=

N/0.30103

=

3.321 N digits. The standard numerical word in the Rice Computer has from 40 to 47 significant bina~y places. This is equivalent to about 12 to 14 decimal places.

The problem of conversion between base two and base ten is actually simple but need not concern the reader at the moment. The process will be carried out essentially automatically by the computer by means of subroutines, so that the average machine user; will supply decimal input data and the computer will deliver decimal final results.

In order to discuss the instruction word and numerical word structure of the computer, we must use the full

I

I-1

- - - - - - - - - - - - - -

..

54 bit binary machine words. It is very inconvenient to write out such words in full and i t is equally inconvenient to type them into a typewriter-tape punch.

As a shorthand, we use "octal" notation. The binary number is divided into triads (groups of three bits). Instead of writing each triad in full, we write instead an integer between zero and seven inclusive: binary octal

000

001

010

0 11

100

101

110

111

3

4

5

6

7

0

1

2

Each triad is thought of as an octal integer, and the digit written is the usual symbol for this integer. The reader is advised to memorize this conversion table. This conversion is of course very easy in either direction. The resulting shorthand number is actually the equivalent of the binary number written to base eight, i . e . , an octal number.

A 54 bit machine word becomes an 18 octal digit number, much more manageable in length. We shall use expressions such as "the second octal figure" and "the second triad" essentially synonymously. In the computer we have triads; on paper or at the flexowriter we shall use octal figures.

As an example, 000101011001010100111 is equivalent to 000, .. 101, 011, 001, 010, 100, 111, or the octal number

II-2

- - - - ---------··--·-----------------------·-------------

0531247. the octal form is obviously much easier to write and to absorb at a glance.

In referring to an octal or binary number we read it f:t:"om left to right. For example, "the first octal figure" refers to the figure furthest to the left (0 in the above ex amp 1 e ) ;

11 the s e con d o c ta 1 f i g u re " o r

II the s e con d t r i a d" in the number above is

So

.. 11-3

III,

NUMERICAL WORD STRUCTURE

The standard word of 54 bits is divided into two numerical fields for arithmetic operations. Bits 1 through

6 represent an exponent E, which is an integer in the range

[-31,+31}

Bits 7 through 54 represent a mantissa M, which in floating point work is taken to be a fraction with magnitude in the range ro,1~2- 47 ].

In each field, the first bit represents the sign of the number. If the sign is positive, i t is represented by a

11

0", and the remaining bits in the field give the magnitude of the number in binary form. If the sign is negative, i t is represented by a

11

1

11 , and the remaining bits in the field must then be complemented to obtain the magnitude of the number in binary form. This is the so-called 'one's complement' representation of numbers, which is used throughout the machine.

Examples

E

=

2 7 8 ::::: 0 10 1112

=

2 3 in de c i ma 1 no ta ti on o

E

=

72 8

=

1110102

=

-(00101 2 )

=

-5 in decimal

(sign and magnitude) notation.

M

=

200 ••• 0 8

=

0.10000 ••• 000 2

=

0.5 decimal

M

=

477 ••• 7 8

=

1;00111 ••• 1112

=

-(0.11000 ••• 000 2 )

=

- • 7 5 de c ima

1.

,'·II I-1

..

The main advantage of one's complement notation is that addition and subtraction of two numbers can be carried out electronically without distinguishing the sign bits from any of the others, provided any 'spill' out of the sign position is added back into the low o~der position of the sum.

This effect is termed 'end-around' carry, and is illustrated by the following example of exponent addition:

E

1

=

0101012

=

21 in decimal notation

E

2

=

1110012

=

-6 in decimal notation

E1

+

E2 =r0:110

+

1 ( en d a round ca r r y )

=

001111

=

15 in decimal notation~

There are two 'zeros' in this system, namely numerical fields of all O's or all l ' s . As in the sign-andmagnitude scheme, these are termed 'plus zero' and 'minus zero' when i t is necessary to distinguish between them.

The floating point value of a machine word is given by

MX256E, which is a number in the approximate r~nge

[lo- 75 , 10 7

3]•

For full details on tloating point operations, see Section XI •

_···III-2

RICE COMPUTER

INFORMATION FLOW ARITHMETIC UNIT

II

CONTROL UNIT RITER ------,

I iJ

PARITY CHECK

ARITHMETIC (FULL INSTRUCTION OR

I

TYPEW

I __ -

- - - - - e < , , - - - - - - i , I I '

INSTRUCTION 31-54) 21fzs

39

1

I

. : :

}°-

TAG REGISTER r - - , - - - - - - - -

1 s

1

1

CENT

RAL

I I

I

~ - - - - - -

DISTRIBUTOR

I

i

I

JT

I

---------'j'- ---

.J

'

-----=-=:::;.:,_ _ - - ---']'- --

I I

L_

CONTROL UNIT

-

_A___

I

---~-L-t-~-1

_J

I

I r----

_j

I

I

:

I I

- _I

I+

J

I

I

I

L_INDICATOR LIGHTS 1, 2, 3

(DECODED OUTPUT!

(CONTROL TAG REGISTER)

~ 1

I

I

I

I

I

I

I

I

28

I

I

I

40

I

9

I

I

I

I I

I

I

I

I

I

I

I

I I

I I

I

I

I

I

I

I

1

S i

I

L - - - - P A P E R TAPE PUNCH

: , - - , · - - - - - - - - - - -

- - -

ADDER

I

I

I

I

I I

I

I

I

I

I I

I

I

II:

I

.:J

1

1--r=----_ -

----r

== == ::__

=

---r----------=-

=-=

=-

.:_·:c:c.--- -

---r----------=--=--=-

:

I

---.:-:1_ ----

I

I

I

_J

- --- - --i

[._CONTROL UNIT (B-ADDERJ

J--;----------------

- - 1

_________________ J

T4

TS

------

I

~[ov]

I

tov]

,---> u

I<--

r-- -

--,-PAPER TAPE READER

J

-, T7

R

FULL WORD (54 BITS) INTRA-FLOW

PARTIAL WORD INTRA-FLOW

STATIC FULL WORD CONNECTION

FULL WORD INTER-FLOW

PARTIAL WORD INTER-FLOW

- - - ADDRESSABLE REGISTER

NON-ADDRESSABLE REGISTER

- - - - SYNTHESIZED NON-ADDRESSABLE REGISTER

FIG. 2

IV.

ARITHMETIC UNIT

The -arithmetic unit accomplishes all arithmetic functions and has, in addition, facilities for temporary

( o r e r a s a b 1 e ) s to ra g e • The execution time for each operation varies from function to function and from operand to operand depending upon the number of zero bits in the ope rand.

The arithmetic unit is built around an information distributing device called "the central distributor", or

CD. CD is not a register since i t cannot store inform-

·ation but is only used to transfer information between registers and to and from the other units in the machine •

. Figure 2 is a block diagram of the arithmettc unit and is an expansion of part of the general diagram in Figure

I

1. The various registers are listed below and a paragraph descr~ption of each register and its function is given: registers abbreviation u

R s

T4

TS

T6

T7 name universal register remainder register second operand register temporary store rio.

4 tempera ry store rio ..

5

temporary store no.

6 temporary store no. 7

.:,,1-.IV-l

Universal Register

The U register is involved in all arithmetic and logical operations.

It is sometimes said to contain the

' f i r s t operand' (to distinguish this from the number brought to S before executing an operation). In arithmetic operations, the first operand will.normally be the addend, minuend, multiplicand, or the high order part of the dividend. At the end of each operation, the principal result is in U, viz, a sum or difference, the high order part of a product or a quotient.

U may·also be shifted left or right either logically (all 54 bits) or arithmetically (mantissa only).

Remainder Register

The R register is used partly as an intermediate store in some operations, and partly as storage for results. Before division, R contains the low order part of the dividend; after division, i t contains the remainder. After multiplication, R contains th~ low order part of a product. R may also be shifted, with ~r without Connections to U.

Second Operand Register

Numbers coming from memory or from the control unit first appear in S before an operation is executed.

Thus in arithmetic operations S initially contains the subtra-

. i hend, the multiplier or divisor. The contents of S after

I V-2

- - - - - - - - - ~ - - - · - - - - · - · an operation is normally a complicated intermediate result and as such i t is seldom used.

Temporary Storage Reg~sters

There are four fast registers primarily used for storing temporary results. Instructions may be stored here to minimize execution time and may be fetched by the control unit in a manner similar to instructions in main memory.

0

IV-3

cc

Bl

82

83

84

85

86

PF

TT

FT

I +l I

L----------------1

RICE COMPUTER

INFORMATION FLOW IN CONTROL UNIT

-

ARITHMETIC UNIT

(CD 1-54)

31

ARITHMETIC UNIT

I

(CD 31-54) :

-----L-----

39

I

40

I

I

I

- - - - - - __ .J

ARITHMETIC UNIT I

(CD 55,56) :

54

I

.1--,

CONTROL TAG

L_j

REGISTER

. ARITHMETIC UNIT

(CD 40-54)

INPUT l

(15

BITS)

SINGLE

INPUT

B-ADDER

SINGLE

INPUT

INPUT

2

(15 BITS)

INPUT l

+

INPUT 2

IF BOTH

PRESENT

SL

IL

ML

TL

P2 x

- ----r l ________ _

---.,

I

I

I

--,

I

I

-, I

I I

I I

I I

I

I

I

I

I

I

CONSOLE

SWITCHES

!

+l I

L----------------J

1_1 _______________

1

- - - FULL REGISTER INTRA-FLOW

FULL REGISTER INTER-FLOW

- - - - - PARTIAL REGISTER INTRA-FLOW - - - - - - PARTIAL REGISTER INTER-FLOW

- - - - ACTUAL REGISTER

- - - - SYNTHESIZED REGISTER

FIG. 3

v.

CONTROL UNIT

The machine's control unit has the task of accepting orders one by one into the I register and of causing the machine to carry out the operations specified according to the order in the I register. All address modification also takes place in this unit. Normally orders are obeyed by the control unit in the sequence in which they are stored in the memory. Sometimes, however, this sequence is broken and the control unit starts over at some new position in the memory. This is called a trans.fer of control. If control is transferred to a few locations back in the memory, the machine will repeat ilie operations specified by the intervening orders. I t is possible to cause this repetitian to occur any number of times. The machine also has special facilities for the repetition of a single instruction (see Section IX).

Because of the importance of program cyclic control, emphasis has been placed on special facilities in the control section to help the coder. This tends to make the description of the control section involved. However, the prospective coder is advised to master these additional features since they make possible most of the interesting calculations and will greatly shorten his time spent in coding.

The control unit is centered around a B-adder. This plays the part of a central distributor for the control section. The last 15 bits of the instruction register or the X register* can be connected to one side of this adder and one of 8 other registers described below can be connected to the other side. The adder output may then be gated (i.e., transferred) to any of these control registers, the arithmetic central distributor, or the memory. Figure

3 is a block diagram of the control registers and their interrelations. The various registers are listed below, and a brief description of each one is given: abbreviation

I cc

Control registers name instruction register control counter (or location register)

Bl

B2

B3

B4

BS

B6

PF

B register 1

B register 2

B register

3

B register 4

B register 5

B register

6

pathfinder

*

Details of the special registers are given in Section IX.

V-2

-

- - · · · -

-

- - · · - - - - - - - - - - - - - - - -

Instruction Register

When an instruction is brought from memory into the control unit, i t is placed in the instruction register, where i t is decoded. The instruction register is a full length 54 bit word. The last 15 binary digits (bits 40-

54) specify an address or location number. It is this number that is subject to modification. A summary of the instruction codes is given in Section VII.

Control Counter or Location Register

This register with a capacity of 15 bits determines the location in memory from which the next- instruction is taken. Whenever.:a new instruction is brought into the instruction register fiom m~mory, CC (control counter) is advanced by 1. However, during the execution·of a transfer or skip, the contents of CC may be changed to any number in the address range.

The control counter may also be used in exactly the same way as one of the B-registers.

B Registers

The Rice Computer has six B registers each containing 15 bits. One of the primary usei of B registers arises from their ability to modify the instruction address. When a given B registe~ is appropriately specif i e d ( th i s i s exp 1 a in e d in the de ta i 1 e d di s cu s s ion o f t~h e

order code), .the instruction is executed as if its address had contained the stated address plus the c-0ntents of the specified B register. The actual addition is carried out in the B-adder and only the right hand 15 bits of I are affected by this addition. The result of the addition is placed in M, the address section of I.

As in the arithmetic section, the B-adder operates on numbers in the one~ complement notation.

Thus, if i t is required to decrement the address portion of I by 1, the number 77776 should be placed in an appropriate

Bregistero

Pathfinder Register PF

Whenever the order 'Transfer to subroutine' (operation code 40000) is about to be executed, the contents of

CC are placed in PF: normally this will have the effect of automatically recording the address following that· from which the transfer was made, and i t is used in 'returnlng' from a subroutine.

The pathfinder may also be used as a B-register.

·· V-4

..

· - - - - - -

- - - - - - - - - - -

VI •

A SUMMARY OF THE RICE MACHINE ADDRESSING SYSTEM

OCTAL ADDR

NAME DESCRIPTION AND USE

A Series F Registers

0 z

1 u

2

3

4

R s

T4

5

6

7

T5

T6

T7

54 zeros, used for clearing,

54 bits + 2 overflow bits. Universal.

54 bi ts. Remainder.

54 bits. Secondary operand.

54 bits. Temporary storage.

54 bits. Temporary storage.

54 bits. Temporary storage.

54 bits. Temporary storage.

Electrostatic Memory Addresses

10 to 77767

54 bits+ 2 tag bits+ 7 automatic parity check bits.

Special Purpose Registers

77770

SL

15 bits. Sense

1i gh ts.

77771

IL

15 bits. Indicator lights.

77772

ML

15 bits. Mode lights.

77773

TL

15 bi ts. Trapping lights.

77774 P2 15 bi ts. Pathfinder 2.

CC+P2 on all non-sequen tia 1 transfers of control.

77775 x

15 bits. Increment register.

77776

77777

TT

FT

15 bits. Magnetic tape output.

15 bits. Magnetic tape input.

B Series F Registers (addressable only in Field 1 and Field

3)

0 cc

15 bits. Control counter. Holds address of next instruction.

1 to

6

Bl. •• B6

7 PF

15 bits. Used to modify addresses.

15 bits. Pathfinder. CC+PF on Class

4 tr•nsfers (Field 2

= octal 40000}.

·,,,VI-1

VII.

SUMMARY OF THE INSTRUCTION WORD STRUCTURE

AND OPERATION CODES

All instructions are divided into four major fields as illustrated, each field being given a name which indicates its general function. In addition, certain subfields are named for reference purposes.

1 2 3 4 5 6 7 8

9

10 11 12 13 14 15 16 17 18

I

111

I I

1·111 I 11

I I I I

I

Jv..___..___

------""''-

~

"'----=-----

- - . . . . . . . . - - - - - - - - - -

__,,)

I

Field

SETU

1

I

Field

I

2 Field

3

OPERATION AUX

I

Field

SETS

4

I

,,---· ,,....

- ~

I

~

,r-.

I

~

I

-------

I 1.1

L , r

I I I I

1

1

1

1

I

I

I

r

I

I I Ii I I I

1 ~ ,

"r-_ _

IF

F

COP10P2 OP30P4 OFF IM IA,BM M

Instructions are interpreted in the following sequencee

1. The contents of the location indicated by CC are brought to I, the Instruction registero CC is advanced by 1.

2.

Field

1 is decoded, and a word in an F address is sent to u.

,,VII-1

3.

Field 4 is decoded, and a word is sent to So An address (possibly new) is left in the M portion of I.

4. Field 2 is decoded, and arithmetical or logical work is done using the contents of U and Sand/or the final address M.

5. Field

3

is decoded, and the contents of either U or

R is sent to an F address, or certain changes are made in the contents of one of the B registersa

,, VI I-2

- - - - - - - ~ -

------------------

FIELD 1. Individual bits of IF are interpreted as follows:

Bit 1. o,

A series address.

1,

B series address.

Bit

2. O, algebraic value of contents of

F goes to U.

1, absolute value of contents of F goes to u.

Bit

3.

O, do not change sign of

Uo

1, change sign of u.

F is interpreted octally as an address .. Octal interpretation of IF yields the following: o,

+A

4,

+B

1, -A

5,

-B

2,

+IAI

6,

+IBI

3,

-IA I

7,

-IBI

-- ·-· VII-3

~

.

FIELD 4. Individual bits are interpreted as follows:

Bit 1

0

O, contents of location M, (M), goes to s.

1, address M goes to s.

IM Bit

2. O, algebraic value of (M) or M goes to

S.

1, absolute value of (M) or M goes to s.

Bit

3.

O, do not change sign of s.

1, change sign of S.

IA Bit O, do nothing.

1, replace last

24 bits of

I by last

24 bi ts of

(M).

PF

B6

BS

BM B4

B3

B2

Bl cc o, do nothing.

1, add contents of cortesponding B-register to address Mand leave sum in M portion of I.

M 15 bits.

Permissible M addresses include A series

F regi~ters (0-7), electrostatic memory addresses (10-77767)*, and special purpose registers (77770~77777).

*

10~20007 when only one memory bank is used.

···VII-4

- - - - - - - - - - - - - - -

------

---

---------- ----------

- - - - - - - - - - - - - - - - ~ - - -

Octal interpretation of IM yields the following:

0,

+

(M)

4,

+M

1, -(M)

5, -M

2'

6,

+

I

(M)

I

+IMI

3, -

I

(M)

I

7, -

IM_I

Field 4 is decoded in the following sequence:

1. Increment M by the sum of all the B-regist~rs corresponding to ones in BM, leaving the result in the

M portion of I.

2. If IA bit is 1, replace last 24 bits of I by last

24 bits of (M) and return to step 1.

3.

If IM bit 1 is O, send (M) to s.

If IM bit 1 is 1, send M to s.

4. Modify the sign of Sas indicated by IM bits 2 and

3.

NOTE. Whenever a 15-bit quantity is sent to a 54-bit register, i t occupies the last 15 bits of that register.

Bits 1-6 are cleared to zero, and bits

7-39 are set equal to bit 40.

: ,-VII-5

I

1,,

1,'

'•

···"'

FIELD 2.

The first triad, interpreted octally, determines the Class of operation as follows:

O, Compare or test, and skip, jump, or transfer.

1, Arithmetic operations.

2, Substitute, set tags.

3,

Not used.

4, Short registers, shifts.

5,

Logical operations.

6,

Input - output.

7; Not used.

Class o.

OPl specifies the type of transfer to be made if certain conditions are satisfied. OP2, OP3 and OP4 specify a set of zero, one, two, or three conditions. HALT and TRANSFER means stop; then when "continue" button is pressed,

(M)

+

CC

TRANSFER means

(M)

+

CC

SKIP means

(cc)+

1

+

CC

JUMJ? means

(cc)+ (X:)

+

CC

(all) means execute tr~nsfer only if all tests are satisfied

(any) means exec\,lte transfer if any of tests are satisfied

OPl. O, if (any) halt and transfer.

1, if (any) transfer.

: ·VII-6

2, if (any) skip by 1.

3,

if (any) jump by

(x).

4, if (a 11) halt and transfer.

5, if (a 11) :transfer.

6,

if (a 11) skip by 1.

7, if (a 11) jump by

(x).

OP2. o, no test.

1, is U mantissa sign positive

( 0).

2, is mantissa overflow indicator light on.

3,

is exponent overflow indicator light on~

4, no test.

5, is U mantissa sign negative (1).

6,

is mantissa overflow indicator light off.

7, is exponent overflow indicator light off,

OP3. o, no test.

1, is U mantissa equal to zero.

2, is bit 54 of u equa 1 to zero.

3,

are all the .sense lights corresponding to ones in

M on.

4, is every bit in u zero.

5, is U mantissa different from zero.

6,

is bit 54 of u equa 1 to one.

7, a re a 11 the sense lights c-orres ponding to ones in

M off.

·VII-7

OP49 o, no test.

1, is tag 1 indicator light on.

2, is tag 2 indicator light on.

3,

is tag

3

indicator light on.

4, are all tag indicator lights off. s, is tag 1 indicator light off.

6,

is tag 2 indicator light off.

7, is tag

3

indicator light off.

NOTES.

Tag and overflow indicator lights are turned off when tested. Sense lights are not altered when tested.

In SKIP or JUMP (OPl = 2,

3, 6

or 7) the contents of

U and Sare combined in a way determined by the test called for in

OP3:

If

OP3

= o,

1, 2, 5 or

6, the arithmetic difference

U - S i s formed in U, fixed point or floating point according to the nature of the two numbers. See the discussion in class 1.

If OP3

=

4, U and Sare compared logically through

Ras a masko If U and Sare identical in the bits where

R is zero, U ends up all zeros; otherwise U will not be null.

The "if null" test is then performed.

If

OP3

=

3

or 7 (sense light test), U is not changed.

VII-8

- - - - · - - - - - - - - - - - - - · - · · -

C la

SS

1.

Bits not mentioned a·re not used.

Bits mentioned individually have no effect when equa

1 to zero.

OP2 and OP4 are interpreted octally.

Operations are carried out in the order listed.

OPl. Bit

1. 1, interchange

(u) and

( s).

Bit 2.

1, clear R mantissa to sign of u mantissa.

Bit 3.

1,. interchange

(u) and ( R).

OP2. o, fixed point add.

( u )+ ( s)

-+ u.

1, fixed point subtract.

2, fixed point multiply.

(u)-(s)

-+· u.

(u)x(s)

-+

U,R.

3, fix.ed point divide.

( U, R )-;-( S )

-+

U,R.

4, floating point add.

( u )+ (

s)

-+ u.

5, floating point subtract.

(u)_-(s)

-+ u.

6, floating point. multiply.

(u)x(s)

-+

U,R.

7, floating point d.ivide.

( u )-;-( s )

-+

U,R.

OP3. Bit

1.

1, do not nor~alize after a floating

Bit 2. operation.·

1, then if OF2

=

0 or

1, the exponents of U and Sare added or subtracted

(as int~gers) i~ addition to the mantissa addition or subtraction.

If OP2

=

2,

3 or 7, U and Rare interchanged after the arithmetic operation.

If OP2

=

4 or

5,

U and Rare adjusted so that the two represent a double pre c is ion f lo a ting point sum or di f ference.

VII-9

OP4. o, not used.

1, store

(u)

-+ M.

2, not used.

3,

store

( u)

-+

M

+

( B6).

4, thru 7, not used.

NOTES.

Fixed point numbers normally have an exponent of

00. Fixed point operations on suGh numbers give a result in the same form.

If either or both numbers have any other exponent, the exponent of the result is usually useless.

A floating point operation on two floating point numbers

(u, s) normally gives a proper, normalized floating point result. If one of the two numbers is fixed point (expotient

=

00), i t is treated as if i t were zero. The most important result of this convention is that an all zero word, nulJ, behaves as a true floating point zero., However, if both U and Sare fixed point, they are combined by a floating point operation properly as fixed point numbers.

After a multiplication, the high-order bits of the product are in u, the low-order bits in R. Before a division, the high-order bits of the dividend are in U and the low-order bits in R. After a division, the quotient is in U and the remainder in R.

VII-10

······-····-··

- - - - - - - - - -

--------------- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

After either floating point multiplication or division, the exponent of R is set equal to the final exponent of U.

Examples:

10300 (U,R)

7

(S), fixed point

12300 (U) -;- (S) , fixed point

13300 integer divide

16300 (S)

7

(U) , fixed point

10401 floating point _add to memory

10700 (U,R) -;- (S), floating point

12700 (U) -;- (S) , floating point

VII-11

Class

2o

Bi ts mentioned individually have no effect when equal to zero.

OP3 and OP4 are interpreted octally.

OPl. Bit

9•

1, bi ts 1-6 of s replace bits 1-6 of u.

OP2. Bit 1.

1, bi ts 7-27 of s replace bi ts 7-27 of

Ua

Bit 2.

1, bi ts 28-39 of s replace bits 28-39 of u.

Bit 3.

1, bits 40-54 of s replace bits 40-54 of

Uo o, clear ATR (Arithmetic Tag Register).

1, set tag 1 in ATR.

2, set tag 2 in A.TR.

3, set tag 3 in ATR.

4, do not change ATR.

5, not used.

6, not used.

OP4.

7, not used. o, not used.

1, store

(u) in location M.

2, not used.

3, store

(u) in location M+(B6).

4, not used.

5, not used.

6, not used.;

7, not used.,

VII-12

RICE COMPUTER

SHIFTING OPERATIONS

ARITHMETIC SHIFTS u

I . - - - - - ' - - - - - - - - - - - .

1:1: 1~ 1···1~ 11~ 1~1~1 · · · -1;1

R

.-------r---,1:

~~

~

~

I - . ; I

~

v----,_

RIGHT SHIFTS:

LEFT SHIFTS:

'00

\JV

U MANTISSA SIGN:

U MANTISSA SIGN:

I

I

V v

{9 ____ _

R SPILL:

U SPILL:

---->

<---u e

I e

I e

S O 1

:11:1:,~

~ - - - ~ ~

~------

: R

1:1~1 · · -1~11~171 . . .

..----_..w:::~

l~I

RIGHT SHIFTS:

LEFT SHIFTS:

\_,A_)

V J

OPTIONAL END

CONNECTIONS:

! ~ I

SPILL:

AFTER EACH LOGICAL SHIFT OF U, THE EXPONENT AND MANTISSA OVERFLOW BITS ARE SET EQUAL

TO THE CORRESPONDING SIGN BITS. ZEROS FILL IN WHERE END CONNECTIONS ARE NOT SPECIFIED.

FIG. 4

Class

3.

There are no orders in Class

3.

Any Field 2 code of the form 3XXXX will be ignored.

Class 4. OPl is interpreted octally, and its value determines the meaning of the other bits of the field. In each case, bits not mentioned are not used, and bits mentioned individually have no e.ffect when equal to zero.

OPL O, set the B-register designated octally by OP4 to the value given by

M.

1, add the number given by M to the B-register designated octally by OP4.

2, turn on or off the lights corresponding to ones in

M, as indicated octally by OP4.

OP4. o, turn on designated sense lights.

1, turn on designated indicator lights.

2, turn on designated mode lights.

3, turn on designated trapping ·lights.

4, turn off designated sense lights.

5, turn off designated indicator lights.

6,

turn off designated mode lights.

7, turn off designated trapping lights.

3, set the speci~l purpose register designated octally by OP4 to the value given by

M.

OP4. o, not used.

1, not used.

VII-13

2, not used.

3,

not used.

4 , P2 , pa th find e r 2 •

S, X, increment register.

6,

TT, words-to-tape.

7, FT, words-from-tape.

OPl.

4, arithmetically shift the mantissa of U and

R, connecting bit 47 of U mantissa to Bit 1 of

R mantissa. Ignore exponent bits.

Send

U mantissa sign to R mantissa sign, and to vacated bits.

OP3. Bit

3. o, shift right

M places.

1, shift left M places.

5, logically shift all

54 bits of

U and/or

R, ignoring overflow bits in U.

Bit

1. o, fi 11 vacated bits of

U with

OP4.

Bit 2.

Bit

3.

Bit

1. zeros.

1, f i l l vacated bits of

U with s pi 11 from R.

1, shift u left

M places.

1, shift u right

M places. o, fi 11 vacated bits of R with zeros.

1, f i l l vacated bits of R with spill from

U.

VII-14

....

------- ---------------------

Bit 2. 1, shift R left M places.

Bit

3.

1, shift R right M p laces •

6, bit count. Clear U, shift R right M places, and add each 1 which spills from Rone at a time into U.

7, not used.

NOTES.

Shifts and bit count use the integer in M modulus

12 8 ( de c ima 1 ly). If Mis negative (bit 40

=

1), a shift will be carried out along the specified path but in the reverse direction.

'>

Class 5. All 54 bits are treated on the same basis.

OPl, 2,

3 and 4 are decoded and executed in succession.

NOP .means no operation. Hang up means a machine stop.

Some meaning ~ay be attached to these cases at a later time. A bar above a register symbol means logical complement. Address Mis the final address formed in field 4.

AND and OR have the usual logical meanings, i.e~,

AND: if both registers have a 1, the result is 1, otherwise a zero; OR: if either or both registers have a 1, the result is 1, otherwise zero. EXTRACT: wherever a bit of R is equal to one, the bit in that position of S replaces the corresponding bit in u.

Other bits of U are unchanged.

OPL o,

NOP.

1,

Hang up.

OP2.

·2, Hang up.

3, u

+

R, s

+ u.

4,

U~·R (including overflow bits).

5, Hang up.

6,

Hang up.

7, Hang up. o,

NOP.

1, u

-+ u.

2, s

+ s.

.••. ~· VII-16

Examples:

AND

ORU

OP3.

OP4.

3,

u

+ u,

s

+ s.

4, s

+ R·

5,

Hang up.

6,

Hang up.

7, Hang up. o,

NOP.

1, s

OR u

+ u.

2,

EXTRACT s thru R

+ u

(thru 1

1 s of

R)'

3,

Hang up,

4, Hang up,

5, Hang up.

6,

Hang up,

7, _ Hang up, o,

NOP.

1, U

+

M

(store).

2, NOP.

3, u

+ M +

( B6 ).

4, u

+ u.

5, u

+ u ..,,.

M.

6, u

..,,.

u .

1,

u

..,,.

u

+

M +

( B6),

50314

50010

SAND U

+

U

SOR U

+

U

VII-17

- - - · · ~ · · ·

- - - - - - - - - - - - ~

SYM

SYD

SYS

LDR

ORU+

53220

53220

53120

50400

50011 s,u symmetric difference s,u symmetric difference s,u symmetric sum

Load R from s

(M) OR u

+ M vr1 ... 1s

Class

6.

Input-Output Orders

OPl. o, paper tape and typewriter control~'e

OP2. o, read triads:

3 bits (from channels

1,2,3 of the tape frame currently in the optical reader) are stored in the first

3 bits of

R.

A logica

1 shift of UR left

3 places is carried out.

If a ' l ' bit is spilled from the high order (exponent sign) bit of U before the last shift takes place, OPN is complete. Otherwise, a further triaq is read.

1, read hexads:

6 bits (from channels

1,2,3,4,5,6 of the tape frame currently in the optical reader) are stored in the first

6 bits of

R. A logical shift of

UR left

6 places is carried out.

OPN is completed by a spill from U as in the case of reading triads.

2, not used~

3, not used.

*

See Table 1 for complete paper tape codes.

VII-19

OP2.

4, punch hexads. A frame of six bits is punched from the exponent position of s, and the code 02 is inserted in the last

6

bits of U. U and Sare then shifted left logically

6

places.

If a spill from U is detected in the first 5 shifts, OPN is complete.

Otherw\se, a further hexad is punched.

S,

punch hexads with 7th hole. As for

OP2=4, except that a hole is punched in channel 7 of the paper tape.

6, punch triads. A frame of

3

bits is punched from the high order triad of s, and the code 2 is inserted in the last triad of U. U and Sare then shifted left logically

3

places. If a spill from U is detected on the first two shifts, OPN is complete.

Otherwise, a further triad is punched.

7, type.

An eighteen digit octal number is typed from S by the console typewriter.

VII-20

OPl. 1, printer control**·

OP2. o, print nothing.

1, print character codes 00-37 only.

OP3.

2, print character codes 00-77. o, do not space after printing.

1, space one line ( 1/66 page).

2, advance paper to first 1/22 page mark.

3,

4, s,

II

6,

7,

"

II

"

"

II

II

II

"

II

II

II

II

1/11

1/6

"

l/3

" " II 1/2

" "

new page

II

"

" "

II "

" "

** Printing takes place from a \rint matrix of either

100 or 200 words in memory, whose first word address ~s given by the final address, M, formed in I.

Each pair of words in the matrix correspond to a line of a particular character code of 108 characters. Thus, ~ords 1,

2 give the code for character 'O'; a ' l ' in either,of these words ca~ses a

1

0

1 to be printed in the appropriate type position on the line. Words 3,

4 correspond to character

1

1

1 ,

5, 6 to character '2', etc. See Table 2 for complete printer character codes.

VII-21

July 10, 1963

Supplement to Class 6, Input-Output Orders

OP1=4, 5, 6 Magnetic Tape Orders

The magnetic tape orders use the special registers

TT, located at 77776, and F.T, located at 77777, to address information which is being written on or read from tape, the address field (M) of the ins.truction register to determine the nu~ber of words to be written or read, and the last 8 bits of S to define a marker

0

Information may be written from or read into any part of electrostatic memory. Do not attempt to read or write blocks which include fast or special registers.

When reading in a forward direction, the informatioq is stored in the word addressed by FT and the (M)-1 words immediately following; when reading in a backward direction, the infromation is stored in (FT) and the (M)-1 words immediately preceeding. Similarly, (TT) addresses the first word of a block to be written forward or the last word of a block to be written backwards. FT is incremented during a forward read operation and decremented during a backward operation, so that its final contents address the word immediately after the last_ word read forward or the word immediately before the las·t word read backward. TT is stepped similarly for write operations.

The read and write operations are such that a block written backwards exists on tape in exactly the same format as a block written forwards, and a block written in either direction may be read in either direction. In other words, the read and write magnetic tape orders relate the word nearest the front of the tape to the word in the lowest numbered address of the memory block referenced.

Reading should not be attempted unless the tape has been positioned with a search for marker or the last read executed read exactly the number of words that were in the block from which i t was reading.

No difficulty will arise if fewer words than are in a block are read~ It is not meaningful to read more words than are in a block with clock track A; clock B, however, may be used to read successive data blocks with one instruction.

OPl.

OPl.

4, write on magnetic tape unit specified octally by OP2.

OP3. Bit 1=0, write in forward direction.

=1, write in backward direction.

Bit 2=0, write (M) words of .data from memory.

=1, write marker which is in last 8 bits of

(TT is not used.) s.

5, read from magnetic tape ~nit specified octally by OP2.

OP3. Bit 1=0, read (M) words in forward direction.

=1, read (M) words in backward direction.

OP4. Bit 1=0, store words in memory.

=1, do not store to memory (FT i i not used).

Bit 2=0, use clock track A for reading. This is the normal form.

=1, use clock track B. This is normally used only for certain types of specialized data tapes.

OPl.

6, search magnetic tape unit specified octally by OP2 for marker specified by last 8 bits of s.

OP3. Bit 1=0, search forward.

=1, search backward.

OP4. Bit 2=0, normal.

=1, momentary forward. OP2 is ignored.

The tape on unit 2 is moved forward approximately 1/4 inch

0

Bit 3=0, normal.

=1, rewind tape unit specified by OP2.

Example 1:

Assume that a block of 200 words from 10001 to 10200 is to be written on tape unit 2 preceeded by a marker 177 and followed by a marker 42, starting from the present position of the tape. In this example, markers are written at both ends of the block in order that either end may be found with a search MT order. These orders will perform the desired procedure;

01

01

01

01

64220

43006

64200

64220

00

00

00

00

4000

4000

4000

4000

00177

10001

00200

00042

Example 2:

Assume that after execution of the orders in example

1, the tape has been moved forward well past the block just written. If there is no intervening marker 42, the following orders will read the block into memory in locations 15041 to

15240:

01

01

01

66240

43007

65240

00

00

00

4000

4000

4000

00042

15240

00200

TABLE 1

FLEXOWRI TE R CODES d e b c key code

L-case

U-case

7654 321 a

A 0100

000

0100 001

0100 010

E

F

0100 011

0100 100

0100 101 f g

G

H

0100 110

0100 111 h i j k

1

B c

D

I

J

K

L

0101 000

0101 001

0101

010

0101 011

0 p s t u q r m n v

M

N

0 p

Q

R s

T u v

0101 100

0101 101

0101 110

0101 111

0110 000

0110 001

0110 010

0110 011

0110 100

0110 101 key code

L-case

U-case

7654

321 w w

0110 110 x x

0110 111 y y

0111 000 z z

0111

001

0

1

(

)

0000 000

0000

001 ·

7

8

9

1T x

+

2

5

6

3

4

<

= carriage return

'

I

+

~·(

IT

0000

010

er

A

*

0000

011

0000 100

0000 101 a, 0000

110 s

0000

111

'Y

0001 000

A 0001 001

0001 010

I: 0011 101

~

0010 000

0010 001

0111 010

0011 111

0011 110

0010 100

,,VII-22

key code

L-case U-case

7654 321 upper case 0111 100 lower case tab tape feed back space

0111

0010

1011

0010

110

101

000

110 key code

L-case U-case 7654 • 321

1/2 space down

0010 011

1/2 space up

0010 010 space

0001 100 code stop

1010 111 code delete

1111 111

Control punches

"stop code" turns off repeat mode light when reading

7th hole frame is not read into U

\."'.;,VII-23

- - - - - - · · - - - - - · · - · - - · - - ·

..

TABLE 2

PRINTER CODES symbol

,o e f

+ b c d

9 a

1

2

3

4

7

8

5

G

I

x

:x

21

22

·23

24

25

26

03

1

04

05

:06 octal biria ry code code

00

01

02

1

00 0000

00 •0001

00 0010

00 0011

00 0100

00 0101

00 0110

00 0111

07

10

11

12

00 1000

00 1001

00 1010

13

14

00 1011

00 1100

15

00,..1101

16

00 1110

17

2·0

00 1111

·01 0000

01 0001

01 0010

01 0011

01 0100

01 0101

01 0110

G

H

I

J

K

L

M

N

0 p

Q

R s

T u

·V w symbol

A

B c

D

E

·F

63

64

65

66

53

54

55

56

57

60

61

62

47

50

51

52

43

44

45

46 octa 1 binary code code

40

41

42

10 0000

10 0001

10 0010

10

0011

10 0100

10 0101

10 0110

10 ·o 111

10 1000

10 1001

10 1010

10 1011

10 1100

10 1101

10 1110

10 1111

11 0000,_

11 0001

11 00101

11 0011

11 0100

11 0101

11c,0110

·VII..;24

TABLE 2 cont'd

(

) x

=

' symbol

b. b.

* oc ta 1 binary code code

27

30

01 0111

01 1000

31

32

01 1001

01 1010

01 1011

33

34

35

36

37

01 1100

01 1101

01 1110

01 1111 symbol x y z

<

-

< t

._.

+

J oc ta 1 binary code code

67

70

71

72

73

74

75

76

77

11 0111

11 1000

11 1001

11 1010

11 1011

11 1100

11 1101

11 1110

11 1111

VII-25

,I

- - - - · - - · · · -

- - -

FIELD

3.

OF is interpreted octally as follows.

F i s interpreted octally as an A or B series ad-

OF. dress. o, store U in the A-series register designated by F.

1, store R in the A-series register designated by F.

2, add 1 to the contents of the B-series register designated by F.

3, add (X) to the contents of the B-series register designated by F.

Xis the increment register.

4, store the last 15 bits of u in the B-series register designated by

F.

5, store the last 15 bits of

R in the B-series register designated by

F.

6,

subtract

1 from the contents of the Bseries register designated by F.

7, store the M portion of I in the B-series register designated by F.

VII-26

..

- - - -

---·-····--·-·-··· .

-

~ - - - - - - - - - - - ~ ·

VII Ia

EXAMPLES OF SINGLE INSTRUCTIONS

In order to illustrate the procedure of composing single instructions, the following list is presenteda The instructions are grouped according to operation class: for each, its numerical code is given, together with an equivalent symbolic representation. No explanation of the latter is offered, but full details of the symbolic representation of orders may be obtained from programming memoranda.

Following each symbolic code is a brief interpre= tation of the order. The reader is strongly advised to check these numbers against the outline of the instruction codes given in Section VII~

Class O

01 03030 00 4000 30002 symbolically: IF(SLN)JMP a 30002

Interpretation: if sense lights 2,

3

and 14 are on,

(cc) t

(x)+CC; otherwise proceed to next instruction. When

3

or 7 in Op

3

of OPN(SLN or SLF, respectively) is used, the address portion of the instruction &lways denotes the lights to be tested; thus, only SKP or JMP options may be elected with these tests.

..vIII-1

01 00000 00 4000 55555 symbolically: HTR a55555

The program halts unconditionally with this instruction displayed in I. Such an instruction may provide a stop at the end of a program; an appropriate address field will then allow re-entry when the 'continue' switch is depressed.

04 02110 21 0002 01000 symbolically: T4 IF(POS)SKP lOOO+Bl,Bl+l

Interpretation: if (1000+(Bl))<(T4), next execute instruction two beyond one given; if (lOOO+(Bl))>

(T4), next execute instruction immediately following one given; always increment (Bl) by 1.

01 05552 00 4000 00134 symbolically: IF(NNZXTG2)TRA al34

Transfer is effected if all tests are satisfied; no subtraction takes place. The presence of the numeric bit saves the time of a fetch from memory in SETS since (134) does not pertain to the execu~ tion of this instruction. Interpretation: if

(U)<O and indicator light 2 (arithmetic tag 2 indicator) on, transfer to location 134.

·VIII-2

Class 1

06 10401 00 0000 03742 sym,bo lica l ly: T6 FAD+ 3742

Interpretation: floating point (T6)+(3742)+3742.

With this instruction a cumulative sum may be collected at location 3742, successive terms having been computed and stored in T6.

41 13300 53 4004 00000 symbolically: Bl IDV aB2, R+B3

Interpretation: (Bl)+u, then (B2)+s, then UM+~, s then interchange (u)+-+(R), then fixed point division (U,R)/(s)+U (quotient) and R (remainder), then (R)+B3 in AUXILIARY; hence, (Bl) modulo

(B2)+B3.

Class 2

01 21700 07 0040 00032 symbo lica 1 ly: CLA 32+B5, U+T7

Interpretation: (32+(BS))+S in SETS; (s) 1 , 54+

Ul, 54 in OPERATION, then (U)+T7 in F3; hence,

(32+(B5))+T7.

44 21641 00 0000 05120 symbo lica 1 ly: B4 RPA,WTG 5120

Interpretation: (B4)+U; (5120)+S; then (s)l,39+ u

1 ,39, and

(u) with cild tag +5120; hence, (B4)

VIII-3

, replaces address at location 5120 and tags are unchanged.

Class 4

Note: all instructions of this class operate with the last 15 bits of the instruction register so that

(s) never pertains to execution.

46 40006 45 4000 00001 symbolically: B6 SB6 al,U+B5

Interpretation: (B6)+U in SETU, l+B6 in OPERATION, then (U)+BS in AUX; hence, B6 is set to 1 and old

(B6) is retained in BS. The U register may be used for transfer of data since i t is not involved in the execution of OPERATION.

15 42002 05 4000 20000 symbolically: -TS MLN a20000,U+T5

Interpretation: -(TS)+U in SETU, then ML#2 turned on in OPERATION, then (U)+TS in AUX. The U register is used for implementation of -(T5)+T5. Only lights designated by l's in the address of the instruction are affected; all others are left unchanged.

04 43005 02 4000 77774 symbolically: T4 STX a-3,U+R

Interpretation: (T4)+U in SETU, 77774-+X in OPERATION,

_ · VII I-4

.,· then (u)+R in AUX.

07 44000 07 4000 00001 symbolically: T7 DMR al,U+T7

Interpretation: (T7)+U in SETU, then arithmetic shift of connected U and R (double mantissa) right

1 in OPERATION, then (U)+T7 in AUX. Effectively,

(T7)/2+T7. Similarly, multiplication by a power of

2 can be accomplished by a doµble mantissa left shift, provided (R) is appropriately pre-set and overflow is observed.

04 45066 51 4000 00005 symbolically: T4 CRL aS,R+Bl

Interpretation: (T4)+U in SETU, then logical circular shift of U and R left 5 places, then (R)+Bl in AUX. If (R) is all zeros b~fore this instru~tion is executed, the first 5 bits of (T4) are sent to Bl as an integer.

Class 5

05 50314 00 0000 00061 symbolically: TS AND 61

Interpretation: (TS) 'and' (61)+U, logical conjunctive operation. If TS contains a mask, those bits of (61) correspondiµg to l's in the mask are retained. in U; all other bits of

(u) will be zero.

·· VI II-5 ·

Class

6

00 60001 00 4002 00100 s ym b o 1i ca 11 y : Z RTR+ alOO+Bl

Interpretation: read successive triads f,r,ow,.,;,paper

-

~

'.J ' :, • tape into R and shift U and R connected logically e left

3 places after each read; when spill from high order U is detected, (u)+lOO+(Bl) to terminate OPERATION. Thus, the first non-zero triad read from paper tape is that which is detected as spill when i t is shifted off the high order end of U, and the following 18 triads read from paper tape are stored at lOO+(Bl). If each absolute numeric word (18 triads) punched on paper tape is preceded by a carriage return or tabulate punch, the carriage control characters provide spill, and successive numeric words will be stored correspondingly in memory by such an instruction provided

Bl is incremented appropriately.

VIII-6

-----

---------

'"

- - - -

IXo

SPECIAL REGISTERS AND TAGS

SPECIAL REGISTERS

The eight machine addresses

77770 through

77777 refer to eight 15-bit registers in the control section of the machineo Four of the registers are displayed at the coniole and in each of these individual bits may be set to uou or u1u states by means of toggle switches:

~hese are the Sense, Indicator, Mode and Trapping registerso Individual bits in these registers are numbered

1 15 from left to right in the word, i.eo, the high order bit is number 1.

A brief summary of the function of each special purpose reg~ster follows.

Sense Lights (SL) Address 77770

By means of Class

4 operati-0ns, individual sense lights may be turned on or off. By means of Class O operations, these may be interrogated one or more at a time, and followed by a SKP or JMP type transfer. The status of the lights is not affected by a Class O int e r r O ga t i On

O

Indicator Lights (IL) Address

77771

By means of Class

4 operations, individual indicator lights may be turned on or off. The first five lights will also be turned on by particular conditions

·· IX-1

.,.,

- - - - · - - -

· · · · - - - - - - - -

- - - - - - - - - - --------·-··which arise in the machine, i.e.,.

IL,rl

IL=l/:2

IL=l/,3

IL#4

IL,N,5

By a word carrying Tag l

(2 or

3) being brought from memory to s after the decoding of the SET s field.

By a mantissa overflow in u.

By an exponent overflow in u.

The~e lights may be interrogated by any Class O order.

They remain on until tested, or until tur~ed off manu~

~lly or by a Class 4 order.

Mode Lights (ML) Address 77772

By means of Class 4 operations,, individual mode lights may be turned on or off. Only mode lights nos •

1, 2,

3, and 4 have particular significance at present.

ML#l: Non-rounding Mode.

When ML

#1 is on, a rounding bit (bit

18 or octal

1 in OP3) in a Class 1 instruction is ignored.

ML ,j/,2.: Repeat Mode.

When ML

#2 is turned on, ~he normal sequencing of instructions is halted after the next command is fetched into

I: the machine is then said to be in the 'Repeat

Mode.

1

In this situation, _the command in I will be obeyed repeatedly until one of four conditions arises:

(a) AB-register is counted to ~era in AUX.

(b) A tagged word enters the arithmetie unit.and a tag indicator light is turned on.

IX-2

....

(c) A test in Class O is satisfied.

(d)

[rt the command is a

I read' o_rder

..,

J

A 'stop code' is sensed on paper tape.

When one of these conditions is satisfied, the current executive sequence is completed and then the next instruction is fetched to I in the 'normal' way. It is important to note that i f I is subject to B-modification, the last 15 bits of I will change at each decoding of the SETS field.

EXAMPLE:

Let (Bl) = 1, (B2) = 200.

Then the order

I = 00 20001 62 4002 00777, when executed in the repeat mode, will c.lear to zero the words in addresses 1000 to

1177 •

ML

,i,3:

Trapping Mode.

When ML

#3 is turned on, the normal sequencing of instructions may be changed if certain conditions (selected by the status of the Trapping Lights) arise in the machine. The point at which normal sequencing is disturbed is also determined by the status of TL. If

ML

#3 is off, no trapping will occur, irrespective of the condition of TL. When a 'trap transfer' takes place,

ML

#3 is automatically turned off, and transfer is made through a 'trap address' by means of the following instruction, which is placed automatically in I:

IX-3

..,.

..

01 01000 00 4400 AAAAA

Here 'AAAAA' stands for one of eight possible trap addresses, which is dependent on the selected trap condition.

ML =#=4:

Suppress Tag Mode,

When ML #4 is on, indicator lights 1, 2, and

3

(the tag indicators) are not turned on when a tagged number is brought into the arithmeti~ section.

This mode is primarily useful in avoiding exiting from the repeat mode when a tagged number is brought into S.

Trapping Lights (TL) Address 77773

By means of Class 4 operations, individual trapping lights may be turned on or off. When the machine is running in the trapping mode, trap transfers will take place if the lights corresponding to the conditions listed below are turned on: in each case the corresponding trap address and the point of trapping are given, and i t is a matter for the coder to ensure that this completes a transfer to a sequence of coding to be obeyed if a trap condition is satisfied.

LIGHT

CONDITION TRAP TIME

#1

Ari th. Tag 1

ADDRESS

(OCTAL)

15

Ari th. Tag 2

After SETS, before OPN 16

=#=2

#3 Ari th. Tag

3

17

IX-4

- - - - - - ~ - - - - - - - - -

#10

#11

,H,12

#13

#7

#8

#9

LIGHT

#4

#5

#6

CONDITION TRAP TIME

Control Tag 1 After fetch-

Control Tag 2 ing I, before

Control Tag 3 SETU

ADDRESS

(OCTAL)

11

12

13

Control Tag 1 After

Control Tag

2

AUXILIARY

Control Tag 3

(u) positive

(u) negative

MOV Light on

EOV Light on

After AUXIL-

14

IARY, and after 14 tag tests in-

14

14 dicated by TL

#7,#8 and #9

11

12

13

#14

#15

Not used.

Second Pathfinder (P2) Address 77774

On all modifications to CC except for the initial increment by 1 at the beginning of an instruction sequence, the initial contents of CC are stored in P2.

This register is mainly used for engineering purposes.

Increment Register (X) Address 77775

The contents of this register are used in Class O transfers of the 'JMP' variety (03XXX or 07XXX), and

IX-5

by the AUXILIARY operation 'Bi+X', i.e., the code 3i.

It may be loaded by a Class 4 order.

To Tape (TT) Address 77776

From Tape (FT) Address 77777

These registers are used in control of magnetic tape input and output by the machine and are not generally used by the coder.

Storage in Special Purpose Registers

A special purpose register may be treated partly, but not entirely, as any other storage register in the machine. It contains only 15 bits, and hence on fetching i t to S i t is stored in bits 40-54 of s, while bits

1-6 of Sare set to O, and bits

7-39 are set equal to bit 40. A fifteen bit number may be stored in

P2, X,

TT or FT from bits 40-54 of U. Upon storing to SL, TL,

ML or IL however, a logical 'or' takes place with the bit pattern already in that register. It should be noted for a bit in one of the latter four registers that unless the corresponding toggle switch is in the 'neutral' position, its status is invariant with respect to store operations.

TAGS

Each general location in electrostatic memory contains, in addition to a 54-bit instruction or data word,

· IX-6

two tag bits. It has already been indicated that when such a word is brought to s, the condition of the tag bits may cause IL #1, #2 or

#3 to be turned on. Additionally, the tag bits are stored temporarily in a nonaddressable two-bit Arithmetic Tag Register (ATR). The status of ATR is only changed when a new word is brought from electrostatic memory (by substitution of the new tag bits). When a fast register, or one of the special purpose registers, is brought to s, ATR is unchanged, and so are IL #1, #2 and

#3.

Arithmetic tag trapping takes place on the basis of the bits in ATR. The operations in Class 2 provide for ATR to be cleared, or set to any particular value after loadings.

When a store sequence takes place, the tag bits are taken from.ATR.

In the control unit, corresponding to ATR is a control tag register, CTR, of two bits, which is reset and loaded when any instruction is brought to I. Control trap transfers take place on the basis of the bits in CTR. There is no means of directly altering CTR.

Figure 2 illustrates the role of the tag bits in data transfers in the machine.

IX-7

x.

MAGNETIC TAPES

The magnetic tape facilities are not yet finished.

All of the machine users await their completion hopefully and impatiently.

X-1

XI.

BINARY POINT LOCATION AND FLOATING

POINT ARITHMETIC

Fixed point

In fixed point operations the exponent bits are not used • U, R and S sh o u 1 d be though t o f a s 4 7 bi t (man tissa) registers, each supplied with a sign bit (bit 7).

These registers obey rules very much the same as those obeyed by the registers of a desk calculator. Any of the usual desk calculator conventions may be used in regard to the location of the binary point in each register.

There are two simple and common conventions, however, that are used more than any others:

Fractional fixed point: The binary point in all registers is assumed to be between bits 7 and 8, just to the left of the mantissa. The number range is therefore from

The result of any arithmetic operation must also fall in this range. In the case of addition or subtraction, i t is possible to exceed the permissible number range (indicated by the mantissa overflow indicator, IL#4, turning on). It is not possible to develop overflow in multiplication. After multiplication, the upper half of the product is found in U (with the standard binary point convention); the mantissa of R is

. , XI-1

the continuation of this product.

The sign bit of R will agree with the sign bit of U. After two fixed point numbers, A and

B, are multiplied (with the operation code

10200), we have

Ax B

=

(U) + (R)2- 47

After a division of A by B (code 10300), we have

(U) x B

+

(R)x2- 47

=

A.

Note that the remainder, in R, may be interpreted in two ways (1) using the standard binary point of R, the true re ma in de r i s ( R ) 2 - 4

7; (

2 ) a 1 t e r n a t iv e 1 y , th e b in a r y p o in t of the remainder in R is actually 47 places to the left of the usual point in R. These remarks are also true of a desk calculator.

Ordinary division (code 10300) uses the double length register U, Ras the dividend. The code 12300 will clear R to zero (of appropriate sign) and thus accomplish the single length division,

(u) 7 (s).

In case the quotient exceeds the permissible number range

(i.e., magnitude~ 1), the divide check light (IL#6) will turn on.

Integer fixed point:

The standard binary point convention in this system is that the point lies at the right end of all registers, i . e . , all numbers are signed integers.

The operation codes 10000 and 10100, of course, serve as integer add and subtract orders. Multiplication

, XI-2

may be accomplished by 10200; however, the integer product will be found in

Ro

If one is sure the product will not be as large in magnitude as 2 47 , the code 10220 will introduce

a

final u,

R interchange, leaving the product in

U.

Integer divide is accomplished by 13300.

The integral quotient will be found in

U and the remainder in

R.

For some purposes, one may want to use 13320, thus leaving the remainder in

Uo

Note that addresses and the contents of

B registers are brought into the arithmetic unit as integers according to these conventions. However, the integer address range is effectively -(2 14 - 1) to +(2

14

1), since the left-most bit of an address acts as

a

sign bit when a short register is brought into a long register.

Floating Point

As has been explained previously, floating point numbers use for a fractional part the same mantissa as do fixed point numbers.

The binary point convention is the same as in fractional fixed point.

The left-most six bits of the word are used to hold an integral exponento The highest order bit is used as a sign bit (in the usual one's-complement system) so the exponent range is -31 to +31 (decimally) or

-37

to +37 (octally). The assumed base is 2 8

=

256.

XI-3

- - - - - - - - - - ~

The floating. point arithmetical orders are primarily designed to accept normalized floating point numbers and produce normalized floating point an-swers.

A normalized floating point number has no more than seven lead zeros in the mantissa of a positive number

(or no more than seven lead ones in a negative number) so the mantissa is in the range

2

-a

<

I mantissa

I

<

1 - 2

-41

The operation codes 10400 and 10500 will form

(u)

+

(s) in u and

(u) -

(s) in u, respectively. Code

10600 will f6rm

(U) X

(s) in u, with the lower (less significant) portion of the product in

R. R will have the same exponent and mantissa sign as u, so the exact product is

(u) + (R)

2- 47 • The cdde 10700.will divide

(U,R) by (s), leaving trre quotient in

U and the remainder in

R.

Just as in fixed point division, if

A is divided by

B,

(U) X B

+

(R) X 247 ; A.

The code 12700 clears R before performing the division; the result is then that the single lengt~ number in U

· is divided by the number i n s .

In floating point arithmetic it is not possible to get mantissa overflow~

Ii during the process of the floating -0peration and subsequent normalization, an

XI-4

----- - -------- -- - - exponent larger than decimal 31 appears, the exponent overflow light (IL#S) turns on. On the other hand, if the exponent should count down to less than ~31, we have an exponent underflow condition

0

No indicator light is provided; instead the U and R registers are both cleared to null, i . e . , to plus zero. The philosophy is that any number requiring an exponent less than -31 is to be treated as zero.

After addition or subtraction, a maximum of five normalization left shifts (of eight bits each) is allowed. The difference between two identical floating point numbers, for example, will appear with mantissa equal to zero (minus zero, as is the rule in one'scomplement systems) and with an exponent decreased by five.

After multiplication, a maximum of twelve normalization left shifts is allowed. No provision is made for normalization after division since i t is not needed if the dividend and divisor are normalized.

If one of the two input numbers to a floating operation is fixed poirit (distinguished by a plus zero

(octal 00) exponent) and the other is floating point, the fixed point number is treated as a true zero. This feature is primarily useful in making the null number,

XI-5

plus zero, obtained as an underflow or from the address zero, behave as a true floating point zero:

A

+

0

=

A

A X O

= 0

0 ; A

=

0

In addition, floating point addition of a (possibly unnormalized) number A to the contents of address zero serves to normalize A.

If both of the two input numbers are fixed point, a fixed point operation is carried out.

Zero. In all floating point systems, the number zero always requires special treatment. We have given some of the properties of zero in the preceding paragraphs.

I t may be well to summarize them here.

If the mathematical result of an arithmetic operation is zero, in our one's-complement system i t normally appears as minus zero (all ones). The only exceptions are such cases as

(+O) + (+o), (+O)

X

(+O), etc. In exponents, a plus zero is taken as an indication of a fixed point number. Null (z, +O or the contents of the

Z register (address o)) behaves as a proper fixed point or floating point zero.

XI-6

If two equal floating point numbers are subtracted

(and exponent underflow does not occur during the subsequent normalization), the result is an approximate zero.

The exponent will be different from 00 ( i t will be exactly five less than the exponents of the two numbers) but the mantissa will be minus zero.

This number will behave as a true zero when added to another floating point number with equal or greater exponent~ when added to a floating point number with an exponent smaller by six or more, all of the mantissa of the number with the smaller exponent will be shifted off and lost when i t is unnormalized in preparation for the addition.

The result will be another approximate zero.

If the difference in exponents is less than six, some of the low order bits in the non-zero mantissa will be lost.

XI-7

~

RICE COMPUTER

CONSOLE DISPLAY AND CONTROLS

TURNING OFF

TURNING ON

OFF-, , - B-REGS

LIGHTS

MEMORY

T-REGS

I

FEED PAPER TAPE

!ADVANCE PRINTER PAPER

RESET CONTROL

I .-

LOAD PAPER TAPE U,R,S TURN ON/OFF

ON

CIIID OITD OIID OTID aITD

SENSE

EB ElHB EB EB EB EB EB EB EB EB EB EB E!HB

CITID CITID

a:rro

CITID ODD

INDICATOR

EB EB EB EB EB EB EB EB EB EB EB EB EB EB EB aa~I I

Ell Ell e

Ell e j [:

Ell e

Ell

UNCORRECTABLE

MEMORY ERROR

LOW

PAPER TAPE

OTID OIID CITID CITID CITID

MODE

EIHB EB EB EB EB EB EB EB EB EB EB EB EB EB m:ID aaD

CIITD arrD

OlID

TRAP

EB EB EB EB EB EB EB EB EB EB EB EB EB EB EB

TRAP l

Q

TRAP 2

Q

TRAP 3

Q Q

TRAP 4

CID CID

CIT)

GJ

<ID

O O O

I

le

I

/e

I

/G;J

I

/(ff;

'+ +

+

°%%°%%%~%%~%%%~%%%%%u

O

TYPE

ooouoocH)oooooooo oo

~

%~~%%%%~%%%%%%%%%~

I

%~~~~cc

FO Fl F4

FETCH SETU SETS

F2 F3

OPN AUX

TRAP CONTINUE

+

PUSHBUTTON

Q

LIGHT

$

SWITCH

FIG. 5

XII.

MANUAL CONTROLS

A modified IBM typewriter and a set of switches and lights for controlling the machine and observing the status of particular registers are located at the operator's console. In addition, other units on the machine have controls which are of interest to the operator.

Typewriter

This is used for input and output of octal numbers only. On the typed form, all input information appears in red and output in black. Apart from its own keys, the typewriter is controlled by a set of push-buttons situated on the console immediately to the left of the typewriter. In order to type into a register, the following procedure is sufficient:

1.

Depress the red 'Read-in' button~ At this point the red light on the typewriter control panel will be turned on, indicating that i t is ready to read information to the machine.

2. Depress the white button corresponding to the register which is to be loaded. Any fast or special purpose register may be selected, together with the instruction register and a number of others (corresponding to the unlabelled buttons) which are used

XII-1

for engineering purposes. At this point the typewriter carriage will retuin, and a one or two letter mnemonic corresponding to the selected register will be typed at the beginning of the line. If a short register has been selected, the carriage will 'tab

0 across 13 positions. The selected register will be cleared.

3.

Type the octal number to be loaded into the register

(either 5 or 18 digits). After completing the loading, the carriage automatically 'tabs' across five positions. At this point on the line, notes may be typed without affecting the status of the machine.

4.

To type into other registers, repeat from step

(2).

In order to type out the contents of a register, the following procedure is sufficient:

1. Depress the green

1

Read-out' button.

2.

Depress the white button corresponding to the register which is to be read out. At this point, the carriage automatically returns, and

a

one or two letter mnemonic is typed out, followed by the content of the selected register.

3.

To read out of the other registers, repeat step

(2).

XII-2

Portable Keyboard

Situated on the console is a small keyboard which may be used in a manner analogous to the typewriter for the input of numbers to u,

I and CCo Depressing one of these three keys is equivalent to performing step 1 of the typewriter read-in sequence, followed by the selection of

U,

I or CC in step

2.

Step

3 may be execut.ed from this keyboard, ·or from the typewriter.

Console Switches

At the left side of the console display panel is a bank of four registers (Figure 5), each containing 15 bits grouped into five triads. These registers are

(reading downwards) the Sense, Indicator,·Mode and Trapping Light displays, together with their associated toggle switches. Each toggle switch has three positions: up ("on",

11

1

11 ) , down (ttoff", "O") and neutral. Only when a toggle switch is neutral may the corresponding light be turned on and off under machine control.

Console Controls

At the center of the console display are pushbuttons and switches which are used to control the execution of programs. Starting at the top left-hand corner are the following sets of controls:

,· XII-3

Machine On-Off Switch and Lights: The on/off switch may be used to turn the machine on whenever the

(white) 'off' light is on. The sequence of turning on various sections of the machine is automatically controlled and is completed aftet about 4 ~inutes, when the

(green) 'on' light will be turned on. This switch also controls input-output equipment, and i t is therefore advisable to run out printed paper or punched tape before turning off the machine.

Clear Switches: Depressing one of these five switches causes the registers in the corresponding section of the machine to be cleared to zero, viz:

1. u,

R and s

2.

T4, TS, T6, T7

3.

All eight B-registers

4.

All special purpose registers, I,

ATR, and CTR.

S.

Memory (including tags). To clear memory completely, this switch must be held down for about a second.

Many-One Switch:

This is used for engineering tests only and should normally be in the neutral position.

Feed Paper Tape: Depressing this switch causes paper tape to be punched at the tape punch with 'tape feed'

XII-4

characters for as long as the switch is held down.

Advance Printer Control:

Depressing this switch causes paper to be passed through the printer until a new page is positioned for printing, or until the switch is released. Raising the switch effects continual paper advance until the switch is released.

Reset Control: Depressing this switch turns off all control flip-flops.

Load Paper Tape: Depressing this switch has the following effect, assuming paper tape has been placed in the reader:

(1) U, I and CC are cleared.

The number

00 60020 00 0000 00000 is stored in

I .

(A read triads order).

(2) An execution sequence is started in OPN

(Field 2).

The effect of this is that triads are read into U until a spill occurs at the high order end of U. At this point Field 2 terminates, Field

3

(no oper~tion) is executed, and the next instruction is brought to I from U.

(3)

Since the machine is in the repeat mode, i t will execute the order in I until one of the

XII-5

.. four necessary conditions ·arises for leaving the repeat mode. During execution of this order,

(cc)= 1.

Field Control: Corresponding to each field in an instruction are two lights, a switch and a push button on the Console Controls.

A single instruction cycle is executed in five separate steps, during each of which a certain field is decoded, and at the end of which the following step is initiated or 'primed'. ln order to initiate a program, therefore, i t is sufficient to prime manually the execution of one field of the instruction cycle. An instruction cycle is considered to begin with the 'FETCH' (Field 0) in which the next instruction to be executed is brought to I.

On the console, the field control lights are arranged from left to right according to their order of execution:

FETCH, SETU, SETS, OPN,

AUX (See Section VII).

In order to prime a field, the appropriate switch should be raised and then lowered to neutral. In this state, the left one of its two lights will be on.

In order to execute a primed field, the appropriate switch should be depressed. During execution, the right one of its two lights will be on. At the end of execution, the following field (FETCH following AUX)

XII-6

• w i 11 be primed. An alternative method of executing a primed field when the switch is neutral is to press the appropriate push-button.

Each field control switch may be locked in any of i t s three positionso

The 'normal' state during program execution is to have all five switches down, permitting fully automatic execution once the cy~le has been entered.

Continue Light, Switch and Push Button: The continue switch is effective only when a 'halt and transfer' order (Class o) is about to alter

(cc).

If the switch is locked down, the 'halt' is not observed, and the transfer will be made in the same way as a 'transfer' code. If the switch is neutral, the machine will halt in executing OPN (Field 2) and the· continue light will be turned on. The normal cycle is re-entered when the continue button is pressed.

If the switch is locked up, the machine will halt and sound a bell.

Trap Lights:

The four trap lights and the trapping light, switch and push button are effective only when a trap transfer is about to take. place.

If the trap switch is locked down, the transfer will be made immediately.

I f the trap switch is neutral, a halt will occur with the

..xII-7

0

..

..

- - - - - - - - --------

- - - - trapping light and one of the four trap lights on; at this point, pressing the trap button will cause calculation to proceed.

The trap light which is on indicates the point of the instruction cycle at which trapping has occurred, i . e . ,

Trap 1. After loading I (Control Tag Trap)

Trap 2. After loading S (Arithmetic Tag Trap)

Trap

3.

After executing AUXILIARY (Control

Tag Trap)

Trap 4. After executing AUXILIARY (Ar~thmetic Status Trap).

Console Displays

At the right side of the control panel are three groups of lights which display the contents of the registers U, I and CC. Associated with I is the two bit control tag register (CTR) display.

A fourth display of nineteen lights indicates the position of the typewriter carriage relative to a machine register during a type-in or type-out operation.

Printer

There are two push-buttons on the printer. The upper one, when held down, will restore paper to a new page • The lower one will feed paper as long as i t is

--XII-8

..

Q

d

held down.

All printer operations stop automatically when the end of the paper is sensed.

Punch

There is a single push-button on the punch, which causes tape to be punched continuously with 'tape feed' characters as long as i t is held down •

XII-9

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