User manual | TLK2711 1.6 TO 2.7 GBPS TRANSCEIVER D

TLK2711

1.6 TO 2.7 GBPS TRANSCEIVER

1.6 to 2.7 Gigabits Per Second (Gbps)

Serializer/Deserializer

Hot-Plug Protection

High-Performance 80-Pin BGA Microstar

Junior



Package (GQE)

2.5-V Power Supply for Low Power

Operation

Programmable Preemphasis Levels on

Serial Output

Interfaces to Backplane, Copper Cables, or

Optical Converters

On-Chip 8-bit/10-bit Encoding/Decoding,

Comma Detect

On-Chip PLL Provides Clock Synthesis

From Low-Speed Reference description

Receiver Differential Input Thresholds

200 mV Minimum

Low Power: < 500 mW

3 V Tolerance on Parallel Data Input Signals

16-Bit Parallel TTL Compatible Data

Interface

SLLS501 – SEPTEMBER 2001

Ideal for High-Speed Backplane

Interconnect and Point-to-Point Data Link

Industrial Temperature Range (–40

C to

85 C RCP Package Only)

Loss of Signal (LOS) Detection

Integrated 50-

Ω

Termination Resistors on

RX

The TLK2711 is a member of the WizardLink transceiver family of multigigabit transceivers, intended for use in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK2711 supports an effective serial interface speed of 1.6 Gbps to 2.7 Gbps, providing up to 2.16 Gbps of data bandwidth.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50

Ω

. The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over parallel solutions, as well as scalability for higher data rates in the future.

The TLK2711 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 2.7 Gbps.

The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (TXCLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8b/10b) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (TXCLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the recovered clock (RXCLK). It then decodes the 20-bit wide data using the 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 2 Gbps to 2.5 Gbps (16 bits data x the frequency).

The TLK2711 is provided in two packages options: a 80-pin ball grid array MicroStar Junior package and a

64-pin VQFP (RCP) package.

The TLK2711 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, providing the protocol device with a functional self-check of the physical interface.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar Junior and PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.



2001, Texas Instruments Incorporated

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description (continued)

The TLK2711 has a loss of signal (LOS) detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock.

The TLK2711 allows users to implement redundant ports by connecting receive data bus terminals from two

TLK2711 devices together. Asserting the LCKREFN to a low state will cause the receive data bus terminals,

RXD[0:15], RXCLK, RKLSB, and RKMSB to go to a high-impedance state. This places the device in a transmit-only mode since the receiver is not tracking the data.

The TLK2711 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power efficient, consuming less than 450 mW typically. The TLK2711 is characterized for operation from –40

C to 85

C (RCP only).

The TLK2711 is designed to be hot-plug capable. An on-chip power-on reset circuit holds the RXCLK low and goes to high impedance on the parallel side output signal terminals as well as TXP and TXN during power up.

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TXCLK

TXD8

TXD10

TXD12

GND

TXD3

TXD5

TXD6

VDD

TXD9

TXD11

TXD13

TXD14

TXD1

TXD2

TXD4

TXD7

TLK2711

1.6 TO 2.7 GBPS TRANSCEIVER

SLLS501 – SEPTEMBER 2001

TXP

TXD0

VDD

GQE PACKAGE

(TOP VIEW)

5 4

TXN PRE RXP

GNDA VDDA GNDA

VDD

GND

VDD

GND

TKMSB LOOPEN LCKREFN TESTEN RKMSB

TXD15

TKLSB ENABLE PRBSEN RKLSB

3 6 5

RCP PACKAGE

(TOP VIEW)

RXN

RXD0

GND

RXCLK

RXD11

RXD12

RXD14

RXD15

RXD1

RXD2

RXD4

RXD6

GND

RXD3 H

RXD5

RXD7 F

RXD8 E

RXD9 D

RXD10

RXD13

GND

TXD3

TXD4

TXD5

GND

TXD6

TXD7

GTX_CLK

TXD8

TXD9

TXD10

GND

TXD11

TXD12

TXD13

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19

20 21 22 23 24 25 26 27 28 29 30 31 32

RXD3

RXD4

RXD5

RXD6

GND

RXD7

RX_CLK

RXD8

RXD9

RXD10

RXD11

RXD12

RXD13

GND

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block diagram

LOOPEN

PRBSEN

TXD0–TXD15

TKLSB

TKMSB

PRBSEN

8b/10b Encoder

MUX

PRBS

Generator

2:1

MUX

Parallel to

Serial

BIAS

TXCLK

TESTEN

PRBSEN

ENABLE

RKLSB

RXCLK

RXDO–RXD15

RKMSB

Controls:

PLL,Bias,Rx,

Clock

Synthesizer

Interpolator and

Clock Recovery

2:1

MUX

2:1

MUX

PRBSEN

PRBS

Verification

Recovered

Clock

Comma

Detect and 8b/10b

Decoding

Comma

Detect and 8b/10b

Decoding

1:2

MUX

Serial to

Parallel

Signal Detect

(LOS)

Figure 1. TLK2711 Block Diagram

2:1

MUX

Data

Clock

TXP

TXN

PRE

RXP

RXN

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Terminal Functions

NAME

ENABLE

TERMINAL

NO.

GQE

RCP

GND

GNDA

LCKREFN

A1, J1,

D3, E3,

F3, G3,

C4, D4,

E4, F4,

G4, A9, J9

H4, H6

5, 13, 18,

28, 33, 43

52, 58, 61

B5 25

I† Device enable. When this terminal is held low, the device is placed in power-down mode. Only the signal detect circuit on the serial receive pair is active. When asserted high while the device is in power-down mode, the transceiver goes into power-on reset before beginning normal operation.

Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.

LOOPEN

PRE

PRBSEN

RKLSB

RKMSB

RXCLK

RX_CLK

† Internal 10k pullup

‡ Internal 10k pulldown

I†

I‡

Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and

TX.

Lock to reference.

When LCKREFN is low, the receiver clock is frequency locked to TXCLK.

This places the device in a transmit only mode since the receiver is not tracking the data.

When LCKREFN is asserted low, the receive data bus terminals, RXD[0:15], RXCLK and

RKLSB, RKMSB are in a high-impedance state.

When LCKREFN is deasserted high, the receiver is locked to the received data stream.

Loop enable. When LOOPEN is active high, the internal loop-back path is activated. The transmitted serial data is directly routed internally to the inputs of the receiver. This provides a self-test capability in conjunction with the protocol device. The TXP and TXN outputs are held in a high-impedance state during the loop-back test. LOOPEN is held low during standard operational state with external serial outputs and inputs active.

Preemphasis control. Selects the amount of preemphasis to be added to the high speed serial output drivers. Left low or unconnected, 5% preemphasis is added. Pulled high, 20% preemphasis is added.

PRBS test enable. When asserted high results of pseudo random bit stream (PRBS) tests can be monitored on the RKLSB terminal. A high on RKLSB indicates that valid PRBS is being received.

K-Code indicator/PRBS test results. When RKLSB is asserted high, an 8-bit/10-bit K code was received and is indicated by data bits RXD0–RXD7. When RKLSB is asserted low an

8-bit/10-bit D code is received and is presented on data bits RXD0–RXD7.

When PRBSEN is asserted high this pin is used to indicate status of the PRBS test results

(high = pass).

K-code indicator. When RKMSB is asserted high an 8-bit/10-bit K code was received and is indicated by data bits RXD8 –RXD15. When RKMSB is asserted low an 8-bit/10-bit D code was received and is presented on data bits RXD8 – RXD15. If the differential signal on RXN and RXP drops below 200 mV, then RXD [0:15], RKLSB, and RKMSB are all asserted high.

Recovered clock. Output clock that is synchronized to RXD [0..9], RKLSB, and RKMSB.

RXCLK is the recovered serial data rate clock divided by 20. RXCLK is held low during power-on reset.

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RXD0

RXD1

RXD2

RXD3

RXD4

RXD5

RXD6

RXD7

RXD8

RXD9

RXD10

RXD11

RXD12

RXD13

RXD14

RXD15

RXN

RXP

DINRXN

DINRXP

TESTEN

TKLSB

TLK2711

1.6 TO 2.7 GBPS TRANSCEIVER

SLLS501 – SEPTEMBER 2001

Terminal Functions (Continued)

NAME

TERMINAL

NO.

GQE

RCP

I‡

I†

Receive data bus. These outputs carry 16-bit parallel data output from the transceiver to the protocol device, synchronized to RXCLK. The data is valid on the rising edge of RXCLK as shown in Figure 5. These terminals are in high-impedance state during power-on reset.

Serial receive inputs. RXP and RXN together are the differential serial input interface from a copper or an optical I/F module.

TKMSB

TXCLK

GTX_CLK

I†

Test mode enable. This terminal should be left unconnected or tied low.

K-code generator (LSB). When TKLSB is high, an 8-bit/10-bit K code is transmitted as controlled by data bits TXD0 –TXD7. When TKLSB is low an 8-bit/10-bit D code is transmitted as controlled by data bits TXD0 – TXD7.

K-code generator (MSB). When TKMSB is high an 8-bit/10-bit K code is transmitted as controlled by data bits TXD8 –TXD15. When TKMSB is low an 8-bit/10-bit D code is transmitted as controlled by data bits TXD8 – TXD15.

Reference clock. TXCLK is a continuous external input clock that synchronizes the transmitter interface signals TKMSB, TKLSB and TXD [0..15]. The frequency range of TXCLK is 80 MHz to 135 MHz. The transmitter uses the rising edge of this clock to register the 16-bit input data

TXD [0..15] for serialization.

Transmit data bus. These inputs carry the 16-bit parallel data output from a protocol device to the transceiver for encoding, serialization, and transmission. This 16-bit parallel data is clocked into the transceiver on the rising edge of TXCLK as shown in Figure 2.

TXD0

TXD1

TXD2

TXD3

TXD4

TXD5

TXD6

TXD7

TXD8

TXD9

TXD10

TXD11

TXD12

TXD13

TXD14

TXD15

TXN

TXP

DOUTTXN

DOUTTXP

† Internal 10k pullup

‡ Internal 10k pulldown

O Serial transmit outputs. TXP and TXN are differential serial outputs that interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the TXCLK value. TXP and TXN are put in a high-impedance state when LOOPEN is high and are active when LOOPEN is low. During power-on reset these terminals are high impedance.

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Terminal Functions (Continued)

NAME

VDD

VDDA

TERMINAL

NO.

GQE

C5, D5,

E5, F5,

G5, C6,

D6, E6,

F6, G6,

C7, D7,

E7, F7,

G7, E8

RCP

1, 9, 23,

38, 48

H5 55, 57

I/O

Digital logic power. Provides power for all digital circuitry and digital I/O buffers.

Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and transmitter

detailed description transmit interface

The transmitter portion registers valid incoming 16-bit wide data (TXD[0:15]) on the rising edge of the TXCLK.

The data is then 8-bit/10-bit encoded, serialized, and transmitted sequentially over the differential high-speed

I/O channel. The clock multiplier multiplies the reference clock (TXCLK) by a factor of 10 times, creating a bit clock. This internal bit clock is fed to the parallel-to-serial shift register which transmits data on both the rising and falling edges of the bit clock, providing a serial data rate that is 20 times the reference clock. Data is transmitted LSB (TXD0) first.

transmit data bus

The transmit bus interface accepts 16-bit single-ended TTL parallel data at the TXD[0:15] terminals. Data and

K-code control is valid on the rising edge of the TXCLK. The TXCLK is used as the word clock. The data, K-code, and clock signals must be properly aligned as shown in Figure 2. Detailed timing information can be found in the electrical characteristics table.

TXCLK

TXD[0–15] tsu th

TKLSB, TKMSB

Figure 2. Transmit Timing Waveform transmission latency

The data transmission latency of the TLK2711 is defined as the delay from the initial 16-bit word load to the serial transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly.

The minimum transmit latency t d(Tx latency) is 34 bit times; the maximum is 38 bit times. Figure 3 illustrates the timing relationship between the transmit data bus, the TXCLK, and the serial transmit terminals.

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detailed description (continued)

TXP,

TXN

TXD[0–15]

t d(Tx latency)

16 bit Word to Transmit

TXCLK

Transmitted 20 bit Word

Figure 3. Transmitter Latency

8-bit/10-bit encoder

All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving

PLL has a minimal number of transitions to stay locked on. The encoding scheme maintains the signal dc balance by keeping the number of ones and zeros the same. This provides good transition density for clock recovery and improves error checking. The TLK2711 uses the 8-bit/10-bit encoding algorithm that is used by fibre channel and gigabit ethernet. This is transparent to the user, as the TLK2711 internally encodes and decodes the data such that the user reads and writes actual 16-bit data.

The 8-bit/10-bit encoder converts 8-bit wide data to a 10-bit wide encoded data character to improve its transmission characteristics. Since the TLK2711 is a 16-bit wide interface, the data is split into two 8-bit wide bytes for encoding. Each byte is fed into a separate encoder. The encoding is dependent upon two additional input signals, the TKMSB and TKLSB.

Table 1. Transmit Data Controls

TKLSB

TKMSB

16 BIT PARALLEL INPUT

Valid data on TXD(0–7), Valid data TXD(8–15)

Valid data on TXD(0–7), K code on TXD(8–15)

K code on TXD(0–7), Valid data on TXD(8–15)

K code on TXD(0–7), K code on TXD(8–15)

PRBS generator

The TLK2711 has a built-in 2

-1 PRBS (pseudorandom bit stream) function. When the PRBSEN terminal is forced high, the PRBS test is enabled. A PRBS is generated and fed into the 10-bit parallel-to-serial converter input register. Data from the normal input source is ignored during the PRBS mode. The PRBS pattern is then fed through the transmit circuitry as if it were normal data and sent out to the transmitter. The output can be sent to a BERT (bit error rate tester), the receiver of another TLK2711, or looped back to the receive input. Since the

PRBS is not really random but a predetermined sequence of ones and zeroes, the data can be captured and checked for errors by a BERT.

parallel-to-serial

The parallel-to-serial shift register takes in the 20-bit wide data word multiplexed from the two parallel 8-bit/10-bit encoders and converts it to a serial stream. The shift register is clocked on both the rising and falling edge of the internally generated bit clock, which is 10 times the TXCLK input frequency. The LSB (TXD0) is transmitted first.

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detailed description (continued) high-speed data output

The high-speed data output driver consists of a voltage mode logic (VML) differential pair optimized for a 50-

Ω impedance environment. The magnitude of the differential pair signal swing is compatible with pseudo emitter coupled logic (PECL) levels when ac-coupled. The line can be directly-coupled or ac-coupled. Refer to

Figure 11 and Figure 12 for termination details. The outputs also provide preemphasis to compensate for ac loss when driving a cable or PCB backplane trace over a long distance (see Figure 4). The level of preemphasis is controlled by PRE as shown in Table 2 .

VOD(p)

Table 2. Programmable Preemphasis

VOD(d)

V(TERM)

PRE

PREEMPHASIS LEVEL(%)

VOD(P), VOD(D)†

Bit

Time

Bit

Time

VOD(p)

VOD(d)

Figure 4. Output Voltage Under Preemphasis (|VTXP–VTXN|)

20%

† VOD(p) : Voltage swing when there is a transition in the data stream

VOD(d): Voltage swing when there is no transition in the data stream.

receive interface

The receiver portion of the TLK2711 accepts 8-bit/10-bit encoded differential serial data. The interpolator and clock recovery circuit locks to the data stream and extract the bit rate clock. This recovered clock is used to retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit decoded and output on a 16-bit wide parallel bus synchronized to the extracted receive clock. The data is received LSB (RXD0) first.

receive data bus

The receive bus interface drives 16-bit wide single-ended TTL parallel data at the RXD[0:15] terminals. Data is valid on the rising edge of the RXCLK. The RXCLK is used as the recovered word clock. The data, RKLSB,

RKMSB, and clock signals are aligned as shown in Figure 5. Detailed timing information can be found in the switching characteristics table.

RXCLK

RXD[0–15] tsu th

RKLSB, RKMSB

Figure 5. Receive Timing Waveform

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detailed description (continued) data reception latency

The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output in the aligned parallel word. The receive latency is fixed once the link is established. However, due to silicon process variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly. The minimum receive latency t d(Rx latency)

is 76 bit times; the maximum is 107 bit times. Figure

6 illustrates the timing relationship between the serial receive terminals, the recovered word clock (RXCLK), and the receive data bus.

20-Bit Encoded Word

RXN,

RXP

t d(Rx latency)

RXD[0–15]

16-Bit Decoded Word

RXCLK

Figure 6. Receiver Latency serial-to-parallel

Serial data is received on the RXP and RXN terminals. The interpolator and clock recovery circuit locks to the data stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel shift registers. The 10-bit wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders where the data is then synchronized to the incoming data stream word boundary by detection of the comma

8-bit/10-bit synchronization pattern.

comma detect and 8-bit/10-bit decoding

The TLK2711 has two parallel 8-bit/10-bit decode circuits. Each 8-bit/10-bit decoder converts 10 bit encoded data (half of the 20-bit received word) back into 8 bits. The comma detect circuit is designed to provide for byte synchronization to an 8-bit/10-bit transmission code. When parallel data is clocked into a parallel to serial converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data.

When the serial data is received and converted to parallel format again, a method is needed to recognize the byte boundary. Generally this is accomplished through the use of a synchronization pattern. This is generally a unique pattern of 1’s and 0’s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. The 8-bit/10-bit encoding contains a character called the comma (b0011111 or b1100000), which is used by the comma detect circuit on the TLK2711 to align the received serial data back to its original byte boundary. The decoder detects the comma, generating a synchronization signal aligning the data to their 10-bit boundaries for decoding; the comma is mapped into the LSB. The decoder then converts the data back into 8-bit data. The output from the two decoders is latched into the 16-bit register synchronized to the recovered parallel data clock (RXCLK) and output valid on the rising edge of the RXCLK.

NOTE:

The TLK2711 only achieves byte alignment on the 0011111 comma.

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comma detect and 8-bit/10-bit decoding (continued)

Decoding provides two additional status signals, RKLSB and RKMSB. When RKLSB is asserted , an 8-bit/10-bit

K code was received and the specific K code is presented on the data bits RXD0–RXD7; otherwise, an

8-bit/10-bit D code was received. When RKMSB is asserted, an 8-bit/10-bit K code was received and the specific

K-code is presented on data bits RXD8–RXD15; otherwise, an 8-bit/10-bit D code was received (see Table 3).

The valid K codes the TLK2711 decodes are provided in Table 4. An error detected on either byte, including K codes not in Table 4, causes that byte only to indicate a K0.0 code on the RK

SB and associated data pins, where K0.0 is known to be an invalid 8-bit/10-bit code. A loss of input signal causes a K31.7 code to be presented on both bytes, where K31.7 is also known to be an invalid 8-bit/10-bit code.

RKLSB

RKMSB

Table 3. Receive Status Signals

DECODED 20 BIT OUTPUT

Valid data on RXD(0–7), Valid data RXD(8–15)

Valid data on RXD(0–7), K code on RXD(8–15)

K code on RXD(0–7), Valid data on RXD(8–15)

K code on RXD(0–7), K code on RXD(8–15)

Table 4. Valid K Characters

K CHARACTER

K28.0

K28.1†

K28.2

K28.3

RECEIVE DATA BUS

(RXD[7–0]) OR (RXD[15–8])

000 11100

001 11100

010 11100

011 11100

K28.4

K28.5†

K28.6

K28.7†

100 11100

101 11100

110 11100

111 11100

K23.7

K27.7

111 10111

111 11011

K29.7

111 11101

K30.7

111 11110

† Should only be present on RXD[7–0] when in running disparity < 0.

power down mode

When the ENABLE pin is pulled low, the TLK2711 goes into power-down mode. In the power-down mode, the serial transmit pins (TXN), the receive data bus pins (RXD[0:15]), and RKLSB goes into a high-impedance state. In the power-down condition, the signal detection circuit draws less than 15 mW. When the TLK2711 is in the power-down mode, the clock signal on the TXCLK terminal must be provided.

loss of signal detection

The TLK2711 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage level to keep the clock recovery circuit in lock. The signal detection circuit is intended to be an indication of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an indication of signal coding health. The TLK2711 reports this condition by asserting RKLSB, RKMSB and

RXD[0:15] terminals to a high state. As long as the differential signal is above 200 mV in differential magnitude, the LOS circuit does not signal an error condition.

PRBS verification

The TLK2711 also has a built-in BERT function in the receiver side that is enabled by the PRBSEN. It can check for errors and report the errors by forcing the RKLSB terminal low.

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detailed description (continued) reference clock input

The reference clock (TXCLK) is an external input clock that synchronizes the transmitter interface. The reference clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal serialization bit clock is frequency-locked to the reference clock and used to clock out the serial transmit data on both its rising and falling edges, providing a serial data rate that is 20 times the reference clock.

operating frequency range

The TLK2711 can operate at a serial data rate from 1.6 Gbps to 2.7 Gbps. To achieve these serial rates, TXCLK must be within 80 MHz to 135 MHz. The TXCLK must be within

100 PPM of the desired parallel data rate clock.

testability

The TLK2711 has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable terminal allows for all circuitry to be disabled so that a quiescent current test can be performed. The PRBS function allows for BIST (built-in self-test).

loopback testing

The transceiver can provide a self-test function by enabling (LOOPEN) the internal loop-back path. Enabling this terminal causes serial-transmitted data to be routed internally to the receiver. The parallel data output can be compared to the parallel input data for functional verification. (The external differential output is held in a high-impedance state during the loopback testing.)

built-in self-test (BIST)

The TLK2711 has a BIST function. By combining PRBS with loopback, an effective self-test of all the circuitry running at full speed can be realized. The successful completion of the BIST is reported on the RKLSB terminal.

power-on reset

Upon application of minimum valid power, the TLK2711 generates a power-on reset. During the power-on reset the RXD[0..15], RKLSB, and RKMSB signal terminals go to a high-impedance state. The RXCLK is held low.

The length of the power-on reset cycle is dependent upon the TXCLK frequency, but is less than 1 ms.

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1.6 TO 2.7 GBPS TRANSCEIVER

SLLS501 – SEPTEMBER 2001

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at TXD[0..15], ENABLE, TXCLK, TKMSB, TKLSB, LOOPEN,

PRBSEN, LCKREFN, PRE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

– 0.3 V to 3 V

– 0.3 V to 4 V

Voltage range at any other terminal except above . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V

+0.3 V

Package power dissipation, P

Storage temperature, T stg

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65

C to 150

Electrostatic discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Characterized free-air operating temperature range, T

: RCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

HBM: 4 kV, CDM:1.5 kV

–40

C to 85

C to 70

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

260

† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.

Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values, except differential I/O bus voltages, are stated with respect to network ground.

PACKAGE

DISSIPATION RATING TABLE‡

(

C/W) (

C/W)

TA = 25

POWER RATING

GQE 37.8

4.56

3.3 W

‡ This data was taken using 2 oz trace and copper pad that is soldered directly to a JEDEC standard 4 layer 3 in

3 in PCB.

DISSIPATION RATING TABLE

PACKAGE

RCP64§

≤

2 5

POWER RATING

5.25 W

DERATING FACTOR‡

ABOVE TA = 25

46.58 mW/

TA = 70

POWER RATING

2.89 W

RCP64¶ 3.17 W 23.70 mW/

C 1.74 W

RCP64# 2.01 W 13.19 mW/

C 1.11 W

‡ This is the inverse of the traditional junction-to-ambient thermal resistance (R

JA).

§ 2 oz. Trace and copper pad with solder.

¶ 2 oz. Trace and copper pad without solder.

# Standard JEDEC High-K board.

For more information, refer to TI application note PowerPAD



Thermally Enhanced package, TI literature number SLMA002.

electrical characteristics over recommended operating conditions

PARAMETER

Supply voltage, VDD

TEST CONDITIONS

Frequency = 1.6 Gbps, PRBS pattern

Frequency = 2.7 Gbps, PRBS pattern

Frequency = 1.6 Gbps, PRBS pattern

Frequency = 2.7 Gbps, PRBS pattern

Frequency = 2.7 Gbps, worst case pattern||

Shutdown current

PLL startup lock time

Enable = 0, VDDA, VDD terminals, VDD = MAX

VDD, VDDC = 2.3 V

Data acquisition time

Operating free-air temperature, TA

|| Worst case pattern is a pattern that creates a maximum transition density on the serial transceiver.

MIN NOM MAX UNIT

2.3

2.5

2.7

105

156

– 40

262

390

0.1

1024

0.4

85 mW mW

550 mW mA ms

Bits

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

TLK2711

1.6 TO 2.7 GBPS TRANSCEIVER

SLLS501 – SEPTEMBER 2001

reference clock (TXCLK) timing requirements over recommended operating conditions (unless otherwise noted)

PARAMETER

Frequency

Frequency tolerance

Duty cycle

Jitter

TEST CONDITIONS

Minimum data rate

Maximum data rate

Peak-to-peak

MIN

Typ –0.01%

– 100

40%

TYP MAX

80 Typ+0.01%

135 Typ+0.01%

100

50% 60%

UNIT

MHz

MHz ppm ps

TTL input electrical characteristics over recommended operating conditions (unless otherwise noted), TTL signals: TXDO–TXD15, TXCLK, LOOPEN, LCKREFN, ENABLE, PRBS_EN, TKLSB,

TKMSB, PRE

PARAMETER

IIL

CI tr

VIH High-level input voltage

VIL Low-level input voltage

IIH Input high current

Input low current

Receiver input capacitance

Rise time, TXCLK, TKMSB, TKLSB, TXD[0..15] tf tsu th

Fall time, TXCLK, TKMSB, TKLSB, TXD[0..15]

TXD[0..15], TKMSB, TKLSB setup to

↑

TXCLK

TXD, TKMSB, TKLSB hold to

↑

TXCLK

TEST CONDITIONS

See Figure 7

VDD = MAX, VIN = 2 V

VDD = MAX, VIN = 0.4 V

0.7 V to 1.9 V, C = 5 pF, SeeFigure 7

1.9 V to 0.7 V, C = 5 pF, See Figure 7

See Figure 7

MIN NOM MAX UNIT

1.7

– 40

3.6

0.80

A pF ns

1.5

1 ns ns

0.4

TXCLK

3.6 V

2.0 V

0.8 V

0 V tr tf

TKLSB, TKMSB,

TXD[0–15]

2.0 V

3.6 V

0.8 V

0 V tsu tf th

Figure 7. TTL Data Input Valid Levels for AC Measurements

POST OFFICE BOX 655303

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DALLAS, TEXAS 75265

TLK2711

1.6 TO 2.7 GBPS TRANSCEIVER

SLLS501 – SEPTEMBER 2001

TTL output switching characteristics over recommended operating conditions (unless otherwise noted)

VOH

VOL tr(slew) tf(slew)

PARAMETER

High-level output voltage

Low-level output voltage

Slew rate (rising), magnitude of RXCLK, RKLSB,

RKMSB, RXD[0..15]

Slew rate (falling), magnitude of RXCLK, RKLSB,

RKMSB, RXD[0..15]

TEST CONDITIONS

IOH = –1 mA, VDD = MIN

IOL = 1 mA, VDD = MIN

0.8 V to 2 V, C = 5 pF, See Figure 8

MIN NOM MAX UNIT

2.10

2.3

GND 0.25

0.5

V/ns

V/ns t tsu t th

RXD[0 15] RKMSB RKLSB setup to

↑

RXCLK

RXD[0 15] RKMSB RKLSB hold to

↑

RXCLK

50% voltage swing,

TXCLK = 80 MHz, Figure 8

50% voltage swing,

TXCLK = 135 MHz, See Figure 8

50% voltage swing,

TXCLK = 80 MHz, See Figure 8

50% voltage swing,

TXCLK = 135 MHz, See Figure 8

2.5

ns ns ns ns

RXCLK

RKLSB, RKMSB,

RXD[0–15] tr(slew) tsu tf(slew) th

Figure 8. TTL Data Output Valid Levels for AC Measurements

2.7 V

2.0 V tf(slew)

0.8 V

0 V

2.0 V

2.7 V tr(slew)

0.8 V

0 V

POST OFFICE BOX 655303

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DALLAS, TEXAS 75265

TLK2711

1.6 TO 2.7 GBPS TRANSCEIVER

SLLS501 – SEPTEMBER 2001

transmitter/receiver characteristics

PARAMETER

VOD(d)

VOD(pp_d)

V(cmt)

VID

V(cmr)

Ilkg

)

VOD(p) = |VTXP – VTXN| preemphasis

Deemphais output voltage, |VTXP – VTXN|

Differential, peak-to-peak output voltage with deemphasis

Transmit common mode voltage range,

(VTXP + VTXN)/2

Receiver input voltage differential,

|VRXP – VRXN|

Receiver common mode voltage range,

(VRXP + VRXN)/2

Receiver input leakage current

Receiver input capacitance

TEST CONDITIONS

Rt = 50

Ω

, PREM = high, dc-coupled,

See Figure 9

Rt = 50

Ω

, PREM = low, dc-coupled,

See Figure 9

Rt = 50

Ω

, PREM = high, dc-coupled,

See Figure 9

Rt = 50

Ω

, PREM = low, dc-coupled,

See Figure 9

Rt = 50

Ω

, DC-coupled, See Figure 9

Rt = 50

Ω

, dc-coupled, See Figure 9

Rt = 50

Ω

, See Figure 9 tt, tf

Differential output signal rise, fall time

(20% to 80%)

Jitter tolerance td(Tx latency) Tx latency td(Rx latency) Rx latency

† UI is the time interval of one serialized bit.

Differential output jitter at 2.7 Gbps,

Random + deterministic, PRBS pattern

Differential output jitter at 1.5 Gbps,

Random + deterministic, PRBS pattern

RL = 50

Ω

, CL = 5 pF, See Figure 9

Differential input jitter, random + determinisitc, PRBS pattern at zero crossing

See Figure 3

See Figure 6

VOD(p)

VOD(d)

MIN TYP MAX UNIT

655 725 795

590 650 710

1310 1450 1590

1180 1300 1420

540 600 660 mV

1080 1200 1320 mVp-p

1000 1250 1400 mV

200 1600 mV

1000 1250 2250

–10 10

0.20

A pF

UI†

0.60

0.16

150

UI† ps

107 bits bits

V(cmt)

VOD(pp_d) VOD(pp_p) tf tr

Bit

Time

Bit

Time

VOD(p)

VOD(d)

Figure 9. Differential and Common-Mode Output Voltage Definitions

POST OFFICE BOX 655303

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DALLAS, TEXAS 75265

TLK2711

1.6 TO 2.7 GBPS TRANSCEIVER

SLLS501 – SEPTEMBER 2001

THERMAL INFORMATION thermal characteristics

PARAMETER

Junction-to-free-air thermal resistance

Junction-to-case thermal resistance

TEST CONDITION

Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land

Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land

Board-mounted, no air flow, JEDEC test board

Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land

Board-mounted, no air flow, high conductivity TI recommended test board with thermal land but no solder or grease thermal connection to thermal land

Board-mounted, no air flow, JEDEC test board

MIN TYP MAX UNIT

21.47

42.20

C/W

75.88

0.38

7.8

C/W

POST OFFICE BOX 655303

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DALLAS, TEXAS 75265

TLK2711

1.6 TO 2.7 GBPS TRANSCEIVER

SLLS501 – SEPTEMBER 2001

APPLICATION INFORMATION

VDD

Recommended use of 0.01

Capacitor per VDD terminal

Ω

at 100 MHz

1 nF – 10 nF 1 nF – 10 nF

1 nF – 10 nF

0.01

1 nF – 10 nF

0.01

9 8 7 6 5 4 3

Figure 10. External Component Interconnection

2 1

POST OFFICE BOX 655303

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DALLAS, TEXAS 75265

APPLICATION INFORMATION

TLK2711

1.6 TO 2.7 GBPS TRANSCEIVER

SLLS501 – SEPTEMBER 2001

TXP

Ω

Transmission

Line

RXP

Ω

VDDA

4 k

Ω

TXN

Transmitter

Ω

Transmission

Line

Media

RXN

Ω

6 k

Ω

GND

Receiver

Figure 11. High-Speed I/O Directly-Coupled Mode

TXP

Ω

RXP

Transmission

Line

Ω

VDDA

4 k

Ω

6 k

Ω

GND

TXN

Transmitter

Transmission

Line

Media

RXN

Receiver

Figure 12. High-Speed I/O AC-Coupled Mode

POST OFFICE BOX 655303

•

DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

6-Apr-2015

PACKAGING INFORMATION

Orderable Device

TLK2711IRCP

TLK2711IRCPG4

Status

(1)

NRND

Package Type Package

Drawing

Pins Package

Qty

HVQFP

RCP

160

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU

MSL Peak Temp

(3)

Level-3-260C-168 HR

Op Temp (°C)

-40 to 85

Level-3-260C-168 HR -40 to 85

Device Marking

(4/5)

TLK2711I

TLK2711JRGQE OBSOLETE BGA

MICROSTAR

JUNIOR

GQE 80 TBD Call TI Call TI 0 to 70

TLK2711JRZQE LIFEBUY BGA

MICROSTAR

ZQE 80 360 Green (RoHS

& no Sb/Br)

JUNIOR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

SNAGCU Level-3-260C-168 HR

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

0 to 70 TLK2711JR

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

Samples

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

6-Apr-2015

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLK2711 :

•

Space: TLK2711-SP

NOTE: Qualified Version Definitions:

•

Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 2

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

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