LTC3676/LTC3676-1 Power Management Solution for Application Processors FeaTures

FeaTures

n

Quad I

2

C Adjustable High Efficiency Step Down

n

DC/DC Converters: 2.5A, 2.5A, 1.5A, 1.5A

Three 300mA LDO Regulators (Two Adjustable)

n

DDR Power Solution with V

TT

and VTTR Reference

n

Pushbutton ON/OFF Control with System Reset

n

Independent Enable Pin-Strap or I

2

C Sequencing

n

Programmable Autonomous Power-Down Control

n

Dynamic Voltage Scaling n

Power Good and Reset Functions n

Selectable 2.25MHz or 1.12MHz Switching Frequency n

Always Alive 25mA LDO Regulator n

12µA Standby Current n

Low Profile 40-Lead 6mm

 6mm QFN and 48-Lead

Exposed Pad LQFP

applicaTions

n

Supports Freescale i.MX6, ARM Cortex, and Other n

Application Processors

Handheld Instruments and Scanners n

Portable Industrial and Medical Devices n

Automotive Infotainment n

High End Consumer Devices n

Multi-Rail Systems

LTC3676/LTC3676-1

Power Management Solution for Application Processors

DescripTion

The LTC

®

3676 is a complete power management solution for advanced portable application processor-based systems. The device contains four synchronous step-down

DC/DC converters for core, memory, I/O, and system on-chip (SoC) rails and three 300mA LDO regulators for low noise analog supplies. The LTC3676-1 has a ±1.5A buck regulator configured to support DDR termination plus a VTTR reference output. An I to control regulator enables, power-down sequencing, output voltage levels, dynamic voltage scaling, operating modes and status reporting.

2

C serial port is used

Regulator start-up is sequenced by connecting outputs to enable pins in the desired order or via the I

2

C port. System power-on, power-off and reset functions are controlled by pushbutton interface, pin inputs, or I

2

C.

The LTC3676 supports i.MX, PXA and OMAP processors with eight independent rails at appropriate power levels.

Other features include interface signals such as the VSTB pin that toggles between programmed run and standby output voltages on up to four rails simultaneously. The device is available in a 40-lead 6mm

 6mm QFN and

48-lead exposed pad LQFP packages.

L

, LT, LTC, LTM, Linear Technology, the Linear logo and Burst Mode are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.

Typical applicaTion

V

IN

2.7V TO 5.5V

Start-Up Sequence

V

RTC

3V

25mA

V

DD(HIGH)

2.97V

300mA

V

LDO3

1.8V

300mA

3V

300mA

LDO1

V

IN

SW3

1.5µH

1µF

LTC3676-1

LDO2 SW2

1.5µH

1µF

1.5µH

LDO3 SW4

1µF

1.5µH

LDO4 SW1

1µF

6

ENABLES

PWR_ON

ON

VTTR

WAKE

PGOOD

GND

I

2

C

2

3676 TA01a

47µF

V

ARM

1.38V

2.5A

47µF

V

SOC

1.38V

1.5A

47µF

V

DDR

(V

1.5V

2.5A

DDQ

)

47µF

V

TT

1/2 V

DDQ

1.5A

VTTR (1/2 V

DDQ

WAKE

)

TO µPROCESSOR

5V/DIV

1V/DIV

1V/DIV

WAKE

V

DD(HIGH)

V

LDO3

V

ARM

AND V

SOC

V

DDR

V

TT

AND V

TTR

1ms/DIV 3676 TA01b

For more information www.linear.com/LTC3676

3676fd

1

LTC3676/LTC3676-1

absoluTe MaxiMuM raTings

(Note 1)

V

IN

, DV

DD

, SW1, SW2, SW3, SW4 ............... –0.3V to 6V

SW1, SW2, SW3, SW4

(Transient t < 1µs, Duty Cycle < 5%) ............... –2V to 7V

PV

IN1

, PV

IN2

, PV

IN3

, PV

V

IN_L3

, V

IN_L4

IN4

, V

IN_L2

,

.................................. –0.3V to V

IN

+ 0.3V

LDO1, FB_L1, LDO2, FB_L2, LDO3, LDO4, FB_L4,

FB_B1, FB_B2, FB_B3, FB_B4, PGOOD, VSTB, EN_B1,

EN_B2, EN_B3, EN_B4, EN_L2, EN_L3, EN_L4, ON,

WAKE, RSTO, PWR_ON, IRQ, VTTR,

VDDQIN ....................................................... –0.3V to 6V

SDA, SCL ......................................–0.3V to DV

Operating Junction Temperature Range

DD

+ 0.3V

(Notes 2, 3) ............................................ –40°C to 150°C

Storage Temperature Range ......................–65 to 150°C

pin conFiguraTion

LTC3676

TOP VIEW

40 39 38 37 36 35 34 33 32 31

FB_L2

V

IN_L2

LDO2

LDO3

V

IN_L3

LDO4

V

IN_L4

FB_L4

EN_L4

7

8

9

EN_L3 10

3

4

5

6

1

2

41

GND

11 12 13 14 15 16 17 18 19 20

30

29

28

27

26

25

24

23

22

21

EN_L2

ON

LDO1

V

IN

FB_L1

FB_B2

FB_B1

FB_B4

FB_B3

PWR_ON

LTC3676-1

TOP VIEW

FB_L2

V

IN_L2

LDO2

LDO3

V

IN_L3

LDO4

V

IN_L4

VDDQIN

VTTR

7

8

9

EN_L3 10

3

4

5

6

1

2

40 39 38 37 36 35 34 33 32 31

41

GND

11 12 13 14 15 16 17 18 19 20

30

29

28

27

26

25

24

23

22

21

EN_L2

ON

LDO1

V

IN

FB_L1

FB_B2

FB_B1

FB_B4

FB_B3

PWR_ON

LTC3676

NC

FB_L2

VIN_L2

LDO2

LDO3

VIN_L3

LD04

VIN_L4

FB_L4

EN_L4

EN_L3

NC

7

8

5

6

3

4

1

2

9

10

11

12

UJ PACKAGE

40-LEAD (6mm

× 6mm) PLASTIC QFN

T

JMAX

= 150°C, 

JA

= 33°C/W

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

TOP VIEW

NC SW1 PGOOD RST0 EN_B1 PV EN_B2 W IRQ SW2 NC

48 47 46 45 44 43 42 41 40 39 38 37

49

GND

32

31

30

29

36

35

34

33

28

27

26

25

NC

EN_L2

ON

LDO1

V

IN

FB_L1

FB_B2

FB_B1

FB_B4

FB_B3

PWR_ON

NC

13 14 15 16 17 18 19 20 21 22 23 24

SW4 DV

DD SDA SCL

EN_B4 EN_B3 VSTB

LXE PACKAGE

48-LEAD (7mm × 7mm) PLASTIC LQFP

T

JMAX

= 150°C, 

JA

= 19°C/W


2

LTC3676-1

UJ PACKAGE

40-LEAD (6mm

× 6mm) PLASTIC QFN

T

JMAX

= 150°C, 

JA

= 33°C/W


TOP VIEW

NC SW1 PGOOD RST0 EN_B1 PV EN_B2 W IRQ SW2 NC

48 47 46 45 44 43 42 41 40 39 38 37

NC

FB_L2

VIN_L2

LDO2

LDO3

VIN_L3

LD04

VIN_L4

VDDQIN

VTTR

EN_L3

NC

7

8

5

6

3

4

1

2

9

10

11

12

49

GND

32

31

30

29

36

35

34

33

28

27

26

25

NC

EN_L2

ON

LDO1

V

IN

FB_L1

FB_B2

FB_B1

FB_B4

FB_B3

PWR_ON

NC

13 14 15 16 17 18 19 20 21 22 23 24

SW4 DV

DD SDA SCL

EN_B4 EN_B3 VSTB

LXE PACKAGE

48-LEAD (7mm

× 7mm) PLASTIC LQFP

T

JMAX

= 150°C, 

JA

= 19°C/W



3676fd

LTC3676/LTC3676-1

orDer inForMaTion

LEAD FREE FINISH

LTC3676EUJ#PBF

LTC3676IUJ#PBF

LTC3676HUJ#PBF

LTC3676EUJ-1#PBF

LTC3676IUJ-1#PBF

LTC3676HUJ-1#PBF

TAPE AND REEL

LTC3676EUJ#TRPBF

LTC3676IUJ#TRPBF

LTC3676HUJ#TRPBF

PART MARKING*

LTC3676UJ

LTC3676UJ

LTC3676UJ

LTC3676EUJ-1#TRPBF LTC3676UJ-1

LTC3676IUJ-1#TRPBF LTC3676UJ-1

LTC3676HUJ-1#TRPBF LTC3676UJ-1

PACKAGE DESCRIPTION

40-Lead (6mm  6mm) Plastic QFN




40-Lead (6mm

 6mm) Plastic QFN


TEMPERATURE RANGE

–40°C to 125°C

–40°C to 125°C

–40°C to 150°C

–40°C to 125°C

–40°C to 125°C

–40°C to 150°C

LEAD FREE FINISH

LTC3676ELXE#PBF

LTC3676ILXE#PBF

LTC3676HLXE#PBF

LTC3676ELXE-1#PBF

LTC3676ILXE-1#PBF

TRAY

LTC3676ELXE#PBF

LTC3676ILXE#PBF

LTC3676HLXE#PBF

LTC3676ELXE-1#PBF

LTC3676ILXE-1#PBF

PART MARKING*

LTC3676LXE

LTC3676LXE

LTC3676LXE

LTC3676LXE-1

LTC3676LXE-1

PACKAGE DESCRIPTION

48-Lead (7mm

48-Lead (7mm

48-Lead (7mm

 7mm) Plastic eLQFP

48-Lead (7mm  7mm) Plastic eLQFP

48-Lead (7mm




TEMPERATURE RANGE

–40°C to 125°C

–40°C to 125°C

–40°C to 150°C

–40°C to 125°C

–40°C to 125°C

LTC3676HLXE-1#PBF LTC3676HLXE-1#PBF LTC3676LXE-1 48-Lead (7mm  7mm) Plastic eLQFP –40°C to 150°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/


3676fd

3

LTC3676/LTC3676-1

elecTrical characTerisTics junction temperature range, otherwise specifications are at T

V

IN_L4

= DV

DD

The

l

denotes the specifications which apply over the specified operating

A

= 25°C (Note 2). V

= 3.8V. All regulators disabled unless otherwise noted.

IN

= PV

IN1

= PV

IN2

= PV

IN3

= PV

IN4

= V

IN_L2

= V

IN_L3

=

PARAMETER

Operating Input Supply Voltage, V

IN

V

IN

Standby Current

Step-Down Switching Regulators 1, 2, 3 and 4

Output Voltage Range

Burst Mode ® V

IN

Quiescent Current

Pulse-Skipping Mode V

Forced Continuous V

Maximum Duty Cycle

IN

IN

SW Pull-Down Resistance

Quiescent Current

Quiescent Current

Feedback Pin Input Current

Feedback Reference Soft-Start Rate

High Feedback Regulation Voltage (V

FB

)

Default Feedback Regulation Voltage (V

Low Feedback Regulation Voltage (V

FB

)

FB

)

CONDITIONS

PWR_ON = 0V

V

V

V

FB

FB

= 850mV (Note 5)

= 850mV (Note 5)

FB

= 0V (Note 5)

V

FB

= 850mV

V

FB

= 0V

Regulator Disabled

(Note 6)

DVBxA[4:0] = DVBxB[4:0] = 11111,

V

IN

= 2.7V to 5.5V

DVBxA[4:0] = DVBxB[4:0] = 11001,

V

IN

= 2.7V to 5.5V

DVBxA[4:0] = DVBxB[4:0] = 00000,

V

IN

= 2.7V to 5.5V

Feedback LSB Step Size

Switching Frequency BUCKx[2] = 0

BUCKx[2] = 1

1.5A Step-Down Switching Regulators 1 and 2

PMOS Current Limit

PMOS On-Resistance (Note 7)

NMOS On-Resistance (Note 7)

2.5A Step-Down Switching Regulators 3 and 4

PMOS Current Limit

PMOS On-Resistance (Note 7)

NMOS On-Resistance (Note 7)

Step-Down Switching Regulator 1 and VTTR (LTC3676-1)

Buck 1 Feedback Regulation Voltage

VTTR Output Voltage

VTTR Maximum Output Current

VDDQIN = 1.5V

VDDQIN = 1.5V

I

VIN

VTTR Enabled

LDO Regulators 2, 3 and 4

Feedback Reference Soft-Start Rate

Output Pull-Down Resistance

LDO Regulator 1

Output Voltage Range

Feedback Regulation Voltage (V

FB_L1

)

Line Regulation

Regulator Disabled

Load Regulation

I

LDO1

V

IN

= 1mA, V

LDO1

= 2.7V to 5.5V

= 1.2V,

I

LDO1

V

LDO1

= 0.1mA to 25mA,

= 3.3V

l l l l l l l l l l l l l l l l

MIN

2.7

V

FB

–0.05

100

788

714

404

1.7

0.85

2

3.0

VTTR – 10 VTTR VTTR + 10

0.49•VDDQIN 0.5•VDDQIN 0.51•VDDQIN

–10 10

1

V

FB_L1

689

TYP

12

23

120

170

625

0.8

800

725

412.5

12.5

2.25

1.125

160

80

120

70

10

625

725

0.15

0.1

MAX

5.5

21

PV

IN

50

200

300

0.05

812

736

421

2.7

1.35

V

IN

761

UNITS

V

µA

µA

%

Ω

V

µA

µA

µA

V/ms mV mV mV mV

MHz

MHz

A mΩ mΩ

A mΩ mΩ mV mV mA mA

V/ms

Ω mV

%/V

%

3676fd

4


LTC3676/LTC3676-1


V

IN_L4

= DV

DD

The

l


A

= 25°C (Note 2). V


IN

= PV

IN1

= PV

IN2

= PV

IN3

= PV

IN4

= V

IN_L2

= V

IN_L3

=

PARAMETER

Available Output Current

Short-Circuit Output Current Limit

Dropout Voltage (Note 4)


LDO Regulator 2

V

IN_L2

Input Voltage

LDO2 Output Voltage Range


V

V

IN_L2

Quiescent Current

IN_L2

Shutdown Current

V

IN

Quiescent Current

Feedback Regulation Voltage (V

FB_L2

)

Line Regulation

Load Regulation

Short-Circuit Current Limit



LDO Regulator 3

V

IN_L3

Input Voltage

Output Voltage


V

V

IN_L3

Quiescent Current

IN_L3

Shutdown Current

V

IN

Quiescent Current

Line Regulation

Load Regulation



LDO Regulator 4

V

IN_L4

Input Voltage

LDO4 Output Voltage Range (LTC3676)

Feedback Regulation Voltage (LTC3676) (V

FB_L4

)

Output Voltage (LTC3676-1)


V

V

IN_L4

Quiescent Current

IN_L4

Shutdown Current

V

IN

Quiescent Current

Line Regulation

CONDITIONS

I

LDO1

= 25mA, V

LDO1

= 3.3V

V

FB_L1

= 850mV

I

LDO2

= 1mA

Regulator Enabled, I

LDO2

Regulator Disabled

= 0A

Regulator Enabled

I

LDO2

=1mA, V

IN

= 2.7V to 5.5V

I

LDO2

= 1mA to 300mA

I

I

LDO2

= 300mA, V

LDO2

LDO2

= 300mA, V

LDO2

= 2.5V

= 1.2V

V

FB_L2

= 725mV

V

IN_L3

= V

IN

, I

LDO3

= 1mA


LDO3

Regulator Disabled

= 0A

Regulator Enabled

I

LDO3

=1mA, V

IN

= 2.7V to 5.5V

I

LDO3

= 1mA to 300mA

I

LDO3

= 300mA, V

LDO3

= 1.8V

I

LDO4

= 1mA

I

LDO4

= 1mA, LDOB[4:3] = 00

LDOB[4:3] = 01

LDOB[4:3] = 10

LDOB[4:3] = 11


LDO4

Regulator Disabled

= 0A

Regulator Enabled

I

LDO4

=1mA, V

IN

= 2.7V to 5.5V

l l l l l l l l l l l l l l l l l l l l l l l

MIN

25

–0.05

1.7

V

FB_L2

300

0.707

–0.05

2.35

1.746

300

1.7

V

FB_L4

0.707

1.164

2.425

2.716

2.91

300

TYP

65

200

12

0

50

0.725

0.01

0.01

210

450

1.8

280

0.725

1.2

2.5

2.8

3.0

12

0

50

0.01

14

0

50

0.01

0.05

MAX

100

280

0.05

V

IN

V

IN_L2

25

1

85

0.743

770

260

615

0.05

V

IN

1.854

25

1

85

25

1

85

770

350

V

IN

V

IN_L4

0.743

1.236

2.575

2.884

3.09

UNITS

mA mA mV

µA

µA

%/V

%

V

V mA

µA

µA mA mV

V

V

V

V

V

V

V mA

µA

µA

µA

%/V

V

%/V

% mA mV mV

µA

V

V mA

µA

µA

µA


3676fd

5

LTC3676/LTC3676-1


V

IN_L4

= DV

DD

The

l


A

= 25°C (Note 2). V


IN

= PV

IN1

= PV

IN2

= PV

IN3

= PV

IN4

= V

IN_L2

= V

IN_L3

=

PARAMETER

Load Regulation (LTC3676)

Load Regulation (LTC3676-1)



CONDITIONS

I

LDO4

= 1mA to 300mA

I

I

LDO4

= 300mA, V

LDO4

LDO4

= 300mA, V

LDO4

= 2.5V

= 1.2V

V

FB_L4

= 725mV

MIN

–0.05

TYP

0.01

0.05

210

450

MAX

770

260

615

0.05

Feedback Pin Input Current (LTC3676)

Enable Inputs

Threshold Rising

Threshold Falling

Precision Threshold

Input Pull-Down Resistance

VSTB, PWR_ON Inputs

Threshold

Pull-Down Resistance

Pushbutton Interface

ON Threshold Rising

ON Threshold Falling

ON Input Current

ON Low Time to IRQ Low

ON High Time to IRQ High

ON Low Time to WAKE High

ON Low Time to Hard Reset

IRQ Minimum Pulse Width

IRQ Blanking from WAKE Low

Minimum WAKE Low Time

WAKE High Time with PWR_ON = 0V

PWR_ON High to WAKE High

PWR_ON Low to WAKE Low

Status Output Pins (WAKE, PGOOD, RSTO, IRQ)

WAKE Output Low Voltage

WAKE Output High Leakage Current

PGOOD Output Low Voltage

PGOOD Output High Leakage Current

PGOOD Threshold Rising

PGOOD Threshold Falling

RSTO Output Low Voltage

RSTO Output High Leakage Current

LDO1 Power Good Threshold Rising

LDO1 Power Good Threshold Falling

IRQ Output Low Voltage

IRQ Output High Leakage Current

All Enables Low

One Enable High

One or More Enables

ON = V

IN

ON = 0V

CNTRL[6] = 0

I

WAKE

= 3mA

V

WAKE

= 3.8V

I

PGOOD

= 3mA

V

PGOOD

= 3.8V

I

RSTO

= 3mA

V

RSTO

= 3.8V

I

IRQ

= 3mA

V

IRQ

= 3.8V

l l l l l l

0.4

0.370

0.370

0.4

–1

–0.1

–0.1

–0.1

–0.1

0.75

0.7

0.400

4.5

0.400

4.5

3

3

1

5

10

50

1

0.75

0.7

–40

50

0.2

400

0.1

0.1

–6

–8

0.1

–7.5

–10

0.1

1.2

0.430

0.430

1.2

1

0.4

0.1

0.4

0.1

0.4

0.1

0.4

0.1

sec sec ms ms sec ms sec ms

µs ms

V

V

µA

µA

UNITS

%

% mA mV mV

µA

V

V

MΩ

V

MΩ

V

µA

%

%

V

µA

V

µA

V

µA

%

%

3676fd

6


LTC3676/LTC3676-1


V

IN_L4

= DV

DD

The

l


A

= 25°C (Note 2). V


IN

= PV

IN1

= PV

IN2

= PV

IN3

= PV

IN4

= V

IN_L2

= V

IN_L3

=

PARAMETER

Undervoltage Lockout Rising

Undervoltage Lockout Falling

CONDITIONS

Undervoltage Warning t f t r t

LOW t

HIGH t

SP t

HD_STA t

SU_STA t

SU_STO t

HD_DAT(O) t

HD_DAT(I) t

SU_DAT

SYMBOL

I

2

C Port

PARAMETER

DV

VDD

I

DVDD

DV

DD

Input Supply Voltage

DV

DD

Quiescent Current

DV

VDD_UVLO

DV

DD

UVLO Level

ADDRESS LTC3676 Device Address

LTC3676-1 Device Address

V

IH

V

IL

I

IH

I

IL

V

OL_SDA f

SCL t

BUF

SDA/SCL Input Threshold Rising

SDA/SCL Input Threshold Falling

SDA/SCL High Input Current

SDA/SCL Low Input Current

SDA Output Low Voltage

Clock Operating Frequency

Bus Free Time Between Stop and Start

Condition

Hold Time After Repeated Start Condition

Repeated Start Condition Setup Time

Stop Condition Setup Time

Data Hold Time Output

Data Hold Time Input

Data Setup Time

SCL Clock Low Period

SCL Clock High Period

Clock/Data Fall Time

Clock/Data Rise Time

Input Spike Suppression Pulse Width

CNTRL[4:2] = 000 (POR Default)

CNTRL[4:2] = 001

CNTRL[4:2] = 010

CNTRL[4:2] = 011

CNTRL[4:2] = 100

CNTRL[4:2] = 101

CNTRL[4:2] = 110

CNTRL[4:2] = 111

CONDITIONS

SCL/SDA = 0kHz

SDA = SCL = 5.5V

SDA = SCL = 0V

I

SDA

C

C

B

B

= 3mA

= Capacitance of BUS Line (pF)

= Capacitance of BUS Line (pF) l l l

MIN

2.35

MIN

1.6

–1

–1

1.3

0.6

0

0

0.6

0.6

100

1.3

0.6

20 + 0.1C

B

20 + 0.1C

B

TYP

2.55

2.45

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

TYP

0.3

1

0111100[R/W]

0111101[R/W]

70

30

0

0

MAX

2.65

MAX

5.5

1

1

1

0.4

400

900

300

300

50

µs

µs

µs ns ns ns

µs

µs ns ns ns

%DV

DD

%DV

DD

µA

µA

V kHz

µs

V

µA

V

UNITS

V

V

UNITS

V

V

V

V

V

V

V

V

Note 1: Stresses beyond those listed Under Absolute Maximum ratings may cause permanent damage to the device. Exposure to any Absolute

Maximum rating condition for extended periods may affect device reliability and lifetime.

Note 2: The LTC3676 is tested under pulsed load conditions such that

T

J

≈ T

A

. The LTC3676E is guaranteed to meet specifications from

0°C to 85°C junction temperature. Specifications over the –40°C to

125°C operating junction temperature range are assured by design, characterization and correlation with statistical process controls. The

LTC3676I is guaranteed over the –40°C to 125°C operating junction temperature range and the LTC3676H is guaranteed over the full –40°C to

150°C operating junction temperature range. High junction temperatures

( degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125°C. The junction temperature (T

J

in °C) is calculated from the ambient temperature (T

(P

D

, in Watts), and package to junction ambient thermal impedance

J

A

A

in °C) and power dissipation

in Watts/°C ) according to the formula:

T

J

= T

A

+ (P

D

• J

A

).

Note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors.


3676fd

7

LTC3676/LTC3676-1

elecTrical characTerisTics

Note 3: The LTC3676 includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction temperature may impair device reliability.

Note 4: Dropout voltage is defined as (V

IN

– V

LDO1

(V

IN_Lx

– V

LDOx

) for other LDOs when V measured with V

IN

= V

IN_Lx

= 4.3V.

LDOx

) for LDO1 or

is 3% lower than V

LDOx

Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency.

Note 6: Soft-Start measured in test mode with regulator error amplifier in unity-gain mode.

Note 7: The switching regulator PMOS and NMOS on-resistance is guaranteed by correlation to wafer level measurements.

Typical perForMance characTerisTics

V

IN

= 3.8V, T

A

= 25°C unless otherwise noted

16

Standby I

VIN

vs V

IN

14

12

10

8

6

4

2

0

2.5

3.0

3.5

4.0

VOLTAGE (V)

4.5

5.0

5.5

3676 G01

140

120

100

80

180

I

Step-Down Switching Regulator

VIN

vs V

IN

Burst Mode OPERATION

160

ENABLE FOUR BUCKS

ENABLE THREE BUCKS

ENABLE TWO BUCKS

ENABLE ONE BUCK

60

40

20

0

2.5

3.0

3.5

4.0

VOLTAGE (V)

4.5

5.0

5.5

3676 G04

250

LDO2 to LDO4 I

VIN

vs V

IN

ENABLE 3 LDOs

200

ENABLE 2 LDOs

150

ENABLE 1 LDO

CURRENT (µA) 100

50

0

2.50

3.50

V

IN

(V)

4.50

5.50

3676 G02

1200

Input Supply Current vs Temperature

ALL REGULATORS ENABLED

1000

PULSE-SKIPPING

800

600

400

Burst Mode OPERATION

200

0

–50

STANDBY

0 50

TEMPERATURE (°C)

100 150

3676 G05

2.20

2.15

2.10

2.05

2.00

–50

900

800

700

600

I


VIN

vs V

IN

PULSE-SKIPPING MODE

ENABLE FOUR BUCKS

ENABLE THREE BUCKS

ENABLE TWO BUCKS

500

400

ENABLE ONE BUCK

300

200

100

0

2.5

3.0

3.5

4.0

VOLTAGE (V)

4.5

5.0

5.5

3676 G03

2.30

Oscillator Frequency vs Temperature

2.25

0 50

TEMPERATURE (°C)

100 150

3676 G06

3676fd

8


LTC3676/LTC3676-1


0.8

Oscillator Frequency Change vs V

IN

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

2.5

3.0

3.5

4.0

V

IN

(V)

4.5

5.0

5.5

3676 G07

100

90

Step-Down Switching Regulators 1 and 2 Efficiency vs I

OUT

40

30

20

10

0

1

80

70

60

50

BURST

PULSE

SKIPPING

FORCED

CONTINUOUS

V

IN

V

OUT

= 3.3V

= 1.2V

10 100

LOAD CURRENT (mA)

1000

3676 G08

100

90


OUT

40

30

20

10

0

1

80

70

60

50

BURST

PULSE

SKIPPING

FORCED

CONTINUOUS

V

IN

V

OUT

= 5V

= 1.2V

10 100

LOAD CURRENT (mA)

1000

3676 G09

50

40

30

20

10

0

1

90

80

70

60

100


OUT

V

IN

= 3.3V

PULSE-SKIPPING MODE

V

OUT

= 2.5V

V

OUT

= 1.2V

10 100

LOAD CURRENT (mA)

1000

3676 G10

4.5

4.0

3.5

3.0

2.5


Current Limit vs Temperature

BUCK 3, 4

BUCK 1, 2

250

200

150

100

50

Buck R

DS(ON)

vs Temperature

BUCK 1, 2 PMOS

BUCK 3, 4 PMOS

BUCK 1, 2 NMOS

BUCK 3, 4 NMOS

PGOOD

5V/DIV

VDDQIN

1V/DIV

VTTR

1V/DIV

VTT (BUCK1)

1V/DIV

0

–50 0 50

TEMPERATURE (°C)

100 150

LTC3676-1 VDDQIN, VTTR and

V

TT

Start-Up

3676 G11

100mV/DIV

500mA/DIV

200

Buck R

DS(ON)

vs V

IN

180

BUCK 3, 4 PMOS

160

140

120

100

80

60

40

20

0

2.5

3.5

BUCK 1, 2 PMOS

BUCK 3, 4 NMOS

BUCK 1, 2 NMOS

4.5

V

IN

(V)

5.5

3676 G12


Load Step

V

OUT

= 1.2V

I

LOAD

= 0.5A TO 1.5A

2.0

1.5

–50 0 50

TEMPERATURE (°C)

100 150

400µs/DIV 3676 G14

C

OUT

= 44µF 10µs/DIV 3676 G15

3676 G13


3676fd

9

LTC3676/LTC3676-1


100mV/DIV

LTC3676-1 V

TT

Load Step

LTC3676-1

V

TT

= 0.75V

I

LOAD

= –1.2A TO 1.2A

1A/DIV

C

OUT

= 88µF

V

LDO1

50mV/DIV

I

LDO1

10mA/DIV

40µs/DIV

LDO1 Load Step Response

1.2V

20mA

3676 G16

40µs/DIV

1mA

400

LDO1 Dropout Voltage vs Temperature

I

LDO1

= 25mA

350

V

LDO1

= 1.8V

300

250

V

LDO1

= 3.3V

200

150

100

50

0

–55 0 50

TEMPERATURE (°C)

100

3676 G19

150

60

55

50

45

40

–55

70

65

80

LDO1 Short-Circuit Current vs Temperature

75

0

50

TEMPERATURE (°C)

100

3676 G17

300

250

200

150

100

50

0

–50

LDO2 to LDO4 Dropout Voltage vs Temperature

450

I

LDO

= 200mA

400

V

LDO

= 1.2V

350

V

LDO

= 1.8V

V

LDO

= 3.3V

0 50

TEMPERATURE (°C)

100 150

3676 G20

800

750

700

650

600

550

500

450

400

LDO SHORT-CIRCUIT CURRENT (mA) 350

300

–50

LDO2 to LDO4 Short-Circuit

Current vs Temperature

0 50

TEMPERATURE (°C)

100 150

50mV/DIV

100mA/DIV

LDO2 to LDO4 Load Step Response

V

LDO

= 1.8V

I

LOAD

= 220mA

10µs/DIV

10mA

3676 G22

150

3676 G18

3676 G21

3676fd

10


LTC3676/LTC3676-1

pin FuncTions

(QFN/LQFP)

FB_L2 (Pin 1/Pin 2): Feedback Input for LDO2. Set fullscale output voltage using a resistor divider connected from LDO2 to this pin to ground.

V

IN_L2

(Pin 2/Pin 3): Power Input for LDO2. This pin should be bypassed to ground with a 1μF or greater ceramic capacitor.Voltage on V voltage on V

IN

pin.

IN_L2

should not exceed

LDO2 (Pin 3/Pin 4): Output Voltage of LDO2. Nominal output voltage is set with a resistor feedback divider that servos to a fixed 725mV reference. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor.

LDO3 (Pin 4/Pin 5): Output Voltage of LDO3. Nominal output voltage is a fixed 1.8V. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor.

V

IN_L3

(Pin 5/Pin 6): Power Input for LDO3. This pin should be bypassed to ground with a 1µF or greater ceramic capacitor.Voltage on V voltage on V

IN

pin.

IN_L3

should not exceed

LDO4 (Pin 6/Pin 7): Output Voltage of LDO4. Nominal output voltage is set with a resistor feedback divider that servos to a fixed 725mV reference. This pin must be bypassed to ground with a 1µF or greater ceramic capacitor.

V

IN_L4

(Pin 7/Pin 8): Power Input for LDO4. This pin should be bypassed to ground with a 1μF or greater ceramic capacitor.Voltage on V voltage on V

IN

pin.

IN_L4

should not exceed

FB_L4 (Pin 8/Pin 9): Feedback Input for LTC3676 LDO4.

Set full-scale output voltage using a resistor divider connected from LDO4 to this pin to ground.

VDDQIN (Pin 8/Pin 9): V

DD

Tie DDR memory V

DD

Sense Input for LTC3676-1.

supply to this pin.

EN_L4 (Pin 9/Pin 10): Enable LDO4 Input for LTC3676.

Active high enables LDO4. A weak pull-down pulls EN_L4 low when left floating.

VTTR (Pin 9/Pin 10): DDR V

Pin 8.

REF

Output Pin for LTC3676-1.

Buffered reference equal to one-half VDDQIN voltage on

EN_L3 (Pin 10/Pin 11): Enable LDO3 Input. Active high enables LDO3. A weak pull-down pulls EN_L3 low when left floating.

SW4 (Pin 11/Pin 14): Switch Pin for Step-Down Switching Regulator 4. Connect one side of step-down switching regulator 4 inductor to this pin.

DV

DD

(Pin 12/Pin 15): Supply Voltage for I

2

C Serial Port.

This pin sets the logic reference level of SCL and SDA I

2

C pins. DV

DD

resets I

2

DV

DD

. Connect a 0.1µF decoupling capacitor from this pin to ground.

C registers to power-on state when driven to <1V. SCL and SDA logic levels are scaled to

SDA (Pin 13/Pin 16): Data Pin for the I

I

2

2

C Serial Port. The

C logic levels are scaled with respect to DV

DD

.

SCL (Pin 14/Pin 17): Clock Pin for the I

I

2

2

C Serial Port. The

C logic levels are scaled with respect to DV

DD

.

PV

IN4

(Pin 15/Pin 18): Power Input for Step-Down Switching Regulator 4. Tie this pin to V

IN

supply. This pin should be bypassed to ground with a 10μF or greater ceramic capacitor.

PV

IN3

(Pin 16/Pin 19): Power Input for Step-Down Switching Regulator 3. Tie this pin to the V

IN


EN_B4 (Pin 17/Pin 20): Enable Step-Down Switching

Regulator 4. Active high input enables step-down switching regulator 4. A weak pull-down pulls EN_B4 low when left floating.

EN_B3 (Pin 18//Pin 21): Enable Step-Down Switching


VSTB (Pin 19/Pin 22): Voltage Standby. When VSTB is low, the DAC registers are selected by command register bit DVBxA[5]. When VSTB is high, the DAC registers are forced to DVBxB registers. Tie VSTB to ground if unused.


PWR_ON (Pin 21/Pin 26): External Power On. Handshaking pin to acknowledge successful power-on sequence.

PWR_ON must be driven high within five seconds of

WAKE going high to keep power on. PWR_ON can be


3676fd

11

LTC3676/LTC3676-1

pin FuncTions

used to activate the WAKE output by driving high. Drive low to shut down WAKE.

FB_B3 (Pin 22/Pin 27): Feedback Input for Step-Down

Switching Regulator 3. Set full-scale output voltage using resistor divider connected from the output of step-down switching regulator 3 to this pin to ground.







FB_L1 (Pin 26/Pin 31): Feedback Input for LDO1. Set output voltage using a resistor divider connected from

LDO1 to this pin to ground.

V

IN

(Pin 27/Pin 32): Supply Voltage Input. This pin should be bypassed to ground with a 1μF or greater ceramic capacitor. All switching regulator PV be tied to V

IN

.

IN

supplies should

LDO1 (Pin 28/Pin 33): Always On LDO1 Output. This pin provides an always-on supply voltage useful for light loads such as a watchdog microprocessor or a real time clock.

Connect a 1μF capacitor from LDO1 to ground.

ON (Pin 29/Pin 34): Pushbutton Input. A weak internal pull-up forces ON high when left floating. A normally open pushbutton is connected from ON to ground forcing a low state when pushed.

EN_L2 (Pin 30/Pin 35): Enable LDO2 Input. Active high enables LDO2. A weak pull-down pulls EN_L2 low when left floating.


IRQ (Pin 32/Pin 39): Interrupt Request Output. Open-drain driver is pulled low for power good, undervoltage, and overtemperature warning and fault conditions. Clear IRQ by writing to the I

2

C CLIRQ command register.

WAKE (Pin 33/Pin 40): System Wake Up. Open-drain driver output releases high when signaled by pushbutton activation or PWR_ON input. It may be used to initiate a pin-strapped power-up sequence by connecting to a regulator enable pin.



PV

IN2

(Pin 35/Pin 42): Power Input for Step-Down Switching Regulator 2. Tie this pin to V

IN


PV

IN1

(Pin 36/Pin 43): Power Input for Step-Down Switching

Regulator 1. Tie this pin to V

IN



Regulator 1. Active high enables step-down switching regulator 1. The LTC3676-1 EN_B1 pin enables both VTTR output and switching regulator 1. A week pull-down pulls

EN_B1 low when left floating.

RSTO (Pin 38/Pin 45): Reset Output. Open-drain output pulls low when the always-on regulator LDO1 is below regulation or during a hard reset initiated by a pushbutton input or command registers.

PGOOD (Pin 39/Pin 46): Power Good Output. Open-drain output pulls low when any enabled regulator falls below power good threshold or during dynamic voltage slew unless disabled in command register. Pulls low when all regulators are disabled.


GND (Exposed Pad Pin 41/Pin 49): Ground. The exposed pad must be connected to a continuous ground plane of the printed circuit board by multiple interconnect vias directly under the LTC3676 to maximize electrical and thermal conduction.

3676fd

12


LTC3676/LTC3676-1

block DiagraM—lTc3676

V

IN

LDO1

EN

LDO1

FB_L1

ON

WAKE

PWR_ON

RSTO

PUSHBUTTON

ON/OFF

CONTROL

725mV

DV

DD

SDA

SCL

IRQ

EN_B1

EN_B2

EN_B3

EN_B4

EN_L2

EN_L3

EN_L4

PRECISION ENABLE

THRESHOLD AND

SEQUENCE DELAY

7

I

2

C COMMAND

REGISTERS

7

PGOOD

FAULT DETECTION

UNDER VOLTAGE

OVER TEMPERATURE

VSTB

VSEL

VA 4x5

VB 4x5

DYNAMIC VOLTAGE

SCALING CONTROL

5

5

5

5

DAC

DEFAULT = 725mV

RANGE = 800mV

TO 412.5mV

V

REF

EN

OK

DAC

DEFAULT = 725mV

RANGE = 800mV

TO 412.5mV

V

REF

EN

OK

7

DAC

DEFAULT = 725mV

RANGE = 800mV

TO 412.5mV

V

REF

EN

OK

DAC

DEFAULT = 725mV

RANGE = 800mV

TO 412.5mV

725mV

EN

OK

V

REF

EN

OK

V

REF

EN

OK

V

REF

BUCK1

BUCK2

BUCK3

BUCK4

LDO2

LDO3

FB_B3

PV

IN4

SW4

FB_B2

PV

IN3

SW3

FB_B4

V

IN_L2

LDO2

FB_L2

V

IN_L3

LDO3

PV

IN1

SW1

FB_B1

PV

IN2

SW2

GND

(EXPOSED PAD)


V

REF

EN

OK

LDO4

V

IN_L4

LDO4

FB_L4

3676 BD

3676fd

13

LTC3676/LTC3676-1

block DiagraM—lTc3676-1

V

IN

LDO1

EN

LDO1

FB_L1

ON

WAKE

PWR_ON

RSTO

PUSHBUTTON

ON/OFF

CONTROL

725mV

EN_B1

EN_B2

EN_B3

EN_B4

EN_L2

EN_L3

VTTR

VDDQIN

PRECISION ENABLE

THRESHOLD AND

SEQUENCE DELAY

VDDQIN/2

7

DV

DD

SDA

SCL

IRQ

I

2

C COMMAND

REGISTERS

7

PGOOD

FAULT DETECTION

UNDER VOLTAGE

OVER TEMPERATURE

VSTB

VSEL

VA 4x5

VB 4x5

DYNAMIC VOLTAGE

SCALING CONTROL

5

5

5

DAC

DEFAULT = 725mV

RANGE = 800mV

TO 412.5mV

V

REF

EN

OK

7

DAC

DEFAULT = 725mV

RANGE = 800mV

TO 412.5mV

V

REF

EN

OK

DAC

DEFAULT = 725mV

RANGE = 800mV

TO 412.5mV

725mV

V

REF

EN

OK

V

REF

EN

OK

V

REF

EN

OK

V

REF

EN

OK

BUCK1

BUCK2

BUCK3

BUCK4

LDO2

LDO3

FB_B2

PV

IN3

SW3

FB_B3

PV

IN4

SW4

FB_B4

V

IN_L2

LDO2

FB_L2

V

IN_L3

LDO3

PV

IN1

SW1

FB_B1

PV

IN2

SW2

V

REF

EN

OK

LDO4

V

IN_L4

LDO4

GND

(EXPOSED PAD)

36761 BD

3676fd

14


LTC3676/LTC3676-1

operaTion

INTRODUCTION

The LTC3676 is a complete power management solution for portable microprocessors and peripheral devices. It generates a total of eight voltage rails for supplying power to the processor core, DDR memory, I/O, always-on realtime clock and HDD functions. Supplying the voltage rails are an always-on low quiescent current 25mA LDO, two

2.5A step-down regulators, two 1.5A step-down regulators, and three 300mA low dropout regulators. Supporting the multiple regulators is a highly configurable power-on sequencing capability, dynamic voltage scaling DAC output voltage control, a pushbutton interface controller, control via an I

2 outputs.

C interface, and extensive status and interrupt

The LTC3676-1 supports DDR memory applications by replacing the LTC3676 LDO4 feedback and enable pins with VDDQIN and VTTR pins. The DDR V

DD

supply is connected to the LTC3676-1 VDDQIN pin. A buffered DDR termination voltage equal to one half the voltage on VD-

DQIN is output on VTTR. The VTTR voltage is connected internally on the LTC3676-1 to the reference side of the

Buck1 error amplifier. When Buck1 is configured with a gain of one, its output can be used as at DDR termination supply. Table 1 shows the functional differences between the LTC3676 and LTC3676-1.

Table 1. Functional Differences LTC3676 vs LTC3676-1

LTC3676

2.25MHz

LTC3676-1

1.125MHz

Buck1 Default

Frequency

Buck1 Default

Mode

Buck1 Output

Pulse-Skipping Forced Continuous

LDO4 Enable

LDO4 Output

FB_L4 Pin

EN_L4 Pin

VDDQIN Pin

VTTR Pin

I

2

C Device

Address

External Resistor Divider.

Slewing DAC Reference

EN_L4 Pin or I

2

C

External Resistor Divider.

725mV Reference

External Unity Gain.

VTTR Reference

I

2

C

I

2

C Select 1 of 4 Fixed

Outputs

External Resistor Divider —

Enable LDO4.

—

— Connect to DDR Memory

Supply

—

Write = 0x78

Read = 0x79

Buffered Output Equals

One-Half VDDQIN

Write = 0x7A

Read = 0x7B

VTTR

VDDQIN

PVINB1

BUCK1

SW1 VDDQIN/2

VDDQIN/2

DDR

REF

ERROR

AMP

C

FB

FB_B1

R1 C

OUT

3676 F01

Figure 1. V

TT

Buck Regulator and VTTR Reference Block Diagram

Always-On 25mA Low Dropout Regulator

The LTC3676 includes a low quiescent current low dropout regulator that remains powered whenever a valid supply is present on V

V

IN

IN

. The always-on LDO1 remains active until

drops below 2.0V (typical). This is below the 2.5V undervoltage threshold in effect for the rest of the LTC3676 circuits. The always-on LDO is used to provide power to a standby microcontroller, real-time clock, or other keep-alive circuits. The LDO is guaranteed to support a 25mA load. A

1µF low impedance ceramic bypass capacitor from LDO1 to

GND is required for compensation. A power good monitor pulls RSTO low whenever LDO1 is 8% below its regulation target. LDO1 has current limit circuitry to protect from short circuit and overloading. The output voltage of LDO1 is set with a resistor divider connected from LDO1 output pin to the feedback pin FB_L1, as shown in Figure 2. The output voltage is calculated using the following formula:

V

LDO1

R1

R2

⎞

⎠⎟

300mA Low Dropout Regulators

Three LDO regulators on the LTC3676 will each deliver up to 300mA output. Each LDO regulator has separate input supply to help manage power loss in the LDO output devices. The LDO regulators are enabled by pin input or I

2

C command register. When disabled, the regulator outputs are pulled to ground through a 625Ω resistor. A low ESR

1µF ceramic capacitor should be tied from the LDO output to ground. The 300mA LDO regulators have current limit control circuits. The LDO input voltages, V and V

IN_L4

must be at potential of V

IN

IN_L2

or less.

, V

IN_L3

,

The LDO regulator I

2

C command register controls are shown in Table 2 and Table 3.


3676fd

15

LTC3676/LTC3676-1

operaTion

LTC3676 Resistor Programmable LDO2 and LDO4

LDO2 and LDO4 output voltages are programmed by resistor dividers tied from the LDO output pin to the feedback pin as shown in Figure 2. The output voltage is calculated using the following formula:

V

LDO

0.725V

+

–

R1

R2

⎞

⎠⎟

V

IN

LDO

FB

R1

R2

3676 F02

1µF

Figure 2. LDO1, LDO2 and LDO4 Application Circuit

Fixed Output LDO3

Regulator LDO3 has a fixed voltage output of 1.8V.

Table 2. LDO2 and LDO3 Control Command Register Settings

COMMAND

REGISTER[BIT] VALUE SETTING

LDOA[0]

LDOA[1]

LDOA[2]

LDOA[3]

0*

1

0*

1

0*

1

0*

1

Do Not Keep Alive LDO2 in Standby

Keep Alive LDO2 in Standby

Enable LDO2 at Any Output Voltage

Enable LDO2 Only if Output Voltage is <300mV

LDO2 Disabled if EN_L2 is Low

LDO2 Enable



LDOA[4]

LDOA[5]

0*

1

0*

1


Enable LDO3 0nly if Output Voltage is <300mV


LDO3 Enabled

*denotes default power-on value.

LDO4 Operation LTC3676-1

LDO4 on the LTC3676-1 has neither enable nor feedback pins. There are four LDO4 output voltages selectable by command register bits LDOB[4:3]. The power-on default output is 1.2V with selectable outputs of 2.5V, 2.8V, and

3.0V. LDO4 is enabled only through the command register bit LDOB[2].

LDO4 Command Register Controls

Table 3. LDO4 Control Command Register Settings

COMMAND


LDOB[0]

LDOB[1]

LDOB[2]

(LTC3676)

LDOB[2]

(LTC3676-1)

LDOB[4:3]

(LTC3676-1)

0*

1

0*

1

0*

1

0*

1




Enable LDO4 Only if Output Voltage is <300mV


LDO4 Enabled

LDO4 Disabled

LDO4 Enabled

00* LDO4 Output = 1.2V

LDOB[4:3]

(LTC3676-1)

LDOB[4:3]

(LTC3676-1)

01

10

LDO4 Output = 2.5V

LDO4 Output = 2.8V

LDOB[4:3]

(LTC3676-1)

11 LDO4 Output = 3V


STEP-DOWN SWITCHING REGULATORS

The LTC3676 contains four buck regulators. Two of the buck regulators are capable of delivering up to 2.5A load current and the other two can deliver up to 1.5A each. The regulators have forward and reverse current limiting, softstart, and switch slew rate control for lower radiated EMI.

The LTC3676 buck regulators are capable of 100% duty cycle, or dropout, regulation. When in dropout the regulator output voltage is equal to PV

R

DS(ON)

IN

minus the load current times

of the converters PMOS device and inductor DCR.

Each buck regulator is enabled using its enable pin or I

2

C command register control. Operating modes, start-up option, reference voltage, and switch slew rate are controlled using the I

2

C port.

The buck converter I

2

C command register controls are shown in Table 4, Table 5, Table 6, and Table 7.

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Operating Modes

The buck regulators can operate in either pulse-skipping,

Burst Mode operation, or forced continuous mode. In pulse-skipping setting the regulator will skip pulses at light loads but will operate at constant frequency. In Burst

Mode setting the regulator operates in Burst Mode operation at light loads and in constant frequency PWM mode at higher load. In forced continuous setting the inductor current is allowed to be less than zero over the full range of duty cycles. In forced continuous operation the buck regulator has the ability to sink output current. Because the regulator is switching every cycle regardless of output load, forced continuous mode results in the least output voltage ripple at light load.

Output Voltage Programming

Each of the step-down converters uses a dynamically slewing DAC for its reference. The output voltage of the DAC reference is selectable using a 5-bit I

2

C command register.

The output voltage is set by using a resistor divider connected from the step-down switching regulator output to its feedback pin as shown in Figure 3. The output voltage is calculated using the following formula:

V

OUT

R1

R2

⎞

⎠⎟

(

+ 412.5

) mV

DVBx is the decimal value of the 5-bit binary number in the I

2

C command registers. The default DAC input code is

11001 (25 in decimal) which corresponds to a reference voltage of 725mV. Typical values for R1 are in the range of 40k to 1M. Capacitor C

FB

cancels the pole created by the feedback resistors and the input capacitance on the

FB pin and helps to improve load step transient response.

A value of 10pF is recommended.

Inductor Selection

The choice of step-down switching regulator inductor influences the efficiency and output voltage ripple of the converter. A larger inductor improves efficiency since the peak current is closer to the average output current. Larger inductors generally have higher series resistance that counters the efficiency advantage of reduced peak current.

Inductor ripple current is a function of switching frequency, inductance, V

IN

, and V

OUT

as shown in this equation:

ΔI

L

=

1 f •L

• V

OUT

V

OUT

V

IN

⎞

⎠⎟

A good starting design point is to use an inductor that gives ripple equal to 30% output current. Select an inductor with a DC current rating at least 1.5 times larger than the maximum load current to ensure the inductor does not saturate.

Input and Output Capacitor Selection

Low ESR ceramic capacitors should be used at both the output and input supply of the switching regulators. Only

X5R or X7R ceramic capacitors should be used since they have better temperature and voltage stability than other ceramic types.

PV

IN

EN

MODE

2

5

PWM

CONTROL

DAC

DEFAULT

725mV

SW

FB

3676 F03

C

FB

R1

R2

C

OUT

Figure 3. Step-Down Switching Regulator Application Circuit

Operating Frequency

The switching frequency of each of the LTC3676 switching regulators may be set using the I

2

C command registers.

The default switching frequency is 2.25MHz and the selectable frequency is 1.125MHz. Operation at lower frequency improves efficiency by reducing internal gate charge and switching losses at the expense of a larger inductor.

The lowest duty cycle of the step-down converter is determined by minimum on-time. Minimum on-time is the shortest time duration that the converter can turn its top

PMOS on and off again. The time is the sum of gate charge


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LTC3676/LTC3676-1

operaTion

time plus internal delays of the peak current sense and

PWM control. If the converters duty cycle will be 20% or less at 2.25MHz it is recommended to use the 1.125MHz setting to avoid minimum duty cycle. If the duty cycle falls below the minimum on-time of the converter, the output voltage ripple will increase as the converter skips cycles.

The default setting for the LTC3676-1 Buck1 switching frequency is 1.125MHz to ensure minimum on time effects are avoided at DDR termination reference voltages.

Phase Selection

I

To reduce the cycle by cycle peak current drawn by the switching regulators, the clock phase at which each of the

LTC3676 buck’s PMOS switch turns on can be set using

2

C command register settings.

φ1 φ2 φ1

2.25MHz

φ1 φ2

1.125MHz

3676 F04

Figure 4. Phase Settings Full- and Half-Speed Buck Clock

Switch Slew Rate Control

To help reduce EMI the switch rise time of each buck regulator is slew limited by default. A faster setting is selectable using the I

2

C buck command registers. The faster setting will improve efficiency if limited edge rate is not required.

Soft-Start

To reduce inrush current at start-up each buck regulator soft starts when enabled. When enabled the internal reference voltage is ramped from ground to the level of the slewing DAC output at a rate of 0.8V/ms. During soft-start the converter is forced to pulse-skipping mode regardless of command register mode settings.

Table 4. Buck1 Control Command Register

COMMAND

REGISTER[BIT]

BUCK1[0]

BUCK1[1]

BUCK1[2]

(LTC3676)

BUCK1[2]

(LTC3676-1)

BUCK1[3]

BUCK1[4]

BUCK1[6:5]

BUCK1[7]

0*

1

00*

01

10

0*

1

VALUE SETTING

0*

1

Switch Slew Rate Normal

Switch Slew Rate Fast

0*

1

Do Not Keep Enabled in Device Standby

Keep Enabled in Device Standby

0*

1

0*

1

0*

1

Switching Frequency 2.25MHz




Clock Phase 1

Clock Phase 2

Enable at Any Output Voltage

Enable Only if Output Voltage Is <300mV

Pulse-Skipping Mode

Burst Mode Operation

Forced Continuous Mode

Buck1 Disabled if EN_B1 Pin Is Low

Buck1 Enabled

*denotes default power on-value.


COMMAND


BUCK2[0]

BUCK2[1]

BUCK2[2]

BUCK2[3]

0*

1

0*

1

0*

1

0*

1







Clock Phase 1

Clock Phase 2

BUCK2[4]

BUCK2[6:5]

0*

1

00*

01

10



Pulse-Skipping Mode



BUCK2[7] 0*

1



Buck2 Enabled

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LTC3676/LTC3676-1

operaTion


COMMAND

REGISTER[BIT]

BUCK3[0]

VALUE SETTING

0*

1



BUCK3[1]

BUCK3[2]

BUCK3[3]

0*

1

0*

1

0*

1





Clock Phase 1

Clock Phase 2

BUCK3[4]

BUCK3[6:5]

0*

1

00*

01

10



Pulse-Skipping Mode



BUCK3[7] 0*

1



Buck3 Enabled


COMMAND

REGISTER[BIT]

BUCK4[0]

VALUE SETTING

0*

1



BUCK4[1]

BUCK4[2]

BUCK4[3]

0*

1

0*

1

0*

1





Clock Phase 1

Clock Phase 2

BUCK4[4]

BUCK4[6:5]

0*

1

00*

01

10



Pulse-Skipping Mode



BUCK4[7] 0*

1



Buck4 Enabled

SLEWING DAC REFERENCE OPERATION

Each LTC3676 step-down switching regulators error amplifier reference voltage is supplied by a 5-bit DAC with an output voltage range of 412.5mV to 800mV in 12.5mV steps. One of two 5-bit codes stored in I

2

C command registers is selected for input to the DAC. When a change in code is detected by the DAC control circuits, the output of the DAC is slewed at 3.5mV/µs to the new value.

Dynamic Voltage Scaling

Table 8 shows the command registers used to control dynamic voltage scaling (DVS) of the step-down switching regulators input reference DAC. The command register bits DVB1A[4:0] and DVB1B[4:0] store two 5-bit inputs to the DAC reference for Buck1. The bit stored in command register DVB1A[5] selects either the 5 bits stored in DVB1A[4:0] or DVB1B[4:0] DAC as input to the DAC reference. Buck2, Buck3, and Buck4 operate the same way using their assigned “A” and “B” command registers shown in Table 8. When the DAC detects a change in its input code it automatically slews to the new value at a rate of 3.5mV/µs. A DVS can be initiated using the I bit or using the VSTB pin.

2

C select

The LTC3676 VSTB pin HIGH selects the 5 bits stored in all four DVBx “B” registers. This facilitates a simultaneous

DAC slew between the values in the “A” registers and the values in the “B” registers. The VSTB pin is logically ORed

2

C select bit is with the I

2

C command register bit. If the I already set high, the “B” registers are already selected and

VSTB will have no effect. If no change in output is desired using the VSTB pin, set the value in the “A” register equal to the value in the “B”.

Command register bits DVB1B[5], DVB2B[5], DVB3B[5], and DVB4B[5] control whether the PGOOD status pin is pulled low while the DAC output is slewing. The default command register setting is to pull PGOOD pin low during DAC slew. During the DVS, PGOOD will be held low for just the duration of the DVS and the PGSTAT register is not affected.

V

OUT

200mV/DIV

PGOOD

5V/DIV

VSTB

5V/DIV

100µs/DIV

3676 F05

Figure 5. Dynamic Voltage Scaling


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LTC3676/LTC3676-1

operaTion

Table 8. Buck1, Buck2, Buck3, and Buck4 Slewing DAC Control

Command Registers

COMMAND

REGISTER[BIT]

DVB1A[4:0]

DVB1A[5]

DVB1B[4:0]

DVB1B[5]

VALUE SETTING

bbbbb Buck1 Reference DAC Input A

0*

1

Select DVB1A[4:0]

Select DVB1B[4:0] bbbbb Buck1 Reference DAC Input B

0*

1

Pull PGOOD Low Slewing Buck1

Do Not Pull PGOOD Slewing Buck1 bbbbb Buck2 Reference DAC Input A DVB2A[4:0]

DVB2A[5]

DVB2B[4:0]

DVB2B[5]

0*

1

Select DVB2A[4:0]


0*

1


Do Not Pull PGOOD Slewing Buck2 bbbbb Buck3 Reference DAC Input A DVB3A[4:0]

DVB3A[5]

DVB3B[4:0]

DVB3B[5]

0*

1

Select DVB3A[4:0]


0*

1


Do Not Pull PGOOD Slewing Buck3

DVB4A[4:0]

DVB4A[5] bbbbb Buck4 Reference DAC Input A

0*

1

Select DVB4A[4:0]

Select DVB4B[4:0] bbbbb Buck4 Reference DAC Input B DVB4B[4:0]

DVB4B[5] 0*

1



Do Not Pull PGOOD Slewing Buck4

ON 10 SEC

OR I

2

C HRST

ENABLE

INHIBITED AND

WAKE LOW

ENABLE

ALLOWED AND

WAKE HIGH

STANDBY

ON 400ms

OR PWR_ON

1 SEC OFF

TIMER

STANDBY ON 10 SEC

OR I

2

C HRST

PWR_ON

OR FAULT

V

IN

HIGH

POR/HRST

5 SEC

PWR_ON

TIMER

ON

ON 400ms

OR PWR_ON

ON 10 SEC

OR I

2

C HRST

1 SEC OFF

TIMER

HRST

3676 F06

PUSHBUTTON OPERATION

Operating Mode State Diagram

Figure 6 shows the state diagram of the LTC3676 enable and sequence controller. First application of power to

V

IN

pin brings the controller to the power-on reset/hard reset (POR/HRST) state. In this state the I

2

C command registers have been set to their default values, only LDO1 is operating, and the device is waiting for pushbutton or

PWR_ON inputs. Regulator enable pins and command register enable bits are ignored in POR/HRST state. In the

POR/HRST state V

IN

draws typically 12µA.

Figure 6. LTC3676 Operating Mode State Diagram

Power Up Using Pushbutton

When the ON pin is held low for 400ms the WAKE pin is pulled high, enable pins are recognized, and the five second

PWR_ON timer is started. If in the ON state and PWR_ON is low or a fault is detected, then WAKE is brought low and after a 1 second power-down time, the STANDBY state is entered. In STANDBY, the enable bits in the command registers are cleared and enable pins are ignored. Table 9 shows the control of command registers, enables, and

WAKE at each state.

The 5 second power-on state is intended for the system to detect that power rails are correct and either drive PWR_ON pin high or set command register bit CNTRL[7] high to keep the rails active. If there were a system level problem

3676fd

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LTC3676/LTC3676-1

operaTion

ON (PB)

400ms

WAKE

PWR_ON

(PIN OR I

2

C)

<5 SEC

µC/µP CONTROL

3676 F07

Figure 7. Power Up Using Pushbutton

keeping the processor from driving PWR_ON, then the

LTC3676 will pull WAKE low, shut off all regulators, and enter the STANDBY state. The STANDBY state is also a low power, 12µA (typical) state.

Table 9. Register, Enable, WAKE Control During Operating

Mode State Control

STATE REGISTERS ENABLES WAKE

POR/HRST DEFAULT

5 SEC PWR_ON TIMER

R/W

R/W

ON R/W

1 SEC OFF TIMER HRST Set to POR

Defaults

1 SEC OFF TIMER

STANDBY

I

2

C Enable and SW

Mode Bits

Cleared

STANDBY R/W

Inhibited

Allowed

LOW

HIGH

Allowed HIGH

Sequence Down LOW

Sequence Down LOW

Inhibited LOW

Power Down Using Pushbutton

When in the ON state, the system controller is responsible for deciding what action to take when a pushbutton event occurs. By monitoring the IRQ status pin and IRQSTAT[0]

<10 SEC

ON (PB)

50ms

IRQ

IRQSTAT[0]

WAKE

3ms

PWR_ON

(PIN OR I

2

C)

µC/µP CONTROL

Figure 8. Power-Down Using Pushbutton

3676 F08 status register bit, the controller can detect a pushbutton request. If a power-down into standby state is desired then the controller should drive PWR_ON low and set command register bit CNTRL[7] low.

Button Status Indication

When a pushbutton pulls ON low for 50ms in the ON state,

IRQ is pulled low and the PB status bit in the IRQSTAT[0] status register is set. IRQ and the IRQSTAT status bit are active while ON is low or for a minimum of 50ms.

Power Up and Down with PWR_ON

The PWR_ON pin is an alternative way to power up the

LTC3676 instead of using the ON pin. When PWR_ON is driven high or command register CNTRL[7] is set high,

WAKE is pulled HIGH and the LTC3676 passes through the 5 second PWR_ON timer to the ON state. Figure 9 shows PWR_ON and WAKE timing. WAKE stays high for a minimum of 5 seconds.

5 SEC

PWR_ON

(PIN OR I

2

C)

3ms

µC/µP CONTROL

3ms

WAKE

3676 F09

Figure 9. Power Up and Down with PWR_ON

POWER ON SEQUENCING

Enable Pin Operation

The LTC3676 enable pins facilitate pin-strapping output rails to enable pins to up-sequence the LTC3676 regulators in any order. Figure 10 shows an example of pin-strapped sequence connections. The enable pins normally have a

0.8V (typical) input voltage threshold.

If any enable is driven high, the remaining enable input thresholds switches to an accurate 400mV threshold. To ensure separation of the sequenced rails, there is a builtin 450µs delay from the enable pin threshold crossing to the internal enable of the regulator. Figure 11 shows the start-up timing of the example shown in Figure 10.


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LTC3676/LTC3676-1

operaTion

bits, or the operating state of the LTC3676. A hard reset or fault shutdown resets the keep alive bits.

V

B3

V

B4

V

L2

V

L3

PWR_ON

EN_B1

EN_B2

EN_B3

EN_B4

EN_L2

EN_L3

EN_L4

ON

PWR_ON

LTC3676

WAKE

SW1

SW2

SW3

SW4

LDO2

LDO3

LDO4

3676 F10

Figure 10. Pin-Strapped Power-On Sequence Application

WAKE

V

B1

0.4V

V

B2

0.4V

450µs

450µs

450µs

V

IN

V

V

V

B1

B2

B3

= 1.2V

= 1.8V

V

B4

= 2.5V

= 1.2V

V

L2

V

L3

V

L4

= 1.2V

= 1.8V

= 2.8V

1.2V

1.8V

2.5V

1.2V

1.2V

1.8V

2.8V

V

L4

3676 F11

Figure 11. Pin-Strapped Power-On Sequence

Software Control Mode

Once a power-up sequence is completed, each regulator may be enabled and disabled individually by the system as needed for power management requirements by using the command register bit CNTRL[5]. When CNTRL[5] is set high the regulators ignore the state of their enable pins and respond only to I

2

C command register bit settings.

The software control mode bit is reset in the one second standby and hard reset timer states so a pin strapped sequence begins at the next LTC3676 power on.

Keep Alive Operation

Each regulator has a dedicated command register keep alive bit that, when set, forces a regulator to be enabled regardless of the enable pins, command register enable

POWER OFF SEQUENCING

Sequence down command registers SQD1 and SQD2 are used to set the time, relative to WAKE falling, that a regulator is disabled either by lowering PWR_ON, or a fault induced shutdown. Table 10 shows register settings for SQD1 and SQD2.

Table 10.Sequence Down Control Command Register Settings

COMMAND


SQD1[1:0]

SQD1[3:2]

SQD1[5:4]

SQD1[7:6]

SQD2[1:0]

00*

01

10

11

00*

01

10

11

00*

01

10

11

00*

01

10

11

00*

01

10

11

Disable Buck1 at Falling WAKE

Disable Buck1 at Falling WAKE + 100ms















Disable LDO2 at Falling WAKE

Disable LDO2 at Falling WAKE + 100ms



SQD2[3:2]

SQD2[5:4]

00*

01

10

11

00*

01

10

11










Figure 12 shows an example of a shutdown sequence. In this example, the bits in command registers SQD1 and

SQD2 are set so that LDO2, LDO3, and LDO4 shut off at the same time as WAKE. Buck2 and Buck4 shut off 100ms after WAKE. Buck3 shuts off 200ms after wake and Buck1 shuts off 300ms after WAKE.

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LTC3676/LTC3676-1

operaTion

WAKE

V

B1

1.2V

V

B2

1.8V

V

B3

2.5V

V

B4

1.2V

V

L2

1.2V

V

L3

1.8V

V

L4

2.8V

100ms

200ms

300ms

3676 F12

Figure 12. Power-Down Sequence

FAULT DETECTION AND REPORTING

The LTC3676 has fault detection circuits that monitor for V

IN

undervoltage, die overtemperature, and regulator output undervoltage. Status of the fault detect circuits is indicated by the IRQ and PGOOD pins and the IRQSTAT and PGSTAT status registers.

V

IN

Undervoltage

The undervoltage (UV) circuit monitors the input supply voltage, V

IN

, and when the voltage falls below 2.45V creates a FAULT condition that forces the LTC3676 into the standby state. The LTC3676 also provides a (UV) warning that is triggered at user programmable V shown in Table 11.

IN

voltages as

Table 11. Undervoltage Warning Threshold Command Register

Settings

COMMAND

REGISTER[BIT] VALUE

CNTRL[4:2] 000*

001

010

011

100

101

110

111

FALLING V

IN

THRESHOLD

2.7V

2.8V

2.9V

3.0V

3.1V

3.2V

3.3V

3.4V


Over Temperature

To prevent thermal damage the LTC3676 incorporates an overtemperature (OT) circuit. When the die temperature reaches 155°C the OT circuits create a FAULT condition that forces the LTC3676 into standby. When the OT circuit detects the temperature falls below 140°C the FAULT condition is cleared. The LTC3676 also has an OT warning circuit that indicates the die temperature is approaching the OT fault threshold. The OT warning threshold is user programmable as shown in Table 12.

Table 12. Overtemperature Warning Threshold Command

Register Settings

COMMAND

REGISTER[BIT] VALUE OT WARNING THRESHOLD

CNTRL[1:0] 00*

01

10

11


10°C Below OT Fault




PGOOD Status Pin

The PGOOD open-drain status pin is pulled low when all regulators are disabled. PGOOD is released when all enabled regulator outputs are above 93% of programmed value.

When any enabled regulator output falls below 92% of its programmed value for longer than 50µs the PGOOD pin is pulled low. The 50µs transient filter on PGOOD prevents

PGOOD glitches due to transients. If the error condition persists for longer than 20ms, the IRQ pin is pulled low and status register IRQSTAT bit 2 is set to indicate a persistent

PGOOD fault. The PGOOD pin is held low for the duration of the low output condition plus 1ms. Figure 13 shows the timing of PGOOD during enable and fault events.

ENx

V

OUTx

450µs

1ms

50µs

1ms

50µs

20ms

PGOOD

IRQ

3676 F13

Figure 13. Output Low Voltage PGOOD and IRQ Timing


3676fd

23

LTC3676/LTC3676-1

operaTion

PGSTAT and MSKPG Registers

The power good status of each regulator is accessible through the LTC3676 I

2

C interface by reading the contents of the PGSTAT status register. Table 13 shows the PGSTAT register contents. The data in the PGSTATL register is held for the length of the low voltage condition plus 1ms. The data in the PGSTATRT register is held only for the duration of the low voltage condition.

Table 13. Power Good Status Register

STATUS

REGISTER[BIT] VALUE REGULATOR OUTPUT LOW STATUS

PGSTAT[0]

PGSTAT[1]

PGSTAT[2]

PGSTAT[3]

PGSTAT[4]

PGSTAT[5]

PGSTAT[6]

PGSTAT[7]

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Buck1 Output Low

Buck1 Output OK

Buck2 Output Low

Buck2 Output OK

Buck3 Output Low

Buck3 Output OK

Buck4 Output Low

Buck4 Output OK

LDO1 Output Low

LDO1 Output OK

LDO2 Output Low

LDO2 Output OK

LDO3 Output Low

LDO3 Output OK

LDO4 Output Low

LDO4 Output OK

Each regulator has a corresponding bit in the MSKPG status register as shown in Table 14. When set, a bit blocks the

PGOOD pin from being pulled low in the event of a low output voltage fault from its matching regulator. Setting a bit in the MSKPG command register does not mask the status in the PGSTAT status register.

Table 14. Power Good Status Masking Command Register

COMMAND

REGISTER[BIT]

MSKPG [0]

MSKPG [1]

MSKPG [2]

MSKPG [3]

MSKPG [5]

0

1*

0

1*

0

1*

VALUE

0

1*

0

1*

MSKPG [6]

MSKPG [7]

0

1*

0

1*


Mask Buck1 PGOOD Status

Pass Buck1 PGOOD Status







Mask LDO2 PGOOD Status

Pass LDO2 PGOOD Status





IRQ Status Pin

The IRQ pin is pulled and latched low when undervoltage, overtemperature or persistent PGOOD events occur. The

IRQ pin is cleared by addressing the CLIRQ command register or by holding ON low for 50ms.

Table 15. Interrupt Request Status Register

STATUS

REGISTER[BIT]

IRQSTAT [0]

IRQSTAT [1]

IRQSTAT [2]

IRQSTAT [3]

IRQSTAT [4]

IRQSTAT [5]

IRQSTAT [6]

0

1

0

1

0

1

VALUE IRQSTAT REGISTER BIT MEANING

0

1 Pushbutton Status Active (Real Time)

0

1 Hard Reset Occurred

0

1

0

1

PGOOD Timeout Occurred

Undervoltage Warning

Undervoltage Standby Occurred

Overtemperature Warning

Overtemperature Standby Occurred

3676fd

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LTC3676/LTC3676-1

operaTion

IRQSTAT and MSKIRQ Registers

The bits in the MSKIRQ command register are set to mask warning, fault, and pushbutton status reporting to the IRQ pin. When set to mask, the IRQ pin is not pulled low as a result of a fault or warning. Even though the IRQ pin is not pulled low the masked bit is set in the IRQSTAT register.

When undervoltage, overtemperature faults, and hard reset signals are masked, the IRQ pin is not pulled low but LTC3676 state controller is pushed into the STANDBY or POR/HRST state. Accessing the CLIRQ status register clears the latched bits in the IRQSTAT status register and releases the IRQ pin.

Table 16. Interrupt Request Mask Command Register

COMMAND

REGISTER[BIT]

MSKIRQ [0]

MSKIRQ [2]

MSKIRQ [3]

MSKIRQ [4]

MSKIRQ [5]

VALUE

0*

1

0*

1

0*

1

0*

1

0*

1

MSKIRQ [6] 0*

1


Pass Pushbutton Status

Mask Pushbutton Status

Pass PGOOD Timeout

Mask PGOOD Timeout

Pass Undervoltage Warning

Mask Undervoltage Warning

Pass Undervoltage Shutdown

Mask Undervoltage Shutdown

Pass Overtemperature Warning

Mask Overtemperature Warning

Pass Overtemperature Shutdown

Mask Overtemperature Shutdown

IRQ and IRQSTAT are not cleared by hard reset or fault shutdown. If V

IN

remains applied while the LTC3676 is in

STANDBY or POR/HRST then IRQSTAT may be read on the subsequent power up to determine if a fault or hard reset occurred.

RSTO Status Pin

The LTC3676 RSTO status pin is pulled low when alwayson LDO1 is 8% below its programmed value or when the

LTC3676 is in the one second HRST timer state.

Hard Reset

A hard reset can be initiated by holding the ON pin low or writing to the HRST command register. Bit six of the

CNTRL command register determines how long ON must remain low to initiate the hard reset. A hard reset sets all I

2

C command register bits to their default power-on state. Table 17 shows the command register control of hard reset function.

Table 17. Hard Reset Time Control Command Register

COMMAND


CNTRL[6] 0*

1


10 seconds

5 seconds

A hard reset command will push the LTC3676 state controller through the 1 second HRST timer state and into the POR/HRST state.

Fault Shutdown

An undervoltage or overtemperature fault will push the

LTC3676 state controller through the 1 second standby timer state and into standby state. If a down sequence is selected in the command registers, it will be executed during the 1 second power down interval.

LTC3676-1 Operation

The LTC3676-1 option supports DDR memory operation by generating a DDR termination reference and supply rail equal to one-half the voltage applied to VDDQIN Pin 8.

An internal resistive divider creates a reference voltage of one-half the voltage on VDDQIN. This reference is used by the V

TT

reference buffer to output one-half of VDDQIN on VTTR Pin 9. The VTTR voltage is used as the reference for 1.5A switching regulator 1 which is used as the DDR termination supply. The LTC3676-1 EN_B1 pin and command register bit Buck1[7] enable both VTTR output and switching regulator 1.

Figure 1 shows typical application connections for the

LTC3676-1 DDR termination reference and termination supply.

LDO4 has I

2

C command register selectable output voltages of 1.2V (default), 2.5V, 2.8V and 3V and is enabled only using the I

2

C command register. Table 18 shows the LDO4 command register controls for the LTC3676-1.


3676fd

25

LTC3676/LTC3676-1

operaTion

Table 18. LDO4 Control Command Register Setting (LTC3676-1)

COMMAND


LDOB[0] 0*

1



LDOB[1] 0*

1


Enable LDO4 Only if Output Voltage Is <300mV

LDOB[2]

LDOB[4:3]

0*

1

00*

01

10

11

LDO4 Disabled

LDO4 Enable

1.2V

2.5V

2.8V

3.0V


I

2

C OPERATION

The LTC3676 communicates with a bus master using the standard I

2

C 2-wire interface. The timing diagram in

Figure 14 shows the relationship of the signals on the bus. The two bus lines, SDA and SCL must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on SDA and SCL. The LTC3676 is both a slave receiver and slave transmitter. The I

2

C control signals,

SDA and SCL are scaled internally to the DV

DV

DD the bus pull-up resistors.

DD

supply.

must be connected to the same power supply as

The I

2

C port has an undervoltage lockout on the DV pin. When DV

DD

is below approximately 1V, the I C serial port is cleared and the command registers are set to default POR values.

The complete I

2

Table 20.

C command register table is shown in

I

2

C Bus Speed

The I

2

C port operates at speeds up to 400kHz. It has built in timing delays to ensure correct operation when addressed from an I

2

C compliant master device. It also contains input filters designed to suppress glitches should the bus become corrupted.

I

2

C START and STOP Conditions

A bus master signals the beginning of communications by transmitting a START condition. A START condition is generated by transitioning SDA from HIGH to LOW while

SCL is HIGH. The master may transmit either the slave write or the slave read address. Once data is written to the

LTC3676, the master may transmit a STOP condition which commands the LTC3676 to act upon its new command set. A STOP condition is sent by the master by transitioning SDA from LOW to HIGH while SCL is HIGH. The bus is then free for communication with another I

2

C device.

I

2

C Byte Format

Each byte sent to or received from the LTC3676 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. The data should be sent to the LTC3676 most significant bit (MSB) first.

I

2

C Acknowledge

The acknowledge signal is used for handshaking between the master and the slave. When the LTC3676 is written to, it acknowledges its write address and subsequent data bytes. When it is read from, the LTC3676 acknowledges its read address only. The bus master should acknowledge data returned from the LTC3676.

An acknowledge generated by the LTC3676 lets the master know that the latest byte of information was received.

The master generates the acknowledge related clock and releases the SDA line during the acknowledge clock cycle.

The LTC3676 pulls down the SDA line during the write acknowledge clock pulse so that it is a stable LOW during the HIGH period of this clock pulse.

At the end of a byte of data transferred from the LTC3676 during a READ operation, the LTC3676 releases the SDA line to allow the master to acknowledge receipt of the data. Failure of the master to acknowledge data from the

LTC3676 has no effect on the operation of the I

2

C port.

3676fd

26


LTC3676/LTC3676-1

operaTion

SDA t

SU, DAT

SCL t

HD, STA

START

CONDITION t

LOW t r t

HIGH t f t

HD, DAT t

SU, STA t

HD, STA t

BUF t

SU, STO

3676 F14 t

SP

REPEATED START

CONDITION

Figure 14. LTC3676 I

2

C Serial Port Timing

STOP

CONDITION

START

CONDITION

I

2

C Slave Address

The LTC3676 responds to factory programmed read and write addresses. The least significant bit of the address byte is 0 when writing data and 1 when reading data. Table 19 shows read and write addresses for the LTC3676 options.

Table 19. LTC3676 and LTC3676-1 I

2

Addresses

C Read and Write

LTC PART NUMBER R/W ADDRESS

LTC3676

LTC3676

LTC3676-1

LTC3676-1

W

R

W

R

0111 1000, 0x78

0111 1001, 0x79

0111 1010, 0x7A

0111 1011, 0x7B

I

2

C Write Operation

The LTC3676 has twenty-two command registers for control input. They are accessed by the I sub-addressed writing system.

2

C port via a

A single write cycle of the LTC3676 consists of exactly three bytes except when a clear interrupt or hard reset command is written. The first byte is always the LTC3676 write address. The second byte represents the LTC3676 sub-address. The sub-address is a pointer which directs the subsequent data byte within the LTC3676. The third byte consists of the data to be written to the location pointed to by the sub-address.

As shown in Figure 15, the LTC3676 supports multiple sub-addressed write operations. Data pairs sent following the chip write address are interpreted as sub-address and data. Any number of sub-address and data pairs may be sent. The data in the command registers is not acted on by the LTC3676 until a STOP signal is issued.

The LTC3676 will keep interim writes to the registers when a repeat START condition occurs. A repeat start may be used to set up other devices on the I

2

C bus prior to sending a STOP condition. The LTC3676 will act on the data written prior to the repeat start when a STOP condition is detected.

I

2

C Read Operation

Figure 16 shows the LTC3676 command register read sequence. The bus master reads a byte of data from a

LTC3676 command or status register by first writing the

LTC3676 write address followed by the sub-address to be read from. The LTC3676 acknowledges each of the two bytes. Next, the bus master initiates a new START condition and sends the LTC3676 read address. Following the acknowledge of the read address by the LTC3676, the LTC3676 pushes data onto the I its ninth clock.

2

C bus for the 8 clock cycles. The bus master then acknowledges the data on

The last read sub-address that is written to the LTC3676 is stored. This allows repeated polling of a command or status register without the need to re-write its sub-address.

Additionally, the last register written may be immediately read by issuing a START condition followed by read address and clocking out the data.


3676fd

27

LTC3676/LTC3676-1

operaTion

28


3676fd

LTC3676/LTC3676-1

operaTion

Table 20. LTC3676 Command Registers

REG NAME B[7]

0x01 BUCK1 Enable:

0 = Disabled if

EN_B1 Low

1 = Enabled

0x02 BUCK2 Enable:

0 = Disabled if

EN_B2 Low

1 = Enabled

0x03 BUCK3 Enable:

0 = Disabled if

EN_B3 Low

1 = Enabled

B[6] B[5]

Mode:

00 = Pulse-Skipping

01 = Burst

10 = Forced Continuous

Mode:

00 = Pulse-Skipping

01 = Burst


Mode:

00 = Pulse-Skipping

01 = Burst


B[4]

Start-Up:

0 = Enable at

Any Output

Voltage

1 = Enable

Only if Output

<300mV

Start-Up:

0 = Enable at

Any Output

Voltage

1 = Enable

Only if Output

<300mV

Start-Up:

0 = Enable at

Any Output

Voltage

1 = Enable

Only if Output

<300mV

B[3]

Phase Select:

0 = Clock

Phase 1

1 = Clock

Phase 2

Phase Select:

0 = Clock

Phase 1

1 = Clock

Phase 2

Phase Select:

0 = Clock

Phase 1

1 = Clock

Phase 2

B[2]

Clock Rate:

0 = 2.25MHz

1 = 1.125MHz

Clock Rate:

0 = 2.25MHz

1 = 1.125MHz

Clock Rate:

0 = 2.25MHz

1 = 1.125MHz

0x04 BUCK4 Enable:

0 = Disabled if

EN_B4 Low

1 = Enabled

0x05 LDOA

0x06 LDOB

Reserved

Reserved

Mode:

00 = Pulse-Skipping

01 = Burst


Reserved

Reserved Reserved

Start-Up:

0 = Enable at

Any Output

Voltage

1 = Enable

Only if Output

<300mV

Enable LDO3:

0 = Disabled if

EN_L3 Low

1 = Enabled

Start-Up LDO3:

0 = Enable at

Any Output

Voltage

1 = Enable

Only if Output

<300mV

Phase Select:

0 = Clock

Phase 1

1 = Clock

Phase 2

Keep Alive

LDO3:

0 = Do Not

Keep Alive

1 = Keep Alive in Shutdown.

LTC3676-1 LDO4 Output

Voltage:

00 = 1.2V

01 = 2.5V

10 = 2.8V

11 = 3.0V

Clock Rate:

0 = 2.25MHz

1 = 1.125MHz

Enable LDO2:

0 = Disabled if

EN_L2 Low

1 = Enabled

Enable LDO4:

0 = Disabled if

EN_L4 Low

1 = Enabled

0x07 SQD1 Sequence Down Buck4:

00 = With WAKE

01 = WAKE + 100ms

10 = WAKE + 200ms

11 = WAKE + 300ms

Sequence Down Buck3:

00 = With WAKE

01 = WAKE + 100ms

10 = WAKE + 200ms

11 = WAKE + 300ms


00 = With WAKE

01 = WAKE + 100ms

10 = WAKE + 200ms

11 = WAKE + 300ms

B[1] B[0]

Keep Alive

Buck1:

0 = Do Not

Keep Alive

1= Keep Alive in

Shutdown.

Switch DV/DT

Control:

0 = Slow

1 = Fast

Keep Alive

Buck2:

0 = Do Not

Keep Alive

1 = Keep Alive in Shutdown

Keep Alive

Buck3:

0 = Do Not

Keep Alive


Keep Alive

Buck4:

0 = Do Not

Keep Alive


Start-Up LDO2:

0 = Enable at

Any Output

Voltage

1 = Enable

Only if Output

<300mV

Start-Up LDO4:

0 = Enable at

Any Output

Voltage

1 = Enable

Only if Output

<300mV

Switch DV/DT

Control:

0 = Slow

1 = Fast

Switch DV/DT

Control:

0 = Slow

1 = Fast

Switch DV/DT

Control:

0 = Slow

1 = Fast

Keep Alive

LDO2:

0 = Do Not

Keep Alive


Keep Alive

LDO4:

0 = Do Not

Keep Alive



00 = With WAKE

01 = WAKE + 100ms

10 = WAKE + 200ms

11 = WAKE + 300ms

DEFAULT

0000 0000

0000 0000

0000 0000

0000 0000

XX00 0000

XX00 0000

0000 0000


3676fd

29

LTC3676/LTC3676-1

operaTion

REG NAME

0x08 SQD2

B[7]

Reserved

B[6]

Reserved

0x09 CNTRL PWR_ON:

0 = Not

PWR_ON

1 = PWR_ON

"ORed" with

PWR_ON PIN

Pushbutton

Hard Reset

Timer:

0 = 10 sec

1 = 5 sec

B[5] B[4]

Sequence Down LD04:

00 = With WAKE

01 = WAKE + 100ms

10 = WAKE + 200ms

11 = WAKE + 300ms

B[3] B[2]

Sequence Down LD03:

00 = With WAKE

01 = WAKE + 100ms

10 = WAKE + 200ms

11 = WAKE + 300ms

Software

Control Mode:

0 = Pin or

Register

Control

1 = Inhibit Pin

Control

UV Warning Threshold:

000 = 2.7V

001 = 2.8V

010 = 2.9V

011 = 3.0V

100 = 3.1V

101 = 3.2V

110 = 3.3V

111 = 3.4V

0x0A DVB1A Reserved

0x0B DVB1B Reserved

0x0C DVB2A Reserved

0x0D DVB2B Reserved

0x0E DVB3A Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Buck1

Reference

Select:

0 =

DVB1A[4-0]

1 =

DVB1B[4-0]

Buck1 Feedback Reference Input (VA):

00000 = 412.5mV

11001 = 725mV

11111 = 800mV

12.5mV Step Size

PGOOD Mask:

0 = PGOOD

Low When

Slewing

1 = PGOOD

Not Forced

Low When

Slewing

Buck1 Feedback Reference Input (VB):

00000 = 412.5mV

11001 = 725mV

11111 = 800mV

12.5mV Step Size

Buck2

Reference

Select:

0 =

DVB2A[4-0]

1 =

DVB2B[4-0]


00000 = 412.5mV

11001 = 725mV

11111 = 800mV

12.5mV Step Size

PGOOD Mask:

0 = PGOOD

Low When

Slewing


00000 = 412.5mV

11001 = 725mV

11111 = 800mV

12.5mV Step Size

1 = PGOOD

Not Forced

Low When

Slewing

Buck3

Reference

Select:

0 =

DVB3A[4-0]

1 =

DVB3B[4-0]


00000 = 412.5mV

11001 = 725mV

11111 = 800mV

12.5mV Step Size

B[1] B[0]

Sequence Down LD02:

00 = With WAKE

01 = WAKE + 100ms

10 = WAKE + 200ms

11 = WAKE + 300ms

Over temperature Warning

Levels:

00 = 10°C Below

Overtemperature

01 = 20°C Below

Overtemperature

10 = 30°C Below

Overtemperature

11 = 40°C Below

Overtemperature

DEFAULT

XX00 0000

0000 0000

XX01 1001

XX01 1001

XX01 1001

XX01 1001

XX01 1001

3676fd

30


LTC3676/LTC3676-1

operaTion

REG NAME B[7]

0x0F DVB3B Reserved

0x10 DVB4A Reserved

0x11 DVB4B Reserved

0x12 MSKIRQ Reserved

0x13 MSKPG Allow LDO 4

PGOOD Fault

0x14 USER User Bit 7

0x1E HRST

0x1F CLIRQ

B[6]

Reserved

Reserved

Reserved

Mask Overtemperature

Shutdown

Allow LDO 3

PGOOD Fault

User Bit 6

B[5] B[4] B[3] B[2]

PGOOD Mask:

0 = PGOOD

Low When

Slewing


00000 = 412.5mV

11001 = 725mV

11111 = 800mV

12.5mV Step Size

1 = PGOOD

Not Forced

Low When

Slewing

Buck4

Reference.

Select:

0 =

DVB4A[4-0]

1 =

DVB4B[4-0]


00000 = 412.5mV

11001 = 725mV

11111 = 800mV

12.5mV Step Size

PGOOD Mask:

0 = PGOOD

Low When

Slewing

1 = PGOOD

Not Forced

Low When

Slewing


00000 = 412.5mV

11001 = 725mV

11111 = 800mV

12.5mV Step Size

Mask Overtemperature

Warning

Mask

Undervoltage

Shutdown

Mask

Undervoltage

Warning

Mask PGOOD

Timeout

Allow LDO 2

PGOOD Fault

User Bit 5

Reserved

User Bit 4

Allow Buck 4

PGOOD Fault

User Bit 3

Hard Reset Command. No Data.

Clear IRQ Command. No Data

Allow Buck 3

PGOOD Fault

User Bit 2

B[1]

Reserved

Allow Buck 2

PGOOD Fault

User Bit 1

B[0]

Mask Push

Button Status

X000 00X0

Allow Buck 1

PGOOD Fault

User Bit 0

DEFAULT

XX01 1001

XX01 1001

XX01 1001

1111 1111

0000 0000

Table 22. LTC3676 Status Registers

REG NAME B[7]

0x15 IRQSTAT Reserved

0x16 PGSTATL LDO4 PGOOD

Hold 1ms

B[6]

Overtemperature

Shutdown

LDO3 PGOOD

Hold 1ms

B[5]

Overtemperature

Warning

LDO2 PGOOD

Hold 1ms

B[4]

Undervoltage

Shutdown

LDO1 PGOOD

Hold 1ms

B[3]

Undervoltage

Warning

Buck4 PGOOD

Hold 1ms

B[2]

PGOOD

Timeout

Buck3 PGOOD

Hold 1ms

B[1]

Hard Reset

Buck2 PGOOD

Hold 1ms

B[0]

Pushbutton

Status (Real

Time)

Buck1 PGOOD

Hold 1ms

0x17 PGSTATRT LDO4 PGOOD LDO3 PGOOD LDO2 PGOOD LDO1 PGOOD Buck4 PGOOD Buck3 PGOOD Buck2 PGOOD Buck1 PGOOD


3676fd

31

LTC3676/LTC3676-1

applicaTions inForMaTion

THERMAL CONSIDERATIONS AND BOARD LAYOUT

Printed Circuit Board Power Dissipation

In order to ensure optimal performance and the ability to deliver maximum output power to any regulator, it is critical that the exposed ground pad on the backside of the

LTC3676 package be soldered to a ground plane on the board. The exposed pad is the only GND connection for the

LTC3676. Correctly soldered to a 2500mm

2

ground plane on a double-sided 1oz copper board, the LTC3676 has a thermal resistance(



JA

) of approximately 34°C/W. Failure to make good thermal contact between the exposed pad on the backside of the package and an adequately sized ground plane will result in thermal resistances far greater than 34°C/W. To ensure the junction temperature of the

LTC3676 die does not exceed the maximum rated limit and to prevent overtemperature faults, the power output of the LTC3676 must be managed by the application. The total power dissipation in the LTC3676 is approximated by summing the power dissipation in each of the switching regulators and the LDO regulators. The power dissipation in a switching regulator is estimated by:

P

( )

= V

OUTx

•I

OUTx

•

100-Eff%

100

Where V

OUTx

is the programmed output voltage I

OUTx

is the load current and Eff is the % efficiency that can be measured or looked up from the efficiency curves for the programmed output voltage.

The power dissipated by an LDO regulator is estimated by:

P

D(LDOx)

= V

IN(LDOx)

− V

LDOx

• I

LDOx

(W) where V

LDOx

is the programmed output voltage, V

IN(LDOx) is the LDO supply voltage, and I

LDOx

is the output load current. If one of the switching regulator outputs is used as an LDO supply voltage, remember to include the LDO supply current in the switching regulator load current for calculating power loss.

An example using the equations above with the parameters in Table 23 shows an application that is at a junction temperature of 120°C at an ambient temperature of 55°C.

LDO2, LDO3, and LDO4 are powered by step-down Buck2 and Buck4. The total load on Buck2 and Buck4 is the sum

32

For more information www.linear.com/LTC3676 of the application load and the LDO load. This example is with the LDO regulators at one third rated current and the switching regulators at three quarters rated current.

LDO2

LDO3

LDO4

Buck1

Buck2

Buck3

Buck4

Table 23. LTC3676 Power Loss Example

LDO1

V

IN

3.8

1.8

3.3

3.3

3.8

V

OUT

1.2

1.2

1.8

2.5

1.2

3.8

1.8

3.8

1.25

3.8

3.3

APPLICATION

LOAD (A)

0.01

0.1

0.1

0.1

1.875

1.775

1.125

0.925

TOTAL

LOAD (A)

0.010

0.100

0.100

0.100

1.875

1.875

1.125

1.125

EFF

(%) P

D

(mW)

– 26.00

– 60.00

–

–

150.00

80.00

80 450.00

85

80

90

506.25

281.25

371.25

Total Power = 1925

Internal Junction Temperature at 55°C Ambient 120°C

Printed Circuit Board Layout

When laying out the printed circuit board, the following checklist should be followed to ensure proper operation of the LTC3676:

1. Connect the exposed pad of the package (Pin 41) directly to a large ground plane to minimize thermal and electrical impedance.

2. The switching regulator input supply traces to their decoupling capacitors should be as short as possible.

Connect the GND side of the capacitors directly to the ground plane of the board. The decoupling capacitors provide the AC current to the internal power MOSFETs and their drivers. It is important to minimize inductance from the capacitors to the LTC3676 pins.

3. Minimize the switching power traces connecting SW1,

SW2, SW3, and SW4 to the inductors to reduce radiated EMI and parasitic coupling. Keep sensitive nodes such as the feedback pins away from or shielded from the large voltage swings on the switching nodes.

4. Minimize the length of the connection between the step-down switching regulator inductors and the output capacitors. Connect the GND side of the output capacitors directly to the thermal ground plane of the board.

3676fd

LTC3676/LTC3676-1

Typical applicaTions

LTC3676 PMIC Configured to Support Freescale i.MX6 Processor

V

V

3.3V TO 5V

RSTO

IRQ

PGOOD

SCL

SCA

VSTB

PWR_ON

IN

V

RTC

3V

25mA

WAKE

ARM

DDHIGH

I/O

I/O

68k

68k

1µF

68k 68k

33

37

34

18

17

30

10

9

1µF

27

36

PV

IN1

V

IN

22µF

35

PV

IN2

22µF

16

PV

IN3

22µF

22µF

15

PV

IN4

SW3

20

FB_B3

22

28

LDO1

634k

26

FB_L1

200k

LTC3676

SW1

FB_B1

40

24

WAKE

EN_B1

EN_B2

EN_B3

EN_B4

EN_L2

EN_L3

EN_L4

SW2

FB_B2

SW4

31

25

11

4.7k

4.7k

14

13

19

21

29

38

32

39

12

RSTO

IRQ

PGOOD

DV

ON

DD

SCL

SDA

VSTB

PWR_ON

FB_B4

V

FB_L2

V

V

IN_L2

LDO2

IN_L3

LDO3

IN_L4

23

2

3

1

5

4

7

1µH

10pF

1.5µH

10pF

1.5µH

10pF

1µH

10pF

1µF

1µF

1µF

LDO4

6

FB_L4

8

GND

41

634k

200k

178k

200k

178k

200k

715k

200k

215k

1µF

(1.37V)

47µF

(1.37V)

47µF

47µF

47µF

LDO4

3V

(3.3V)

300mA

I/O

3.3V

1.5A

ARM

0.9V TO 1.5V

AT 2.5A

SOC

0.9V TO 1.5V

AT 1.5A

DDR

1.5V AT 2.5A

200k

619k

200k

V

DDHIGH

2.97V

300mA

1µF

SEQUENCE:

WAKE ARM

SOC

1µF

LDO3

1.8V

300mA

I/O

3676 TA02

FREESCALE i.MX6

VSNVS_IN

VDDARM_IN

VDDSOC_IN

VDDHIGH_IN

VDD_DDR_IO

GND

DDR

≤ 4 CHIPS

NO TERM

VDDHIGH

LDO3

DDR


3676fd

33

LTC3676/LTC3676-1

Typical applicaTions

LTC3676-1 PMIC Configured to Support Freescale i.MX6 Processor with DDR V

TT

and VTTR

V

V

DDHIGH

ARM

I/O

RSTO

IRQ

PGOOD

SCL

SCA

VSTB

PWR_ON

IN

3V TO 5.5V

LDO1

3V

25mA

WAKE

68k

68k

1µF

68k 68k

17

30

10

33

37

34

18

1µF

27

36

PV

IN1

V

IN

22µF

35

PV

IN2

22µF

16

PV

IN3

22µF

22µF

15

PV

IN4

SW3

20

FB_B3

22

28

LDO1

634k

26

FB_L1

SW2

31

200k

LTC3676-1

FB_B2

25

WAKE

EN_B1

EN_B2

EN_B3

EN_B4

EN_L2

EN_L3

SW4

FB_B4

SW1

11

23

40

4.7k

38

32

39

12

4.7k

14

13

19

21

29

RSTO

IRQ

PGOOD

DV

DD

SCL

SDA

VSTB

PWR_ON

ON

FB_B1

VDDQIN

VTTR

V

IN_L2

LDO2

FB_L2

V

IN_L3

24

8

9

2

3

1

5

1µH

10pF

1.5µH

10pF

1µH

10pF

1µH

10pF

1µF

1µF

LDO3

V

IN_L4

4

7

1µF

LDO4

6

GND

41

178k

(1.37V)

47µF

V

DDHIGH

ARM

0.9V TO 1.5V

AT 2.5A

FREESCALE i.MX6

VSNVS_IN

VDDHIGH_IN

VDDARM_IN

200k

178k

(1.37V)

47µF

SOC

0.9V TO 1.5V

AT 1.5A

VDDSOC_IN

200k

47µF

DDR

1.5V AT 2.5A

VDD_DDR_IO

215k

200k

215k

VTT

0.75V AT 1.5A

47µF

GND

619k

200k

0.047µF

1µF

V

DDHIGH

2.97V

300mA

SEQUENCE:

WAKE ARM

SOC

1µF

LDO3

1.8V

300mA

1µF

3676 TA03

LDO4

3V

300mA

DDR

8 CHIPS

WITH TERM

VDDHIGH

LDO3

DDR

VTT

34


3676fd

LTC3676/LTC3676-1

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UJ Package

40-Lead Plastic QFN (6mm

× 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

0.70 ±0.05

4.42 ±0.05

4.50 ±0.05

(4 SIDES)

5.10 ±0.05

6.50 ±0.05

4.42 ±0.05

0.25 ±0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

PACKAGE OUTLINE

0.75 ±0.05

6.00 ±0.10

(4 SIDES)

PIN 1 TOP MARK

(SEE NOTE 6)

R = 0.10

TYP

R = 0.115

TYP

4.50 REF

(4-SIDES)

4.42 ±0.10

PIN 1 NOTCH

R = 0.45 OR

0.35

× 45°

CHAMFER

39 40

4.42 ±0.10

0.40 ±0.10

1

2

0.200 REF

0.00 – 0.05

NOTE:

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

BOTTOM VIEW—EXPOSED PAD

0.25 ±0.05

0.50 BSC

(UJ40) QFN REV Ø 0406


3676fd

35

LTC3676/LTC3676-1

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LXE Package

48-Lead Plastic Exposed Pad LQFP (7mm

× 7mm)

(Reference LTC DWG #05-08-1927 Rev Ø)

Exposed Pad Variation AA

7.15 – 7.25

5.50 REF

1

48 37

36

0.50 BSC

C0.30

5.50 REF

7.15 – 7.25

0.20 – 0.30

4.15 ±0.05

4.15 ±0.05

12

13

PACKAGE OUTLINE

24

25

1.30 MIN

1

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

9.00 BSC

7.00 BSC

48 37

SEE NOTE: 3

A

36

A

9.00 BSC

7.00 BSC

36

37

4.15 ±0.10

C0.30

48

1

4.15 ±0.10

36

12

C0.30 – 0.50

25

25 12

13

11° – 13°

24 24 13

BOTTOM OF PACKAGE—EXPOSED PAD (SHADED AREA)

1.35 – 1.45

1.60

MAX

R0.08 – 0.20

GAUGE PLANE

0.25

0° – 7°

11° – 13°

1.00 REF

0.45 – 0.75

SECTION A – A

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT

0.17 – 0.27

SIDE VIEW

LXE48 (AA) LQFP 0612

0.05 – 0.15

3. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER

4. DRAWING IS NOT TO SCALE

3676fd


revision hisTory

REV DATE DESCRIPTION

A 12/13 Modified the Typical Application Circuit

Modified Start-Up Sequence Path

Changed Conditions on V

IN

Burst Mode Quiescent Current

Removed Transient Response comment from V

OUT

Programming

Modified Command Registers table

Modified P

D

equation in PCB Power Dissipation section Table 23

Changed R and C values in Typical Applications

B

C

9/14 Changed C values in application circuits

Corrected pin names in Conditions in Electrical Characteristics table

Corrected units on Current Limit graph

Corrected units on LDO1 Dropout and LDO1 Load Response graphs

Corrected Operation Introduction section

Modified LTC3676-1 Operation section

Changed table reference in I

2

C Operation section

Changed table number for Command Registers section

Clarified Command Registers table

9/14 Added LQFP Package (LXE)

D 05/15 Modified Thermal Resistance of LXE Package

Modified Pin Description of EN_B1

Modified Figure 1 GND

Clarified LTC3676-1 Operation Section

Amended Package Drawing

LTC3676/LTC3676-1

PAGE NUMBER

3

16

1

1

28-30

31

32, 33, 36

1, 32, 33, 36

3 to 5

8

9

14

24

25

28

30

1 to 3, 11,

12, 36

2

12

15

25

36

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-


3676fd

37

LTC3676/LTC3676-1

Typical applicaTion

Sequenced Power for High Performance Processor and DDR Memory Using LTC3375 Parallelable Buck Converters

V

TT

0.75V

1.5A

IO18

1.8V

1.5A

SOC

1.35V

2.5A

V

DDHIGH

3V

2.5A

V

IN

5V

POWER GOOD

FROM V

IN

SUPPLY

1.5µH

47µF

215k

10pF

47µF

47µF

294k

200k

174k

200k

47µF

634k

200k

1.2V

300mA

IO18

1.5µH

10pF

1µH

10pF

1µH

10pF

1µF

SW2

FB_B2

SW3

FB_B3

SW4

FB_B4

LDO4

22µF

22µF

22µF

PV

IN4

PWR_ON

PV

IN3

SW1

PV

IN2

PV

IN1

V

IN

LDO1

FB_B1

FB_L1

VIN_L4

LTC3676-1

VIN_L2

LDO2

FB_L2

VIN_L3

LDO3

RSTO

IRQ

PGOOD

WAKE

22µF

634k

200k

576k

200k

1µF

1µF

1µF

V

RTC

3V

25mA

IO33

1µF

2.8V

300mA

10µF

10µF

3.3V

21.5k

V

IN1

V

SHNT

V

CC

V

IN2

V

IN3

1Ω

10µF

1.02M

576k

FBV

CC

10µF

10µF

0.01µF

RT

PB

CT

10µF

10µF

10µF

10µF

V

IN4

V

IN5

V

IN6

V

IN7

LTC3375

FB1

FB2

FB3

FB4

SW5

V

IN8

SW1

SW2

SW3

SW4

FB5

IO33

1µF

IO18ANALOG

1.8V

300mA

SYNC

EN2

EN3

EN4

EN7

EN8

ON

WDO

IRQ

RST

KILL

SW6

SW7

SW8

FB6

FB7

FB8

EN1

EN5

EN6

VTTR

750mV

±10mA

EN_B1

EN_B2

EN_B3

EN_B4

EN_L3

EN_L2

VDDQIN

VTTR

GND

DV

DD

ON

SDA

SCL

VSTB

MICROPROCESSOR

CONTROL

4.7k

4.7k

SDA

SCL

WDI

TEMP

GND

2.2µH

174k

200k

100µF

ARM

1.35V

4A

2.2µH

2.2µH

715k

200k

22µF

I033

3.3V

1A

DRAM

1.5V

3A

68µF

215k

200k

3676 TA04

relaTeD parTs

PART

NUMBER DESCRIPTION

LTC3101 1.8V to USB, Multioutput DC/

DC Converter with Low Loss USB

Power Controller

LTC3375

LTC3589/

LTC3589-1/

LTC3589-2

8-Channel Programmable,

Parallelable 1A Buck DC/DCs

8-Output Regulator with

Sequencing and I

2

C

LTC3586/

LTC3586-1

38

Switching USB Power Manager

PMIC with Li-Ion/Polymer Charger

COMMENTS

Seamless Transition Between Multiple Input Power Sources, V

IN

Converter V

OUT

V

OUT

QFN Package

Range: 1.5V to 5.25V, 3.3V

: 0.6V to V

IN

OUT

at 800mA for V

IN

Range: 1.8V to 5.5V, Buck-Boost

≥ 3V, Dual 350mA Buck Regulators,

, 38μA Quiescent Current in Burst Mode Operation, 24-Lead 4mm  4mm  0.75mm

8-Channel Independent Step-Down DC/DCs. Master Slave Configurable for Up to 4A per Output Channel with a Single Inductor, Die Temperature Monitor Output, 48-Lead 7mm

 7mm QFN Package

Triple I

2

C Adjustable High Efficiency Step-Down DC/DC Converters: 1.6A, 1A, 1A. High Efficiency 1.2A

Buck-Boost DC/DC Converter. Triple 250mA LDO Regulators. Pushbutton ON/OFF Control with System

Reset. Flexible Pin-Strap Sequencing Operation. I

2

C and Independent Enable Control Pins, DVS and

Slew Rate Control, 40-Lead 6mm  6mm  0.75mm QFN Package

Complete Multifunction PMIC: Switching Power Manager, 1A Buck-Boost + 2 Bucks + Boost + LDO,

4mm  6mm QFN-38 Package, LTC3586-1 Version Has 4.1V V

FLOAT

.

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900

●

FAX: (408) 434-0507

●


3676fd

LT 0515 REV D • PRINTED IN USA

© LINEAR TECHNOLOGY CORPORATION 2013

LTC3676/LTC3676-1 Power Management Solution for Application Processors FeaTures

FeaTures

applicaTions

DescripTion

Typical applicaTion

Linear Technology Corporation

Related manuals

Table of contents

LTC3676/LTC3676-1 Power Management Solution for Application Processors FeaTures

FeaTures

applicaTions

DescripTion

Typical applicaTion

Linear Technology Corporation

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Table of contents